Programming method of nonvolatile memristor in storage and calculation integrated array

Abstract

The invention provides a programming method of a nonvolatile memristor in a storage and calculation integrated array, and belongs to the technical field of resistive random access memories. According to the invention, the operation of writing pulse width stepping is introduced and is combined with pulse amplitude stepping, so that the achievable writing intensity range is larger, the programming of the nonvolatile memristor and the array thereof with larger fluctuation can be coped with, and the programming success rate is improved. The method has great value for application scenes such as large-scale memristor in-memory computing application and memristor in-memory computing application with limited edge end resources.

Description

Technical Field

[0001] The invention belongs to the technical field of resistive memory, relates to a non-volatile memristor programming method, and specifically to a programming method capable of improving the success rate of array programming for fluctuations of non-volatile memristors. Background Art

[0002] With the booming development of large-scale data-intensive computing tasks such as large natural language models, the integrated storage and computing architecture that is expected to break through the von Neumann bottleneck is rapidly moving towards scale. At the same time, the exponential growth in the number of intelligent computing devices at the edge also promotes the development of efficient integrated storage and computing. Non-volatile memristors have the advantages of non-volatile storage characteristics, fast operation speed, simple structure, great potential for miniaturization and high-density integration, and compatibility with CMOS processes. They are very suitable for realizing integrated storage and computing units. In particular, the multi-value or analog storage characteristics of non-volatile memristors enable integrated storage and computing arrays based on them to implement matrix-vector multiplication operations commonly seen in integrated storage and computing applications in a very small area. This type of architecture uses basic physical laws such as Ohm's law and Kirchhoff's current law to perform computing operations in storage cells and arrays.

[0003] At present, the manufacturing process fluctuations of non-volatile memristors and arrays are still large, which leads to different programming conditions required to program different devices to the same conductance state. The more commonly used multi-value programming methods include the write verification strategy based on the incremental step pulse programming (ISPP). Under the programming strategy of ISPP write verification, the intensity of the write pulse is only determined by the pulse amplitude applied to both ends of the device. If the type of write operation (SET or RESET) currently required for the memristor is the same as the previous write operation type, it means that the conductivity change brought about by the previous write pulse is still insufficient, so the current pulse amplitude needs to be increased to enhance the write intensity. However, due to the limited pulse height, the write intensity that ISPP can achieve is also limited. In the face of arrays with large fluctuations between devices, the programming success rate of extreme conductance values ​​still has room for improvement. Other programming methods, such as the current step programming strategy based on gate voltage stepping applicable to the 1 transistor + 1 resistor (1T1R) unit structure, also have the same problem. In various applications, devices that fail to program will lead to a decrease in system computing performance. If these devices and their rows and columns are not used, array resources will be wasted, which is not conducive to large-scale application scenarios and resource-limited edge computing scenarios. Therefore, in order to realize various applications of non-volatile memristors based on multi-valued or analog conductance, it is urgent to develop a programming method that can more effectively overcome the fluctuation problem between non-volatile memristor devices. Summary of the invention

[0004] In order to overcome the problem of array programming failure caused by insufficient programming strength of the above-mentioned non-volatile memristor, the present invention proposes a programming method for non-volatile memristors in a storage and computing integrated array, which can improve the array programming success rate, thereby improving array utilization and reducing resource waste.

[0005] The technical solution provided by the present invention is as follows:

[0006] A programming method for a non-volatile memristor in a storage-computing integrated array, wherein G read , G T and G e represent the current conductance value, target conductance value and allowable programmable conductance error obtained by the memristor read operation, respectively, and ΔG represents G read With G T The difference, that is, ΔG = G read -G T , n represents the total number of cycles, i represents the number of times the SET or RESET amplitude step pulse is continuously applied, OP' represents the operation type SET or RESET to which the previous amplitude step write pulse sequence belongs, and the specific steps include the following steps:

[0007] 1) Programming starts, reading memristor G read ;

[0008] 2) For G read Make a judgment, if G read In the target conductance range [G T -G e ,G T +G e ], that is, |ΔG| <G e , then the programming is successful; if G read If it is outside the target conductivity range, n is further judged. If n==n max , the programming fails; otherwise, continue to read Make a judgment, if G read Below the target conductance range, ΔG<-G e , then the SET pulse sequence is applied; otherwise it means G read Higher than the target conductivity range, that is, ΔG>G e , a reset RESET pulse sequence should be applied;

[0009] 3) If it is determined in 2) that a RESET pulse sequence is applied, the RESET sub-process is run, that is, the pulse width stepping phase is first entered, and if OP' == RESET, the pulse width is increased, otherwise the pulse width is reset to the initial width;

[0010] 4) If it is determined in 2) that the SET pulse sequence is applied, the SET sub-process is executed, that is, the pulse width stepping phase is first entered, and if OP' == SET, the pulse width is increased, otherwise the pulse width is reset to the initial width.

[0011] Further, after setting the pulse width in step 3), the pulse amplitude stepping stage is entered. Specifically, a RESET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG>G is still satisfied e And i≠i max , then increase the RESET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the RESET sub-process, OP' becomes RESET, and n becomes n+1, and repeat steps 2)-4).

[0012] Further, after setting the pulse width in step 4), the pulse amplitude stepping stage is entered. Specifically, a SET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG<-G is still satisfied e And i≠i max , then increase the SET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the SET sub-process, OP' becomes SET, and n becomes n+1, and repeat steps 2)-4).

[0013] Furthermore, the integrated storage and computing array is composed of periodically arranged 1T1R, 1T2R, and 2T2R resistive memory cell structures.

[0014] The technical effects of the present invention are as follows:

[0015] The present invention provides a programming method for non-volatile memristors in a storage-computing integrated array. The method is for the non-volatile memristors in the storage-computing integrated array. The type of write pulse sequence that should be currently applied to the non-volatile memristors is the same as the type of write pulse sequence applied last time, which means that the pulse amplitude has reached a maximum value in the last write operation, but the change in conductance is still insufficient. In this way, the pulse width is increased. Based on this and combined with amplitude stepping, the write intensity is enhanced in a larger range. That is, the programming method of the present invention introduces the operation of write pulse width stepping, which is combined with pulse amplitude stepping, so that the achievable write intensity range is larger, and the programming of non-volatile memristors and arrays thereof with larger fluctuations can be coped with, thereby improving the programming success rate of devices and arrays. It has great value for application scenarios such as large-scale memristor in-memory computing applications and memristor in-memory computing applications with limited edge resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the non-volatile memristor programming method of the present invention, wherein a to c are respectively the main process of device programming, the sub-process of applying a SET pulse sequence in the main process, and the sub-process of applying a RESET pulse sequence in the main process.

[0017] Figure 2 It is a sub-flow chart written in the existing commonly used ISPP programming method, wherein a and b are the sub-flow of applying a SET pulse sequence and the sub-flow of applying a RESET pulse sequence respectively.

[0018] Figure 3 A schematic diagram of a 1T1R resistive memory cell provided by an embodiment of the present invention.

[0019] Figure 4 The cumulative distribution diagram of the conductance state under different programming methods provided by the embodiment of the present invention, wherein a and b correspond to the existing ISPP programming method and the programming method of the present invention respectively.

[0020] Figure 5 It is the array programming success rate of the high conductance state (taking 38μS and 44μS as examples) under the existing ISPP programming method and the programming method of the present invention. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings. The description here is only used to explain the present invention and is not used to limit the present invention.

[0022] The present invention proposes a programming method for non-volatile memristor fluctuations that can improve the success rate of array programming. The programming method of the present invention introduces a write pulse width stepping operation, which is combined with a pulse amplitude stepping operation to achieve a larger write intensity range, and can cope with the programming of non-volatile memristors and arrays with larger fluctuations, thereby improving the programming success rate.

[0023] Figure 1 The flowchart of the programming method of the present invention for improving the success rate of array programming for non-volatile memristor fluctuations is as follows:

[0024] 1) Programming starts, reading memristor G read .

[0025] 2) For G read Make a judgment. If G read In the target conductance range [G T -G e ,G T +G e ], that is, |ΔG| <G e , then the programming is successful; if G read If it is outside the target conductivity range, the following judgment is made.

[0026] 3) Judge n. If n == n max , the programming fails; otherwise, continue toread Make a judgment. If G read Below the target conductance range, ΔG<-G e , then the SET pulse sequence is applied; otherwise it means G read Higher than the target conductivity range, that is, ΔG>G e , the RESET pulse sequence should be applied.

[0027] 4) If it is determined in (3) that a RESET pulse sequence is applied, the RESET sub-process is run. First, the pulse width stepping stage is entered. If OP' == RESET, the pulse width is increased, otherwise the pulse width is reset to the initial width. Then the pulse amplitude stepping stage is entered. At this time, a RESET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG>G is still satisfied, e And i≠i max , then increase the RESET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the RESET sub-process, OP' becomes RESET, and n becomes n+1, return to step 2, and repeat.

[0028] 5) If it is determined in (3) that a SET pulse sequence is applied, the SET sub-process is run. First, the pulse width stepping stage is entered. If OP'==SET, the pulse width is increased, otherwise the pulse width is reset to the initial width. Then the pulse amplitude stepping stage is entered. At this time, a SET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG<-G is still satisfied, e And i≠i max , then increase the SET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the SET sub-process, OP' becomes SET, and n becomes n+1, return to step 2 and repeat.

[0029] Figure 2 This is a sub-flow chart written in the existing commonly used ISPP programming method, which provides a comparable object for the programming method of the present invention and provides data support for the embodiments of the present invention. Specifically, in the above-mentioned steps of applying the SET and RESET pulse sequence (steps 4 and 5), the pulse width stepping stage is not performed, and the pulse amplitude stepping stage is directly entered, and the pulse width remains unchanged.

[0030] Figure 3 The 1T1R resistive memory cell structure is a typical 1T1R resistive memory cell structure of a storage-computation integrated array. The embodiment of the present invention is based on this structure and provides data support for the effectiveness of the programming method of the present invention. The 1T1R cell consists of a memristor connected to the source terminal of an NMOS transistor, and the top electrode of the memristor, the gate electrode and the drain electrode of the transistor are used as the leads of the cell, and V a 、V g and V bIn the embodiment of the present invention, when a write pulse is applied, V g Always high, turning on the transistor. When the SET write pulse sequence is applied, V a For this pulse sequence, V b Ground; when applying RESET write pulse, V b For this pulse sequence, V a The programming method of the present invention is also applicable to other types of cell structures, including but not limited to 1T2R, 2T2R and other resistive memory cell structures. Further, the resistive layer material of the memristor can be Ta 2 O 5 , HfO 2 The memristor can have an oxygen storage layer, the material can be TaO x 、TiO x 、AlO x 、SiO x , HfO x The materials of the top electrode and the bottom electrode can be TiN, TaN, Ta, Ti, W, Al, Cu, Ag, Pt, Ir, etc.

[0031] Specifically, TiN / HfO 2 / TaO x / TiN memristor 1T1R cell array as an example, Figure 4 The cumulative distribution diagram of 8 conductance states (2μS, 8μS, 14μS, 20μS, 26μS, 32μS, 38μS and 44μS) of the array under the existing commonly used ISPP and the programming method of the present invention, wherein for a certain conductance value, each data point corresponds to an array unit. It can be seen that the ISPP programming method has limited writing intensity, so that some devices fail to be programmed, while under the programming method of the present invention, almost all devices can be successfully programmed to various conductance states.

[0032] Furthermore, TiN / HfO 2 / TaO x / TiN memristor 1T1R cell array as an example, Figure 5 The array programming success rates of two high-conductance states under the conventional ISPP and the programming method of the present invention are shown in FIG. 1. It can be seen that the present invention introduces pulse width stepping, and if the programming strategy of the present invention is adopted, the array programming success rate is improved.

[0033] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A method for programming a non-volatile memristor in a storage-computation integrated array, characterized in that: Among them G read , G T and G e represent the current conductance value, target conductance value and allowable programmable conductance error obtained by the memristor read operation, respectively, and ΔG represents G read With G T The difference, that is, ΔG = G read -G T , n represents the total number of cycles, i represents the number of times the SET or RESET amplitude step pulse is continuously applied, OP' represents the operation type SET or RESET to which the previous amplitude step write pulse sequence belongs, and the specific steps include the following steps: 1) Programming starts, reading memristor G read ; 2) For G read Make a judgment, if G read In the target conductance range [G T -G e ,G T +G e ], that is, |ΔG| <G e , then the programming is successful; if G read If it is outside the target conductivity range, n is further judged. If n==n max , the programming fails; otherwise, continue to read Make a judgment, if G read Below the target conductance range, ΔG<-G e , then the SET pulse sequence is applied; otherwise it means G read Higher than the target conductivity range, that is, ΔG>G e , a reset RESET pulse sequence should be applied; 3) If it is determined in 2) that a RESET pulse sequence is applied, the RESET sub-process is run, that is, the pulse width stepping phase is first entered, and if OP' == RESET, the pulse width is increased, otherwise the pulse width is reset to the initial width; 4) If it is determined in 2) that the SET pulse sequence is applied, the SET sub-process is executed, that is, the pulse width stepping phase is first entered, and if OP' == SET, the pulse width is increased, otherwise the pulse width is reset to the initial width.

2. The method for programming a non-volatile memristor in a storage-computation-in-one array according to claim 1, characterized in that: After setting the pulse width in step 3), the pulse amplitude stepping stage is entered. Specifically, a RESET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG>G is still satisfied e And i≠i max , then increase the RESET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the RESET sub-process, OP' becomes RESET, and n becomes n+1, and repeat steps 2)-4).

3. The method for programming a non-volatile memristor in a storage-computation-in-one array according to claim 1, characterized in that: After setting the pulse width in step 4), the pulse amplitude stepping stage is entered. Specifically, a SET pulse is applied, i becomes i+1, and then the conductance is read. If ΔG<-G is still satisfied e And i≠i max , then increase the SET pulse amplitude and repeat the pulse amplitude stepping stage; otherwise, end the SET sub-process, OP' becomes SET, and n becomes n+1, and repeat steps 2)-4).

4. The method for programming a non-volatile memristor in a storage-computation-in-one array according to claim 1, characterized in that: The integrated storage and computing array is composed of periodically arranged 1T1R, 1T2R, and 2T2R resistive memory unit structures.

5. The method for programming a non-volatile memristor in a storage-computation-in-one array as claimed in claim 4, characterized in that: The memristor comprises a top electrode layer, a resistive switching layer and a bottom electrode layer stacked from top to bottom, wherein the resistive switching layer is made of Ta2O5 or HfO2 metal oxide.

6. The method for programming a non-volatile memristor in a storage-computation-in-one array as claimed in claim 5, characterized in that: In the memristor, an oxygen storage layer is arranged on the resistive switching layer, and the material of the oxygen storage layer is TaO x 、TiO x 、AlO x 、SiO x , HfO x Metal oxides.

7. The method for programming a non-volatile memristor in a storage-computation-in-one array as claimed in claim 5, characterized in that: The materials of the top electrode and the bottom electrode in the memristor are TiN, TaN, Ta, Ti, W, Al, Cu, Ag, Pt, and Ir metals.

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