Memory device, memory system having same, and operating method thereof

Abstract

A memory device according to various example embodiments includes: a memory cell array having a plurality of memory cells connected to word lines and bit lines; and an error correction circuit configured to perform error correction on data read from the memory cell array, in which the error correction circuit is configured to perform at least one of a 1-bit error correction operation, a 2-bit error detection operation, or a 3-bit error detection operation using a parity check matrix, and the parity check matrix is configured such that the columns are arranged in an odd-odd-even order, and the leading 1 (LO) of each row is arranged in a stepped structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0151085 filed in the Korean Intellectual Property Office on November 3, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments relate to a memory device for supporting triple adjacent error detection, a memory system having the memory device, and / or an operation method thereof. Background Art

[0004] Typically, due to various external factors, errors may occur in memory systems, and these errors can significantly affect system performance. In order to mitigate or reduce this impact, various error correction technologies are being developed. SEC (Single Error Correction) automatically corrects single-bit errors to ensure data integrity. This effectively handles small errors within the memory and contributes to system stability. DED (Double Error Detection) can detect two errors that occur simultaneously, but cannot correct them. This technology alerts the system to abnormalities, allowing appropriate measures to be taken to prevent them from escalating into more significant problems. TAED (Triple Adjacent Error Detection) detects errors that occur in three adjacent bits. This method enables early detection of problems that may be caused by physical damage to the memory chip or related errors. These technologies all enhance the reliability of the memory system based on their characteristics and prevent potential data loss or damage. Summary of the invention

[0005] Various example embodiments may provide a memory device having a novel error correction technology, a memory system having the memory device, and / or an operating method thereof.

[0006] Alternatively or additionally, various example embodiments may provide a memory device supporting triple adjacent error detection (TAED), a memory system having the same, and an operating method thereof.

[0007] According to some example embodiments, a memory device is provided, comprising: a memory cell array having a plurality of memory cells connected to a word line and a bit line; and an error correction circuit configured to perform error correction on data read from the memory cell array. The error correction circuit is configured to perform at least one of a 1-bit error correction operation, a 2-bit error detection operation, and a 3-bit error detection operation using a parity check matrix, and the parity check matrix is ​​configured so that columns are arranged in an odd-odd-even degree order, and leading one (LO) of each row is arranged in a staircase structure.

[0008] Alternatively or additionally, according to various example embodiments, there is provided a memory system, comprising: at least one memory device configured to perform a first error correction operation; and a controller configured to control the at least one memory device and perform a second error correction operation. At least one of the first error correction operation and the second error correction operation includes performing a 1-bit error correction operation, a 2-bit error detection operation, and a 3-bit error detection operation using a parity check matrix, and the parity check matrix is ​​configured such that columns are arranged in an odd-odd-even order, and leading 1s (LOs) of each row are arranged in a staircase structure.

[0009] Alternatively or additionally, a method for operating a memory device is provided, comprising: encoding a message using a parity check matrix; receiving a codeword generated by encoding the message through a channel; and decoding the received codeword using the parity check matrix, wherein the parity check matrix is ​​configured such that columns are arranged in an odd-odd-even order and leading 1s (LOs) of each row are arranged in a staircase structure.

[0010] A memory device having a novel error correction technique, a memory system having the same, and / or an operating method thereof according to various example embodiments may map at least three types of errors into one syndrome.

[0011] A memory device having a novel error correction technique, a memory system having the same, and / or an operating method thereof according to various example embodiments may enable DED by inserting an additional row into an H-matrix in an ECC circuit supporting SEC / TAED. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a diagram illustrating a memory system according to some example embodiments;

[0014] Figure 2 is an example diagram showing a general linear block code;

[0015] Figure 3 is an example diagram showing a channel model for a general linear block code;

[0016] Figure 4 is an example view showing PCM of Hsiao SEC-DED (22, 16) code;

[0017] Figure 5 is an example view showing PCM of Dutta and Touba SEC-DED-DAEC code;

[0018] Figure 6 is an example diagram showing DAEC syndrome sets for Dutta and Touba codes;

[0019] Figure 7 is an example view showing a PCM of a Reviriego code;

[0020] Figure 8 is an example view showing a DAEC correction subset of a Reviriego code;

[0021] Fig. 9 is an example diagram showing PCM of SEC-TAED Sánchez code;

[0022] Fig.10 is an example diagram showing PCM of a SEC-DED-TAED Sánchez code;

[0023] Fig.11 is an example diagram illustrating an algorithm for generating a SEC-TAED code according to an input parity length according to some example embodiments;

[0024] Fig.12 It is shown from the perspective of PCM. PCM of SEC-DED-TAED code with expurgation 's view;

[0025] Fig.13 is a diagram showing the PCM when the PCMH performs the elimination Example view of;

[0026] Fig.14 is an example diagram showing a low latency low complexity PCM low variation for a SEC-DED-TAED code undergoing erasure;

[0027] Fig.15 is an example view of a schematic diagram showing the use of a system SEC-DED-TAED code;

[0028] Fig.16 It shows H sub Example view of SEC-DED-TAED code PCM including two all-1 rows;

[0029] Fig.17 is a graph showing that when the message length generated by the SEC-TAED design method is 16 Example view of;

[0030] Fig.18 It shows that when the message length is 16, is an example view of PCM of a full-rank SEC-TAED code;

[0031] Fig.19 is a diagram showing the H obtained by designing a SEC-TAED code with a parity check length of 6. base A view of an example embodiment of the invention;

[0032] Fig. 20 is a diagram showing the H obtained by designing a SEC-TAED code with a parity check length of 6. base A view of another example embodiment of;

[0033] Fig.21 is an example view showing a SEC-TAED sub-matrix of message length 32 considering elimination;

[0034] Fig. 22 is an example view showing a SEC-TAED sub-matrix with a message length of 32 considering left extension;

[0035] Fig.23 is an example view showing a (39, 32)SEC-DED-TAED code by erasure;

[0036] Fig.24 is an example view showing a (39, 32)SEC-DED-TAED code by left extension;

[0037] Fig.25 is an example diagram showing optimization in PCM of (39, 32)SEC-DED-TAED code by elimination;

[0038] Fig.26 is an example diagram showing optimization in PCM of (39, 32)SEC-DED-TAED code by extension;

[0039] Fig. 27is an example diagram showing PCM of a SEC-TAED code with distributed parity;

[0040] Fig.28 is an example view showing the reselection of submatrix column vectors of full rank (6);

[0041] Fig.29 is an example diagram showing PCM of a (39, 32)SEC-DED-TAED code with local parity check;

[0042] Fig.30 is an example diagram showing a PCM of a diagonalized (39, 32)SEC-DED-TAED code;

[0043] Fig.31 is an example diagram showing PCM of a (72, 64)SEC-DED-TAED code with local parity check;

[0044] Fig.32 is an example diagram showing a PCM of a diagonalized (72, 64)SEC-DED-TAED code;

[0045] Fig.33 is an example diagram showing PCM of a (137, 128)SEC-DED-TAED code with local parity check;

[0046] Fig.34 is an example diagram showing the PCM rule of a diagonalized (137, 128) SEC-DED-TAED code;

[0047] Fig.35 is an example diagram showing PCM of a (22, 16)SEC-DED-TAED code with local parity check;

[0048] Fig.36 is an example diagram showing a PCM of a diagonalized (22, 16)SEC-DED-TAED code;

[0049] Fig.37 is a view illustrating a SEC-DED-TAED code generation method according to some example embodiments;

[0050] Fig.38 is an example diagram illustrating a process of imparting DED characteristics according to some example embodiments;

[0051] Fig.39 is a diagram illustrating PCM weight optimization for low-latency low-complexity decoding according to some example embodiments;

[0052] Fig.40is a diagram illustrating a SEC-DED-TAED code design technique taking into account a systematic code to reduce code complexity according to some example embodiments;

[0053] Fig.41 is a diagram illustrating a TAE syndrome according to some example embodiments; and

[0054] Fig.42 is an example view illustrating a semiconductor package including stacked semiconductor chips according to some example embodiments. DETAILED DESCRIPTION

[0055] Hereinafter, various example embodiments will be described clearly and in detail using the accompanying drawings so that a person having ordinary skill in the art can easily realize some inventive concepts.

[0056] Generally, based on the information theory proposed by C. Shannon, error correction codes (ECC) are being studied to approach channel capacity. Error correction codes include techniques for using parity bits to correct errors that occur during data transmission and reception. This technology has been used in various wireless communication fields to protect messages, and has been applied to the memory semiconductor field to correct and detect errors that occur in cells. Memory technologies such as DRAM (dynamic random access memory) and / or SRAM (static random access memory) must accurately send and store data in a short time. Therefore, it is necessary or desirable to have fast data processing speeds and / or high reliability. However, various errors that occur in memory cells reduce the reliability of the memory. For example, in DRAM, linear block-based error correction codes with relatively few parity bits are introduced to enhance reliability in environments with limited space and delay overhead. Generally, linear block-based error correction codes are used in the fields of communication and data storage to ensure or improve the reliability of data. These linear block codes generate "codewords" by combining additional parity bits generated from data bits. This enables errors that occur during data transmission or storage to be detected and corrected when necessary or possible. The "linear" property means that a linear combination of codewords produces a codeword. These codes are implemented in various forms (one or more of parity check, Hamming code, Reed-Solomon code, etc.) depending on their ability to identify and correct error locations.

[0057] The probability of an error occurring in a typical memory device is very low. In addition, since the error mostly manifests as a single-bit error, a linear block code with SEC (single error correction) capability is being proposed. Recently, in order to improve performance, memory devices have been undergoing densification and low-power operation, which may lead to an increased probability of multi-bit upset (MBU) errors within a codeword. In order to correct or improve MBU, a linear block code with SEC capability is proposed, which uses one or more of BCH (Bose-Chaudhuri-Hocquenghem) code, RS (Reed-Solomon) code and interleaver to distribute multiple errors and convert them into single errors while maintaining the SEC characteristics. However, linear block codes with high error correction capabilities usually have a large amount of space overhead for parity storage. In addition, due to the increased logic complexity, there is a significant delay overhead during decoding. However, MBU mainly occurs in physically adjacent cells in a memory device in a burst form. Therefore, a linear block code that reduces or minimizes space and / or delay overhead when solving burst errors is needed.

[0058] According to various example embodiments, a memory device, a memory system including the memory device, and / or an operation method thereof may support a SEC-DED (Double Error Detection)-TAE (Triple Adjacent Error Detection) code that maps at least three types of errors to a single syndrome. Specifically, various example embodiments may enable DED by inserting additional rows into a parity check matrix (alternatively referred to as an H matrix) of an error correction circuit that supports SEC / TED.

[0059] In various example embodiments, the SEC-DED-TAED code can be configured in an H matrix, where columns are arranged in an [even-odd-odd] pattern. Here, an odd column indicates that the number of 1s in a binary column is an odd number. The i-th odd column can be designed by XORing the (i-1)th column, the (i-3)th column, and the (i-4)th column. In some example embodiments, the SEC-DED-TAED code can support non-systematic encoding (NSE) and systematic encoding. In this context, systematic encoding indicates that the input data is included in the output of the encoding. Typically, in commercial systems, systematic codes that clearly distinguish codewords from data and parity are preferred. The SEC-DED-TAED code adds a full 1 row to the H matrix for DED.

[0060] In some example embodiments, the SEC-DED-TAED code may be designed for arbitrary message lengths. In addition, the SEC-DED-TAED code of various example embodiments may reduce syndrome computation complexity and latency.

[0061] Figure 1 is a diagram illustrating a memory system according to some example embodiments. Figure 1 , the memory system 10 may include a memory module MM 11 and a controller CTRL 12 .

[0062] The memory system 10 may be implemented as included in a personal computer and / or a mobile electronic device. The mobile electronic device may be implemented as one or more of a laptop computer, a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, etc.

[0063] The memory module MM11 may include a plurality of memory devices MEM. In some example embodiments, the memory device MEM may be implemented as a volatile memory device or may include a volatile memory device. The volatile memory device may be implemented as one or more of a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), or a low power double data rate (LPDDR) DRAM. In some example embodiments, the memory device MEM may be implemented as a non-volatile memory device or may include a non-volatile memory device. For example, the memory device MEM may be implemented as one or more of an electrically operable programmable read-only memory (EEPROM), a flash memory, an MRAM, an STT-MRAM, a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive memory (resistive RAM (RRAM)), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, and an insulator resistive change memory.

[0064] The memory device MEM may include a memory cell array including a plurality of memory cells connected to rows (word lines) and columns (bit lines), and a first error correction circuit ECC1 for correcting errors in data read from the memory cell array. In some example embodiments, the first error correction circuit ECC1 may include an error correction unit that performs error correction in different ways according to a physical location (or address). When a non-single-bit error (NSB) occurrence location in data varies for each fault according to a physical location in the memory device MEM, the memory device (MEM) may correct an error in an on-die error correction code (OD-ECC) (e.g., a first error correction circuit (ECC1) of the memory device MEM), and / or may cause a correction error (miscorrection) of the OD-ECC to occur within a correctable range in a second correction circuit (ECC2, system ECC) of the controller 12.

[0065] The first error correction circuit ECC1 can be implemented to correct errors in the memory device MEM. The first error correction circuit ECC1 may include an error correction unit that receives an input of a physical location (e.g., a row address, a memory body (bank) address, etc.) and performs encoding / decoding. In some example embodiments, the error correction unit may be operated by an H matrix. Here, the H matrix is ​​used to generate an error syndrome, such as an error vector, by multiplying with a codeword. The H matrix may include a SEC-DED-TAED code that maps at least three types of errors into one (e.g., exactly one) syndrome.

[0066] In some example embodiments, the first error correction circuit ECC1 may perform one or more of a 1-bit error correction operation, a 2-bit error detection operation, and an adjacent 3-bit error detection operation using an H matrix. Here, the H matrix may be configured so that the columns are arranged in an odd-odd-even order, and the leading 1 (LO) of each column may be arranged in a staircase structure. In some example embodiments, the 1-bit error correction operation may be a single error correction (SEC) operation, or may include a single error correction (SEC) operation, or may be included in a single error correction (SEC) operation, the 2-bit error detection operation may be a error detection (DED) operation, or may include an error detection (DED) operation, or may be included in an error detection (DED) operation; the adjacent 3-bit error detection operation may be a triple adjacent error detection (TAED) operation, or may include a triple adjacent error detection (TAED) operation, or may be included in a triple adjacent error detection (TAED) operation. The first error correction circuit ECC1 may be implemented with a systematic code. In some example embodiments, the H matrix may be implemented using an odd-order column based SEC-DED-TAED code, which may reduce decoding complexity and / or latency.

[0067] The controller CTRL 12 may be implemented as one or more of an integrated circuit, a system on a chip (SoC), an application processor (AP), a mobile AP, a chipset, or a collection of chips. The controller 12 may include one or more of a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), a natural processing unit (NPU), or a modem. In some example embodiments, the controller 12 may perform the functions of a modem and the functions of an AP.

[0068] The controller 12 may be implemented to control the memory module 11 to read data stored in the memory module 11 or to write data to the memory module MM11. The controller 12 may provide a command CMD and an address ADDR to the memory module MM11 in synchronization with the clock CLK, thereby controlling a write operation and / or a read operation relative to the memory module MM11. In addition, data DQ may be sent and received between the controller 12 and the memory module MM11 in synchronization with the data transfer clock WCK. In addition, the controller 12 may include a second error correction circuit ECC2 for correcting errors in the data DQ sent and received with the memory module MM11.

[0069] The memory system 10 according to some example embodiments can be implemented with several parity check matrices (PCM) of specific message lengths. As a detection method for double errors, code extension and code elimination can be added. The PCM of various example embodiments can generate SEC-DED-TAED codes that meet all message lengths. In addition, the memory system 10 of various example embodiments can reduce the space overhead and / or complexity increased by the decoder of the SEC-DED-TAED code. For the actual use of the SEC-DED-TAED code of the example embodiment, the system code can be implemented with a specific message length. Specifically, a system code with local parity can be implemented, in which data and parity are locally separated.

[0070] Error correction codes for general memory devices encode / decode messages based on linear block codes. In this case, the vector generated during the decoding process is called a syndrome. Depending on how the syndrome is used, the detection and correction capabilities of a specific error pattern are determined. In the following, only binary linear block codes are described. Binary linear block codes include n-dimensional Here, n is the block length, n is the message length, and F 2 = {0,1} is the size of the Galois field 2 (property 2). The remainder r = nk is the parity check length. n Select 2 from the vector space formed by the points k The (n,k) block codes are used to generate linear block codes, each of which has a length of n. A linear block code C is generated by a k×n matrix G, called the generator matrix.

[0071] Figure 2 is an example diagram showing a general linear block code. Figure 2 , when there is a message m, the code c is defined as follows.

[0072] c=mG Formula 1

[0073] The generator matrix of a systematic code capable of distinguishing a message bit region and a parity bit region within the code can be expressed as follows.

[0074] G=[I k ∶P] Formula 2

[0075] Here, P is a binary k×(nk) matrix, I k is a k×k identity (uint) matrix. In case of systematic code, the parity check matrix (PCM) H can be easily found using the matrix and is expressed as follows.

[0076] H=[P T :I n-k ] Formula 3

[0077] Here, (·) T represents the transpose of the matrix. The size of PCMH is (nk)×n, and the matrix satisfies Hc for all codes c∈C T = 0. By utilizing this feature, PCM can detect an error included in a vector (y) received through a channel.

[0078] Figure 3 is an example view showing a channel model of a general linear block code. A signal transmitted through a channel considering a binary channel is represented as follows.

[0079] y=c+e Formula 4

[0080] Here, e is the binary error vector and + is F 2 In this case, the syndrome can be obtained in the following way.

[0081] s=Hy T =H(c+e) T =He T Formula 5

[0082] Therefore, the correction factor It can only be obtained by errors, regardless of the code. When no code errors are received, the syndrome has s = 0. The number of syndromes for a linear block code is 2 n-k . Because this is a larger number than the number of all error modes (2 n ) is a small number, so not all errors can be corrected. Therefore, the syndrome corrects the error by assigning each syndrome to the target of the error that occurs as frequently as possible among all error patterns. When f(·) is a table that pre-maps error patterns and syndromes, the decoding process is as follows. The syndrome is obtained by the received signal (s = Hy T ≠0). Then, the error pattern is estimated using table f(·). Then, the error is corrected by adding the estimated error pattern to the received signal

[0083] Error correction based on syndrome error mapping can store mapping information in a table, and can compare the mapping information with the syndrome to correct the error. For this reason, time overhead in the memory semiconductor can be reduced or improved.

[0084] At the same time, the syndrome-error mapping method can be used not only to correct errors but also to detect errors. is a set of possible syndrome values, S in S c can be divided into a set of syndrome values ​​for correcting a specific error pattern, and S dcan be divided into sets of syndrome values ​​for detecting specific error patterns. When the intersection between the two sets is When s is equal to or is empty, each specific error pattern can be corrected and detected without miscorrection. When the syndromes used for error detection and correction are separated from each other, the decoding process is as follows. The syndrome is obtained by receiving the signal (s = Hy T ≠0). If s∈S c , then through To correct the error. If s∈S d , then the received signal is determined to have errors. Therefore, using the syndrome-based error detection and correction method, codes for target error patterns can be designed more efficiently despite the limited parity check length.

[0085] Generally, Hamming code is a binary linear block code with single error correction capability. When there is a parity check bit m, the Hamming code has a code length and a message length (n, k) = (2 m -1,nm). The PCM of Hamming code includes all 2 m -1 different non-zero vector. e i is defined as a vector with weight 1. This corresponds to the vector representing the error at the ith position in the code. When is the i-th column vector of the Hamming code PCM, the syndrome for the single error mode can be obtained as follows.

[0086]

[0087] Therefore, in the Hamming code, the column vector of the PCM is used as a syndrome to correct a single error at each position. Therefore, when the column of the PCM has different vectors other than zero, the PCM can correct a single error by the number of columns.

[0088] Meanwhile, Hsiao code can detect double errors and correct single errors through binary linear block codes.

[0089] Figure 4 is an example view of the PCM showing the Hsiao SEC-DED (22, 16) code. It can be confirmed that the corresponding code preferentially uses a vector in which the message bits are 16 bits, the parity bits are 6 bits, and the Hamming weights (or the number of 1s) of each column vector in the PCM are 1 and 3. When the Hsiao code has the same message length as the Hamming code, the Hsiao code further uses one parity bit, but a double error may be detected. The code design method first uses different vectors as columns of the PCM to have single-error capability. In this case, all the Hamming weights of the column vector have odd values. Therefore, the syndrome vector (S SE) have odd weights and match one of the columns of the PCM. The occurrence of a double error is represented by e = e i +e j , and e i is a vector where the vector weight is 1. In this case, the syndrome of the double error is expressed as follows.

[0090]

[0091] Here, + represents a binary XOR (exclusive OR) operation, and the double error correction code S DE is given as the XOR operation value of different i-th and j-th column vectors, and in this case, when performing an XOR operation on two vectors with odd weights, the two vectors are always converted to even weights. Therefore, since the weights of all double error syndromes are represented as even numbers, and since Or the intersection is empty, thus double errors are detected without miscorrection. In addition, in order to minimize or reduce the number of 1s for PCM, among the vectors with odd weights available for each column vector, the vector with the lowest weight is used first.

[0092] Meanwhile, Dutta and Touba codes have single error correction-double error detection (SEC-DED) performance.

[0093] Figure 5 is an example diagram showing PCM of the (23, 16) Dutta and Touba SEC-DED-DAEC code. Figure 5 As shown, the weights of each column of the PCM are all odd numbers and all meet the SEC-DED requirements on different columns.

[0094] Figure 6 is an example diagram showing the DAEC syndrome set for (23, 16) Dutta and Touba codes. Figure 6 As shown, by matrixing the adjacent double error correction sub-set, each column is different from each other as the elements of the adjacent double error correction sub-set. Therefore, Dutta and Touba codes may have dual adjacent error correction (DAEC) performance as well as SEC-DED performance.

[0095] Dutta and Touba codes also have DAEC performance, which is achieved by properly arranging the column vectors of PCM to distinguish the syndromes of adjacent double errors. Similar to Hsiao codes, Dutta and Touba codes satisfy SEC-DED by selecting different vectors with odd weights as the column vectors of PCM. To satisfy DAEC, when the set of adjacent double error weights is S DAEC When SDAEG The elements of are different from each other. Therefore, the decoding process for the double error that occurs in the received signal is as follows. T ≠0) to calculate the syndrome. The weights of the syndromes are confirmed, and when the weights are equal, a double error is confirmed. DAEC , it is determined to be a neighboring double error, and the error is passed To correct. Then it is determined as a double error that is not adjacent to the received signal.

[0096] At the same time, Reviriego codes can also satisfy SEC-DED-DAEC, just like Dutta and Touba codes.

[0097] Figure 7 is an example view showing a PCM of a (23, 16) Reviriego code, and Figure 8 is an example view showing a DAEC syndrome set for a (23, 16) Revirigo code. The Reviriego code uses a vector with odd weights for PCM as each column, which is the same as the method of Dutta and Touba, and the syndromes of adjacent double errors are arranged in columns in a different way to meet the SEC-DED-DAEC performance. The decoding speed of the Reviriego code is faster than that of the Dutta and Touba code. The corresponding code constantly maintains the weights of the syndromes of adjacent double errors, which can be obtained by columns with column weights that are not 1. Therefore, the delay overhead can be reduced by reducing the amount of logic required for decoding.

[0098] like Figure 8 As shown, the weight of the adjacent double error syndrome for the parity bit is 2, and the weight of the adjacent double error syndrome for the information bit is 4, where each weight has the same value. In this case, for decoding performance, the Reviriego code uses one more parity bit than the Dutta and Touba codes, so that there is a code with a longer parity length compared to the same error correction performance.

[0099] On the other hand, the Sánchez code satisfies SEC-DED-TAED by appropriately using vectors with even weights instead of constructing PCM for error modes other than single errors using only vectors with odd weights.

[0100] Fig. 9 is an example diagram showing PCM of the (50, 43) SEC-TAED A. Sánchez code. Fig. 9As shown, SEC-TAED codes with message lengths of 16 and 32, respectively, can be obtained from the Sánchez (50, 43) SEC-TAED code, which is less than the message length of 43.

[0101] Fig.10 is an example view of PCM of (22, 16)SEC-DED-TAED Sánchez code. Fig.10 As shown, the (22, 16)SEC-DED-TAED code obtains the sub-matrix (21, 16)SEC-TAED and additionally supports DED by extension to form PCM.

[0102] In a binary vector, a leading 1 (LO) refers to the frontmost 1 (or the highest significant index with a value of 1). Assume that the number of elements from LO to the end of the vector in a determined vector is the LOD (depth of leading 1). For example, the LOD of (0 0 1 1 0 1) is 4. Each column vector in PCM uses the vector with the lowest LO (leading 1) from the left to repeatedly enumerate the columns with odd-odd-even weights. In this case, the LOD of the i-th located vector is greater than or equal to the LOD of the i-1 column vector. In addition, the weight of the syndrome of adjacent 3 bit errors is an even number. For this reason, if the column vector is properly arranged so as to be different from the column vector with an even weight in PCM, SEC-TAED is satisfied. When a full 0 column is added to the left side of the PCM that satisfies SEC-TAED, and then a full 1 row is added to the bottom part, an expansion code is obtained. When confirming the syndrome of a double error, a double error is detected by confirming the last bit of the syndrome.

[0103] When the received code includes errors, the correction and detection method can be as follows. T ≠0) to calculate the syndrome. When the last bit of s is 0, the error is determined to be a double error. When the last bit of s is 1 and s∈S SEC When, through to correct errors. When the last bit of s is 1 and the weight of s is an odd number, if An error is then determined to be an error in three adjacent bits.

[0104] The general Sánchez code has SEC-DED-TAED performance and allows code design for all message lengths. However, because expansion is used in the PCM design process, the number of 1s in the total PCM increases as all-1 rows are added, significantly increasing the delay overhead. In addition, because the columns corresponding to the parity check in PCM and the systematic code are not grouped together, the Sánchez code has distributed parity. Because the rearrangement of the columns cannot be applied to respond to TAE due to the PCM structure, it may be difficult to simply perform conversion to a code with local parity check.

[0105] The SEC-DED-TAED code according to some example embodiments has a code length that can be generated according to the parity check length. k message length (where k is a positive integer), but in some cases a different message length is required. Various example embodiments may protect submatrices according to the target message length by SEC-TAED PCM, generate SEC-DED-TAED code PCM by expansion / elimination, and / or reduce the total weight of PCM by modifying the SEC-DED-TAED PCM generated for use in a memory device. Therefore, various example embodiments may improve or reduce space and / or delay overhead. Alternatively or additionally, the code can be easily implemented by generating the code as a systematic code with local parity check.

[0106] Various example embodiments can design SEC-DED-TAED codes for all message lengths. To this end, example embodiments can be designed using SEC-DED-TAED through two processes. First, a SEC-TAED code is designed, and the DED feature is added through code modification. In order to design a code that satisfies SEC-TAED, two conditions need to be met or expected. First, the corresponding column vectors in the PCM are different vectors that are not 0. Second, the syndrome vectors of three adjacent error vectors must not match the elements of the single error syndrome set. The first condition is a condition for correcting a single error, and each column vector of the PCM can be used as a syndrome of a single error. Because the proposed SEC-DED-TAED code only corrects single errors and only considers the detection of adjacent 3-bit errors, TAED can be met by the second condition by allowing overlap between TAE syndromes.

[0107] The SEC-TAED PCM generation algorithm uses a parity length (r) from 1 to LOD input. M ) are generated sequentially in blocks. First, the integer b∈[2 l ] is represented in binary as =(b l-1 ,…,b 0 ) T , where b i is the coefficient of the binary representation of b. When LOD is l, b l-1 is always 1, and the set of its vectors can be represented as follows.

[0108] F l ={<2 l-1 >,…,<2 l -1>} Formula 8

[0109] Using F l Generate Block (B l ), through this block, the basis matrix (H base ) is expressed as follows.

[0110]

[0111] Assumptions is the syndrome of a single error, and the syndrome of TAE in the same LOD can be obtained as In this case, even if the adjacent B l-1 Elements of and in The TAE syndrome with LOD of l can also be obtained. Similarly, there is B l The element b 0 and b 1 , but the coefficient l of LO becomes 0 through the sum of these vectors, and The LOD of B becomes l-1. It can be confirmed that even in B l and B l+1 In, L-2 The LOD of is also l-1. Therefore, when the LOD is l, the set of single-error correction sub-sets is S sEC , and the syndrome of the adjacent 3-bit errors is S TAED , as shown below.

[0112]

[0113]

[0114] For this reason, in the case where the order in which each column vector is formed is such that the weights of the vectors are listed by repeating odd-odd-even from the left, when the i-th column vector of the PCM is h i When H base The following conditions are always met.

[0115] w(h i +h i+1 +h i+2 ) is an even number, (1≤i≤n-2) Formula 11

[0116] Here, w(·) represents the weight (Hamming weight) of ·, + in the formula represents XOR operation (or modulo 2 addition), and n represents the length of the code. Therefore, the weight of the syndrome vector of all TAEs is an even number, and because it must satisfy So S SEC and S TAED The elements must not match each other.

[0117] s sEC ≠s TAED (s SEC ∈S sEC ,s SeC ∈S TAED ) Formula 12

[0118] In F l The total number of vectors with odd weights in the elements of l-2 , and also always make the weight of the TAE vector even when using all of these vectors, requiring 2 with even weights l-3 vector. In order to prevent the elements of the generated TAE syndrome set from belonging to S SEC , when all the syndromes of TAE are composed of the remaining 2 l-3 When the length of each block is composed of vectors, the length of each block can be designed to be the maximum value. Therefore, considering the exclusion of vector 0, the length relative to the parity check length (r M ,r M ≥2) is the maximum length of a code that satisfies SEC-TAED.

[0119]

[0120] H base is configured by connecting consecutive blocks, and when LOD is 1, since only F 1 ={ <1>} exists, so H base Fixed to B 1 =[ <1> ] and have odd weights. B 2 It is through F 2 ={ <2> , <3>} to configure, and for H base TAED performance, B 2 The weights of the elements of must be arranged in the order of odd and even numbers, so B 2 Can be made by B 2 =[ <2> , <3> ] composition. However, for [ <1> , <2> , <3> ], the correction of TAE may become <0> , and may lead to miscorrection without error in the decoding process. Therefore, B 1 and B 2 Fixed to B 1 =[ <1> ] and B 2 =[ <2> ], and B 3 The weights of the first column of B are chosen to be an even-numbered vector. l The number of columns relative to LOD1 is 2 l-2 +2 l-3 =3·2 l-3 , and is a multiple of 3, so the weights of the columns of the block are listed repeatedly in the order of even-odd-odd, so the weight of the first column of a block of LOD with l≥3 is always an even number.

[0121] When designing SEC-TAED PCM code, F l The elements of are classified as follows, since the selection is done based on the weight of the vector. l ={ <j>|2 l-1 ≤j<2 l ,In( <j>) is an odd number.}, E l ={ <j>|2 l-1 ≤j<2 l ,In( <j>) is an even number.}

[0122] Use O l and E l elements to select block B l In this case, if the SE syndrome and TAE syndrome generated by confirming the newly selected vector are provided Then it can be selected as the column of the block. However, when using this method, before the length of the block becomes L, it can be selected by using S SEC and S TAED E in l To prevent this phenomenon, when selecting vectors with odd weights in a block , use the following rules.

[0123]

[0124] Indicates B l The i-th column vector of l The binary sum of the vectors is used to select O l The elements of B l of In addition, due to the inclusion of s TAED Already included in S TAED Therefore, no additional E is used. l Elements. From E l Randomly select vectors with even weights from Since the syndrome of TAE generated by this is and yes It is included in B l In, and s TAED Included in S TAED In, and from E l Since the columns corresponding to even weights are randomly selected, multiple SEC-TAED PCMs can be obtained by the algorithm, and for the input parity length (r M ), the quantities of which are shown below.

[0125] Formula 15:

[0126]

[0127] Here, j is the number of even weight vectors used in SEC-TAED PCM. When it is determined that the code length (n) matches the target message length (k), it can be obtained by H base Generator matrix (H s ).

[0128] Fig.11 1 is an example diagram illustrating an algorithm for generating a SEC-TAED code according to an input parity check length according to some example embodiments of various example embodiments. Various example embodiments may generate a SEC-DED-TAED code through a two-step process. In the first process, a SEC-DED-TAED code may be generated according to a parity check length (r M ) to generate a sub-matrix having a SEC-TAED function according to the target message length In the second process, 1 bit parity is added to the DED When an all-1 row is added below the PCM, if the last bit is 0, the last bit of the non-zero syndrome is confirmed and determined to be a double error. Elimination and extension exist as DED implementation methods. The size of the submatrix required for each method is different. Therefore, after considering the submatrix according to each method, the SEC-DED-TAED code is completed by using this method. When a code with a code length of n exists in the binary linear block code, the elimination method adds the DED property by converting the message bits into parity checks. Therefore, when the SEC-DED-TAED code is (n,k), the message length of the SEC-TAED code has k s , and has k relative to the target message length k s = k + 1. In this case, the code length of SEC-TAED is n s = n, which has n s =k s +r s In the H generated by this base In the configuration, the submatrix of the SEC-TAED code used for elimination is because The size of (r s ×n s ), so the submatrix is ​​configured to combine LOD with r s When performing elimination on the submatrices, we can obtain r = r s +1 and k is the SEC-DED-TAED code of the target message as the parity check length.

[0129] Fig.12 It is shown from the perspective of PCM. PCM of the SEC-DED-TAED code The PCM after elimination is The extended method adds the DED property by adding a parity check to the binary linear block code. Therefore, when the SEC-TAED code is (n s ,k s ), the message length of the SEC-DED-TAED code is k = k s When the SEC-TAED code adopts the extension method, the parity check becomes r = r s +1, and the length of the SEC-DED-TAED code is n=n s +1. On this basis, the SEC-TAED code considering the expansion is obtained And get the SEC-DED-TAED code through the extension method

[0130] Fig.13 is shown by the PCM Extended SEC-DED-TAED PCM An example view of . The all-1 columns added during expansion add the DED property when an all-1 row is added, regardless of whether it is added to either side of the PCM. The Sánchez code uses left expansion, where the (00…01) T The columns are arranged on the left and the added TAE syndrome is fixed to (00…111) T If (00…111) T The columns are arranged on the right. When the weights of the last two columns are odd-even and even-odd, the weights of the generated TAE syndrome may have even numbers and may match the columns of the completed SEC-DED-TAED code PCM, which may cause miscorrection.

[0131] The error correction and detection method of the SEC-DED-TAED code, which is accomplished by using erasure and extension in the SEC-TAED code respectively, uses the same method as the Sánchez code. T ≠0) to calculate the syndrome. If the last bit of s is 0, it is determined to be a double error. If the last bit of s is 1 and s∈S SEC , then through To correct errors. If the last bit of s is 1 and s∈S TAED , then it is determined to be an error in three adjacent bits.

[0132] When designing SEC-TAED PCM, the weight of the adjacent 3-bit error syndrome is set to an even number. However, since all-1 rows are added for DED, the weight of the syndrome of TAE in the SEC-DED-TAED code becomes an odd number.

[0133] The decoding performance of binary linear block based error correction codes is affected by the number of 1s of PCM. The total number of 1s in PCM affects the space overhead. The maximum number of 1s per row affects the delay overhead. PCM of SEC-DED-TAED code with DED added by elimination and extension has high space and delay overhead due to the all-1 rows. To address this problem, a method is proposed to reduce the PCM density to reduce decoding complexity and delay, but correspondingly use modified syndrome decoding. This operation is also applicable to elimination and extension, and also to the completed SEC-DED-TAED code. The total number of 1s in PCM and the number of 1s in all-1 rows are reduced by the following process. They are added to the last row after adding r-1 rows from above. All columns have even parity.

[0134] The PCM generated by basic row operations still maintains the SEC-DED-TAED property. In addition, the decoding delay can be reduced by reducing the weight of the all-1 row. However, the method of double error detection by confirming the last bit of the syndrome is not available because it is not an all-1 row. Therefore, by utilizing the fact that the weight of each column vector of PCM is an odd number, when the syndrome is not a zero vector, the weight of the syndrome is confirmed, and when the weight of the syndrome is confirmed to be an even number, it is detected as a double error. Therefore, the error correction and detection method of SEC-DED-TAED is performed in the following order. Calculate the syndrome s=Hy T If s = 0, the code is determined to be valid. If s∈S SEC , then through Single error correction is performed. If the weight is an even number in the state of s≠0, it is determined that a double error has occurred. If s∈S TAED , it is determined that an adjacent triple error has occurred.

[0135] Fig.14 : is an example view showing the low complexity of the eliminated (39, 32) SEC-DED-TAED code. In the SEC-DED-TAED code with code length 39, in the last row with low complexity, the number of 1s is 13, and the maximum length of each row is 22, which can be reduced by 17 times compared to the previous row, thereby reducing the delay overhead.

[0136] Due to the low complexity of the SEC-DED-TAED code with code length 39, the number of 1s is 13 and the maximum length of each row is 22, which can reduce the delay overhead by 17 times.

[0137] Systematic coding of binary linear block codes with local parity checking is a decisive factor in the use of error correction codes in practical memory environments. In a systematic code with local parity checking, the P corresponding to the message T The partial sum is similar to H = [P T :I n-k ]'s parity check corresponds to I n-k When the message and the parity check are distinguished from each other, the generator matrix G = [I k ∶P]. However, except for the code proposed by Sánchez, the previously designed SEC-DED-TAED codes have the form of distributed parity check. In this case, when column permutation is performed, the TAD performance cannot be maintained, and H=[P T :I n-k ] form. Therefore, some examples can further propose a method in which the SEC-DED-TAED code obtained by the existing design method is a local parity check while maintaining the ladder structure. The corresponding method considers the H of the SEC-TAED code base Configuring SEC-TAED PCM code in the case of right extension Use in The unused vectors in the Right s × s ) is of full rank. Therefore, when the rank of the submatrix reaches full rank, the I shape can be obtained by right diagonalization.

[0138] Fig.15 is a diagram conceptually illustrating the use of a SEC-DED-TAED code with a local parity check according to some example embodiments. Fig.15 , the PCM obtained by performing a process of reducing the PCM weight after right extension in the generated SEC-TAED code is used for decoding, and the generation matrix obtained by using the PCM (H′) having an I shape through diagonalization is used for encoding.

[0139] Typically, since most message lengths used in memory systems are 2 α (where α is a natural number, α ≥ 4), so additional design is required to achieve local parity check of the SEC-DED-TAED code of this length. Local parity check means that the consecutive column vectors corresponding to the parity check of PCM are gathered together to form a sub-matrix. If this sub-matrix is ​​diversified, it becomes an I matrix. The right square matrix of the SEC-DED-TAED code PCM is defined as the sub-matrix (H sub ), and systematic encoding with local parity requires the following conditions.

[0140] rank(H sub )=r Formula 16

[0141] Here, r is the parity length of the SEC-DED-TAED PCM of the target message length, and H sub Is a matrix, which is (r×r) in SEC-DED-TAED code PCM. The rank is a value that determines whether each vector in the matrix is ​​independent of each other. If there are three mutually independent vectors in the (4×4) matrix, the rank is 3. If the rank of a matrix as (r×r) is r, it means that all vectors in the matrix are independent of each other, which is called full rank. If the matrix is ​​of full rank, the vectors of the matrix operate on each other during diagonalization and no zero vector is generated, so that an I shape can be generated.

[0142] According to some example embodiments, a SEC-DED-TAED code may be generated by generating a SEC-TAED code and then supporting DED. In this case, since the matrix corresponding to the two information bits does not circulate in the code, the full rank H of the local parity check is achieved. sub The SEC-DED-TAED code is designed to be executed in blocks according to the LOD. s The size of the column is (r s × s ) contains all zero rows, so when calculating the rank, the complete rank cannot be obtained. Therefore, H sub Exists at the right end of the SEC-DED-TAED code PCM.

[0143] Fig.16 It is shown that H sub An example view of a SEC-DED-TAED code PCM including two all-1 rows. The DED support method includes an elimination method and an extension method, and the extension method includes a left extension method and a right extension method according to the position of the all-0 column vector. In this case, in the case of the elimination method, the DED characteristic can be achieved by adding only all-1 rows without adding columns. Therefore, when the submatrix of full rank When formed on the right side of the SEC-TAED code PCM, such as Fig.16 As shown, there may be two rows of all 1s. In this case, full rank may not be obtained. Similarly, for the elimination method, there are also cases where full rank may not be achieved in left extension. Therefore, in the SEC-DED-TAED code for local parity check, right extension is used as a method of DED characteristics. This can be achieved by utilizing the (00...01) added when performing right extension. T Column to prevent SEC-DED-TAED code PCM in H sub There are two all-1 rows in the SEC-TAED code to achieve full rank. In this case, the weights of the right two columns of the SEC-TAED code PCM are odd-odd. Therefore, in the configuration , this is taken into account and designed to achieve full rank.

[0144] In the method of supporting DED by right extension, when configuring the system code, configure (r s × s )of when is configured so that the rank satisfies r on the far right side of the SEC-TAED-PCM s By extension, all 1 lines and (00…01) T SEC-DED-TAED PCM code (r×r)H sub is configured so that the rank is r. If this PCM is diagonalized, then in the PCM, the part corresponding to the information bit and the part corresponding to the parity check are distinguished from each other. This can be used to generate a generator matrix and encode and transmit the data bits from the memory without additional operations.

[0145] In order to generate SEC-DED-TAED PCM as a code with local parity check, a submatrix with full rank must be generated in SEC-TAED PCM. The corresponding part of the column vector is reselected. The SEC-TAED code is first designed based on the SEC-DED-TAED code design and bits are added to support DED to complete the SEC-DED-TAED code. Therefore, taking this into account, and the rank used to calculate the SEC-TAED code is The size is set to (r s × s ), which is 1 less than the parity check length (r) of the SEC-DED-TAED code, the rank can be set to r s =r-1.

[0146] Since the capacity for SEC-TAED must be maintained even during the reselection of column vectors, the structure of the SEC-TAED PCM must be maintained. For ease of design, only PCM as long as the SEC-TAED code length is generated, taking into account the target message length (k) and right extension. In addition, whenever a column vector is selected that is consistent with The rank is calculated whenever there is a corresponding column vector. SEC and S TAED When the SEC-TAED PCM is finally completed, The rank becomes r s , and when the expansion is performed, the submatrix H of SEC-DED-TAED sub The rank of is r = r s +1.

[0147] The process can be summarized or generally described as follows. s Parity-length SEC-TAED-PCM, taking into account the target message length and right extension, from H base Configuration Configuration Right s Submatrices of size Use exclude include in S SEC The vectors other than the vectors in select the full rank Columns, and when selecting The rank is calculated when the column is increased, and then, when the rank is increased, the corresponding vector is determined as the column. This process is performed to achieve full rank while maintaining SEC-TAED. When full rank is reached, right extension is performed on the DED to complete the PCM of the SEC-DED-TAED code.

[0148] According to some example embodiments, except for vectors used for single error correction and adjacent 3-bit error detection to generate a SEC-DED-TAED code with local parity, the remaining vectors are used to achieve full rank.

[0149] In some cases, even if the SEC and S TAED The vectors in may not be realized on the full rank When the message length is 16, if the base Configuration Then the number of vectors that do not correspond to S_SEC and S_TAED is 2. By using this, it is not possible to achieve The full rank of H base Among the vectors with the highest LOD in , the vectors with odd weights are replaced while maintaining the SEC-TAED performance, so that The rank of can be full rank while keeping the parity length the same.

[0150] Various example embodiments may achieve full rank while maintaining the structure of PCM to generate SEC-TAED codes with local parity, and propose SEC-DED-TAED codes through right extension. Fig.17 is a graph showing that when the message length generated by the SEC-TAED design method is 16 Fig.18 A view illustrating a PCM of a SEC-TAED code is shown, where when the message length is 16, is full rank. Vectors with odd weights at LOD 5 can be swapped to generate Fig.18 The example shown in . Therefore, The rank of can achieve full rank and generate SEC-DED-TAED code with local parity by right extension.

[0151] According to some example embodiments, various SEC-TAED-PCMs may be generated by a SEC-TAED code algorithm, and according to the target message length, SEC-DED-TAED PCMs may be completed using an elimination and expansion method. When the target message length is 32, the parity length to be input is 6, and the SEC-TAED PCM completed by Algorithm 1 is as follows.

[0152] Fig.19 is a diagram showing the H obtained by designing a SEC-TAED code with a parity check length of 6. base Views of some example embodiments. Fig. 20 is a diagram showing the H obtained by designing a SEC-TAED code with a parity check length of 6. base FIG. 1 is a view of another example embodiment of FIG.

[0153] When the parity check length is 6, H base The length of L is L = 3 2 6-2 -1 = 47. When the elimination and extension method is used for DED, considering that 1 bit of the message is converted into 1 bit of the parity check, the extension elimination generates the submatrix In H base The sub-matrices considered for each method are as follows.

[0154] Fig.21 is an example view showing a SEC-TAED sub-matrix of message length 32 considering elimination. Fig. 22 is an example view showing the SEC-TAED submatrix considering a left-extended message length of 32. When the submatrix (H 32 ), the method is executed to complete SEC-DED-TAED PCM with a message length of 32. Fig.23 is an example diagram showing a (39, 32)SEC-DED-TAED code through erasure. Fig.24 is an example diagram showing a (39, 32)SEC-DED-TAED code by left extension.

[0155] The following are the performance comparison results when used for self-interference cancellation. This is a comparison between the optimized extended and eliminated SEC-DED-TAED codes in PCM. When the SEC-TAED code length determined by the target message length is consistent with the input parity check (n max =n=k+r), erasure must use 1 more bit than extension. Therefore, in this case, erasure uses 1 more bit than extension for the parity length of the completed SEC-DED-TAED code.

[0156] For the completed SEC-DED-TAED PCM, an additional operation is performed to reduce the total number of 1s in the PCM. The weight of each PCM column is calculated, and if the weight is even, the last bit of the column is converted to zero. This is done the same for extension and elimination.

[0157] Fig.25 is an example diagram showing optimization in PCM of (39, 32)SEC-DED-TAED code by elimination. Fig.26 is an example diagram showing optimization in PCM of (39, 32)SEC-DED-TAED code by extension.

[0158] By iteratively generating SEC-DED-TAED codes optimized within a PCM (parity check matrix), it has been identified the PCM with the lowest total count of 1s and maximum row weight among the PCMs. This particular SEC-DED-TAED coded PCM is both systematic and has a distributed parity check, making it different from other PCMs. A comparison was made with the Sánchez code, which exhibited similar error correction performance to this PCM. Thus, when a message length of k=16 is considered, a difference of 1's total count between the PCM and the Sánchez code is observed to be 14. It is noteworthy that this difference gradually increases with the increase in message length. Moreover, when the message length is 16, the maximum row weight differs by at most 12, and this difference increases with the increase in message length. These findings indicate that the SEC-DED-TAED code implemented with low complexity outperforms the existing SEC-DED TAD codes in terms of performance.

[0159] Table 1 shows the total number of 1s in the SEC-DED-TAED PCM per message length.

[0160] Table 1:

[0161]

[0162]

[0163] Table 2 shows the low weights with the maximum weight of SEC-DED-TAED PCM per message length.

[0164] Table 2:

[0165]

[0166] Example embodiments may start by generating a SEC-TAED PCM in order to have a local parity check of the SEC-DED-TAED code. In this case, since only right extension is considered as a DED support method, a full-rank SEC-TAED code PCM must be generated considering that the weights of the right two column vectors are odd. In some example embodiments, when generating a SEC-DED-TAED code with a local parity check of message length 32, H is first considered. base and SEC-TAED code When the message length is 32, the weights of the right two columns of the PCM are odd-odd during right expansion, so the code is generated unalterably without window sliding. SEC and S TAED The unused vectors in are used for reselection. Since the parity length of the SEC-DED-TAED code for message length 32 is 7, the full rank Must have a rank of 6 in size (6×6).

[0167] like Fig.28 As shown, by using an SEC and S TAED The SEC-TAED algorithm generates a random vector of rank 6 The SEC-DED-TAED code is obtained by including the full rank This is accomplished by performing a right extension on the SEC-TAEDPCM.

[0168] Fig.26 and Fig. 27 is a view showing PCM of a SEC-TAED code with distributed parity. Fig.28 is an example view showing the reselection of column vectors of a submatrix with a full rank of 6. When the code is diagonalized, it can be confirmed that the code is systematic and has local parity by confirming the I shape in PCM, such as Fig.28 shown. Fig.29 is an example diagram showing PCM of a (39, 32)SEC-DED-TAED code with local parity check. Fig.30 is an example diagram showing PCM of a diagonalized (39, 32)SEC-DED-TAED code. Fig.31 is an example diagram showing PCM of a (72, 64)SEC-DED-TAED code with local parity check. Fig.32 is a view showing the PCM of the diagonalized (72, 64)SEC-DED-TAED code. When the message length is 64, Fig.31 and Fig.32 A systematic code with local parity check is also shown, and Fig.31 shows the use for decoding, and Fig.32 The generator matrix obtained and used for encoding is shown in Fig.31 The column vectors in bold in represent the replaced column vectors.

[0169] When the weights of the two right columns in the SEC-DED-TAED code PCM are not odd like the message length of 128, miscorrection may occur after extension. To prevent this phenomenon, when configuring SEC-TAED PCM, set the right column to odd-odd and then reselect To achieve full rank.

[0170] Fig.33 is an example diagram showing PCM of a (137, 128)SEC-DED-TAED code with a local parity check. Fig.34 is an example diagram showing PCM of a diagonalized (137, 128) SEC-DED-TAED code. Fig.33 and Fig.34 is a diagram showing SEC-DED-TAED PCM and diagonalized PCM, in which a local parity check is formed when the message length is 128. Fig.33 In , the column vectors in bold indicate the replaced column vectors.

[0171] When there is no space for an object that does not correspond to S SEC and S TAED When the vector is The columns in may not achieve full rank. In this case, the columns are replaced in blocks consisting of vectors with the highest LOD, such that becomes full rank.

[0172] Fig.35 is an example diagram showing PCM of a (22, 16)SEC-DED-TAED code with local parity check. Fig.36 is an example diagram showing PCM of a diagonalized (22, 16)SEC-DED-TAED code. Fig.35 and Fig.36 The PCM of the SEC-DED-TAED code with local parity check and diagonalization code when the message length is 16 is shown.

[0173] Various example embodiments can be implemented with a general SEC-DED-TAED code generation technique for all message lengths. Some example embodiments can be implemented by operations that reduce the complexity and delay of decoding performance and decoding methods that take complexity and delay into account. Some example embodiments can be implemented using SEC-DED-TAED code design techniques that take system codes into account. For previously known SEC-DED-TAED codes, it may be difficult to design long codes, and because of system codes with high decoding complexity, high delay time and distributed parity checks, the coding complexity is high. On the other hand, the SEC-DED-TAED codes of the example embodiments define odd column relationship expressions, and long SEC-DED-TAED codes can be designed, and decoding complexity and delay time can be reduced by designing SEC-DED TAED codes based on odd columns, and system SEC-DED TAD codes with local parity checks are designed.

[0174] Fig.37 1 is a diagram illustrating a SEC-TAED code generation technique according to some example embodiments. According to various example embodiments, in a p×nH matrix of a device using a SEC-DED-TAED code, columns in a (p-1)×nH matrix corresponding to SEC-TAED are formed in the order of odd-odd-even, and the i-th column (h i ) conforms to the following relational expression and can include h i =h i-1 +h i-3 +h i-4 . In some example embodiments, all columns in the p×nH matrix may be configured with odd degrees. In some example embodiments, the SEC-DED-TAED code is an H matrix in which the leading 1 (LO) of each column has a staircase structure. In some example embodiments, when a device using the SEC-DED-TAED code uses a parity check p bit, the device may generate a system code using a SEC-DED-TAED code designed so that a p×p submatrix of the H matrix is ​​full rank, and may use the system code to perform encoding.

[0175] The first step is SEC-TAED design. In SEC-TAED design, columns are arranged in the order of odd-odd-even, and when designing odd columns, it is recommended to establish a relationship with the previous columns. When the parity check numbers are the same, in order to design long-length SEC-TAED, when TAE has occurred, it may be necessary to overlap the syndrome values ​​as much as possible. When the column relationship expression of the example embodiment is applied, the three syndromes caused by TAE can be designed to have the same value. The second step is SEC-DED-TAED design. Add rows (add all 1 rows) in the matrix designed in the first step so that all columns become odd columns.

[0176] Fig.38 is a diagram showing a process for imparting DED characteristics according to some example embodiments. Fig.38 As shown, according to the DED method, from SEC-TAEDH base Select the submatrix H k As the DED characteristic imparting method, the left extension method, the elimination method, and the right extension method can be used. If the all-0 column is arranged on the right side of the SEC-TAED PCM, the TAE syndrome overlaps the SE syndrome. The PCM is selected so that the weights of the last two columns of the SEC-TAED PCM are both odd numbers.

[0177] Fig.39 is a diagram illustrating PCM weight optimization for low-latency, low-complexity decoding according to some example embodiments. Fig.39 As shown, decoding complexity and latency are reduced. The decoding latency of PCM is affected by the row weight when calculating the syndrome. The all-1 row added for DED increases complexity and latency. With PCM sparsification, all rows of PCM are added to the last row. The weight of the last row is reduced. The double error detection method is changed to when the syndrome weight is even.

[0178] Fig.40 2 is a diagram illustrating a SEC-DED-TAED code design technique that considers a systematic code to reduce code complexity according to some example embodiments. Fig.40 As shown, the systematic code is considered to replace the vectors to achieve diagonalization by using the SEC-DED-TAED code design technique to reduce the code complexity while maintaining SEC-DED-TAED.

[0179] Fig.41 is a diagram showing TAE syndromes according to various example embodiments. Fig.41 As shown, the syndromes caused by the three TAEs can be designed to have the same value.

[0180] The above-mentioned devices can be implemented with hardware components, software components and / or a combination of hardware components and software components. For example, the devices and components described in some example embodiments can be implemented using one or more general-purpose computers or special-purpose computers, such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of executing and responding to instructions. The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, operate, process, and generate data in response to the execution of software. For ease of understanding, there is a situation where a single processing device is described as being used, but those skilled in the art will understand that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. In addition, other processing configurations, such as parallel processors are available.

[0181] Software may include computer programs, codes, instructions, or a combination of one or more of these, and may configure a processing device to operate as needed or to command the processing device independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual device, computer storage medium, or device so that instructions or data are interpreted by or provided to the processing device. Software may be distributed on computer systems connected via a network and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0182] Fig.42 is an example view illustrating a semiconductor package including stacked semiconductor chips according to some example embodiments. Fig.42 , the semiconductor package 3000 may be a memory module including at least one stacked semiconductor chip 3300 and a system on chip (SoC) 3400, which is mounted on a package substrate 3100 such as a printed circuit board. An interposer 3200 may be optionally further provided on the package substrate 3100. The stacked semiconductor chip 3300 may be formed as a chip on chip (CoC).

[0183] The stacked semiconductor chip 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310 such as a logic chip. The memory chip 3320 may be implemented as an error correction circuit using a parity check matrix supporting a SEC-DED-TAED code, such as Figures 1 to 35 described.

[0184] The buffer chip 3310 and at least one memory chip 3320 may be connected to each other through a through silicon via (TSV). The buffer chip 3310 may perform a training operation on the memory chip 3320. For example, the stacked semiconductor chip 3300 may be or may include a high bandwidth memory (HBM) of, for example, 500 GB / sec to 1 TB / sec or more.

[0185] Some example embodiments disclose an H matrix with a SEC-DED-TAED code, which enhances the life of a memory device. A general H matrix adds parity bits so that the weights of columns are configured in even-odd-odd columns, and for DED, there are all-1 rows in the H matrix. On the other hand, the H matrix according to some example embodiments adds parity bits so that the weights of columns include even-odd-odd columns, the i-th odd column is designed by performing XOR on the (i-1), (i-3) and (i-4) columns, and after adding all-1 rows in the H matrix for DED, all columns become odd. The syndrome calculation complexity and latency can be reduced, and system coding is enabled.

[0186] At the same time, the contents of the above-mentioned example embodiments are only specific examples for executing various embodiments. Example embodiments include not only specific and practically usable methods, but also technical concepts, which are abstract and conceptual ideas that can be used as future technologies. In addition, example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.< / j> < / j> < / j> < / j>

Claims

1. A memory device, comprising: a memory cell array having a plurality of memory cells connected to word lines and bit lines; as well as an error correction circuit configured to perform error correction on data read from the memory cell array, wherein the error correction circuit is configured to perform at least one of a 1-bit error correction operation, a 2-bit error detection operation, or a 3-bit error detection operation using a parity check matrix, and The parity check matrix is ​​configured such that columns are arranged in an odd-odd-even order, and the leading 1 (LO) of each row is arranged in a staircase structure.

2. The memory device of claim 1, wherein The 1-bit error correction operation comprises a single error correction SEC operation, The 2-bit error detection operation includes a double error detection (DED) operation, and The 3-bit error detection operation includes a triple adjacent error detection (TAED) operation.

3. The memory device of claim 1, wherein The parity check matrix comprises a pxn H matrix, and The columns of the (p-1)xn H matrix are arranged in odd-odd-even order.

4. The memory device according to claim 3, wherein: Column i h i Satisfying the equation h i =h i-1 +h i-3 +h i-4 .

5. The memory device according to claim 3, wherein: All columns of the pxn H matrix are configured to be odd degree.

6. The memory device according to claim 5, wherein: The pxn H matrix is ​​configured to implement double error detection DED.

7. The memory device according to claim 1, wherein: The error correction circuit includes a systematic code and has a distributed parity check.

8. The memory device according to claim 7, wherein: The systematic code corresponds to making the pxp submatrix full rank when using parity check p bits.

9. The memory device according to claim 1, wherein: The parity check matrix corresponds to a SEC-DED-TAED code that defines an odd column relational expression.

10. The memory device of claim 1, wherein: The parity check matrix corresponds to a SEC-DED-TAED code based on odd columns to reduce decoding complexity and delay time.

11. A memory system comprising: at least one memory device configured to perform a first error correction operation; as well as a controller configured to control the at least one memory device and perform a second error correction operation, wherein at least one of the first error correction operation and the second error correction operation comprises performing a 1-bit error correction operation, a 2-bit error detection operation, and a 3-bit error detection operation using a parity check matrix, and The parity check matrix is ​​configured such that columns are arranged in an odd-odd-even order, and the leading 1 (LO) of each row is arranged in a staircase structure.

12. The memory system according to claim 11, wherein: The parity check matrix corresponds to a SEC-DED-TAED code.

13. The memory system according to claim 11, wherein: The parity check matrix corresponds to a systematic code for code complexity.

14. The memory system according to claim 13, wherein: The parity check matrix corresponds to replacing the vectors to be diagonalized while maintaining the SEC-DED-TAED code.

15. The memory system according to claim 11, wherein: The parity check matrix corresponds to mapping at least three cases into one syndrome.

16. A method for operating a memory device, comprising: Encode the message using a parity check matrix; receiving, through a channel, a codeword generated by encoding the message; as well as decoding the received codeword using the parity check matrix, The parity check matrix is ​​configured such that columns are arranged in an odd-odd-even order, and the leading 1 (LO) of each row is arranged in a staircase structure.

17. The method for operating a memory device according to claim 16, wherein: The parity check matrix corresponds to a systematic SEC-DED-TEAD code.

18. The method for operating a memory device according to claim 16, wherein: The parity check matrix corresponds to different SEC-DED-TAED codes according to the length of the message.

19. The operating method of the memory device according to claim 16, further comprising: Odd-weight columns of the parity-check matrix are selected according to a previous index column.

20. The method for operating a memory device according to claim 16, wherein: The parity check matrix is ​​based on at least one of erasure, left extension or right extension.

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