Preparation method of semiconductor device and semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device. The preparation method of the semiconductor device comprises the following steps: growing a gate oxide film layer on a silicon carbide substrate; carrying out first annealing treatment on the gate oxide film layer through a nitriding annealing process; and carrying out second annealing treatment on the gate oxide film layer through an inert gas annealing process. By adopting the preparation method, interface state traps can be effectively reduced, and the electrochemical performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] In the field of third-generation semiconductor development, wide-bandgap semiconductor SiC has a very significant advantage. It is the only compound semiconductor that can obtain high-quality SiO2 through thermal oxidation. Therefore, silicon oxide obtained by thermal oxidation of SiC is used as the gate dielectric of metal oxide semiconductor (MOS) devices and the surface passivation of SiC.

[0003] In the related art, for MOS devices made of SiC, during the thermal oxidation process, the carbon atoms in SiC diffuse out in the form of CO molecules under ideal conditions. However, when the oxidation temperature is too high or too low, carbon atoms will diffuse into the SiC body region, forming a large number of dangling bonds, carbon clusters, oxygen vacancies and other trapped charges near the SiO2 / SiC interface. These defects can easily cause the electronic properties of the gate oxide interface layer to degrade, increase the gate-source leakage, and reduce the reliability, which makes it difficult for the performance of the MOS device to meet the expected requirements. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a method for preparing a semiconductor device, which can effectively reduce interface state traps and improve the electrochemical performance of the device.

[0005] A second objective of the present invention is to provide a semiconductor device.

[0006] In order to solve the above problems, a method for preparing a semiconductor device is proposed in an embodiment of the first aspect of the present invention, comprising: growing a gate oxide film layer on a silicon carbide substrate; performing a first annealing treatment on the gate oxide film layer through a nitridation annealing process; and performing a second annealing treatment on the gate oxide film layer through an inert gas annealing process.

[0007] According to the method for preparing a semiconductor device of an embodiment of the present invention, after growing a gate oxide film layer on a silicon carbide substrate, an annealing treatment is first performed through a nitridation annealing process, so that the N element can be introduced into the interface of the gate oxide film layer to passivate the dangling bonds or other defects existing at the interface, improve the defects at the interface of the gate oxide layer, and improve the reliability of the semiconductor device, and then an annealing treatment is performed through an inert gas annealing process, so that the C element at the interface of the gate oxide layer is removed by inert gas annealing, so that the C element-related defects are decomposed and leave the interface position, thereby reducing the mobile ions at the gate oxide interface. In addition, according to the sequence of the above annealing treatments, the problem of blocking the gate oxide interface defects from contacting the outside due to the inertness of the inert gas can also be effectively solved, and the stability of the threshold voltage can be improved.

[0009] In some embodiments, the first annealing treatment and the second annealing treatment are performed continuously in the same heat treatment furnace.

[0010] In some embodiments, the gas used in the nitridation annealing process is at least one of N2, NO, NO2, N2O or NH3.

[0011] In some embodiments, the inert gas used in the inert gas annealing process is at least one of Ar or He.

[0012] In some embodiments, the conditions of the first annealing process include: the first annealing temperature ranges from 800°C to 1400°C.

[0013] In some embodiments, the first annealing temperature ranges from 1150°C to 1200°C.

[0014] In some embodiments, the conditions of the first annealing process include: a first annealing gas pressure ranges from 200 mbar to 1500 mbar.

[0015] In some embodiments, the first annealing gas pressure ranges from 800 mbar to 1000 mbar.

[0016] In some embodiments, the conditions of the first annealing treatment include: a first annealing time ranges from 30 min to 90 min, and a first annealing gas flow ranges from 0.2 slm to 5 slm.

[0017] In some embodiments, the first annealing time ranges from 40 min to 50 min, and the first annealing gas flow ranges from 0.2 slm to 2 slm.

[0018] In some embodiments, the conditions of the second annealing process include: the second annealing temperature ranges from 800°C to 1400°C.

[0019] In some embodiments, the second annealing temperature ranges from 1150°C to 1200°C.

[0020] In some embodiments, the conditions of the second annealing process include: the second annealing gas pressure ranges from 200 mbar to 1500 mbar.

[0021] In some embodiments, the second annealing gas pressure ranges from 800 mbar to 1000 mbar.

[0022] In some embodiments, the conditions of the second annealing treatment include: the second annealing time ranges from 30 min to 180 min, and the second annealing gas flow ranges from 0.2 slm to 5 slm.

[0023] In some embodiments, the second annealing time ranges from 30 min to 90 min, and the second annealing gas flow ranges from 0.2 slm to 2 slm.

[0024] In some embodiments, growing a gate oxide film layer on a silicon carbide substrate includes: obtaining a SiC epitaxial wafer; and oxidizing the SiC epitaxial wafer through a dry oxygen oxidation process to grow the gate oxide layer on the SiC epitaxial wafer.

[0025] In some embodiments, the SiC epitaxial wafer is oxidized by a dry oxygen oxidation process, including: under a first processing condition, the SiC epitaxial wafer is subjected to a temperature-increasing oxidation treatment, wherein the first processing condition includes the processing gas being a mixed gas containing oxygen; under a second processing condition, the SiC epitaxial wafer is subjected to a constant temperature oxidation treatment.

[0026] In some embodiments, the first processing condition further includes a first maximum processing temperature ranging from 1000°C to 1500°C.

[0027] In some embodiments, the first maximum processing temperature ranges from 1150°C to 1200°C.

[0028] In some embodiments, the first processing condition further includes a first gas pressure ranging from 200 mbar to 1500 mbar.

[0029] In some embodiments, the first gas pressure ranges from 800 mbar to 1000 mbar.

[0030] In some embodiments, the first processing condition further includes a first gas flow rate ranging from 0.2 slm to 5 slm.

[0031] In some embodiments, the first gas flow rate ranges from 0.2 slm to 2 slm.

[0032] In some embodiments, the mixed gas containing oxygen is a mixed gas of N2 and O2 or a mixed gas of Ar and O2.

[0033] In some embodiments, the second processing condition includes the processing gas being O2.

[0034] In some embodiments, the second processing condition includes a second maximum processing temperature ranging from 1000°C to 1500°C.

[0035] In some embodiments, the second maximum processing temperature ranges from 1150°C to 1200°C.

[0036] In some embodiments, the second processing condition includes a second gas pressure ranging from 200 mbar to 1500 mbar.

[0037] In some embodiments, the second gas pressure ranges from 800 mbar to 1000 mbar.

[0038] In some embodiments, the second processing condition further includes a second gas flow rate ranging from 0.2 slm to 5 slm.

[0039] In some embodiments, the second gas flow rate ranges from 0.2 slm to 2 slm.

[0040] A second aspect of the present invention provides a semiconductor device manufactured by the method for manufacturing a semiconductor device described in the above embodiment.

[0041] The semiconductor device according to the embodiment of the present invention can effectively reduce interface state traps and improve the electrochemical performance of the device.

[0042] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0044] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0045] Figure 2 is a comparison chart of experimental results of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0047] In the related art, for MOS devices made of SiC, during the thermal oxidation process, under ideal conditions, the reaction equation is shown in equation (1), and the carbon atoms in SiC diffuse out in the form of CO molecules; however, when the oxidation temperature is too high or too low, carbon atoms will diffuse into the SiC body region, forming a large number of trapped charges such as dangling bonds, carbon clusters and oxygen vacancies near the SiO2 / SiC interface, and the reaction equation is shown in equation (2). These defects easily cause the electronic properties of the gate oxide interface layer to degrade, increase the gate-source leakage, and reduce the reliability, thereby making it difficult for the performance of the MOS device to meet the requirements. Therefore, it is very necessary to improve the preparation method of the semiconductor device.

[0048] SiC+O2=SiO2+CO↑ (1)

[0049] SiC+O2=SiO2+C (2)

[0050] In order to solve the above problems, a first embodiment of the present invention provides a method for preparing a semiconductor device. The preparation method can effectively reduce interface state traps and improve the electrochemical performance of the device.

[0051] Reference below Figure 1 Describe the method for preparing the semiconductor device, such as Figure 1 As shown, the method at least includes steps S1 to S3.

[0052] Step S1, growing a gate oxide film layer on a silicon carbide substrate.

[0053] Specifically, a silicon carbide substrate is provided, and the substrate layer of the silicon carbide substrate can be doped with N type or P type. If the silicon carbide substrate is doped with N type, an N type epitaxial layer is grown on the N type substrate, and P type ions are implanted by a SiC high temperature and high energy implanter, such as B or Al, to form a source and a P channel, thereby preparing a PMOS semiconductor device with holes as carriers; if the silicon carbide substrate is doped with P type, a P type epitaxial layer is grown on the P type substrate, and N type ions are implanted by a SiC high temperature and high energy implanter, such as N or P, to form a source and an N channel, thereby preparing an NMOS semiconductor device with electrons as carriers.

[0054] After the epitaxial wafer is grown on the silicon carbide substrate, the wafer is protected by a carbon film and annealed by using an appropriate process to repair the lattice defects caused by the implantation and improve the electrical activation rate, and then a thin oxide layer is grown and removed to remove the implantation damage layer. Then, the wafer is cleaned, such as by using a wet chemical cleaning method, to fully remove dust, metal, polymer and other impurities on the surface of the wafer; and then an oxidation treatment is performed in a high-temperature oxidation furnace to grow a gate oxide film layer on the epitaxial wafer, wherein the oxidation treatment method can be dry oxygen oxidation or wet oxygen oxidation, which is not limited.

[0055] Step S2, performing a first annealing treatment on the gate oxide film layer through a nitridation annealing process.

[0056] In order to solve the problem of forming a large number of trapped charges such as dangling bonds, carbon clusters and oxygen vacancies near the interface, after the gate oxide film layer is grown by thermal oxidation, two annealing treatments are added in the same high-temperature oxidation furnace. Specifically, the annealing treatment is first performed through a nitridation annealing process, so that the N element can be introduced into the interface of the gate oxide film layer to passivate the dangling bonds or other defects at the interface and eliminate the carbon atoms at the interface. This will not only reduce the interface state density near the edge of the conduction band, increase the carrier migration rate of the channel, and thus improve the defects at the interface of the gate oxide layer, but also the use of a nitridation process will increase the threshold voltage, reduce the on-resistance between the source and the drain during the device startup process, reduce the leakage current between the gate-source and the drain-source, and improve the reliability of the semiconductor device.

[0057] Step S3, performing a second annealing treatment on the gate oxide film layer through an inert gas annealing process.

[0058] Specifically, after the nitridation annealing process is completed, the annealing process is continued through the inert gas annealing process, so that the C element at the gate oxide layer interface is removed through the inert gas annealing, so that the C element related defects are decomposed and leave the interface position, thereby reducing the mobile ions at the gate oxide interface.

[0059] In addition, in principle, inert gas annealing can remove the interface state density of shallow energy level, increase the compactness of SiO2 gate oxide film layer, and enhance its reliability. In particular, annealing in an inert gas atmosphere containing O element can promote the decomposition of C element related defects and improve the effect of oxygen annealing. Based on this, it can be seen that inert gas plays a decisive role in reducing the on-resistance Ron. However, without N-containing gas annealing, the inert gas annealing process is not enough to repair surface defects such as carbon clusters, dangling bonds, and oxygen vacancies. The essential reason is that the inert gas acts as a catalyst. If the inert gas annealing treatment is performed first, the inert gas molecules are too heavy and inert, thereby blocking the defects from contacting with the outside, so that the nitrogen-containing gas cannot enter the interior of SiO2. Nitriding annealing is the key step that plays a significant role. Based on the above considerations, in this application, the order of the above annealing treatments can also effectively solve the problem of blocking the gate oxide interface defects from contacting with the outside due to the inert gas being inert, and improve the stability of the threshold voltage.

[0060] According to the method for preparing a semiconductor device of an embodiment of the present invention, after growing a gate oxide film layer on a silicon carbide substrate, an annealing treatment is first performed through a nitridation annealing process, so that the N element can be introduced into the interface of the gate oxide film layer to passivate the dangling bonds or other defects existing at the interface, improve the defects at the interface of the gate oxide layer, and improve the reliability of the semiconductor device, and then an annealing treatment is performed through an inert gas annealing process, so that the C element at the interface of the gate oxide layer is removed by inert gas annealing, so that the C element-related defects are decomposed and leave the interface position, thereby reducing the mobile ions at the gate oxide interface. In addition, according to the sequence of the above annealing treatments, the problem of blocking the gate oxide interface defects from contacting the outside due to the inertness of the inert gas can also be effectively solved, and the stability of the threshold voltage can be improved.

[0061] In some embodiments, the first annealing treatment and the second annealing treatment are performed continuously in the same heat treatment furnace.

[0062] In some embodiments, the gas used in the nitridation annealing process is at least one of N2, NO, NO2, N2O and NH3, for example, it can be a mixed gas of N2O and NH3, or other gases containing N elements can be used to achieve it, without limitation.

[0063] In some embodiments, the inert gas used in the inert gas annealing process is at least one of Ar or He, or other inert gases may also be used, without limitation.

[0064] In some embodiments, the conditions of the first annealing process include a first annealing temperature ranging from 800° C. to 1400° C., for example, 800° C., 1220° C., or 1400° C.

[0065] In some embodiments, the first annealing temperature ranges from 1150° C. to 1200° C. For example, the first annealing temperature may be 1150° C., 1180° C., 1192° C. or 1200° C., without limitation.

[0066] In some embodiments, the conditions of the first annealing process include a first annealing gas pressure ranging from 200 mbar to 1500 mbar, for example, 2000 mbar, 1421 mbar or 1500 mbar.

[0067] In some embodiments, the first annealing gas pressure ranges from 800 mbar to 1000 mbar. For example, the first annealing gas pressure may be 800 mbar, 990 mbar, 991 mbar or 1000 mbar, without limitation.

[0068] In some embodiments, the conditions of the first annealing treatment include a first annealing time ranging from 30 min to 90 min, and a first annealing gas flow ranging from 0.2 slm to 5 slm. For example, the first annealing time may be 30 min, 45 min, 60 min, 90 min; and the first annealing gas flow may be 0.2 slm, 1 slm, 2.3 slm, or 5 slm.

[0069] In some embodiments, the first annealing time ranges from 40 min to 50 min, for example, the first annealing time can be 40 min, 45 min, or 50 min; the first annealing gas flow rate ranges from 0.2 slm to 2 slm, for example, the first annealing gas flow rate can be 0.2 slm, 1 slm, 1.252 slm, or 2 slm, without limitation.

[0070] Exemplarily, when the nitridation annealing process is used for annealing, NO gas is used for the first annealing, and the conditions of the first annealing are: the first annealing temperature is 1180°C, the first annealing time is 45min, the first annealing gas pressure is 800mbar and the first annealing gas flow rate is 0.2slm. Thus, the above-mentioned nitridation annealing process can not only reduce the interface state density near the edge of the conduction band, but also effectively eliminate carbon atoms at the interface, thereby increasing the carrier migration rate of the channel. In addition, the threshold voltage can also be reduced, the on-resistance between the source and the drain during the device startup process is reduced, the leakage current between the gate-source and the drain-source is reduced, and the reliability of the semiconductor device is improved.

[0071] In some embodiments, the second annealing treatment is performed at a temperature ranging from 800°C to 1400°C, for example, 800°C, 1220°C or 1400°C.

[0072] In some embodiments, the second annealing temperature ranges from 1150°C to 1200°C. For example, the second annealing temperature may be 1150°C, 1167°C, 1180°C, or 1200°C.

[0073] In some embodiments, the conditions of the second annealing process include a second annealing gas pressure ranging from 200 mbar to 1500 mbar, for example, 2000 mbar, 1421 mbar or 1500 mbar.

[0074] In some embodiments, the second annealing gas pressure ranges from 800 mbar to 1000 mbar. For example, the second annealing gas pressure may be 800 mbar, 990 mbar, 991 mbar or 1000 mbar, without limitation.

[0075] In some embodiments, the conditions of the second annealing treatment include a second annealing time range of 30 min to 180 min, and a second annealing gas flow range of 0.2 slm to 5 slm. For example, the second annealing time may be 30 min, 45 min, 60 min, 180 min; and the second annealing gas flow may be 0.2 slm, 1 slm, 3.3 slm, or 5 slm.

[0076] In some embodiments, the second annealing time ranges from 30 min to 90 min, for example, the second annealing time can be 30 min, 45 min, 60 min or 90 min; the second annealing gas flow rate ranges from 0.2 slm to 2 slm, for example, the second annealing gas flow rate can be 0.2 slm, 1 slm, 1.252 slm or 2 slm, without limitation.

[0077] Exemplarily, when an inert gas annealing process is used for annealing, Ar gas is used for a second annealing process, and the conditions of the second annealing process are: annealing temperature 1180°C, annealing time 180min, annealing gas pressure 800mbar and annealing gas flow rate 1slm. Therefore, on the basis of the first annealing process, the above-mentioned inert gas annealing process can effectively reduce the mobile ions at the gate oxide interface and improve the stability of the threshold voltage.

[0078] The effects of the preparation method of the present application are further described in detail below through specific examples. Figure 2 As shown, semiconductor devices are prepared under different conditions, and various parameters of the products are tested, such as the threshold voltage Vt at room temperature, the threshold voltage drift rate at high temperature, and the on-resistance Ron. Figure 2The parameters of each product in the test are as follows. From the perspective of temperature and post-oxidation annealing process atmosphere / temperature, at the same temperature, the performance of the device with NO annealing is better than that of the device without NO annealing, which means that if the oxidation temperature is only 1250℃, the threshold voltage will be completely lost; then, by adding secondary annealing and temperature optimization, the semiconductor device has further obtained better performance, that is, the Vt drift is reduced and the on-resistance Ron is also reduced. In addition, refer to Figure 2 As shown, for the experimental scheme of exchanging the order of N-containing gas annealing and Ar annealing, that is, first Ar annealing and then N-containing gas annealing, the result yield is 0%. Therefore, according to the order of first performing nitrogen annealing and then performing inert gas annealing after growing the gate oxide film layer in the present application, the problem of forming a large number of dangling bonds, carbon clusters and oxygen vacancies and other trapped charges near the interface can be solved, and the problem of blocking the gate oxide interface defects from contacting the outside due to the inertness of the inert gas can be avoided, thereby improving the stability of the threshold voltage.

[0079] In some embodiments, growing a gate oxide film layer on a silicon carbide substrate includes obtaining a SiC epitaxial wafer; and oxidizing the SiC epitaxial wafer through a dry oxygen oxidation process to grow a gate oxide layer on the SiC epitaxial wafer.

[0080] In some embodiments, the SiC epitaxial wafer is oxidized by a dry oxygen oxidation process, including: performing a temperature-elevated oxidation treatment on the SiC epitaxial wafer under a first processing condition; and performing a constant-temperature oxidation treatment on the SiC epitaxial wafer under a second processing condition.

[0081] Among them, the first processing condition includes that the processing gas is a mixed gas containing oxygen. Therefore, the use of a mixed gas can significantly reduce the defects of the silicon carbide wafer interface compared to the use of only N2 or inert gas. Among them, there is no restriction on the mixed gas, for example, it can be a mixed gas of N2 and O2 or a mixed gas of Ar and O2. In addition, the ratio of the mixed gas can be set according to actual conditions, and there is no restriction on this. For example, the ratio can be 3:1, 5:1 or 10:1, etc.

[0082] In addition, the constant temperature oxidation time of the dry oxygen oxidation process can be determined according to the thickness of the gate oxide film layer. For example, the thickness range of the gate oxide film layer is The constant temperature oxidation time is 120 min to 600 min. The thickness of the gate oxide film layer can be or The constant temperature oxidation time can be 120 min, 400 min or 600 min.

[0083] In some embodiments, the oxidation treatment of the SiC epitaxial wafer may also be performed in the same heat treatment furnace as the first annealing treatment and the second annealing treatment.

[0084] In some embodiments, the first processing condition further includes a first maximum processing temperature ranging from 1000° C. to 1500° C. For example, the first maximum processing temperature may be 1000° C., 1180° C., or 1500° C.

[0085] In some embodiments, the first maximum processing temperature, ie, the ramping temperature at room temperature, ranges from 1150°C to 1200°C. For example, the first maximum processing temperature may be 1150°C, 1180°C, or 1200°C.

[0086] In some embodiments, the first processing condition further includes a first gas pressure ranging from 200 mbar to 1500 mbar. For example, the first gas pressure may be 200 mbar, 1220 mbar or 1500 mbar.

[0087] In some embodiments, the first gas pressure ranges from 800 mbar to 1000 mbar. For example, the first gas pressure may be 800 mbar, 990 mbar or 1000 mbar.

[0088] In some embodiments, the first processing condition further includes a first gas flow rate ranging from 0.2 slm to 5 slm. For example, the first gas flow rate may be 0.2 slm, 3 slm or 5 slm.

[0089] In some embodiments, the first gas flow rate ranges from 0.2 slm to 2 / slm. For example, the first gas flow rate may be 0.2 slm, 1 slm, or 2 slm.

[0090] In some embodiments, the mixed gas containing oxygen is a mixed gas of N 2 and O 2 or a mixed gas of Ar and O 2 .

[0091] Exemplarily, in the heating stage, the first processing condition is: the mixed gas is a mixed gas of N2 and O2, the ratio of N2 to O2 is 10:1, the maximum processing temperature is 1180°C, the gas pressure is 990mbar, and the gas flow rate is 2slm. Comparing the experimental results prepared using the first processing condition with the experimental results prepared by only introducing N2, it can be found that both Si control wafers and SiC control wafers will have fogging and particulate matter, which are analyzed to be silicon nitrogen compounds. However, the Si control wafer grown with SiO2 does not have the above problems. Therefore, the use of a mixed gas containing oxygen for oxidation treatment in the heating stage can effectively protect the wafer surface from nitridation and reduce the defects of the silicon carbide wafer interface.

[0092] In some embodiments, the second process condition includes the process gas being O2.

[0093] In some embodiments, the second processing condition includes a second maximum processing temperature ranging from 1000°C to 1500°C, for example, 1000°C, 1300°C or 1500°C.

[0094] In some embodiments, the second highest processing temperature ranges from 1150°C to 1200°C. For example, the second highest processing temperature may be 1150°C, 1180°C, or 1200°C.

[0095] In some embodiments, the second processing condition includes a second gas pressure ranging from 200 mbar to 1500 mbar, for example, the second gas pressure may be 200 mbar, 1390 mbar or 1500 mbar.

[0096] In some embodiments, the second gas pressure ranges from 800 mbar to 1000 mbar, for example, the second gas pressure may be 800 mbar, 990 mbar or 1000 mbar.

[0097] In some embodiments, the second processing condition further includes a second gas flow rate ranging from 0.2 slm to 5 slm. For example, the second gas flow rate may be 0.2 slm, 4 slm or 5 slm.

[0098] In some embodiments, the flow rate of the second gas ranges from 0.2 slm to 2 slm. For example, the flow rate of the second gas may be 0.2 slm, 1 slm or 2 slm.

[0099] Exemplarily, in the constant temperature stage, the second processing conditions are: the processing gas is O 2 , the processing temperature is 1180° C., the processing gas pressure is 990 mbar, and the processing gas flow rate is 1 slm.

[0100] A second aspect of the present invention provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device according to the above embodiment.

[0101] The semiconductor device according to the embodiment of the present invention can effectively reduce interface state traps and improve the electrochemical performance of the device.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0103] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: growing a gate oxide film layer on a silicon carbide substrate; Performing a first annealing treatment on the gate oxide film layer by a nitridation annealing process; The gate oxide film layer is subjected to a second annealing treatment by an inert gas annealing process.

2. The method for preparing a semiconductor device according to claim 1, wherein: The first annealing treatment and the second annealing treatment are continuously performed in the same heat treatment furnace.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The gas used in the nitridation annealing process is at least one of N2, NO, NO2, N2O or NH3.

4. The method for preparing a semiconductor device according to claim 1, wherein: The inert gas used in the inert gas annealing process is at least one of Ar and He.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The conditions of the first annealing treatment include: the first annealing time ranges from 30 minutes to 90 minutes, and the first annealing gas flow ranges from 0.2 slm to 5 slm.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The first annealing time ranges from 40 minutes to 50 minutes, and the first annealing gas flow ranges from 0.2 slm to 2 slm.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The conditions of the first annealing treatment include: the first annealing temperature range is 800° C. to 1400° C.; Preferably, the first annealing temperature ranges from 1150°C to 1200°C.

8. The method for preparing a semiconductor device according to claim 1, wherein: The conditions of the first annealing treatment include: the first annealing gas pressure ranges from 200 mbar to 1500 mbar; Preferably, the first annealing gas pressure ranges from 800 mbar to 1000 mbar.

9. The method for preparing a semiconductor device according to claim 1, wherein: The conditions of the second annealing treatment include: the second annealing time ranges from 30 minutes to 180 minutes, and the second annealing gas flow ranges from 0.2 slm to 5 slm.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The second annealing time ranges from 30 minutes to 90 minutes, and the second annealing gas flow ranges from 0.2 slm to 2 slm.

11. The method for preparing a semiconductor device according to claim 1, wherein: The conditions of the second annealing treatment include: the second annealing temperature range is 800°C to 1400°C; Preferably, the second annealing temperature ranges from 1150°C to 1200°C.

12. The method for preparing a semiconductor device according to claim 1, wherein: The conditions of the second annealing treatment include: the second annealing gas pressure ranges from 200 mbar to 1500 mbar; Preferably, the second annealing gas pressure ranges from 800 mbar to 1000 mbar.

13. The method for preparing a semiconductor device according to claim 1, characterized in that: A gate oxide film layer is grown on a silicon carbide substrate, comprising: Obtain SiC epitaxial wafers; The SiC epitaxial wafer is oxidized by a dry oxygen oxidation process to grow the gate oxide layer on the SiC epitaxial wafer.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The SiC epitaxial wafer is oxidized by a dry oxygen oxidation process, comprising: Under a first processing condition, performing a temperature-raising oxidation treatment on the SiC epitaxial wafer, wherein the first processing condition includes that the processing gas is a mixed gas containing oxygen; Under the second processing condition, the SiC epitaxial wafer is subjected to a constant temperature oxidation treatment.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The first processing condition also includes a first maximum processing temperature range of 1000°C to 1500°C; Preferably, the first maximum processing temperature ranges from 1150°C to 1200°C.

16. The method for preparing a semiconductor device according to claim 14, characterized in that: The first processing condition also includes a first gas pressure range of 200 mbar to 1500 mbar; Preferably, the first gas pressure ranges from 800 mbar to 1000 mbar.

17. The method for preparing a semiconductor device according to claim 14, characterized in that: The first processing condition also includes a first gas flow rate range of 0.2slm to 5slm; Preferably, the first gas flow rate ranges from 0.2slm to 2slm.

18. The method for preparing a semiconductor device according to any one of claims 14 to 24, characterized in that: The mixed gas containing oxygen is a mixed gas of N2 and O2 or a mixed gas of Ar and O2.

19. The method for preparing a semiconductor device according to claim 14, characterized in that: The second processing condition includes the processing gas being O2.

20. The method for preparing a semiconductor device according to claim 14, characterized in that: The second processing condition includes a second maximum processing temperature ranging from 1000°C to 1500°C; Preferably, the second maximum processing temperature ranges from 1150°C to 1200°C.

21. The method for preparing a semiconductor device according to claim 14, characterized in that: The second processing condition includes a second gas pressure range of 200 mbar to 1500 mbar; Preferably, the second gas pressure ranges from 800 mbar to 1000 mbar.

22. The method for preparing a semiconductor device according to claim 14, characterized in that: The second processing condition also includes a second gas flow rate range of 0.2slm to 5slm; Preferably, the second gas flow rate ranges from 0.2slm to 2slm.

23. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 22.

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