Semiconductor package with at least one prefabricated conductive unit and panel-level manufacturing method thereof

Abstract

The invention relates to a semiconductor package with at least one prefabricated conductive unit and a panel-level manufacturing method thereof. The semiconductor package includes at least one semiconductor die, a molding layer for packaging the at least one semiconductor die; at least one prefabricated conductive unit, the at least one prefabricated conductive unit being prepared from a molded conductive substrate; a front-side build-up layer electrically coupled to the at least one semiconductor die and the at least one prefabricated conductive unit; and an external connection layer electrically coupled to the front-side build-up layer. The at least one semiconductor die may include a first semiconductor die and a second semiconductor die, which may be arranged in a juxtaposed manner or a vertical manner. The invention also relates to a panel-level manufacturing method for manufacturing the semiconductor package with the prefabricated conductive unit. The invention also relates to several methods for preparing the prefabricated conductive unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Singapore application 10202303101X, filed on November 02, 2023, the disclosure of which is incorporated in its entirety into this patent application. Technical Field

[0003] The present application relates to a semiconductor package with a prefabricated conductive unit. The present application also relates to a panel-level manufacturing method for manufacturing the semiconductor package with the prefabricated conductive unit. The present application also relates to several methods for preparing the prefabricated conductive unit. Background Art

[0004] Traditionally, vertical electrical connections are usually formed during the process of manufacturing semiconductor packages. For example, multiple layers of the build-up layer can be formed using an on-site metal plating process during small-scale manufacturing of semiconductor packages. However, these traditional methods will cause serious warpage problems if used in large-scale panel-level processes. In addition, the speed of forming vertical electrical connections by on-site metal plating processes is too slow. Summary of the invention

[0005] Therefore, the present application discloses a plurality of panel-level methods to solve the warpage problem when manufacturing semiconductor packages on a large panel-level size. At the same time, the panel-level methods can be performed quickly to improve productivity.

[0006] As a first aspect of the present application, a panel-level manufacturing method for forming a semiconductor package is disclosed. The panel-level method includes providing at least one semiconductor die and a plurality of prefabricated conductive units to a predetermined position on a first carrier, wherein the prefabricated conductive units are prepared from a molded conductive substrate; forming a molded layer for encapsulating the at least one semiconductor die and the plurality of prefabricated conductive units to form a reconstructed panel; transferring the reconstructed panel to a second carrier; forming a front-side building layer on the active surface of the at least one semiconductor die; forming an external connection layer that can be electrically coupled to the front-side building layer; and dividing the reconstructed panel, the front-side building layer, and the external connection into the semiconductor package. Wherein, the at least one semiconductor die and the plurality of prefabricated conductive units are configured to be electrically coupled to the external connection layer through the front-side building layer.

[0007] As a second aspect of the present application, another panel-level manufacturing method for forming a semiconductor package is disclosed. The panel-level method includes bonding a plurality of semiconductor dies to predetermined positions on a first carrier, forming a molding layer for encapsulating the plurality of semiconductor dies to form a reconstructed panel, transferring the reconstructed panel to a second carrier, forming a front-side building layer on the active surfaces of the plurality of semiconductor dies, forming an interposer on the front-side building layer, wherein the interposer includes a prefabricated conductive unit, and the prefabricated conductive unit is prepared from a molded conductive substrate, forming an external connection layer on the interposer, and dividing the reconstructed panel, the front-side building layer, the interposer, and the external connection layer into the semiconductor package.

[0008] The above two panel-level manufacturing methods also involve several methods for preparing prefabricated conductive units. The first method for preparing the prefabricated conductive unit includes mounting the molded conductive substrate on the first carrier. Then, the insulating portion of the molded conductive substrate is removed on the first carrier. Therefore, the conductive portion of the molded conductive substrate is retained separately as a prefabricated conductive unit. The second method for preparing the prefabricated conductive unit includes removing the insulating portion from the molded conductive substrate and leaving the conductive portion of the molded conductive substrate as a separate prefabricated conductive unit. Then, the prefabricated conductive units are bonded to predetermined positions on the first carrier, respectively.

[0009] As a third aspect of the present application, a semiconductor package having at least one prefabricated conductive unit is disclosed, which includes at least one semiconductor bare chip; a molding layer for encapsulating the at least one semiconductor bare chip; at least one prefabricated conductive unit, wherein the at least one prefabricated conductive unit is prepared from a molded conductive substrate; a front side building layer electrically coupled to the at least one semiconductor bare chip and the at least one prefabricated conductive unit; and an external connection layer electrically coupled to the front side building layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings show embodiments of the present application for explaining the principles disclosed in the present application. However, it should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of the present application.

[0011] Figure 1 FIG. 1 is a flowchart of a panel-level method S10 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0012] Figure 2a to Figure 2g A first embodiment of steps S11 and S12 of the panel level method S10 is shown.

[0013] Figures 3a to 3f A second embodiment of steps S11 and S12 of the panel level method S10 is shown.

[0014] Figures 4a to 4dA third embodiment of steps S11 and S12 of the panel level method S10 is shown.

[0015] Figure 5a and Figure 5b Step S13 of the panel level method S10 is shown.

[0016] Figure 6 Step S14 of the panel level method S10 is shown.

[0017] Figures 7a to 7c Step S15 of the panel level method S10 is shown.

[0018] Figure 8 and Fig. 9 Step S16 of the panel level method S10 is shown.

[0019] Fig.10a and Fig.10b Step S17 of the panel level method S10 is shown.

[0020] Fig.11 Step S18 of the panel level method S10 is shown.

[0021] Fig.12 Step S19 of the panel level method S10 is shown.

[0022] Figures 13a to 13e Several embodiments of semiconductor packages (single chip modules (SCMs)) obtained from the panel level method S10 are shown.

[0023] Figures 14 to 17 Another embodiment of the panel level method S10 is shown.

[0024] Figures 18a to 18c Shows the use of Figures 14 to 17 The method shown may provide several embodiments of a semiconductor package (SCM).

[0025] Figures 19a to 19c A variation of the first embodiment of steps S11 and S12 of the panel level method S10 is shown for a multi-chip module (MCM).

[0026] Figures 20a to 20c A variation of the second embodiment of steps S11 and S12 of the panel level method S10 is shown for a multi-chip module (MCM).

[0027] Figures 21a to 21c A variation of the third embodiment of steps S11 and S12 of the panel level method S10 is shown for a multi-chip module (MCM).

[0028] Fig.22a and Figure 22bStep S13 of the panel level method S10 for a multi-chip module (MCM) is shown.

[0029] Fig.23 Step S14 of the panel level method S10 for a multi-chip module (MCM) is shown.

[0030] Fig.24 Step S15 of the panel level method S10 for a multi-chip module (MCM) is shown.

[0031] Fig.25 and Fig.26 Step S16 of panel level method S10 for a multi-chip module (MCM) is shown.

[0032] Fig.27a and Figure 27b Step S17 of the panel level method S10 for a multi-chip module (MCM) is shown.

[0033] Fig.28 Steps S18 and S19 of the panel level method S10 for a multi-chip module (MCM) are shown.

[0034] Figures 29a to 29e Several embodiments of semiconductor packages (multi-chip modules (MCMs)) obtained from the panel level method S10 are shown.

[0035] Figure 30 to Figure 33 A variation of the panel-level method S10 is shown.

[0036] Figures 34a to 34c Shown as Figure 30 to Figure 33 The method shown may provide several embodiments of a semiconductor package (multi-chip module (MCM)).

[0037] Fig.35 Another embodiment of step S12 of the panel level method S10 is shown.

[0038] Figures 36a to 36c Shown as Fig.35 Several embodiments of semiconductor packages (multi-chip modules (MCM)) are obtained by the method shown.

[0039] Figures 37a to 37d Several embodiments of semiconductor packages (multi-chip modules (MCMs)) obtained from the panel level method S10 are shown.

[0040] Fig.38 FIG. 2 is a flow chart of another panel-level method S20 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0041] Figures 39a to 39iA schematic diagram of the panel level method S20 is shown.

[0042] Fig.40a and Fig.40b Shown as Figures 39a to 39i Two embodiments of available semiconductor packages (multi-chip modules (MCM)) are shown.

[0043] Reference numerals:

[0044] 100a Molded Interconnect Substrate (MIS) 110a First Conductive Part

[0045] 110b second conductive portion 112a interconnect wiring layer

[0046] 1122a first wiring layer 1123a first side

[0047] 1124a second wiring layer 1125a second side

[0048] 112b conductive through hole 1122b through hole front surface

[0049] 1124b through hole rear surface 1126 hollow through hole

[0050] 1128 side wall 114a / 114b insulation assembly

[0051] 1142a / 1142b first surface 1144a / 1144b second surface

[0052] 116 prefabricated conductive unit 1162 first prefabricated conductive unit

[0053] 1164 second prefabricated conductive unit 116 1 The first prefabricated conductive unit

[0054] 116 2 Prefabricated conductive unit second piece 116 3 Prefabricated conductive unit third piece

[0055] 118 gap 1182 first gap

[0056] 1184 second gap 120 insulation part

[0057] 130 first carrier 132 die bonding area

[0058] 133 Main mark 134 Unit bonding area

[0059] 135 auxiliary mark 136 reference point

[0060] 140 first heat release tape 150 semiconductor bare chip

[0061] 150a first semiconductor die 150b second semiconductor die

[0062] 1502 active surface 1504 back surface

[0063] 152 contact pad 154 protective layer

[0064] 156 Pre-through hole 158 Filling through hole

[0065] 160 molding layer 162 top

[0066] 164 grinding equipment 170 reconstructed panel

[0067] 180 front side building layer 182 front side dielectric layer

[0068] 1822 first dielectric surface 184 front side trace

[0069] 186 front stud 1862 first stud surface

[0070] 188 stud cavity 190 rear side building layer

[0071] 192 rear side through hole 194 rear side filling through hole

[0072] 1942 first through hole surface 1944 second through hole surface

[0073] 196 Back side dielectric layer 198 Back side trace

[0074] 199 rear stud 1992 second stud surface

[0075] 200 second carrier 210 second heat release tape

[0076] 220 External connection layer (solder ball) 230a-230e Semiconductor package (single chip

[0077] 240 Passive Device Module (SCM)

[0078] 250 top semiconductor package 254 internal connection layer (solder ball)

[0079] 252 package dielectric layer 260 heat sink

[0080] 256 internal space 272 additional traces

[0081] 270 additional build-up layer 276 additional through hole

[0082] 274 additional dielectric layer 280a-280c ​​semiconductor package (SCM)

[0083] 278 Additional filled vias 292 Antenna

[0084] 290a-290e semiconductor package (MCM) 322 copper pillar

[0085] 300a-300c, 310a-310c, 320a-320d, 340a 332 intermediate dielectric layer

[0086] -340b semiconductor package (MCM) 336 intermediate traces

[0087] 330 Interposer 350 External Devices

[0088] 334 Intermediary filling via 3362 First intermediary trace surface DETAILED DESCRIPTION

[0089] Figure 1 A flow chart of a panel-level method S10 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure is shown. The panel-level method S10 includes steps S11 to S19.

[0090] Figures 2a to 4d Three embodiments of steps S11 and S12 of the panel level method S10 are shown. Figure 2a to Figure 2g A first embodiment is shown, wherein step S11 includes a first sub-step S112, namely mounting the molded conductive substrate on the first carrier 130. Optionally, a first heat release tape 140 is applied between the molded conductive substrate and the first carrier 130. The first heat release tape 140 is used to fix the molded conductive substrate to the first carrier 130 at room temperature. The molded conductive substrate has a conductive portion that passes through the molded conductive substrate along the thickness direction. The molded conductive substrate may also have an insulating portion 120, which can keep the molded conductive substrate as a single piece when the molded conductive substrate is mounted on the first carrier 130. The insulating portion 120 may be made of any electrically insulating material, such as a molding material. The conductive portion may also include a conductive component and an insulating component.

[0091] Figure 2a A cross-sectional view of one embodiment of a molded conductive substrate is shown, wherein the molded conductive substrate may be a molded interconnect substrate (MIS) 100a. The molded interconnect substrate (MIS) 100a has a first conductive portion 110a (as a type of conductive portion) separated by an insulating portion 120; while the insulating portion 120 may be removed along the dashed line shown. Figure 2a' shows an enlarged cross-sectional view of the independent first conductive portion 110a after the insulating portion 120 is removed. Therefore, the independent first conductive portion 110a becomes a form of a separate prefabricated conductive unit 116. As a type of conductive component, the first conductive portion 110a includes a plurality of interconnect wiring layers 112a for conducting electricity along the thickness direction of the first conductive portion 110a located between the first wiring layer 1122a and the second wiring layer 1124a. The first conductive portion 110a also includes an insulating component 114a, such as a molding material, for encapsulating the interconnect wiring layer 112a. The insulating component 114a can be a part of the electrically insulating material of the insulating portion 120 extending into the first conductive portion 110a. However, the first wiring layer 1122a and the second wiring layer 1124a are not enclosed within the insulating component 114a. In other words, the first side 1123a for defining the first thickness of the first wiring layer 1122a is exposed from the first surface 1142a of the insulating component 114a. Likewise, the second side 1125a for defining the second thickness of the second wiring layer 1124a is also exposed from the second surface 1144a of the insulating component 114a. The first thickness of the first wiring layer 1122a and the second thickness of the second wiring layer 1124a may be the same or different.

[0092] Figure 2b A cross-sectional view of another embodiment of a molded conductive substrate is shown, wherein the molded conductive substrate may be a molded via substrate (MVS). Similarly, the molded via substrate (MVS) also has a second conductive portion 110b (as another type of conductive portion) separated by an insulating portion 120. The insulating portion 120 may also be removed along the dashed line shown. Figure 2b ' shows an enlarged cross-sectional view of the independent second conductive part 110b after the insulating part 120 is removed. Therefore, the independent second conductive part 110b becomes another form of a separate prefabricated conductive unit 116. The second conductive part 110b includes one or more conductive through-holes 112b as another type of conductive component. It can be electrically conductive along the thickness direction between the through-hole front surface 1122b and the through-hole rear surface 1124b. The second conductive part 110b may also include an insulating component 114b, such as a molding material for encapsulating the conductive through-hole 112b. The insulating part 114b may be a part of the electrically insulating material of the insulating part 120 extending into the second conductive part 110b. Specifically, the conductive through-hole 112b extends through the insulating component 114b; and the through-hole front surface 1122b and the through-hole rear surface 1124b of the conductive through-hole 112b are flush with the first surface 1142b and the second surface 1144b of the insulating component 114b, respectively.

[0093] The molded through-hole substrate (MVS) can be formed by first forming one or more hollow through-holes 1126 through the insulating component 114b in the second conductive part 110b, and then completely or partially filling the hollow through-holes 1126 with any conductive material such as copper. Preferably, the hollow through-holes 1126 are partially filled to save the conductive material used to fill the hollow through-holes 1126, thereby reducing the weight of the second conductive part 110b, thereby further eliminating the warpage that may occur in subsequent processes. Figure 2b As shown, the conductive material is only adhered to the sidewall 1128 of the hollow through hole 1126, so that the hollow through hole 1126 is not filled in the central area. However, the filled conductive material is sufficient to form a continuous conductive path along the sidewall 1128 between the through hole front surface 1122b and the through hole rear surface 1124b of the conductive through hole 112b. It should be understood that the molded interconnect substrate (MIS) 100a and the molded through hole substrate (MVS) are only two embodiments of molded conductive substrates; other forms of molded conductive substrates are also within the scope of the present application. Accordingly, the first conductive portion 110a and the second conductive portion 110b are only two embodiments of the conductive portion (and the prefabricated conductive unit 116 after separation); other forms of conductive portions (and the prefabricated conductive unit 116 after separation) are also included in the scope of the present application. For ease of explanation, only the molded interconnect substrate (MIS) 100a is used as the molded conductive substrate, and only the first conductive portion 110a is used as the conductive portion (and the prefabricated conductive unit 116 after separation) to illustrate the subsequent steps of S10. However, it should be understood that the following description is also applicable to other forms of molded conductive substrates and conductive portions, including molded through-hole substrates (MVS) and second conductive portions 110b.

[0094] Figure 2c As shown in the top view, the insulating portion 120 can be removed along the dashed line in the width direction. Then, the first conductive portion 110a of the molded interconnect substrate (MIS) 100a can also be divided along the dashed line in the length direction. In this way, the first conductive portion 110a surrounded by the dashed line and the dashed line can form a prefabricated conductive unit 116. Figure 2dThe cross-sectional view of step S11 including the second sub-step S114 is shown, i.e., the insulating portion 120 is removed from the molded interconnect substrate (MIS) 100a as described above, and the first conductive portion 110a is segmented, thereby forming a prefabricated conductive unit 116. In this way, a gap 118 is formed at the original position of the insulating portion 120 between the first conductive portions 110a. Compared with the conventional method of making vertical electrical connections in the semiconductor packaging process, such as on-site metal plating, the prefabricated conductive unit 116 is made before the panel-level packaging process of bonding the semiconductor die 150 to the first carrier 130. Therefore, S10 of the present application can significantly reduce or even eliminate the serious warpage problem that occurs in the conventional method.

[0095] Figure 2e The top view of FIG. 1 shows that the first carrier 130 has a die bonding area 132 (as shown by a dashed rectangle) at the gap 118 for accommodating a semiconductor die 150. The die bonding area 132 has a main mark 133 therein for guiding the semiconductor die 150 to be bonded to its corresponding predetermined position in the die bonding area 132. Although it is shown here that the die bonding area 132 has four main marks 133 at four corners, respectively, other numbers of main marks 133 and distributions are also within the scope of the present application.

[0096] Figure 2f The cross-sectional view of step S12 is shown, i.e., bonding the semiconductor die 150 in its die bonding region 132. The semiconductor die 150 has one or more contact pads 152 for leading out functional circuits at its active surface 1502, a protection layer 154 formed on the active surface 1502 for protecting the functional circuits, and one or more pre-through holes 156 in the protection layer 154 for exposing the contact pads 152 from the protection layer 154. The semiconductor die 150 is bonded face-down so that the protection layer 154 contacts the first thermal release tape 140 or the first carrier 130. Figure 2g The top view of FIG. 1 shows that the semiconductor die 150 has been bonded to the die bonding area 132 on the first carrier 130. Preferably, the primary mark 133 is not covered by the semiconductor die 150, so that a post-bonding inspection process can be performed to check whether the semiconductor die 150 is bonded to the predetermined position within its respective die bonding area 132.

[0097] Contrary to the first embodiment, the insulating portion 120 may not be removed after the molded conductive substrate is mounted on the first carrier 130. Instead, the insulating portion 120 is removed elsewhere, and the independent conductive portion becomes a separate prefabricated conductive unit 116. Then, the prefabricated conductive unit 116 is bonded to its predetermined position on the first carrier 130. Figure 3a to Figure 3f A second embodiment of steps S11 and S12 of the panel level method S10 is shown. Figure 3a and Figure 3b The cross-sectional view of step S11 is shown, that is, prefabricating the conductive unit 116 (for example, Figure 3a and Figure 3b The semiconductor die 150 is bonded to the first carrier 130 in the form of the first conductive portion 110a and the second conductive portion 110b. In addition to the die bonding area 132 and the main mark 133 for accommodating the semiconductor die 150, Figure 3c As shown in the top view of FIG. 1 , the first carrier 130 may also have a unit bonding area 134 (as shown by the dashed rectangle in the figure) for accommodating the prefabricated conductive unit 116. The auxiliary mark 135 in the unit bonding area 134 may be used to guide the prefabricated conductive unit 116 to bond to its predetermined position. Although the figure shows four auxiliary marks 135 located at the four corners of the unit bonding area 134, it is understood that other numbers of auxiliary marks 135 and distributions are also within the scope of the present application. Preferably, the auxiliary marks 135 are not covered by the prefabricated conductive unit 116, so that a post-bonding inspection process can be performed to check whether the prefabricated conductive unit 116 is bonded to its respective predetermined position. Alternatively, if the first carrier 130 does not have the auxiliary marks 135, the main marks 133 may also be used to guide the prefabricated conductive unit 116 for bonding. In addition, the first carrier 130 may also have a reference point 136 for locating the die bonding area 132 and the unit bonding area 134 on the first carrier 130.

[0098] Figure 3d A cross-sectional view of step 12 in the second embodiment is shown, ie, bonding the semiconductor die 150 to the corresponding die bonding area 132 on the first carrier 130 . Figure 3e and Figure 3f 1 shows a cross-sectional view and a top view of bonding the prefabricated conductive unit 116 and the semiconductor die 150 to the first carrier 130 according to the package design. Instead of the main mark 133, the semiconductor die 150 can also be guided by the auxiliary mark 135 for bonding. If the bonding is accurately performed, the semiconductor die 150 and the prefabricated conductive unit 116 can be easily positioned on the first carrier 130 by the main mark 133 and / or the auxiliary mark 135, and the main mark 133 and / or the auxiliary mark 135 can be further positioned by the reference point 136.

[0099] Similar to the second embodiment described above, Figures 4a to 4c A third embodiment of steps S11 and S12 of the panel level method S10 is shown. In the third embodiment, steps S11 and S12 are performed in the reverse order of the second embodiment. Figure 4aAs shown, firstly, step S12 is performed to bond the semiconductor die 150 to the first carrier 130. Then, step S11 is performed to bond the prefabricated conductive unit 116 (shown in the form of the first conductive portion 110a) to the first carrier 130, as shown in FIG. Figure 4b As shown. Figure 4c The cross-sectional view of FIG. 1 shows that the prefabricated conductive unit 116 and the semiconductor die 150 are bonded to respective predetermined positions on the first carrier 130 . Figure 4d and Figure 4c The difference is that the prefabricated conductive unit 116 is bonded in the form of the second conductive portion 110b. Therefore, the third embodiment can also achieve the same Figure 3f If bonding is performed accurately, the semiconductor die 150 and the prefabricated conductive unit 116 can be easily positioned on the first carrier 130 by the main mark 133 and / or the auxiliary mark 135 , and the main mark 133 and the auxiliary mark 135 can be further positioned by the fiducial 136 .

[0100] Figure 5a and Figure 5b Step S13 of the panel-level method S10 is shown, i.e., forming a molding layer 160 for encapsulating the prefabricated conductive unit 116 (shown in the form of the first conductive portion 110a) and the semiconductor die 150, thereby forming a reconstructed panel 170. In particular, the first wiring layer 1122a and the second wiring layer 1124a of the first conductive portion 110a are encapsulated in the molding layer 160. The molding layer 160 can be performed by any known molding process such as compression molding. Figure 5a The cross-sectional view of FIG. 1 shows that the pre-via 156 of the semiconductor die 150 is not filled before the semiconductor die 150 is bonded to the first carrier 130. Figure 5b As shown, before bonding the semiconductor die 150 to the first carrier 130, the pre-via 156 of the semiconductor die 150 may also be filled with a conductive material. Therefore, a filled via 158 is formed in the protection layer 154 and electrically coupled to the contact pad 152 to further lead out the functional circuit of the semiconductor die 150.

[0101] Figure 6 Step S14 of the panel-level method S10 is shown, that is, a portion of the mold layer 160 is removed from the back side 1504 of the semiconductor die 150 by any known method (e.g., a grinding device 164), thereby thinning the mold layer 160. When the thickness of the mold layer 160 is greater than the package design, step S14 is optionally performed. Specifically, the top 162 of the mold layer 160 is still retained for encapsulating the prefabricated conductive unit 116 and the semiconductor die 150 (including the back side 1504 of the semiconductor die 150).

[0102] Figures 7a to 7c Step S15 of the panel-level method S10 is shown, namely forming a back-side build-up layer 190 on the prefabricated conductive unit 116 . Figure 7a A first sub-step S152 of step S15 is shown, namely forming a backside through hole 192 in the top portion 162 of the mold layer 160 for exposing the second wiring layer 1124a of the first conductive portion 110a. Figure 7b The second sub-step S154 of step S15 is shown, that is, filling the backside via 192 with a conductive material to form a backside filled via 194. The backside filled via has a first via surface 1942 electrically coupled to the second wiring layer 1124a, and a second via surface 1944 exposed from the top 162 of the mold layer 160. Figure 7c A third sub-step S156 of step S15 is shown, namely forming a backside trace 198 electrically coupled to the backside filled via 194 , and a backside dielectric layer 196 for encapsulating the backside trace 198 .

[0103] Figure 8 and Fig. 9 Step S16 of panel-level method S10 is shown, namely transferring reconstructed panel 170 with backside build-up layer 190 onto second carrier 200 . Figure 8 The first sub-step S162 of step S16 is shown, which is to separate the reconstructed panel 170 with the backside building layer 190 from the first carrier 130 and the first thermal release tape 140. The first sub-step S162 can be performed by heating the first thermal release tape 140 to a certain elevated temperature, because at a certain elevated temperature, the first thermal release tape 140 will lose its adhesion ability to the reconstructed panel 170. Fig. 9 The second sub-step S164 of step S16 is shown, that is, the reconstructed panel 170 with the backside building layer 190 is mounted on the second carrier 200 in a flipped manner, so that the backside dielectric layer 196 is in contact with the second carrier 200; and the contact pad 152 (through the pre-via 156) and the first wiring layer 1122a of the first conductive portion 110a are exposed from the mold layer 160. Similarly, the second thermal release tape 210 can also be applied between the backside building layer 190 and the second carrier 200 to fix the reconstructed panel 170 with the backside building layer 190 to the second carrier 200 at room temperature.

[0104] Fig.10a and Fig.10b Step S17 of the panel level method S10 is shown, namely forming a front side build-up layer 180 on the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122 a of the first conductive portion 110 a . Fig.10a The first sub-step S172 of step S17 is shown, as shown above Figure 5aAs shown, if the pre-via 156 is not filled before the semiconductor die 150 is bonded to the first carrier 130, the pre-via 156 is filled with a conductive material to form a filled via 158. Figure 5b , that is, the pre-via 156 has been filled before the semiconductor die 150 is bonded to the first carrier 130 , then the sub-step S172 may be skipped. Fig.10b A second sub-step S174 of step S17 is shown, i.e., forming a front side build-up layer 180 on the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122a of the first conductive portion 110a. The front side build-up layer 180 includes a front side trace 184 electrically coupled to the filled via 158, a front side stud 186 electrically coupled to the front side trace 184, and a front side dielectric layer 182 encapsulating the front side trace 184 and the front side stud 186. The front side stud 186 has a first stud surface 1862 exposed from the front side dielectric layer 182. In one embodiment, the first stud surface 1862 is coplanar with the first dielectric surface 1822 of the front side dielectric layer 182. In another embodiment, the first stud surface 1862 is exposed from the first dielectric surface 1822 of the front side dielectric layer 182 through the stud cavity 188. The stud cavity 188 may have a cavity depth in the range of 1 to 15 micrometers (μm), or more specifically in the range of 1 to 5 micrometers (μm), in the range of 3 to 6 micrometers (μm), or in the range of 5 to 15 micrometers (μm).

[0105] Fig.11 Step S18 of the panel-level method S10 is shown, that is, forming an external connection layer 220, such as a solder ball. The cross-sectional view shows that the solder ball (as the external connection layer 220) is placed and electrically coupled to the front-side stud 186. Preferably, the solder ball is first melted and fused into the stud cavity 188, and then coupled to the front-side stud 186, so that the solder ball can be firmly fixed during subsequent processes. It should be understood that other forms of the external connection layer 220 are also within the scope of the present application, such as copper pillars 322.

[0106] Fig.12 Step S19 of the panel-level method S10 is shown, which is to separate the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 from the second carrier 200 and the second thermal release tape 210, and then divide the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 into individual semiconductor packages (single-chip modules (SCM)) along saw lines (as shown by dotted lines in the figure).

[0107] Figures 13a to 13e A plurality of embodiments of semiconductor packages 230 a to 230 e (single chip modules (SCMs)) obtained from the panel level method S10 are shown. Fig.13aA cross-sectional view of semiconductor package 230a is shown, in which functional circuitry of semiconductor die 150 is electrically brought out through contact pads 152, filled vias 158, front side traces 184 and front side studs 186 of front side build-up layer 180, and external connection layer 220 (eg, solder balls). Fig.13b A cross-sectional view of a semiconductor package 230 b is shown, wherein the backside build-up layer 190 further includes a backside stud 199 coupled to the backside trace 198. The backside stud 199 has a second stud surface 1992 exposed from the backside dielectric layer 196 so that a passive device 240 (e.g., a capacitor) can be mounted on and electrically coupled to the backside build-up layer 190. Fig.13c A cross-sectional view of the semiconductor package 230c is shown, wherein the back side 1504 of the semiconductor die 150 is exposed from the molding layer 160. Thus, the heat sink 260 may be mounted to and in direct contact with the back side 1504 of the semiconductor die 150 to enhance heat dissipation. Fig.13d A cross-sectional view of a semiconductor package 230d is shown, wherein a top semiconductor package 250 can be mounted and electrically coupled to a backside build layer 190 to form a package-on-package (PoP) configuration. Preferably, the top semiconductor package 250 is encapsulated within a package dielectric layer 252. At the same time, the package dielectric layer 252 can also act as an underfill to protect an internal connection layer 254 (e.g., solder balls). Compared to conventional molding materials (e.g., Sumitomo G730), the package dielectric layer 252 has a smaller filling size, so that the package dielectric layer 252 can enter the internal space 256 around the internal connection layer 254. Optionally, the filling size of the package dielectric layer 252 is less than 20 microns (μm); preferably, the filling size of the package dielectric layer 252 is between 10 and 20 microns (μm). Fig.13e A cross-sectional view of a semiconductor package 230 e without the backside build-up layer 190 is shown; the first conductive portion 110 a as a prefabricated conductive unit 116 is completely encapsulated within the mold layer 160 .

[0108] Figures 14 to 17 A variation of the panel-level method S10 is shown, which further includes an additional build-up layer 270 located above the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122a of the first conductive portion 110a. Fig.10a , Fig.14 The cross-sectional view shows that the additional build-up layer 270 includes an additional trace 272 electrically coupled to the filled via 158 of the semiconductor die 150 and the first wiring layer 1122a (as a prefabricated conductive unit 116) of the first conductive portion 110a; an additional dielectric layer 274 for encapsulating the additional trace 272; and an additional through hole 276 for exposing a portion of the additional trace 272 from the additional dielectric layer 274. Fig.15As shown, additional vias 276 may be filled with any conductive material to form additional filled vias 278 that are electrically coupled to additional traces 272 . Fig.16 The front side build-up layer 180 is shown formed on the additional build-up layer 270, wherein the front side traces 184 are electrically coupled to the additional filled vias 278; the external connection layer 220 is then formed as described above. Fig.12 , Fig.17 The reconstructed panel 170 with the front side building layer 180 , the back side building layer 190 and the additional building layer 270 is shown to be first separated from the second carrier 200 and the second thermal release tape 210 ; and then divided into individual semiconductor packages, which are single chip modules (SCMs) with only one semiconductor die 150 .

[0109] Figure 18a to Figure 18c Shows from Figure 14 to Figure 17 1 and 2. Multiple embodiments of semiconductor packages 280a to 280c (single chip modules (SCM)) obtained by deformation of the semiconductor packages 280a to 280c. Figures 18a to 18c Cross-sectional views of semiconductor packages 280 a , 280 b , and 280 c are shown, which have similar structures to semiconductor packages 230 b , 230 d , and 230 e , respectively, except that semiconductor packages 280 a , 280 b , and 280 c also have an additional build-up layer 270 sandwiched between reconstruction panel 170 and front-side build-up layer 180 . Fig.18b The internal connection layer 254 in the embodiment may also be used as an underfill as described above to protect the internal connection layer 254 (eg, solder balls).

[0110] The following description also illustrates a variation of the panel-level method S10 for manufacturing a multi-chip module (MCM) having two or more semiconductor dies 150 . Figures 19a to 19c It briefly shows that Figure 2a to Figure 2g The panel level method S10 shown in FIG. 1 is a variation of the first embodiment of steps S11 and S12. Fig.19a It is shown that the molded interconnect substrate (MIS) 100a is first mounted on the first carrier 130 and the first heat release tape 140, and then the insulating portion 120 is removed from the molded interconnect substrate (MIS) 100a along the dotted line in the figure to obtain the first conductive portion 110a as the prefabricated conductive unit 116. Fig.19b As shown, two types of prefabricated conductive units 116 can be prepared from the first conductive portion 110a, namely, a first prefabricated conductive unit 1162 and a second prefabricated conductive unit 1164. Accordingly, two types of gaps 118, namely, a first gap 1182 and a second gap 1184, can be formed between the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 to accommodate two types of semiconductor dies 150, namely, a first semiconductor die 150a and a second semiconductor die 150b. Fig.19c The first semiconductor die 150 a and the second semiconductor die 150 b are shown bonded in the first gap 1182 and the second gap 1184 on the first carrier 130 and the first thermal release tape 140 , respectively.

[0111] Figures 20a to 20c Briefly shows Figure 3a to Figure 3f The second embodiment of the step S11 and S12 of the panel level method S10 shown in FIG. Fig.20a It is shown that the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 are bonded to their predetermined positions on the first carrier 130 and the first thermal release tape 140, respectively, which are separated by the first gap 1182 and the second gap 1184. Then, Fig.20b It is shown that the first semiconductor die 150 a and the second semiconductor die 150 b are bonded to the first carrier 130 at predetermined positions within the first gap 1182 and the second gap 1184 , respectively. Fig.20c Step S11 and step S12 are completed, wherein the first semiconductor die 150 a is located in the first gap 1182 between the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 , and the second semiconductor die 150 b is located in the second gap 1184 between the second prefabricated conductive unit 1164 and the first prefabricated conductive unit 1162 .

[0112] Figures 21a to 21c Shows Figures 4a to 4d The third embodiment of the panel level method S10 shown in FIG. 1 is a variation of steps S11 and S12. Fig.21a The first semiconductor die 150 a and the second semiconductor die 150 b are shown bonded to their predetermined positions on the first carrier 130 . Figure 21b It is shown that the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 are also subsequently bonded to their predetermined positions on the first carrier 130 . Fig.21c It is shown that after completing steps S11 and S12, the Fig.20c The same packaging structure.

[0113] Fig.22a and Figure 22b Step S13 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 5a , forming a molding layer 160 for encapsulating the first prefabricated conductive unit 1162 , the second prefabricated conductive unit 1164 , the first semiconductor die 150 a and the second semiconductor die 150 b to form a reconstructed panel 170 . Fig.22a The cross-sectional view of FIG. 1 shows that the pre-via 156 is not filled before bonding. Figure 22bThe cross-sectional view of FIG. 1 shows that the pre-via 156 is filled to form a filled via 158 before bonding.

[0114] Fig.23 Step S14 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 6 After the mold layer 160 passes through the grinding device 164, the top 162 is left; then a rear side through hole 192 is formed in the top 162, thereby exposing the second wiring layer 1124a of the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164.

[0115] Fig.24 Step S15 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 7c Similarly, backside vias 192 are filled with a conductive material to form backside filled vias 194 ; backside dielectric layer 196 and backside traces 198 are then formed to form backside build-up layer 190 .

[0116] Fig.25 and Fig.26 Step S16 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 8 and Fig. 9 , the reconstructed panel 170 having the rear-side building layer 190 is separated from the first carrier 130 and the first thermal release tape 140 at an elevated temperature, and then mounted on the second carrier 200 and the second thermal release tape 210 in a flip-chip manner, and the rear-side dielectric layer 196 of the rear-side building layer 190 is in contact with the second carrier 200 and the second thermal release tape 210.

[0117] Fig.27a and Figure 27b Step S17 of the panel level method S10 for a multi-chip module (MCM) is shown. Fig.10a , Fig.27a As shown, the pre-vias 156 of the first semiconductor die 150a and the second semiconductor die 150b are filled with conductive material to form filled vias 158. If the pre-vias 156 have been filled to form filled vias 158 before bonding the first semiconductor die 150a and the second semiconductor die 150b to the first carrier 130 and the first thermal release tape 140, the pre-vias 156 may be skipped. Fig.27a . Similar to Fig.10b , Figure 27b The front side building layer 180 (not shown) is shown. Fig.10b The stud cavity 188 in is formed as described above.

[0118] Fig.28 Steps S18 and S19 of the panel level method S10 for a multi-chip module (MCM) are shown. Fig.11Similarly, an external connection layer 220 (such as solder balls) is formed on the front side building layer 180; then similarly Fig.12 , the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 is separated from the second carrier 200 and the second thermal release tape 210; and then divided into individual semiconductor packages (multi-chip modules (MCMs)) having the first semiconductor die 150a and the second semiconductor die 150b.

[0119] Figures 29a to 29e Several embodiments of semiconductor packages (MCMs) 290 a to 290 e obtained from the panel level method S10 are shown. Fig.29a Shown as Fig.28 The resulting first semiconductor package (MCM) 290 a includes the reconstructed panel 170 having the front-side build-up layer 180 and the back-side build-up layer 190 . Fig.29b A second semiconductor package (MCM) 290b is shown, wherein the passive device 240 and the top semiconductor package 250 are mounted on the front side build-up layer 180 and electrically coupled to the back side studs 199 of the back side build-up layer 190. In addition, the antenna 292 may also be mounted on the back side studs 199 of the back side build-up layer 190. Fig.29c A third semiconductor package (MCM) 290c is shown in which a heat sink 260 is mounted to and in direct contact with the back side 1504 of the semiconductor die 150 to enhance heat dissipation. Fig.29d A fourth semiconductor package (MCM) 290d is shown in which a top semiconductor package 250 is mounted to the backside build-up layer 190 to form a package-on-package (PoP) configuration. In addition, the package dielectric layer 252 may also be used as an underfill as described above. Fig.29e A fifth semiconductor package (MCM) 290 e is shown whose reconstitution panel 170 has a front-side build-up layer 180 but no back-side build-up layer 190 .

[0120] Similar to Figures 14 to 17 , Figure 30 to Figure 33 A variation of panel-level method S10 for a multi-chip module (MCM) is shown, further including an additional build-up layer 270 . Fig.30 The cross-sectional view shows that the additional build-up layer 270 includes an additional trace 272 electrically coupled to the first wiring layer 1122a of the first conductive portion 110a; an additional dielectric layer 274 for encapsulating the additional trace 272; and an additional through hole 276 for exposing a portion of the additional trace 272 from the additional dielectric layer 274. Fig.31 Additional vias 276 are shown filled with a conductive material to form additional filled vias 278 that are electrically coupled to additional traces 272 . Fig.32Front side build-up layer 180 is shown formed on additional build-up layer 270 , with front side traces 184 electrically coupled to additional filled vias 278 ; external connection layer 220 (eg, solder balls) is then formed, electrically coupled to front side studs 186 of front side build-up layer 180 . Fig.33 As shown, the reconstructed panel 170 having the front-side building layer 180, the back-side building layer 190 and the additional building layer 270 is first separated from the second carrier 200 and the second thermal release tape 210; and then divided along the saw lines into individual semiconductor packages (multi-chip modules (MCMs)) having the first semiconductor die 150a and the second semiconductor die 150b.

[0121] Figures 34a to 34c Shows from Figure 30 to Figure 33 Multiple embodiments of semiconductor packages (MCM) 300a to 300c obtained by deformation. Fig.34a Shows from Fig.33 A cross-sectional view of the resulting first semiconductor package (MCM) 300 a . In the backside build-up layer 190 , the backside traces 198 are encapsulated in the backside dielectric layer 196 . Fig.34b A cross-sectional view of a second semiconductor package (MCM) 300 b is shown, wherein the passive device 240 , the top semiconductor package 250 , and the antenna 292 are mounted on the back side studs 199 of the back side build-up layer 190 . Fig.34c A cross-sectional view of a third semiconductor package (MCM) 300c is shown, forming a package-on-package (PoP) configuration by mounting a top semiconductor package 250 to a backside build-up layer 190. As described above, the package dielectric layer 252 may also serve as an underfill.

[0122] Fig.35 Another variation of the panel level method S10 for a multi-chip module (MCM) is shown. Fig.19c , Fig.20c and Fig.21c As shown, the first semiconductor die 150a and the second semiconductor die 150b are bonded to the first carrier 130, but here the first conductive portion 110a (as the prefabricated conductive unit 116) only uses one or more first prefabricated conductive units 1162 to surround the first semiconductor die 150a and the second semiconductor die 150b, but is not located between the two. Here, since the first semiconductor die 150a and the second semiconductor die 150b are adjacent to each other, the communication between the two can be faster. The subsequent process of the deformation here is the same as above and is omitted here.

[0123] Figures 36a to 36c Shown as Fig.35 The illustrated variations provide multiple embodiments of semiconductor packages (MCM) 310 a to 310 c . Fig.36a A cross-sectional view of a first semiconductor package (MCM) 310 a is shown. Similar to the first semiconductor package (MCM) 300 a, here the backside traces 198 of the backside build-up layer 190 are encapsulated in the backside dielectric layer 196 . Fig.36b A cross-sectional view of a second semiconductor package (MCM) 310 b is shown. Similar to the second semiconductor package (MCM) 300 b, the passive device 240 , the top semiconductor package 250 , and the antenna 292 are mounted on the backside studs 199 of the backside build-up layer 190 . Fig.36c A cross-sectional view of a third semiconductor package (MCM) 310c is shown. Similar to the third semiconductor package (MCM) 300c, a package-on-package (PoP) configuration is formed by a top semiconductor package 250 mounted on a backside build-up layer 190. As described above, the package dielectric layer 252 may also be used as an underfill.

[0124] Figures 37a to 37d Several embodiments of semiconductor packages (MCMs) 320 a to 320 d obtained from the panel level method S10 are shown. Fig.37a The semiconductor package (eg Fig.29a FIG. 3 is a cross-sectional view of a first semiconductor package 320a similar to the semiconductor package 290a in FIG. 3 . However, the semiconductor package 320a uses the second conductive portion 110b as the prefabricated conductive unit 116 instead of the first conductive portion 110a in the semiconductor package 290a. Therefore, the through-hole front surface 1122b and the through-hole rear surface 1124b of the second conductive portion 110b are electrically coupled to the rear trace 198 of the rear side building layer 190 and the front trace 184 of the front side building layer 180, respectively.

[0125] Figure 37b A cross-sectional view of a second semiconductor package 320b is shown. The second semiconductor package 320b further includes an additional build-up layer 270 located between the reconstruction panel 170 and the front-side build-up layer 180. In addition to the second conductive portion 110b, the semiconductor package 320b further includes one or more copper pillars 322 located between the first semiconductor die 150a and the second semiconductor die 150b for electrical coupling. It should be understood that other structures similar to the copper pillars 322 are also within the scope of the present application. Fig.37c A cross-sectional view of a third semiconductor package 320 c is shown, wherein the backside studs 199 , the passive device 240 , and the top semiconductor package 250 are mounted on the backside build-up layer 190 , and are electrically coupled to the backside studs 199 of the backside build-up layer 190 . Fig.37dA cross-sectional view of a fourth semiconductor package 320d is shown, wherein the top semiconductor package 250 is mounted onto the backside build-up layer 190 to form a package-on-package (PoP) configuration. As described above, the package dielectric layer 252 may also be used as an underfill.

[0126] For all of the above-mentioned semiconductor packages (MCMs) made by the panel level method S10, including semiconductor packages 290a to 290e, 300a to 300c, 310a to 310c and 320a to 320d, the first semiconductor die 150a and the second semiconductor die 150b, and the prefabricated conductive unit 116 (in the form of the first conductive part 110a or the second conductive part 110b) are encapsulated in a parallel manner in the mold layer 160 and become part of the reconstructed panel 170.

[0127] Fig.38 FIG. 2 is a flow chart of another panel-level method S20 for manufacturing a semiconductor package (MCM) according to an exemplary embodiment of the present disclosure. The panel-level method S20 includes steps S21 to S29. Accordingly, Figures 39a to 39i A cross-sectional view of the panel level process S20 is shown.

[0128] Fig.39a The first step S21 of the panel level method S20 is shown, namely bonding the semiconductor die 150 to the first carrier 130 and possibly the first heat release tape 140. Only the first semiconductor die 150a and the second semiconductor die 150b are shown here, but it should be understood that more semiconductor dies 150 may be bonded to the first carrier 130. Fig.39b A second step S22 of the panel level method S20 is shown, namely forming a reconstructed panel 170 by forming a molding layer 160 for encapsulating the first semiconductor die 150 a and the second semiconductor die 150 b . Fig.39c The third step S23 of the panel level method S20 is shown, which is to thin the molding layer 160 with a grinding device 164 but leave the top 162, so that the top 162 still encapsulates the backside 1504 of the first semiconductor die 150a and the second semiconductor die 150b.

[0129] Fig.39d The first sub-step S242 of the fourth step S24 of the panel level method S20 is shown, namely separating the reconstituted panel 170 from the first carrier 130 and the first thermal release tape 140 at an elevated temperature. Fig.39eThe second sub-step S244 of the fourth step S24 is shown, that is, the reconstructed panel 170 is mounted on the second carrier 200 in a flipped manner, and may also be on the second thermal release tape 210. Therefore, the contact pads 152 can be exposed from the pre-through holes 156 of the first semiconductor die 150a and the second semiconductor die 150b. In this way, the reconstructed panel 170 is transferred from the first carrier 130 to the second carrier 200. Fig.39f A fifth step 25 of the panel level method S20 is shown, namely forming a front side build-up layer 180 on the reconstructed panel 170 ; and the contact pads 152 are electrically coupled to the front side traces 184 and the front side studs 186 of the front side build-up layer 180 . Figure 39g The sixth step S26 of the panel-level method S20 is shown, that is, the prefabricated conductive unit 116 (for example, in the form of a first conductive portion 110a) is mounted on the front side building layer 180, wherein the internal connection layer 254 is electrically coupled to the front side stud 186 of the front side building layer 180. As described above, the first conductive portion 110a is made by removing the insulating portion 120 from the molded interconnect substrate (MIS) 100a. Alternatively, as described above, the prefabricated conductive unit 116 can also be a second conductive portion 110b made by removing the insulating portion 120 from the molded through-hole substrate (MVS). Of course, other forms of prefabricated conductive units 116 are also within the scope of the present application. Instead of solder balls, the external connection layer 220 may also include a back surface texture (surface finish) for providing a flat surface for input / output (I / O). The back surface texture may be made of a single layer of metal such as tin or a single layer of metal composite material such as nickel / gold. Alternatively, the back surface texture may also be made of multiple layers. In some embodiments, the back surface texture is made of Electroless Nickel Immersion Gold (ENIG), which has two layers of metal surface coating, wherein the first nickel layer can be formed using an electroless plating chemical reaction; and then a very thin layer of gold is plated on the nickel layer. In other embodiments, the back surface texture can be made of Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), which is formed by depositing electroless nickel, followed by depositing electroless palladium, and finally immersion gold flash. The back surface texture is compatible with I / O chemistry to improve the stability of the connection. The thickness of the back surface texture can be in the range of 1 micron (μm) to 10 microns (μm), preferably, in the range of 1 micron (μm) to 5 microns (μm), or more preferably in the range of 1 micron (μm) to 3 microns (μm).

[0130] Figure 39hThe seventh step S27 of the panel-level method S20 is shown, which is to form an interposer 330, which includes an interposer filling via 334 electrically coupled to the first wiring layer 1122a of the first conductive portion 110a; an interposer trace 336 electrically coupled to the interposer filling via 334; and an interposer dielectric layer 332 for encapsulating the internal connection layer 254, the first conductive portion 110a (including the first wiring layer 1122a), the interposer filling via 334, and the interposer trace 336. However, the first interposer trace surface 3362 of the interposer trace 336 is exposed from the interposer dielectric layer 332. In addition, similar to the encapsulation dielectric layer 252, the interposer dielectric layer 332 can also be used as an underfill to protect the internal connection layer 254. Optionally, the filler size of the interposer dielectric layer 332 is less than 20 micrometers (μm); preferably, the filler size is 10 to 20 micrometers (μm). Fig.39i The eighth step S28 of the panel-level method S20 is shown, i.e., forming an external connection layer 220 (such as solder balls shown here) electrically coupled to the interposer traces 336. And the ninth step S29 of the panel-level method S20 is shown, i.e., separating the reconstructed panel 170 having the front-side building layer 180 and the interposer 330 from the second carrier 200 and the second thermal release tape 210 at an elevated temperature, and singulating the reconstructed panel 170 having the front-side building layer 180 and the interposer 330 into individual semiconductor packages (MCMs).

[0131] Fig.40a and Fig.40b Shows from Figures 39a to 39i Two examples of semiconductor packages (MCM) were obtained. Fig.40a The cross-sectional view of FIG. 1 shows a first semiconductor package (MCM) 340a mounted on an external device 350 (e.g., a PCB). The first semiconductor die 150a and the second semiconductor die 150b are electrically led out through the front-side building layer 180, the internal connection layer 254, the prefabricated conductive unit 116 (e.g., in the form of the first conductive portion 110a), the interposer-filled vias 334 and the interposer traces 336 of the interposer 330, and the external connection layer 220, and finally reach the external device 350. Fig.40a Also shown is a prefabricated conductive unit first piece 116 for electrically coupling the first semiconductor die 150a to the prefabricated conductive unit 116 of the external device 350. 1 , a prefabricated conductive unit second piece 116 for electrically coupling the second semiconductor die 150 b to the prefabricated conductive unit 116 of the external device 350 2 , and a prefabricated conductive unit third piece 116 for internal electrical coupling between the first semiconductor die 150a and the second semiconductor die 150b 3 , which can also be further led out to an external device 350 . Fig.40bFIG. 4 shows a cross-sectional view of a second semiconductor package (MCM) 340 b similar to the semiconductor package 340 a. However, the semiconductor package 340 b only has a third prefabricated conductive unit 116 . 3 , used for internal electrical coupling between the first semiconductor die 150a and the second semiconductor die 150b, which will also be further led to the external device 350. Although not shown here, it should be understood that the prefabricated conductive unit 116 can also take the form of the second conductive portion 110b. Other forms of prefabricated conductive units 116 are also within the scope of the present application.

[0132] For all semiconductor packages (MCMs) formed using the panel-level method S20 as described above, including semiconductor packages 340a and 340b, the first and second semiconductor dies 150a and 150b and the prefabricated conductive unit 116 (for example, in the form of the first conductive portion 110a or the second conductive portion 110b) are arranged in a vertical manner. Therefore, the first semiconductor die 150a and the second semiconductor die 150b are encapsulated in the mold layer 160 and become part of the reconstructed panel 170; and the prefabricated conductive unit 116 is encapsulated in the additional dielectric layer 274 and becomes part of the additional building layer 270.

[0133] The present disclosure may be implemented in other specific forms without departing from the spirit or essential characteristics of the present disclosure. Therefore, the foregoing embodiments are considered to be illustrative in all respects and not intended to limit the present disclosure. Therefore, the scope of the present disclosure is described by the appended claims rather than the foregoing description, and all changes within the meaning and scope of the claims are included in the present disclosure. In this application, unless otherwise stated, the terms "comprises", "including" and their grammatical variants are intended to represent "open" or "comprising" language, such that they include the listed elements, but also allow for the inclusion of additional, non-explicitly recited elements.

Claims

1. A panel-level manufacturing method for forming a semiconductor package, characterized in that: include: Providing at least one semiconductor die and a plurality of prefabricated conductive units to predetermined positions on a first carrier, wherein the prefabricated conductive units are prepared from a molded conductive substrate; forming a molding layer for encapsulating the at least one semiconductor die and the plurality of prefabricated conductive units to form a reconstructed panel; transferring the reconstructed panel to a second carrier; forming a front side build-up layer on the active surface of the at least one semiconductor die; forming an external connection layer electrically coupled to the front side building layer; as well as singulating the reconstructed panel, front side build-up layers and external connections into the semiconductor packages, The at least one semiconductor die and the plurality of prefabricated conductive units are configured to be electrically coupled to the external connection layer through the front-side building layer.

2. The method according to claim 1, wherein: The step of providing the plurality of prefabricated conductive units to predetermined positions on the first carrier comprises: placing the molded conductive substrate at a predetermined position on a first carrier; and The insulating portion of the molded conductive substrate is removed, and the conductive portion of the molded conductive substrate remains on the first carrier as a separate prefabricated conductive unit.

3. The method according to claim 1, wherein: The step of providing the plurality of prefabricated conductive units to predetermined positions on the first carrier comprises: removing the insulating portion of the molded conductive substrate and retaining the conductive portion of the molded conductive substrate as a separate prefabricated conductive unit; and The prefabricated conductive unit is bonded to a predetermined position on the first carrier.

4. The method according to claim 1, wherein: The prefabricated conductive unit includes a plurality of interconnect wiring layers, and a first wiring layer of the plurality of interconnect wiring layers is configured to be electrically coupled to the front-side build-up layer.

5. The method according to claim 1, wherein: The prefabricated conductive unit includes at least one conductive via, and a via front surface of the at least one conductive via is configured to be electrically coupled to the front-side build-up layer.

6. The method according to claim 1, wherein: Before transferring the reconstructed panel to a second carrier, the method further comprises: A backside building layer is formed on the plurality of prefabricated conductive units, wherein the backside building layer is opposite to the frontside building layer and is electrically coupled to the plurality of prefabricated conductive units.

7. A panel-level manufacturing method for forming a semiconductor package, characterized in that: include: bonding a plurality of semiconductor bare chips to predetermined positions on the first carrier respectively; forming a molding layer for encapsulating the plurality of semiconductor dies to form a reconstructed panel; transferring the reconstructed panel to a second carrier; forming a front-side build-up layer on the active surfaces of the plurality of semiconductor dies; forming an interposer on the front-side building layer, wherein the interposer comprises a prefabricated conductive unit, and the prefabricated conductive unit is prepared from a molded conductive substrate; forming an external connection layer on the interposer layer; as well as dividing the reconstructed panel, the front-side building layer, the interposer and the external connection layer into the semiconductor packages, The semiconductor die is configured to be electrically coupled to the external connection layer through the front-side build-up layer and the interposer.

8. The method according to claim 7, wherein: Before forming an intermediate layer, the method further includes: The plurality of prefabricated conductive elements are provided by removing insulating portions of the molded conductive substrate, wherein conductive portions of the molded conductive substrate are left alone as the prefabricated conductive elements.

9. The method according to claim 7, wherein: The prefabricated conductive unit includes a plurality of interconnect wiring layers, and a first wiring layer of the plurality of interconnect wiring layers is configured to be electrically coupled to the front-side build-up layer.

10. The method according to claim 7, wherein: The prefabricated conductive unit includes at least one conductive via having a via front surface that can be configured to be electrically coupled to the front-side build-up layer.

11. A semiconductor package having at least one prefabricated conductive unit, characterized in that: include: at least one semiconductor die; a molding layer for encapsulating the at least one semiconductor die; at least one prefabricated conductive unit, wherein the at least one prefabricated conductive unit is prepared from a molded conductive substrate; a front-side build-up layer electrically coupled to the at least one semiconductor die and the at least one prefabricated conductive element; and An external connection layer is electrically coupled to the front side building layer.

12. The semiconductor package according to claim 11, wherein Also includes: A rear side building layer is located on the prefabricated conductive unit and is opposite to the front side building layer.

13. The semiconductor package according to claim 11, wherein: The at least one prefabricated conductive unit includes a plurality of interconnect wiring layers, and a first wiring layer of the plurality of interconnect wiring layers is configured to be electrically coupled to the front-side build-up layer.

14. The semiconductor package according to claim 11, wherein The at least one prefabricated conductive unit includes at least one conductive via, and a via front surface of the at least one conductive via is configured to be electrically coupled to the front-side build-up layer.

15. The semiconductor package according to claim 11, wherein Also includes: An additional build-up layer is located between the at least one semiconductor die and the front-side build-up layer.

16. The semiconductor package according to claim 11, wherein The at least one semiconductor die includes a first semiconductor die and a second semiconductor die, both of which are electrically coupled through the at least one prefabricated conductive unit.

17. The semiconductor package according to claim 16, wherein: The at least one prefabricated conductive unit is packaged in the molding layer in a parallel manner with the first semiconductor die and the second semiconductor die.

18. The semiconductor package according to claim 16, wherein: The at least one prefabricated conductive unit is packaged vertically with the first semiconductor die and the second semiconductor die in a dielectric layer.

19. The semiconductor package according to claim 13, wherein: The at least one prefabricated conductive unit includes an insulating component, and the first wiring layer is exposed from the insulating component.

20. The semiconductor package according to claim 14, wherein The at least one conductive through hole of the prefabricated conductive unit is formed by filling any conductive material into a hollow through hole in the insulating component of the prefabricated conductive unit.

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