Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same may be provided herein. A method of manufacturing a semiconductor device may include: forming a stack in which first and second material layers are alternately stacked, the stack being formed in a chip region and a protection region, where the protection region is adjacent to the chip region; forming a plurality of first openings passing through the laminate of the protection region, the plurality of first openings being spaced apart from each other; forming a second opening from the plurality of first openings by expanding each of the plurality of first openings such that the plurality of first openings are coupled to each other; and forming a chip protector by filling the second opening with an insulating material.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to semiconductor devices and methods of manufacturing the semiconductor devices, and more particularly to semiconductor devices including a chip guard adjacent to a chip region and methods of manufacturing the semiconductor devices. Background Art

[0002] Through the semiconductor integration process, multiple chip regions can be formed on the semiconductor substrate. The multiple chip regions can be separated from each other by the scribing lane region. Since the semiconductor chip regions can be separated from each other by the cutting process, they can be manufactured into multiple semiconductor chips.

[0003] In order to protect the integrated circuit inside the chip area, a chip protection member may be formed adjacent to the chip area. For example, the chip protection member may be arranged to surround the chip area. The chip protection member may block defect-causing factors that may originate from outside the chip area and may be transmitted to the chip area. Summary of the invention

[0004] An embodiment of the present disclosure may provide a method for manufacturing a semiconductor device. The method may include the following steps: forming a stacked body in which a first material layer and a second material layer are alternately stacked, the stacked body being formed in a chip region and a protection region, wherein the protection region is adjacent to the chip region; forming a plurality of first openings passing through the stacked body in the protection region, the plurality of first openings being spaced apart from each other; forming a second opening from the plurality of first openings by extending each of the plurality of first openings so that the plurality of first openings are connected to each other; and forming a chip protection member by filling the second opening with an insulating material.

[0005] An embodiment of the present disclosure may provide a semiconductor device. The semiconductor device may include: a chip region; and a chip protection member, the chip protection member being adjacent to the chip region, and at least a portion of the chip protection member may have a width ranging from a first width to a second width, the second width being greater than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a view illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0007] Figure 2 is a view illustrating a structure of a chip protection member according to one embodiment of the present disclosure.

[0008] FIG. 3A to FIG. 3C is a view illustrating a method of manufacturing a chip protection member according to an embodiment of the present disclosure.

[0009] FIG. 4A to FIG. 4Dis a view illustrating a method of manufacturing a chip protection member according to an embodiment of the present disclosure.

[0010] FIG. 5A to FIG. 5F are views illustrating various layouts of a chip protection member according to an embodiment of the present disclosure.

[0011] Figure 6 is a view illustrating the structure of a chip protection member and a slit according to one embodiment of the present disclosure.

[0012] 7A to 7E is a view illustrating a method of simultaneously forming a chip protection member and a slit according to one embodiment of the present disclosure.

[0013] Figure 8 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied.

[0014] Fig. 9 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0015] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are provided as examples to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings in which embodiments of the present disclosure are illustrated so that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0017] Various embodiments of the present disclosure are directed to a semiconductor device and a method of manufacturing the semiconductor device, which can simplify a process of forming a chip protection member and improve performance of the chip protection member.

[0018] Figure 1 is a view illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0019] The semiconductor device may include a structure STR. For example, the structure STR may be a substrate (eg, a silicon wafer, a SiGe wafer, or an SOI wafer) or at least some material patterns formed on the substrate.

[0020] Reference Figure 1The structure STR may include a chip region CHA, a protection region GDA, and a scribe lane region SLA. For example, the structure STR may include a chip region CHA, a protection region GDA surrounding the chip region CHA, and a scribe lane region SLA surrounding the protection region GDA.

[0021] The chip area CHA may be a region in which a semiconductor chip is formed. Figure 1 , in a plan view, the chip area CHA can be arranged on the structure STR on the XY plane. Through the semiconductor integration process performed on the chip area CHA, semiconductor chips can be formed separately. The semiconductor chips formed in a plurality of chip areas CHA respectively within one structure STR can be substantially the same. After the semiconductor integration process is completed on the substrate, the structure STR can be separated into the chip areas CHA so that each of the chip areas CHA can be separated into the shape of a semiconductor chip.

[0022] Each of the protection areas GDA may be adjacent to a corresponding one of the chip areas CHA. Each protection area GDA may surround the corresponding chip area CHA. For example, the protection area GDA may be formed within a certain distance from the boundary of the chip area CHA. When the plane of the chip area CHA has a rectangular shape, the plane of the protection area GDA may have a rectangular ring shape surrounding the chip area CHA and contacting the periphery of the chip area CHA. In other words, the outer surface of the chip area CHA and the inner surface of the protection area GDA may contact each other.

[0023] A chip protection member may be formed in each protection area GDA. The chip protection member may prevent moisture or oxygen from penetrating into the chip area CHA. In addition, the chip protection member may reduce interference between dies during a packaging step performed after the chip area CHA is separated into each semiconductor chip. Figures 2 to 7E The shape and manufacturing method of the chip protection member formed in the protection area GDA are described.

[0024] The scribe lane area SLA may be located outside the chip area CHA and the protection area GDA. For example, the scribe lane area SLA may be located between the chip areas CHA. After the semiconductor integration process is completed, the scribe lane area SLA may be cut off during the scribing process of separating the semiconductor chip. Each chip area CHA may be separated by cutting the structure STR along the scribe lane area SLA. Each separated semiconductor chip may include a chip area CHA and a protection area GDA, which surrounds the chip area CHA. The process for cutting the structure STR may be implemented by a sawing process using a blade, a laser process using a laser, or an invisible scribing process. Electrical test patterns, process monitoring patterns, and alignment keys may be set in the scribe lane area SLA.

[0025] Although for the convenience of description, Figure 1 Six chip areas CHA are illustrated, but the present disclosure is not limited to this. For example, the structure STR may include 7 or more chip areas CHA of varying numbers. In the present disclosure, the chip area CHA, the protection area GDA, and the scribe lane area SLA are described separately. However, this is for the convenience of description, and the chip area CHA, the protection area GDA, and the scribe lane area SLA may be continuously connected to each other without being physically separated. For example, the positions of the chip area CHA, the protection area GDA, and the scribe lane area SLA on the substrate may vary.

[0026] Figure 2 is a view illustrating a structure of a chip protection member according to one embodiment of the present disclosure.

[0027] Reference Figure 2 , the protection area GDA may be defined between the chip area CHA and the scribe lane area SLA. The protection area GDA may be positioned adjacent to the chip area CHA. The protection area GDA may be disposed to surround the chip area CHA and may be in contact with the periphery of the chip area CHA. For example, the plane of the chip area CHA may have a rectangular shape, and the protection area GDA may extend along the boundary of the chip area CHA.

[0028] The chip protection member may be formed in the protection area GDA. For example, the first chip protection member GD1 may be located in the protection area GDA. The chip protection member (e.g., the first chip protection member GD1) may be formed adjacent to the chip area CHA. The chip protection member may or may not contact the chip area CHA. The chip protection member (e.g., the first chip protection member GD1) may surround the chip area CHA. For example, in the X direction of the chip area CHA (i.e., on the right and left sides of the chip area CHA), the chip protection member (e.g., the first chip protection member GD1) may extend along the Y direction. In addition, in the Y direction of the chip area CHA (i.e., above and below the chip area CHA), the chip protection member (e.g., the first chip protection member GD1) may extend along the X direction. The chip protection member (e.g., the first chip protection member GD1) may have a linear plane. For example, a portion of the first chip protection member GD1 located in the Y direction of the chip area CHA may have a linear plane extending along the X direction.

[0029] At least a portion of the chip protection member (e.g., the first chip protection member GD1) may have a width in which the first width W1 and the second width W2 are repeated alternately. The second width W2 may be greater than the first width W1. In the present disclosure, the width of the chip protection member may refer to the length of the chip protection member in a direction perpendicular to the direction in which the chip protection member extends on a plane. For example, Figure 2 A portion of the first chip protection member GD1 may extend in the X direction, and the width of the first chip protection member GD1 may refer to the length of the first chip protection member GD1 in the Y direction.

[0030] The chip protection member (eg, the first chip protection member GD1) may have a width in the range from the first width W1 to the second width W2. The range may be defined to include the end values ​​of the first width W1 and the second width W2. Figure 2 The minimum value among the widths of the first chip protection member GD1 may be the first width W1, and the maximum value may be the second width W2. In addition to the first width W1 and the second width W2, the first chip protection member GD1 may also have any width between the first width W1 and the second width W2.

[0031] The chip protection member (e.g., the first chip protection member GD1) may have a curved border. The chip protection member (e.g., the first chip protection member GD1) may include a protrusion protruding in a direction perpendicular to the direction in which the chip protection member extends. For example, a portion of the first chip protection member GD1 may extend in the X direction, and a portion of the first chip protection member GD1 may have a curved border that is curved in the Y direction or in a direction opposite to the Y direction. The chip protection member (e.g., the first chip protection member GD1) may have a shape in which a plurality of holes arranged along one direction (e.g., the X direction) are expanded and connected to each other.

[0032] FIG. 3A to FIG. 3C is a view illustrating a method of manufacturing a chip protection member according to an embodiment of the present disclosure.

[0033] Reference Figure 3A , a first opening OP1 may be formed in the protection area GDA. The first opening OP1 may be arranged along a first direction. For example, the first opening OP1 may be arranged along an X direction and a Y direction to surround the chip area CHA. Figure 3A It is shown that the first opening OP1 is arranged along the X direction. However, due to Figure 3A Only a portion of the protection area GDA is illustrated, and thus the first opening OP1 may be arranged along the Y direction at a position relative to the chip area CHA. Figure 2 The left or right side in the X direction.

[0034] The first opening OP1 may be holes spaced apart from each other. The planar shape of each first opening OP1 may be circular or elliptical. Each first opening OP1 may be a hole extending along the Z direction. The first opening OP1 may pass through at least a portion of the structure STR. In order to form the first opening OP1 at a designated position of the protection area GDA, an anisotropic dry etching process may be performed.

[0035] The first opening OP1 may be formed while forming a hole for forming a cell plug inside the chip area CHA. Alternatively, the first opening OP1 may be formed while forming a hole for forming a slit inside the chip area CHA. When the process of forming the first opening OP1 by etching the protection area GDA and the process of forming a hole for a cell plug or a hole for a slit by etching the chip area CHA are simultaneously performed, since the process of etching a hole with a large aspect ratio is integrated, the required process cost and time can be reduced. This will be referred to later. 7A to 7E An embodiment is described in which the first opening OP1 is formed while forming a hole for a slit inside the chip area CHA.

[0036] Reference Figure 3B, each first opening OP1 may be expanded to form a second opening OP2. For example, the inner wall of the first opening OP1 may be etched through the first opening OP1. The expansion of each first opening OP1 may indicate an increase in the area of ​​the first opening OP1 in a plan view. As each first opening OP1 is expanded, the first openings OP1 may be connected to each other. The second opening OP2 may include first openings OP1 that are each expanded and connected to each other. An isotropic wet etching process may be performed to expand the first opening OP1, thereby forming the second opening OP2. For example, a hard mask may be formed to expose the protection area GDA, and an isotropic wet etching process may be performed on the portion of the protection area GDA exposed by the hard mask.

[0037] Reference Figure 3C , a chip protection member (eg, a first chip protection member GD1) may be formed in the second opening OP2. The chip protection member (eg, the first chip protection member GD1) may include an insulating material filling the second opening OP2. For example, the second opening OP2 may be filled with a dielectric material having a low dielectric constant (low-k).

[0038] FIG. 4A to FIG. 4D is a view illustrating a method of manufacturing a chip protection member according to an embodiment of the present disclosure. FIG. 4A to FIG. 4D is along the different manufacturing steps Figure 2 A cross-sectional view taken along line AA' and line BB'.

[0039] Reference Figure 4A , a stacked body in which the first material layer M1 and the second material layer M2 are alternately stacked may be formed in the protection area GDA. For example, the first material layer M1 may be formed of an oxide layer (e.g., a silicon oxide layer). The second material layer M2 may be formed of a material that can be selectively removed in a subsequent process. The second material layer M2 may be formed of a material having an etching selectivity different from that of the first material layer M1. For example, the second material layer M2 may be formed of a nitride layer. Although Figure 4A Only the stacked body formed in the protection area GDA is illustrated, but a stacked body in which the first material layers M1 and the second material layers M2 are alternately stacked may also be formed in the chip area CHA.

[0040] The first opening OP1 may be formed in the protection area GDA. A portion of the stack of the protection area GDA may be etched to form the first opening OP1. The first opening OP1 may pass through the stack in which the first material layer M1 and the second material layer M2 are alternately stacked. In addition, the first openings OP1 may be arranged to be spaced apart from each other along the X direction. Figure 4A The cross-sectional view can be compared with Figure 3A corresponds to the floor plan.

[0041] Reference Figure 4B , at least a portion of the first material layer M1 may be removed through the first opening OP1. For example, the first material layer M1 may be etched using HF or a buffered oxide etchant (BOE). At least a portion of each first material layer M1 exposed through each first opening OP1 may be etched to form a first recess RC1. The first openings OP1 may be coupled to each other through the first recess RC1.

[0042] Reference Figure 4C , at least a portion of the second material layer M2 may be removed through the first opening OP1 and the first recess RC1. For example, phosphoric acid may be used to etch the second material layer M2. At least a portion of each second material layer M2 exposed through each first opening OP1 and each first recess RC1 may be etched to form the second opening OP2. The second opening OP2 may have a shape of a line extending along the X direction. Figure 4C The cross-sectional view can be compared with Figure 3B corresponds to the floor plan.

[0043] Reference Figure 4B and Figure 4C , the second opening OP2 may be formed by etching the laminated body exposed through each first opening OP1. A portion of the laminated body between the first openings OP1 may be removed to connect the first openings OP1 to each other. Figure 4B and Figure 4C As described, after etching the first material layer M1 exposed through the first opening OP1, the second material layer M2 may be etched to form the second opening OP2. In another example, after etching the second material layer M2 exposed through the first opening OP1, the first material layer M1 may be etched to form the second opening OP2. In yet another example, the first material layer M1 and the second material layer M2 exposed through the first opening OP1 may be etched simultaneously to form the second opening OP2.

[0044] Reference Figure 4D The second opening OP2 may be filled with an insulating material to form a chip protection member (eg, a first chip protection member GD1). For example, to fill the second opening OP2 with an insulating material, a thermal atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) method may be used. Figure 4D The cross-sectional view can be compared with Figure 3C corresponds to the floor plan.

[0045] The chip protection member (e.g., the first chip protection member GD1) can prevent or reduce the inflow of harmful substances (e.g., H2O, O2) from the outside of the chip area CHA. In addition, the chip protection member (e.g., the first chip protection member GD1) can reduce interference between semiconductor chips in a packaging process performed after the chip area CHA is separated into semiconductor chips. Since the chip protection member (e.g., the first chip protection member GD1) includes an insulating material in the second opening OP2, it can electrically separate the chip area CHA and can play a passivation role.

[0046] According to the present disclosure, since the boundary of the chip protection member (eg, the first chip protection member GD1 ) is a curved surface, crack propagation may be prevented or reduced when the scribe lane area SLA is cut to separate the chip areas CHA from each other.

[0047] FIG. 5A to FIG. 5F are views illustrating various layouts of a chip protection member according to an embodiment of the present disclosure.

[0048] although Figure 2 , FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4D The first chip protection member GD1 having a width gradually alternating between the first width W1 and the second width W2 is illustrated, but the chip protection member according to the present disclosure may be formed to have various layouts in addition to the layout of the first chip protection member GD1. Figure 2 similar, FIG. 5A to FIG. 5F It can also be understood that only a portion of the chip protection member formed in a portion of the protection area GDA is illustrated. According to the present disclosure, in order to explain various shapes of the chip protection members, they are respectively referred to as the first chip protection member GD1 to the fourth chip protection member GD4. However, the first chip protection member GD1 to the fourth chip protection member GD4 can be understood to correspond to various examples of the chip protection member.

[0049] Reference Figure 3A , the first chip protection member GD1 may be formed by first openings OP1 having substantially the same planar shape and area and arranged in one direction. However, the scope of the present disclosure is not limited to the first chip protection member GD1. For example, a portion of the chip protection member (eg, Figure 5A The second chip protection component GD2, Figure 5B The third chip protection part GD3 and Figure 5C The fourth chip protection member GD4 of the embodiment may have a width greater than or equal to the first width W1 and less than or equal to the second width W2, and another portion may have a width greater than or equal to the first width W1 and less than or equal to the third width W3 (for Figure 5A)、W3'(for Figure 5B ) or W3" (for Figure 5C ) width. The third widths W3, W3' and W3" may be greater than the second width W2. In addition to the first openings OP1 having the same planar shape and area and being arranged in one direction, Figure 2 , FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4D The information of the first chip protection member GD1 described in the Figure 5A The second chip protection component GD2, Figure 5B The third chip protection element GD3 and Figure 5C The fourth chip protection member GD4.

[0050] Reference Figure 5A , a portion of the second chip protection member GD2 may have a width within a range from the first width W1 to the second width W2, and another portion may have a width within a range from the first width W1 to the third width W3. The second chip protection member GD2 may be formed in a second opening OP2' in which the first openings OP1a and OP1b are extended to be connected. The first openings OP1a and OP1b may include a first type opening OP1a and a second type opening OP1b. In a plan view, the first type opening OP1a may have a first area, and the second type opening OP1b may have a second area larger than the first area. For example, the area of ​​the opening may mean a cross-sectional area of ​​the opening at any position on the Z axis.

[0051] For example, a portion of the stack of the protection area GDA may be etched to form a first type opening OP1a and a second type opening OP1b. The first type opening OP1a and the second type opening OP1b may be arranged to be spaced apart from each other along the X direction. The plane of each first type opening OP1a may have a circular shape of a first size, and the plane of each second type opening OP1b may have a circular shape of a second size. The second size may be larger than the first size. The first type opening OP1a and the second type opening OP1b may have a regularly repeated pattern. For example, a certain number (e.g., three) of the first type openings OP1a may be arranged between the second type openings OP1b. The distance between consecutive second type openings OP1b may be 100nm to 10um.

[0052] Subsequently, the first openings OP1a and OP1b may be expanded to be connected to each other. Thus, a second opening OP2' including the expanded first openings OP1a and OP1b may be formed. In the first region corresponding to the first type opening OP1a, the second opening OP2' may have a width ranging from the first width W1 to the second width W2. In addition, in the second region corresponding to the second type opening OP1b, the second opening OP2' may have a width ranging from the first width W1 to the third width W3. The second chip protection member GD2 may be formed by filling the second opening OP2' with an insulating material.

[0053] Reference Figure 5B , a portion of the third chip protection member GD3 may have a width within a range from the first width W1 to the second width W2, and another portion may have a width within a range from the first width W1 to the third width W3'. The third chip protection member GD3 may be formed in a second opening OP2" in which the first openings OP1a and OP1c are extended to be connected. The first openings OP1a and OP1c may include a first type opening OP1a and a second type opening OP1c. In a plan view, the first type opening OP1a may have a circular shape of a first area, and each second type opening OP1c may have an elliptical shape of a second area. In addition to the cross-sectional shape of each second type opening OP1c, with respect to the reference Figure 5A The information of the second type opening OP1b, the second opening OP2' and the third width W3 described above can also be applied to Figure 5B The second type opening OP1c, the second opening OP2″ and the third width W3′.

[0054] Reference Figure 5C , a portion of the fourth chip protection member GD4 may have a width within a range from the first width W1 to the second width W2, and another portion may have a width within a range from the first width W1 to the third width W3". The fourth chip protection member GD4 may be formed in the second opening OP2"' in which the first opening OP1a is extended to be connected. In a plan view, the first opening OP1a may have a circular shape of a first area.

[0055] Unlike the second type openings OP1b and OP1c formed between the first type openings OP1a when forming the second chip protection member GD2 and the third chip protection member GD3, the second type openings OP1b and OP1c may not be formed when forming the fourth chip protection member GD4. For example, the fourth chip protection member GD4 may be formed using the first openings OP1a having the same cross-sectional shape and cross-sectional area. Instead of forming the second type openings OP1b and OP1c, a plurality of first openings OP1a may be formed in a direction perpendicular to the direction in which the fourth chip protection member GD4 extends. For example, referring to Figure 5C , between the first openings OP1 a arranged along the X direction, a pair of first openings OP1 a may be formed side by side along the Y direction.

[0056] In addition to the fact that the second type openings OP1b are not formed and the positions where some of the first type openings OP1a are arranged are different, with respect to the reference Figure 5A The information of the first opening OP1a, the second opening OP2' and the third width W3 described above can also be applied to Figure 5C The first opening OP1a, the second opening OP2″ and the third width W3″ are formed.

[0057] like FIG. 5A to FIG. 5C exemplified in , and Figure 2 Compared with the first chip protection member GD1 illustrated in the figure, the second chip protection member GD2 to the fourth chip protection member GD4 may have widths corresponding to various values. For example, while the first chip protection member GD1 may have a width in the range from the first width W1 to the second width W2, the second chip protection member GD2 may have a width in the range from the first width W1 to the third width W3. In addition, compared with the planar shape of the first chip protection member GD1, the second chip protection member GD2 to the fourth chip protection member GD4 may have a planar shape in which the length of the repeated pattern is longer. For example, the period of shape repetition of the first chip protection member GD1 may correspond to the distance between the centers of adjacent first openings OP1 among the first openings OP1. On the other hand, the period of shape repetition of the second chip protection member GD2 may correspond to the distance between the centers of adjacent continuous second type openings OP1b among the second type openings OP1b with the first type opening OP1a therebetween.

[0058] When the first openings OP1a, OP1b, and OP1c are formed to have various shapes or areas in a plan view, the performance of the chip protection member (e.g., the second chip protection member GD2 to the fourth chip protection member GD4) can be improved. For example, as the pattern of the width of the chip protection member (e.g., the second chip protection member GD2 to the fourth chip protection member GD4) becomes more complex, the chip protection member can more effectively prevent cracks from propagating from the outside of the chip area CHA.

[0059] Reference Figure 5D , at least two chip protection members (e.g., first chip protection member GD1 to fourth chip protection member GD4) may be disposed around one chip region CHA. At least two chip protection members (e.g., first chip protection member GD1 to fourth chip protection member GD4) may surround one chip region CHA. For example, the second chip protection member GD2 may be disposed to surround the chip region CHA, and the first chip protection member GD1 may be disposed to surround the chip region CHA and the second chip protection member GD2.

[0060] For example, a first opening group OPG1 including openings arranged along the X direction may be formed in the protection area GDA. In addition, a second opening group OPG2 arranged around the first opening group OPG1 may be formed in the protection area GDA. The openings of the first opening group OPG1 may be spaced apart from the openings of the second opening group OPG2. The openings included in the first opening group OPG1 may be coupled to each other, and the openings included in the second opening group OPG2 may be coupled to each other. Figure 5D The second chip protection member GD2 may be formed in a region where the openings of the first opening group OPG1 are connected to each other. Figure 5D The first chip protection member GD1 may be formed in a region where the openings of the second opening group OPG2 are coupled to each other.

[0061] When two chip protection members surround one chip area CHA, the two chip protection members may be of the same type (e.g., at least two first chip protection members GD1) or of different types (e.g., a first chip protection member GD1 and a second chip protection member GD2). In addition, when more than three chip protection members surround one chip area CHA, two or more chip protection members may be of the same type, and the other chip protection members may be chip protection members of different types. For example, referring to Figure 5E , two first chip protection members GD1 and two second chip protection members GD2 may be located around one chip area CHA.

[0062] Reference Figure 5D and Figure 5E The chip protection member (e.g., the first chip protection member GD1 to the fourth chip protection member GD4) may be formed to surround any one chip region CHA at least twice. When the chip region CHA is surrounded by the chip protection member at least twice, the chip protection member may more effectively protect the chip region CHA, compared to the case where the chip protection member (e.g., the first chip protection member GD1 to the fourth chip protection member GD4) surrounds only once.

[0063] In addition, according to the present disclosure, after forming the hole-shaped first openings OP1, OP1a, OP1b and OP1c, the first openings OP1, OP1a, OP1b and OP1c can be expanded to form line-shaped second openings OP2, OP2', OP2", and OP2'". Therefore, since the method of arranging the hole-shaped first openings OP1, OP1a, OP1b and OP1c can be easily changed, the number or shape of the chip protection parts can be easily adjusted during the design process of the semiconductor device.

[0064] Reference Fig. 5F , any chip protection member may have different shapes depending on its location. For example, in the protection area GDA located above and below the chip area CHA, the chip protection member may have the same shape as Figure 5B In addition, in the protection area GDA located on the left and right sides of the chip area CHA, the chip protection member may have a shape similar to that of the third chip protection member GD3. Figure 2 The shape of the first chip protection member GD1 is similar to the shape of FIG.

[0065] FIG. 5A to FIG. 5F The layout of the chip protection member illustrated in the figure corresponds to some embodiments included in the scope of the present disclosure, and other embodiments are also possible. For example, in a plan view, the first openings OP1, OP1a, OP1b, and OP1c may have various shapes such as a circle, an ellipse, or a square with rounded corners. Alternatively, there may be at least three types of first openings OP1, OP1a, OP1b, and OP1c corresponding to one chip protection member. That is, as long as the chip protection member is formed by forming first openings spaced apart from each other and then forming a second opening by expansion and connection of the first openings, it may fall within the scope of the present disclosure.

[0066] Figure 6 is a view illustrating the structure of a chip protection member and a slit according to an embodiment of the present disclosure. Figure 6 In the configurations shown, the following may be briefly described or omitted: Figure 2 Example configuration.

[0067] Reference Figure 6 , the chip area CHA may include a memory area MMA. The memory area MMA may be formed in the chip area CHA. The 3D NAND memory cell may be formed in the memory area MMA. The slit area STA may be located around the memory area MMA. The slit area STA may be arranged adjacent to the memory area MMA. For example, the slit area STA may surround at least a portion of a corner of the memory area MMA.

[0068] The cell plugs CPL may be located in the memory area MMA. The cell plugs CPL may be arranged in the memory area MMA along the X direction and the Y direction. Each cell plug CPL may extend along the Z direction. Each cell plug CPL may penetrate at least a portion of the structure STR.

[0069] The slit (e.g., the first slit ST1) may be located in the slit area STA. The slit (e.g., the first slit ST1) may include an insulating material. The slit (e.g., the first slit ST1) may separate the memory area MMA from other memory areas. For example, a word line of the memory area MMA may be electrically separated from a word line of another memory area by the slit (e.g., the first slit ST1). Although Figure 6 Only a portion of the shape of the slit (eg, the first slit ST1 ) is illustrated, but it should be understood that the slit (eg, the first slit ST1 ) also extends in the direction in which the slit area STA extends.

[0070] The slit (e.g., first slit ST1) formed in the slit area STA may have a shape similar to that of the chip protection member (e.g., first chip protection member GD1) formed in the protection area GDA. For example, the slit (e.g., first slit ST1) may have a planar shape similar to that of the first chip protection member GD1. In another example, the slit may have a planar shape similar to that of the first chip protection member GD1. FIG. 5A to FIG. 5F Since the chip protection member (e.g., the first chip protection member GD1) is formed in the protection area GDA while the slit (e.g., the first slit ST1) is formed in the slit area STA, the shapes of the slit (e.g., the first slit ST1) and the chip protection member (e.g., the first chip protection member GD1) may be similar. 7A to 7E A method of forming a chip protection member (eg, first chip protection member GD1 ) and a slit (eg, first slit ST1 ) will be described.

[0071] 7A to 7E is a view illustrating a method of simultaneously forming a chip protection member and a slit according to one embodiment of the present disclosure. 7A to 7E It is along Figure 6 A cross-sectional view taken along line CC' and a corresponding plan view.

[0072] Reference Fig. 7A , a stacked body in which the first material layer M1 and the second material layer M2 are alternately stacked may be formed in the protection area GDA and the slit area STA. The first material layer M1 and the second material layer M2 may be alternately stacked with the reference Figure 4A The first material layer M1 and the second material layer M2 described are the same.

[0073] The first opening OP1 may be formed in the protection area GDA, and the third opening OP3 may be formed in the slit area STA. A portion of the stacked body of the protection area GDA may be etched to form the first opening OP1. In addition, a portion of the stacked body of the slit area STA may be etched to form the third opening OP3. The process of etching the stacked body of the protection area GDA and the process of etching the slit area STA of the chip area CHA may be performed simultaneously. In order to form the first opening OP1 and the third opening OP3 at designated positions of the protection area GDA and the slit area STA, an anisotropic dry etching process may be performed.

[0074] Each of the first opening OP1 and the third opening OP3 may pass through a stack in which the first material layer M1 and the second material layer M2 are alternately stacked. In addition, the first opening OP1 and the third opening OP3 may be arranged along the X direction or along the Y direction. The first opening OP1 may be arranged to be spaced apart from each other. The third opening OP3 may be arranged to be spaced apart from each other. The first opening OP1 and the third opening OP3 may be arranged to be spaced apart from each other. The planar area of ​​the first opening OP1 and the planar area of ​​the third opening OP3 (i.e., the area of ​​the opening in the plan view) may be formed differently. For example, the planar area of ​​the first opening OP1 may be formed to be larger than the planar area of ​​the third opening OP3. In another example, the first opening OP1 and the third opening OP3 may be formed to have substantially the same planar area.

[0075] Reference Figure 7B , the first opening OP1 may be expanded to form the second opening OP2, and the third opening OP3 may be expanded to form the fourth opening OP4. The process in which the first opening OP1 is expanded to be connected to each other and the process in which the third opening OP3 is expanded to be connected to each other may be performed simultaneously. For example, when the inner wall of the first opening OP1 is etched through the first opening OP1, the inner wall of the third opening OP3 may be etched simultaneously through the third opening OP3. As the third opening OP3 is expanded, the third openings OP3 may be connected to each other. The portion of the fourth opening OP4 at CC' may have the shape of a line extending in the Y direction. The fourth opening OP4 may include the third opening OP3 that is expanded and connected to each other. An isotropic wet etching process may be performed to form the second opening OP2 by expanding and connecting the first opening OP1 and to form the fourth opening OP4 by expanding and connecting the third opening OP3. For example, a hard mask may be formed to expose the protection area GDA and the slit area STA, and an isotropic wet etching process may be performed on the portion of the protection area GDA exposed by the hard mask and the portion of the slit area STA exposed by the hard mask.

[0076] Reference Figure 7C, the second material layer M2 may be removed through the second opening OP2 and the fourth opening OP4. The second material layer M2 exposed through the second opening OP2 and the fourth opening OP4 may be etched. Since the second material layer M2 is formed of a material having an etching selectivity different from that of the first material layer M1, the second material layer M2 may be selectively removed. An isotropic wet etching process may be performed to selectively remove the second material layer M2.

[0077] As the second material layer M2 is removed, a second recess RC2 may be formed between the first material layers M1. The second opening OP2 and the fourth opening OP4 may be used as a channel for introducing an etchant for removing the second material layer M2. In addition, the second opening OP2 and the fourth opening OP4 may be used as a channel for removing the etched second material layer M2.

[0078] Reference Fig.7D , the second recess RC2 may be filled with the third material layer M3. The third material layer M3 may fill the second recess RC2 through the second opening OP2 and the fourth opening OP4. The second opening OP2 and the fourth opening OP4 may be used as a channel for introducing the third material layer M3. The third material layer M3 formed adjacent to the second opening OP2 and the third material layer M3 formed adjacent to the fourth opening OP4 may include the same material. The third material layer M3 may include a conductive layer. For example, the third material layer M3 may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si). At least some of the third material layer M3 may be used as a gate electrode. For example, the third material layer M3 formed in the memory area MMA may be used as a word line or a select line.

[0079] Reference Fig. 7E , a chip protection member (e.g., a first chip protection member GD1) may be formed in the second opening OP2, and a slit (e.g., a first slit ST1) may be formed in the fourth opening OP4. The inside of the second opening OP2 and the inside of the fourth opening OP4 may be filled with an insulating material at the same time. The chip protection member (e.g., the first chip protection member GD1) and the slit (e.g., the first slit ST1) may be formed at the same time. Therefore, the chip protection member (e.g., the first chip protection member GD1) and the slit (e.g., the first slit ST1) may include the same material.

[0080] Reference 7A to 7ESince the memory areas MMA are separated from each other and the gate electrode (e.g., the third material layer M3) is formed during the process of forming the chip protection member (e.g., the first chip protection member GD1), the manufacturing process of the semiconductor device can be simplified. Therefore, the cost and time required to manufacture the semiconductor device including the chip protection member (e.g., the first chip protection member GD1) and the slit (e.g., the first slit ST1) according to the present disclosure can be reduced.

[0081] Figure 8 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied.

[0082] Reference Figure 8 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0083] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200 or may control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In one embodiment, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0084] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. For example, the controller 3100 can communicate with an external device through at least one of the following communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, Non-Volatile Memory Express (NVMe), etc. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0085] The memory device 3200 may include a plurality of memory cells.

[0086] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device and then may form a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, mini SD, micro SD or SDHC), and a Universal Flash Storage (UFS).

[0087] Fig. 9 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0088] Reference Fig. 9 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0089] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In one embodiment, the signal may indicate a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, Non-Volatile Memory Express (NVMe), etc.

[0090] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells storing data. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0091] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a power supply voltage from the host 4100 and may be charged. When the power supply from the host 4100 is not performed smoothly, the auxiliary power supply 4230 may provide a supply voltage of the SSD 4200. For example, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on a mainboard and may also provide auxiliary power to the SSD 4200.

[0092] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0093] According to the present disclosure, a process of forming a chip protection member is improved, thereby simplifying the process of forming the chip protection member and improving the performance of the chip protection member.

[0094] CROSS-REFERENCE TO RELATED APPLICATIONS

[0095] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0148866, filed on November 1, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a stacked body in which first material layers and second material layers are alternately stacked, wherein the stacked body is formed in a chip region and a protection region, wherein the protection region is adjacent to the chip region; forming a plurality of first openings through the stack of layers in the protection region, the plurality of first openings being spaced apart from one another; forming a second opening from the plurality of first openings by expanding each of the plurality of first openings so that the plurality of first openings are coupled to each other; and A chip protection member is formed by filling the second opening with an insulating material.

2. The method according to claim 1, in, The first openings are formed in the shape of holes spaced apart from each other along a first direction, and The second opening is formed in a line shape extending along the first direction.

3. The method according to claim 1, wherein: The protection area surrounds the chip area, and The step of forming the plurality of first openings includes etching a portion of the stacked body in the protection region surrounding the chip region.

4. The method according to claim 1, wherein: The step of forming the second openings includes etching the stacked body exposed through each of the first openings.

5. The method according to claim 4, wherein: The step of etching the stacked body comprises: forming a plurality of first recesses by removing at least a portion of each of the first material layers exposed through each of the plurality of first openings; and The second opening is formed by removing at least a portion of each of the second material layers exposed through each of the plurality of first openings and each of the plurality of first recesses.

6. The method according to claim 1, wherein: The step of forming the second opening includes coupling the plurality of first openings to each other by removing a portion of the stacked body between adjacent first openings among the plurality of first openings in the stacked body.

7. The method according to claim 1, wherein: The step of forming the second opening includes etching a portion of the stacked body so that the second opening has a width ranging from a first width to a second width, the second width being larger than the first width.

8. The method according to claim 1, wherein: The step of forming the plurality of first openings comprises: forming a plurality of first type openings having a first area in plan view; and A plurality of second type openings having a second area in the plan view are formed, the second area being larger than the first area.

9. The method according to claim 8, wherein: The step of forming the plurality of first type openings and the plurality of second type openings includes etching a portion of the stacked body to have a pattern including a regularly repeated combination of the plurality of first type openings and at least one second type opening.

10. The method according to claim 8, wherein: The step of forming the first type opening includes forming the first type opening in a circular shape having the first area in the plan view.

11. The method according to claim 8, wherein: The step of forming the second type opening includes forming the second type opening in a circular shape or an elliptical shape having the second area in the plan view.

12. The method according to claim 8, wherein: The step of forming the second type openings includes forming the second openings having a width ranging from a first width to a second width in a first region corresponding to the plurality of first type openings and having a width ranging from the first width to a third width in a second region corresponding to the plurality of second type openings, and The second width is greater than the first width, and the third width is greater than the second width.

13. The method according to claim 1, wherein: The step of forming the plurality of first openings includes: forming a first opening group and a second opening group, the first opening group including a plurality of openings arranged along a first direction in the protection area, the second opening group including a plurality of openings arranged along the first direction and spaced apart from the plurality of openings of the first opening group in a second direction, the second direction intersecting the first direction.

14. The method according to claim 13, wherein: The step of forming the second opening comprises: coupling the plurality of openings included in the first opening group to each other; and The plurality of openings included in the second opening group are coupled to each other.

15. The method according to claim 1, wherein: Forming the plurality of first openings is performed simultaneously with forming a plurality of third openings penetrating the laminated body in the chip region, the plurality of first openings being spaced apart from the plurality of third openings.

16. The method according to claim 15, wherein: Forming the second opening is performed simultaneously with forming a fourth opening from the plurality of third openings by expanding each of the plurality of third openings such that the plurality of third openings are coupled to each other in the chip region.

17. The method according to claim 16, further comprising the steps of: After forming the second opening and the fourth opening, forming a plurality of second recesses by removing a plurality of the second material layers exposed through the second opening and the fourth opening; as well as The plurality of second recesses are filled with a plurality of third material layers.

18. The method according to claim 17, wherein: Forming the chip protection member is performed simultaneously with forming a slit by filling the fourth opening with the insulating material.

19. A semiconductor device, comprising: Chip area; as well as a chip protection member, the chip protection member being adjacent to the chip area, At least a portion of the chip protection component has a width ranging from a first width to a second width, and the second width is greater than the first width.

20. The semiconductor device according to claim 19, wherein The width of the chip protection member gradually alternates between the first width and the second width, and Wherein, the chip protection component surrounds the chip area.

21. The semiconductor device according to claim 19, in, The first region of the chip protection member has a width ranging from the first width to the second width, and The second region of the chip protection component has a width ranging from the first width to a third width, and the third width is greater than the second width.

22. The semiconductor device according to claim 19, wherein In a plan view, at least a portion of the chip protection member is in a line shape extending in a first direction and has a curved boundary curved in a second direction and a direction opposite to the second direction, the second direction intersecting the first direction.

23. The semiconductor device according to claim 19, wherein At least a portion of the chip protection member has a shape in which holes arranged along the first direction are expanded and coupled to each other.

Images