Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a to-be-processed structure comprising a wafer substrate; arranging a first composite layer on the first surface of the to-be-treated structure; arranging a buffer layer on the first composite layer; and arranging a metal film on the buffer layer to obtain the semiconductor structure. Before the metal film is arranged, the buffer layer is arranged on the first composite layer, and the metal film grows on the buffer layer, so that the grain size of the metal film obtained through growth is reduced, and the tensile stress generated on the wafer substrate after the metal film grows is reduced; therefore, the influence of the growth of the metal film on the warping degree of the wafer substrate can be reduced, the adsorption and movement effects of the vacuum chuck on the wafer substrate are ensured, the probability of error reporting and shutdown is reduced, and the normal production efficiency of the subsequent technological process of the wafer substrate is improved; and meanwhile, by setting the thickness of the buffer layer, the control of the buffer layer on the tensile stress generated by the metal film is optimized, and the warping degree of the wafer substrate is minimized.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a semiconductor structure and a preparation method thereof. Background Art

[0002] The fabrication of semiconductor integrated circuits requires multiple processes on wafers to create various circuit component structures. During this process, the temperature conditions required for different processes can cause stress changes between the wafer and adjacent structural layers with different thermal expansion coefficients. This stress can cause wafer warping.

[0003] The greater the degree of wafer warping, the greater the deformation, and the wafer deformation will have an adverse effect on subsequent process steps, such as increasing the alarm frequency of the wafer in the machine, and even causing defects such as wafer cracks and wafer breakage, thereby reducing production yield; at the same time, when the wafer warping is too large, the vacuum suction cup used to adsorb the wafer surface will find it difficult to effectively and reliably adsorb the warped wafer surface, making it impossible to effectively transfer, move, and other operations on the wafer, resulting in the inability to carry out the process, greatly reducing production efficiency, and even affecting the normal progress of subsequent processes.

[0004] Therefore, there is an urgent need for a structure or method that can reduce wafer warpage.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0006] In view of the above shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, so as to solve the problem of large wafer warpage in the prior art.

[0007] To achieve the above object, the present invention provides a method for preparing a semiconductor structure, the method comprising:

[0008] Providing a structure to be processed, wherein the structure to be processed includes a wafer substrate;

[0009] Disposing a first composite layer on the first surface of the structure to be processed;

[0010] providing a buffer layer on the first composite layer;

[0011] A metal film is disposed on the buffer layer to obtain the semiconductor structure.

[0012] Optionally, the material of the wafer substrate is silicon.

[0013] Optionally, the structure to be processed further includes a TEOS layer, and the TEOS layer is located between the wafer substrate and the first composite layer.

[0014] Optionally, the material of the first composite layer is Ti / TiN.

[0015] Optionally, the buffer layer is made of titanium, and the metal film is made of aluminum.

[0016] Optionally, the buffer layer has a thickness of 80 angstroms to 120 angstroms.

[0017] Optionally, the preparation method further comprises: after providing the metal film, providing a second composite layer on the metal film to obtain the semiconductor structure.

[0018] Optionally, the preparation method further comprises: after providing the second composite layer, patterning the obtained structure so that the bottom surface of the groove formed by patterning is not higher than the bottom surface of the metal film.

[0019] Optionally, the preparation method further includes: after setting the second composite layer, setting an anti-reflective coating on the second composite layer; setting a photoresist on the anti-reflective coating; exposing and developing the photoresist to obtain a patterned photoresist; and using the patterned photoresist as a mask to perform patterned etching on the structure after setting the anti-reflective coating.

[0020] The present invention also provides a semiconductor structure, which is obtained by any of the above-mentioned preparation methods. The semiconductor structure comprises, from bottom to top, a wafer substrate, a first composite layer, a buffer layer, and a metal film.

[0021] As described above, the semiconductor structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0022] The present invention provides a buffer layer on the first composite layer before providing the metal film, so that the metal film grows on the buffer layer instead of the first composite layer, thereby reducing the grain size of the grown metal film and reducing the tensile stress generated by the metal film on the wafer substrate after growth, thereby reducing the warpage effect of the growing metal film on the wafer substrate, ensuring the vacuum chuck's adsorption and movement effect on the wafer substrate, reducing the probability of error reporting and shutdown, and improving the production efficiency of the subsequent process flow of the wafer substrate.

[0023] The present invention optimizes the control of the tensile stress generated by the buffer layer on the metal film by setting the thickness of the buffer layer, thereby minimizing the warping of the wafer substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram showing the structure of the wafer warping when subjected to tensile stress of the upper structural layer in the prior art.

[0025] Figure 2 It is a schematic diagram showing the structure of the wafer warping when it is subjected to compressive stress from the upper structural layer in the prior art.

[0026] Figure 3 It shows a schematic structural diagram of the structure to be processed in step 1 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0027] Figure 4 It shows a schematic structural diagram of providing a first composite layer in step 2 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0028] Figure 5 It is a schematic structural diagram showing the provision of a buffer layer in step 3 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0029] Figure 6 It shows a schematic structural diagram of growing a metal thin film on a first composite layer in the prior art.

[0030] Figure 7 It shows a schematic structural diagram of the metal film provided in step 4 of the method for preparing the semiconductor structure according to embodiment 1 of the present invention.

[0031] Figure 8 It is a schematic structural diagram showing the arrangement of a second composite layer in an example of step 4 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0032] Figure 9 It is a schematic structural diagram showing a structure obtained by patterning in an example of step 4 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0033] Figure 10 It is a schematic structural diagram showing the provision of an anti-reflection coating in an example of step 4 of the method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0034] Figure 11 Shown is a schematic structural diagram of a patterned photoresist obtained in step 4 of an example of a method for preparing a semiconductor structure according to embodiment 1 of the present invention.

[0035] Figure 12 It shows a schematic diagram of the structure of the patterned photoresist obtained in the prior art.

[0036] Figure 13 It shows a schematic structural diagram of a wafer substrate after a metal thin film is provided on the wafer substrate using the preparation method in Example 1 of the present invention.

[0037] Figure 14 It shows a schematic diagram of the structural warping of a wafer substrate after a metal film is provided on the wafer substrate using the conventional preparation method.

[0038] Figure 15 It shows a schematic structural diagram of the semiconductor structure in Example 2 of the present invention.

[0039] Explanation of Figure Numbers

[0040] 11. Wafer; 12. Structural layer thin film material;

[0041] 21. Wafer substrate; 22. TEOS layer; 23. First composite layer; 24. Buffer layer; 25. Metal film; 26. Second composite layer; 27. Groove; 28. Anti-reflective coating; 29. ​​Photoresist. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0044] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0045] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0047] In the current manufacturing process of semiconductor integrated circuits, the temperature conditions required for each link are different. The specific temperature environment required by these different process steps often leads to inevitable stress changes between the wafer and its adjacent structural layer film material 12 with different thermal expansion coefficients during the heating process. The generation of this stress is mainly due to the inconsistent expansion degree of the wafer and the structural layer film material 12 when heated, which in turn causes the accumulation of internal stress. The existence of this internal stress will directly cause the wafer 11 to undergo the following Figure 1-Figure 2 The warping, Figure 1 Indicates the warping of the wafer 11 when subjected to tensile stress. Figure 2 Indicates the warping of the wafer when it is subjected to compressive stress. The greater the degree of wafer warping, the greater the amplitude of its deformation will be. This deformation of the wafer will bring a series of adverse effects on the subsequent process. For example, during the processing of the wafer in the machine, the alarm frequency may increase significantly due to warping deformation, which will affect the smoothness of the production process. When the wafer is severely warped, it may also cause cracks on the wafer surface and even cause serious defects such as wafer breakage. These problems will directly lead to a decrease in production yield. In addition, when the warping of the wafer exceeds a certain limit, it will be difficult for the vacuum suction cup to achieve effective and reliable adsorption of the warped wafer surface during the adsorption operation. This will undoubtedly greatly reduce the efficiency and accuracy of the wafer operation, and hinder the subsequent process steps, making the entire production process unable to proceed normally, thereby affecting the efficiency of the entire production line. The present invention provides the following solution for solving the problem of wafer warping to improve product yield and production efficiency.

[0048] Example 1:

[0049] This embodiment provides a method for preparing a semiconductor structure, the method comprising:

[0050] Step 1: providing a structure to be processed, wherein the structure to be processed includes a wafer substrate;

[0051] Step 2: providing a first composite layer on the first surface of the structure to be processed;

[0052] Step 3: Disposing a buffer layer on the first composite layer;

[0053] Step 4: Disposing a metal film on the buffer layer to obtain the semiconductor structure.

[0054] The preparation method of the semiconductor structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the semiconductor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0055] First, proceed to step 1, such as Figure 3 As shown, a structure to be processed is provided, and the structure to be processed includes a wafer substrate 21 .

[0056] Specifically, the wafer substrate 21 can be a substrate material of various semiconductor structures, and can be a single material or a composite material. Those skilled in the art can select according to their needs, and all are within the scope of protection of the present invention.

[0057] In one embodiment, Figure 3 As shown, the structure to be processed further includes a TEOS layer 22 , and the TEOS layer 22 is located between the wafer substrate 21 and the first composite layer 23 .

[0058] In this embodiment, the wafer substrate 21 of the structure to be processed including the TEOS layer 22 includes silicon elements.

[0059] The present invention provides a TEOS (tetraethoxysilane) layer on the wafer substrate 21 of the structure to be processed. This TEOS layer 22 can serve as a silicon source during the CVD (Chemical Vapor Deposition) process to efficiently form a uniform and dense SiO2 (silicon dioxide) film on the wafer substrate 21. The resulting silicon dioxide film has excellent insulation properties, effectively isolating different circuit components on the wafer substrate 21, preventing mutual interference between electrical signals, and ensuring the stability and reliability of the circuit system. Furthermore, the silicon dioxide film formed by the TEOS layer 22 also has good adhesion properties, which can significantly improve the surface quality of the wafer substrate 21, allowing subsequent process steps to be performed on a smoother and more stable surface. Furthermore, if a subsequent photolithography process is performed, the silicon dioxide film formed by the TEOS can also act as an anti-reflective film, effectively reducing light reflection on the wafer surface, thereby significantly improving the resolution and imaging effect during the photolithography process and ensuring the accuracy and clarity of the photolithographic pattern. Finally, the silicon dioxide film formed by the TEOS layer 22 also has a certain protective function. It can serve as a strong protective layer to protect the structures formed below the TEOS layer 22 from physical or chemical damage that may occur in subsequent process steps, thereby ensuring the smooth progress of the entire manufacturing process and the quality of the final product.

[0060] In one embodiment, other suitable structures may be provided between the TEOS layer 22 and the wafer substrate 21 , all of which are within the protection scope of the present invention.

[0061] Then, proceed to step 2, such as Figure 4 As shown, a first composite layer 23 is provided on the first surface of the structure to be processed.

[0062] In one embodiment, the material of the first composite layer 23 is Ti / TiN.

[0063] Specifically, the Ti layer in the first composite layer 23 acts as an adhesion layer, which can improve the adhesion between the metal film 25 and the wafer substrate 21 to ensure the firm adhesion of the metal film 25 on the wafer substrate 21; and the TiN in the first composite layer 23 acts as a barrier layer, which can prevent the mutual diffusion between the metal film 25 and the surface of the structure to be processed. This diffusion may cause instability in electrical performance, so the presence of TiN helps to maintain the stability and reliability of the device; at the same time, TiN can also improve the electromigration phenomenon of Al. On a connection line with high current density and high frequency changes, the atoms in the metal film 25 may migrate, resulting in an open circuit, and the Ti ions in TiN can react with the metal ions in the metal film 25 to generate a very stable substance (such as TiAl3), which can effectively resist the electromigration phenomenon; in addition, TiN acts as an auxiliary layer of the metal film 25, which helps to improve the conductive and mechanical properties of the metal film 25.

[0064] Then, proceed to step 3, as Figure 5 As shown, a buffer layer 24 is provided on the first composite layer 23 .

[0065] The present invention provides a buffer layer 24 on the first composite layer 23 before providing the metal film 25, so that the metal film 25 grows on the buffer layer 24 instead of the first composite layer 23, which is similar to the above. Figure 6 As shown (the warped state of the wafer substrate 21 is not shown), compared with the metal film 25 directly grown on the first composite layer 23, the metal film 25 grown on the buffer layer 24 has smaller grains, thereby reducing the tensile stress on the wafer substrate 21 after the growth of the metal film 25, and reducing the influence of the warping of the wafer substrate 21 caused by the growing metal film 25, ensuring the vacuum suction cup's adsorption and movement effect on the wafer substrate 21, reducing the probability of error shutdown, and improving the production efficiency of the subsequent process flow of the wafer substrate 21.

[0066] Specifically, the materials of the buffer layer 24 and the metal film 25 can be selected according to the actual grown grains. As long as the grains of the metal film 25 grown on the buffer layer 24 are smaller than the grains of the metal film 25 grown on the first composite layer 23, thereby reducing the tensile stress on the wafer substrate 21, it is within the protection scope of the present invention.

[0067] Finally, proceed to step 4, such as Figure 7 As shown, a metal film 25 is disposed on the buffer layer 24 to obtain the semiconductor structure.

[0068] Preferably, the material of the buffer layer 24 is titanium, and the material of the metal film 25 is aluminum.

[0069] The present invention has proved through experiments that when the buffer layer 24 is titanium and the metal film 25 is aluminum, a more significant reduction effect on the tensile stress of the wafer substrate 21 can be achieved compared with other commonly used material combinations. Moreover, since this material combination is a commonly used combination in semiconductor structures, it can achieve excellent adhesion and strongly controlled grain orientation. In addition, by utilizing the lower surface energy of titanium, the overall film quality of the aluminum serving as the metal film 25 can be improved. At the same time, it adapts to existing processes and has low improvement costs.

[0070] Preferably, the wafer substrate 21 is made of silicon, the first composite layer 23 is made of Ti / TiN, the buffer layer 24 is made of titanium, and the metal film 25 is made of aluminum. This material combination achieves the best product yield and production efficiency in the design and experimental verification of this embodiment.

[0071] Specifically, other processes or preparation of structural layers may be added in some steps according to specific product or process requirements, all of which are within the scope of protection of the present invention.

[0072] Example 2:

[0073] This embodiment provides a method for preparing a semiconductor structure. Other features of the method are substantially the same as those of Embodiment 1, except that:

[0074] In this embodiment, the buffer layer 24 is made of titanium, and the thickness of the buffer layer 24 is 80 angstroms to 120 angstroms.

[0075] The present invention optimizes the control of the tensile stress generated by the buffer layer 24 on the metal film 25 by setting the thickness range of the buffer layer 24 , thereby minimizing the warpage of the wafer substrate 21 .

[0076] Example 3:

[0077] This embodiment provides a method for preparing a semiconductor structure. Other features of the method for preparing a semiconductor structure are substantially the same as those of Embodiment 1, except that:

[0078] In this embodiment, Figure 8 As shown, the preparation method further includes: after providing the metal film 25 , providing a second composite layer 26 on the metal film 25 to obtain the semiconductor structure.

[0079] In the present invention, the second composite layer 26 is provided on the metal film 25 to form a sandwich structure with the first composite layer 23 , thereby providing better protection for the metal film 25 .

[0080] Specifically, the second composite layer 26 can be provided or removed according to product and process requirements, which is within the scope of protection of the present invention.

[0081] In one embodiment, the material of the second composite layer 26 is Ti / TiN.

[0082] Specifically, the Ti included in the second composite layer 26 above the metal film 25 can improve the adhesion between the metal film 25 and the structural layer above. The TiN included in the second composite layer 26 has a high-density crystal structure, which can effectively prevent the upward diffusion of metal atoms in the metal film 25. Since metal diffusion may cause changes in electrical properties and device failure, the anti-diffusion effect of TiN can maintain the electrical performance and stability of the device. At the same time, TiN has a high absorption coefficient, especially in the ultraviolet light band, which can effectively reduce light reflection. During the photolithography process, reflected light from below the metal film 25 upward may cause a standing wave effect, thereby affecting the accuracy of the photolithographic pattern. The anti-reflection effect of TiN can improve the patterning accuracy of subsequent structures. In addition, TiN has a high hardness, which can enhance the mechanical strength of the overall structure, thereby improving the durability and reliability of the device. In addition, TiN has good conductivity and can form good electrical contact with the metal film 25, thereby ensuring low resistance and efficient current conduction of the circuit. Finally, the Ti / TiN layer above the metal film 25 can provide important protection and performance improvement for the semiconductor devices below the second composite layer 26.

[0083] In one embodiment, Figure 9 As shown, the preparation method further includes: after providing the second composite layer 26 , patterning the obtained structure so that the bottom surface of the patterned groove 27 is not higher than the bottom surface of the metal film 25 .

[0084] In one embodiment, the bottom surface of the patterned groove 27 is carved through the metal film 25 .

[0085] In one embodiment, the bottom surface of the patterned groove 27 not only carves through the metal film 25 but also partially etches away the first composite layer 23 as required.

[0086] Specifically, the depth of the patterning of the obtained structure can be set according to specific needs, all within the scope of protection of the present invention.

[0087] In one embodiment, the preparation method further comprises: after providing the second composite layer 26, Figure 10 As shown, an anti-reflective coating 28 is provided on the second composite layer 26; a photoresist 29 is provided on the anti-reflective coating 28; the photoresist 29 is exposed and developed to obtain a patterned photoresist 29, as shown in FIG. Figure 11 The structure shown, with Figure 12 Compared with the semiconductor structure obtained by setting the photoresist 29 in the structure of the prior art (the warping of the wafer substrate 21 is not shown), the warping of the wafer substrate 21 obtained by the present invention is greatly reduced; the structure after setting the anti-reflective coating 28 is patterned and etched using the patterned photoresist 29 as a mask.

[0088] In one embodiment, the anti-reflection coating 28 is made of SiON.

[0089] Specifically, the anti-reflection coating 28 may also be made of other suitable materials, all of which are within the protection scope of the present invention.

[0090] Specifically, the anti-reflective coating 28 is used to prevent deviations in patterning accuracy caused by light reflection during the photolithography process. When the size required for photolithography is larger or other methods are used for patterning, the anti-reflective coating 28 can be removed as needed.

[0091] Specifically, other suitable methods may also be used to pattern the obtained structure, all of which are within the scope of protection of the present invention.

[0092] Preferably, the material of the wafer substrate 21 is silicon, the material of the first composite layer 23 is Ti / TiN, the material of the buffer layer 24 is titanium, the material of the metal film 25 is aluminum, and the material of the second composite layer 26 is Ti / TiN. This material combination is the best combination for product yield and production efficiency obtained in the solution concept and experimental verification of the present invention. Figure 11 The Bow value of the wafer substrate 21 obtained by the structure shown is 33kAl~60-80 microns, which means that the warpage (WARP) of the wafer substrate 21 with a thickness of 330 microns is 60-80 microns when the aluminum metal layer is provided. Figure 12The Bow value of the wafer substrate 21 obtained by the structure shown is 33kAl~180 microns, and the warpage of the wafer substrate 21 is compared with Figure 13-14 (Other structures are omitted, only the wafer substrate 21 and the metal film 25 are retained), Figure 13 FIG. 2 is a schematic diagram showing the warping of the wafer substrate 21 after the metal film 25 is provided by the preparation method of the present invention. Figure 14 3 is a schematic diagram of the warping of the wafer substrate 21 after the metal film 25 is provided by the preparation method in the prior art. By comparison, it can be seen that the warping of the wafer substrate 21 obtained by the solution of the present invention is significantly reduced.

[0093] Example 4:

[0094] This embodiment provides a semiconductor structure, which is obtained by using any one of the semiconductor structure preparation methods in embodiments 1-3. Figure 15 As shown, the semiconductor structure includes, from bottom to top, a wafer substrate 21 , a first composite layer 23 , a buffer layer 24 and a metal film 25 .

[0095] In one embodiment, the semiconductor structure is an interconnect structure or an interconnect contact in a semiconductor device.

[0096] In one embodiment, the semiconductor structure is a conductive layer or an interconnect layer in an electronic package substrate.

[0097] In one embodiment, the semiconductor structure is located in a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device or a high-temperature semiconductor device.

[0098] In one embodiment, the semiconductor structure is an ohmic contact layer in a GaN-based semiconductor device. Specifically, due to the wide bandgap characteristics of GaN, it is difficult to directly form a low-resistivity ohmic contact. However, the semiconductor structure of the present invention can effectively reduce contact resistance and achieve good electrical performance. The semiconductor structure obtained using the preparation method of Example 1 can achieve a higher device yield, thereby further ensuring the electrical performance of the GaN-based semiconductor device.

[0099] In one embodiment, the semiconductor structure is an ohmic contact layer in a photodiode or a light emitting diode.

[0100] In one embodiment, the semiconductor structure is a sensitive element in a pressure sensor, which is used to achieve high-precision detection of pressure changes.

[0101] In one embodiment, the semiconductor structure is a contact layer of an electrode material in a temperature sensor.

[0102] Specifically, the semiconductor structure may also be located in other suitable semiconductor device structures, all of which are within the protection scope of the present invention.

[0103] In one embodiment, the material of the wafer substrate 21 is silicon, SiC or GaN, and the materials of the first composite layer 23, the buffer layer 24 and the metal film 25 can be set according to the requirements of the wafer substrate 21 and the semiconductor device where the semiconductor structure is located.

[0104] In one embodiment, the material of the wafer substrate 21 is silicon, the material of the first composite layer 23 is Ti / TiN, the material of the buffer layer 24 is titanium, and the material of the metal film 25 is aluminum.

[0105] In one embodiment, Figure 15 As shown, the semiconductor structure further includes a second composite layer 26 , and the second composite layer 26 is located on the metal film 25 .

[0106] In one embodiment, the material of the second composite layer 26 is Ti / TiN.

[0107] In one embodiment, Figure 15 As shown, a TEOS layer 22 is further included between the wafer substrate 21 and the first composite layer 23 .

[0108] In one embodiment, Figure 15 As shown, an anti-reflection coating 28 is provided on the second composite layer 26 .

[0109] In one embodiment, Figure 15 As shown, the semiconductor structure includes a groove 27 , and the groove 27 passes through the anti-reflection coating 28 , the second composite layer 26 and the metal film 25 .

[0110] Specifically, the bottom surface of the groove 27 is not higher than the bottom surface of the metal film 25 .

[0111] In one embodiment, Figure 15 As shown, the bottom surface of the groove 27 is located in the first composite layer 23 .

[0112] In summary, the semiconductor structure and preparation method thereof of the present invention can be achieved by setting a buffer layer on the first composite layer before setting the metal film, so that the metal film grows on the buffer layer instead of the first composite layer, thereby reducing the grain size of the grown metal film and reducing the tensile stress generated on the wafer substrate after the metal film grows, thereby reducing the effect of the grown metal film on the warping of the wafer substrate, ensuring the vacuum suction cup's adsorption and movement effect on the wafer substrate, reducing the probability of error shutdown, and improving the production efficiency of the subsequent process flow of the wafer substrate; at the same time, by setting the thickness of the buffer layer, the control of the tensile stress generated by the buffer layer on the metal film is optimized, and the warping of the wafer substrate is minimized.

[0113] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a structure to be processed, wherein the structure to be processed includes a wafer substrate; Disposing a first composite layer on a first surface of the structure to be processed; Disposing a buffer layer on the first composite layer; A metal film is disposed on the buffer layer to obtain the semiconductor structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the wafer substrate is silicon.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The structure to be processed further includes a TEOS layer, and the TEOS layer is located between the wafer substrate and the first composite layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the first composite layer is Ti / TiN.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The material of the buffer layer is titanium, and the material of the metal film is aluminum.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The buffer layer has a thickness of 80 angstroms to 120 angstroms.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further comprises: after providing the metal film, providing a second composite layer on the metal film to obtain the semiconductor structure.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further comprises: after the second composite layer is provided, patterning the obtained structure so that the bottom surface of the groove formed by patterning is not higher than the bottom surface of the metal film.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The preparation method also includes: after the second composite layer is provided, an anti-reflection coating is provided on the second composite layer; a photoresist is provided on the anti-reflection coating; the photoresist is exposed and developed to obtain a patterned photoresist; and the structure after the anti-reflection coating is provided is patterned and etched using the patterned photoresist as a mask.

10. A semiconductor structure, characterized in that: The semiconductor structure is obtained by the preparation method described in any one of claims 1 to 9, and the semiconductor structure comprises, from bottom to top, a wafer substrate, a first composite layer, a buffer layer and a metal film.

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