Bonding detection method, light-emitting diode and preparation method of light-emitting diode
By forming a detection groove on the surface of the epitaxial layer for bonding layer thickness detection, the product damage and high cost problems caused by FIB equipment detection are solved, and the detection efficiency and cost improvement are achieved.
Patent Information
- Application Number
- CN202411881878.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-05-06
AI Technical Summary
In the prior art, when using FIB equipment to detect the bonding layer thickness of the light emitting diode, the product needs to be cut, resulting in damage to the product, which is relatively high.
By forming a detection groove sequentially through the epitaxial layer and the bonding layer on the surface of the epitaxial layer, the detection is performed using the position where the detection groove is opened in the invalid area, thereby avoiding damage to the product.
The efficiency and cost reduction of bonded layer thickness detection are achieved, avoiding high costs of using FIB equipment and product damage.
Smart Images
Figure CN119943692A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a bonding detection method, a light emitting diode and a preparation method thereof. Background Art
[0002] Light Emitting Diode (LED) is a new product with great influence in the optoelectronics industry. Light Emitting Diode usually includes substrate, bonding layer and epitaxial layer. Among them, the bonding layer is located between the epitaxial layer and the substrate, and plays a key role in supporting the epitaxial layer. If the thickness of the bonding layer does not meet the design requirements, it will have an adverse effect on the size of the subsequent light emitting diode and the back-end use.
[0003] In the related art, a focused ion beam (FIB) device is usually used to detect the thickness of the bonding layer in the prepared product.
[0004] When using FIB equipment to inspect products, it is necessary to first cut the products to expose the bonding layer of the products so that the thickness of the bonding layer and other characteristics can be inspected. However, the FIB equipment will damage the products after cutting, making the products unusable. Therefore, the cost of using FIB equipment to inspect the bonding layer is high. Summary of the invention
[0005] The embodiments of the present disclosure provide a bonding detection method, a light-emitting diode and a method for manufacturing the same, which can improve the detection efficiency of the bonding layer and reduce the cost of detecting the bonding layer. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides a bonding detection method, which includes: providing a product, the product including a substrate, a bonding layer and an epitaxial layer stacked in sequence, the surface of the substrate including an effective area and an invalid area surrounding the effective area, and at least a part of the orthographic projection of the bonding layer on the substrate is located in the invalid area; forming a detection groove on the surface of the epitaxial layer that sequentially penetrates the epitaxial layer and the bonding layer, and detecting the thickness of the bonding layer through the detection groove, and the orthographic projection of the detection groove on the substrate is located in the invalid area.
[0007] Optionally, forming a detection groove on the surface of the epitaxial layer and sequentially penetrating the epitaxial layer and the bonding layer includes: forming a mask on the surface of the epitaxial layer, the mask having an etching opening exposing the epitaxial layer, the orthographic projection of the etching opening on the substrate being located in the invalid area; and etching the detection groove on the surface of the epitaxial layer through the etching opening.
[0008] Optionally, etching the detection groove on the surface of the epitaxial layer through the etching port includes: performing a first etching stage and a second etching stage in sequence on the surface of the epitaxial layer, and the etching power of the etching equipment during the first etching stage is greater than the etching power of the etching equipment during the second etching stage.
[0009] Optionally, when performing the first etching on the surface of the epitaxial layer, the upper power of the etching device is controlled to be 450W to 550W, and the lower power is controlled to be 200W to 300W; when performing the second etching, the upper power of the etching device is controlled to be 0W, and the lower power is controlled to be 50W to 150W.
[0010] Optionally, the duration of the first etching stage is 450s to 550s, and the duration of the second etching stage is 250s to 350s.
[0011] Optionally, the depth of the first etching section is less than or equal to 80% of the first thickness, and the first thickness is the sum of the thickness of the epitaxial layer and the thickness of the bonding layer; the depth of the second etching section is greater than or equal to 20% of the first thickness, and the sum of the depth of the first etching section and the depth of the second etching section is equal to the first thickness.
[0012] Optionally, forming a detection groove on the surface of the epitaxial layer and sequentially penetrating the epitaxial layer and the bonding layer includes: forming a plurality of the detection grooves on the surface of the epitaxial layer, and the plurality of the detection grooves are circumferentially spaced around the effective area.
[0013] In a second aspect, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the method comprising: providing a temporary substrate; forming an epitaxial layer and a bonding layer on the temporary substrate; bonding a substrate to the bonding layer, and removing the temporary substrate; using the bonding detection method as described above to detect the thickness of the bonding layer; if the thickness of the bonding layer meets the designed thickness, forming an electrode on the epitaxial layer.
[0014] In a third aspect, an embodiment of the present disclosure provides a light emitting diode, which is prepared by the light emitting diode preparation method as described above, and the light emitting diode includes a substrate, a bonding layer and an epitaxial layer stacked in sequence.
[0015] In another implementation of the present disclosure, the bonding layer includes a silicon oxide layer and a support column located in the silicon oxide layer, and the hardness of the support column is greater than the hardness of the silicon oxide layer.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0017] The bonding detection method provided by the embodiment of the present disclosure forms a detection groove on the surface of the epitaxial layer when detecting the thickness of the bonding layer, and the detection groove runs through the epitaxial layer and the bonding layer in sequence. That is, the position where the detection groove is opened is in the invalid area. The invalid area is a useless area on the product, which is not used to prepare light-emitting diodes, that is, the invalid area belongs to the waste part on the product. Therefore, forming a detection groove in the invalid area will not cause damage to the product, and will not affect the subsequent processing of the product into a light-emitting diode. In addition, during detection, it is only necessary to open a detection groove in the invalid area, so there is no need to use FIB equipment for detection, which can greatly reduce the detection cost and detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a flow chart of a bonding detection method provided by an embodiment of the present disclosure;
[0020] Figure 2 is a structural schematic diagram of a product provided by an embodiment of the present disclosure;
[0021] Figure 3 is a top view of a product provided by an embodiment of the present disclosure;
[0022] Figure 4 is a flow chart of another bonding detection method provided by an embodiment of the present disclosure;
[0023] Figure 5 It is a state diagram of opening a detection slot provided by an embodiment of the present disclosure.
[0024] The descriptions of the marks in the figure are as follows:
[0025] 10. substrate; 11. effective area; 12. ineffective area;
[0026] 20. bonding layer; 21. supporting column;
[0027] 30. epitaxial layer; 300. detection groove;
[0028] 31. first semiconductor layer; 32. active layer; 33. second semiconductor layer;
[0029] 41. Mask; 42. Etching opening;
[0030] 51. electrode; 52. welding point block;
[0031] 60. Passivation layer. DETAILED DESCRIPTION
[0032] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0033] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0034] Figure 1 FIG. 1 is a flow chart of a bonding detection method provided by an embodiment of the present disclosure. Figure 1 As shown, the bonding detection method includes:
[0035] Step 101: Provide a product.
[0036] Figure 2 Schematic diagram of a product provided by an embodiment of the present disclosure. Figure 2 As shown, the product includes a substrate 10, a bonding layer 20 and an epitaxial layer 30 which are stacked in sequence.
[0037] Figure 3 is a top view of a product provided by an embodiment of the present disclosure. Figure 3 As shown, the surface of the substrate 10 includes an active area 11 and an inactive area 12 surrounding the active area 11 , and at least a portion of the orthographic projection of the bonding layer 20 on the substrate 10 is located in the inactive area 12 .
[0038] Step 102 : forming a detection groove 300 on the surface of the epitaxial layer 30 and sequentially penetrating the epitaxial layer 30 and the bonding layer 20 , and detecting the thickness of the bonding layer 20 through the detection groove 300 .
[0039] The orthographic projection of the detection groove 300 on the substrate 10 is located in the invalid area 12 .
[0040] The bonding detection method provided in the embodiment of the present disclosure forms a detection groove 300 on the surface of the epitaxial layer 30 when detecting the thickness of the bonding layer 20, and the detection groove 300 passes through the epitaxial layer 30 and the bonding layer 20 in sequence. That is, the position where the detection groove 300 is opened is in the invalid area 12. The invalid area 12 is a useless area on the product and is not used to prepare light-emitting diodes, that is, the invalid area 12 belongs to the waste part on the product. Therefore, the formation of the detection groove 300 in the invalid area 12 will not cause damage to the product, and will not affect the subsequent processing of the product into a light-emitting diode. In addition, during detection, it is only necessary to open the detection groove 300 in the invalid area 12, so there is no need to use FIB equipment for detection, which can greatly reduce the detection cost and detection efficiency.
[0041] Figure 4 FIG. 1 is a flow chart of another bonding detection method provided by an embodiment of the present disclosure. Figure 4 As shown, the bonding detection method includes:
[0042] Step 201: Provide a product.
[0043] Alternatively, if Figure 2 As shown, the product includes a substrate 10, a bonding layer 20 and an epitaxial layer 30 stacked in sequence. The bonding layer 20 covers the effective area 11 of the substrate 10, and at least part of the bonding layer 20 is located in the ineffective area 12, and the epitaxial layer 30 is stacked on the bonding layer 20. In this way, it is ensured that the detection groove 300 is opened in the ineffective area 12 to expose the bonding layer 20, so as to detect the thickness of the bonding layer 20.
[0044] Exemplarily, the bonding layer 20 may include a silicon oxide layer and a support column 21 located in the silicon oxide layer, and the hardness of the support column 21 is greater than the hardness of the silicon oxide layer.
[0045] As an example, a plurality of support pillars 21 may be disposed in the silicon oxide layer, and the plurality of support pillars 21 may be arranged at intervals.
[0046] By embedding the support pillars 21 in the silicon oxide layer, the hardness of the bonding layer 20 can be improved, and the bonding layer 20 can be prevented from collapsing and affecting the epitaxial layer 30 formed on the bonding layer 20 .
[0047] Exemplarily, the support column 21 may be a columnar structure made of high borosilicate glass.
[0048] Exemplarily, the epitaxial layer 30 may include a first semiconductor layer 31, an active layer 32, and a second semiconductor layer 33 stacked in sequence. The first semiconductor layer 31 has a first conductivity type, the second semiconductor layer 33 has a second conductivity type different from the first conductivity type, and the active layer 32 is used to generate light through electron-hole recombination.
[0049] One of the first semiconductor layer 31 and the second semiconductor layer 33 is a p-type layer, and the other of the first semiconductor layer 31 and the second semiconductor layer 33 is an n-type layer.
[0050] As an example, the first semiconductor layer 31 is a p-type layer, and the second semiconductor layer 33 is an n-type layer.
[0051] Step 202 : forming a mask 41 on the surface of the epitaxial layer 30 , wherein the mask 41 has an etching opening 42 exposing the epitaxial layer 30 , and an orthographic projection of the etching opening 42 on the substrate is located within the ineffective region 12 .
[0052] Figure 5 3 is a state diagram of opening a detection slot 300 provided by an embodiment of the present disclosure. Figure 5 As shown, a mask 41 is formed on the surface of the epitaxial layer 30 of the product. The etched opening 42 of the mask 41 exposes the surface of the epitaxial layer 30 .
[0053] like Figure 3 As shown, the etch opening 42 is opposite to the inactive region 12 on the substrate.
[0054] Step 203 : forming a detection groove 300 by etching on the surface of the epitaxial layer 30 through the etching opening 42 , and detecting the thickness of the bonding layer 20 through the detection groove 300 .
[0055] Specifically, the method may include: introducing etching gas into the reaction chamber, and sequentially performing a first etching stage and a second etching stage on the surface of the epitaxial layer 30 .
[0056] The etching power of the etching equipment during the first etching stage is greater than the etching power of the etching equipment during the second etching stage.
[0057] During the etching process, the etching power of the first etching stage is relatively large, which is beneficial to improving the etching speed and etching away most of the epitaxial layer 30 and the bonding layer 20 relatively quickly.
[0058] After the first stage of etching, the second stage of etching with reduced etching power is used to continue etching. This not only reduces the etching speed, but also reduces the etching damage to subsequent structures. Therefore, it can avoid damage to the substrate after the etching is completed. Preventing the substrate from being damaged during the etching process can also improve the accuracy of detecting the thickness of the bonding layer 20.
[0059] Optionally, when performing the first stage of etching on the surface of the epitaxial layer 30 , the upper power of the etching equipment is controlled to be 450W to 550W, and the lower power is controlled to be 200W to 300W.
[0060] Exemplarily, during the first etching stage, the upper power of the etching equipment is controlled to be 500W, and the lower power is controlled to be 250W.
[0061] Limiting the upper power and lower power of the etching equipment within the above range can avoid the etching speed being too slow and affecting the etching efficiency; at the same time, it can also avoid the etching speed being too fast and causing damage to the film layer.
[0062] Optionally, the duration of the first etching period is 450 s to 550 s. As an example, the duration of the first etching period is 500 s.
[0063] By controlling the duration of the first etching stage within the above range, it can be ensured that the depth of the first etching stage is less than or equal to 80% of the first thickness.
[0064] The first thickness is the sum of the thickness of the epitaxial layer 30 and the thickness of the bonding layer 20 .
[0065] In this way, up to 80% of the film layers of the epitaxial layer 30 and the bonding layer 20 can be quickly etched away through the first etching stage, thereby improving the etching efficiency.
[0066] Optionally, when performing the second etching, the upper power of the etching equipment is controlled to be 0W, and the lower power is controlled to be 50W to 150W.
[0067] Exemplarily, during the second etching stage, the upper power of the etching equipment is controlled to be 0W, and the lower power is controlled to be 100W.
[0068] Setting the upper power and lower power of the etching equipment within the above range is equivalent to etching in a pure chemical manner relying only on etching gas, which can more effectively avoid damaging the sapphire substrate.
[0069] Optionally, the duration of the second etching is 250s to 350s. As an example, the duration of the second etching is 300s.
[0070] By controlling the duration of the second etching stage within the above range, the second etching stage can etch through the remaining 20% of the film layer, that is, the depth of the second etching stage is greater than or equal to 20% of the first thickness.
[0071] The sum of the depth of the first etching stage and the depth of the second etching stage is equal to the first thickness, that is, the two etching stages can completely etch through the epitaxial layer and the bonding layer.
[0072] In this way, the last 20% of the film layer is slowly etched through the second etching stage, which can effectively avoid damage to the sapphire substrate and improve the detection accuracy of the thickness of the bonding layer 20.
[0073] Optionally, a plurality of detection grooves 300 are formed on the surface of the epitaxial layer 30 , and the plurality of detection grooves 300 are arranged at intervals in the circumferential direction around the effective area 11 .
[0074] For example, Figure 3As shown, two detection grooves 300 are formed on the surface of the epitaxial layer 30 , and the two detection grooves 300 are distributed on opposite sides of the active area 11 .
[0075] By arranging a plurality of detection slots 300 in a manner of surrounding the effective area 11 , the plurality of detection slots 300 are arranged more reasonably, and the thickness of the bonding layer 20 can be detected from different positions, thereby improving the accuracy of the detected thickness of the bonding layer 20 .
[0076] The present disclosure provides a method for preparing a light emitting diode, the method comprising the following steps:
[0077] The first step is to provide a temporary substrate.
[0078] Illustratively, the temporary substrate may be a GaAs wafer.
[0079] In the second step, an epitaxial layer 30 and a bonding layer 20 are formed on the temporary substrate.
[0080] The preparation of the epitaxial layer 30 may include: growing a second semiconductor layer 33 , an active layer 32 , and a first semiconductor layer 31 which are sequentially stacked on a GaAs wafer.
[0081] For example, the second semiconductor layer 33 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0082] Exemplarily, the first semiconductor layer 31 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0083] Optionally, the active layer 32 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The active layer 32 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
[0084] As an example, in the embodiment of the present disclosure, the active layer 32 includes five periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
[0085] Optionally, the thickness of the active layer 32 may be 150 nm to 200 nm.
[0086] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 33 , and an AlInP carrier confinement layer may be grown before growing the active layer 32 .
[0087] A GaP window layer may be further grown after the first semiconductor layer 31 is grown, wherein the thickness of the GaP window layer is 10000 angstroms to 50000 angstroms.
[0088] Exemplarily, the GaP window layer has a thickness of 40,000 angstroms.
[0089] The preparation of the bonding layer 20 may include: first, coating 12000 angstroms of bonding material on the epitaxial layer 30, baking it at 100° C. for 5 minutes using a hot plate, and then baking it at 150° C. for 3 minutes using a hot plate to form a first bonding material layer.
[0090] Wherein, the first bonding material layer is a silicon oxide layer.
[0091] Then, a support column 21 with a height of 6000 angstroms was formed on the surface of the first bonding material layer, and baked at 150° C. for 5 minutes using a hot plate to solidify the support column 21 on the first bonding material layer.
[0092] Next, 8000 angstroms of bonding material is coated on the first bonding material layer, and baked at 150° C. for 3 minutes using a hot plate to form a second bonding material layer covering the support pillars 21. The first bonding material layer, the support pillars 21, and the second bonding material layer together form a bonding layer 20.
[0093] In the third step, the substrate is bonded to the bonding layer 20 and the temporary substrate is removed.
[0094] Exemplarily, the substrate is a sapphire substrate. Since the sapphire substrate has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of a sapphire substrate can enable the light-emitting diode to have good light-emitting effect and stability.
[0095] In the fourth step, the thickness of the bonding layer 20 is detected using the bonding detection method as described above.
[0096] Since the thickness of the epitaxial layer 30 is known during the preparation of the light-emitting diode, while the preparation process of the bonding layer 20 is complicated and has a large error, when the thickness of the bonding layer 20 is detected by the detection groove 300, the groove depth of the detection groove 300 is first bonded, so that the thickness of the bonding layer 20 can be calculated and determined by the groove depth of the detection groove 300 and the thickness of the epitaxial layer 30.
[0097] The fifth step is to determine whether to continue manufacturing the light emitting diode based on the thickness of the bonding layer 20 .
[0098] If the thickness of the bonding layer 20 meets the designed thickness, the electrode 51 is formed on the epitaxial layer 30; if the thickness of the bonding layer 20 does not meet the designed thickness, the product is re-prepared.
[0099] In step 6, the surface of the second semiconductor layer 33 is etched to form a groove exposing the first semiconductor layer 31. The epitaxial layer 30 is etched to expose the substrate.
[0100] In the seventh step, the electrode 51 is evaporated on the surface of the second semiconductor layer 33 and in the groove.
[0101] The electrode 51 in the groove may have the same conductivity type as the first semiconductor layer 31. For example, if the first semiconductor layer 31 is an n-type layer, the electrode 51 in the groove may be an n-electrode 51.
[0102] The electrode 51 located on the surface of the second semiconductor layer 33 has the same conductivity type as the second semiconductor layer 33. For example, if the second semiconductor layer 33 is a p-type layer, the electrode 51 located on the second semiconductor layer 33 may be a p-electrode 51.
[0103] Illustratively, the evaporated electrode 51 may include an Au layer, an AuGe layer, and a Pt layer stacked in sequence.
[0104] Optionally, the thickness of the Au layer is 80 angstroms to 150 angstroms. The Au layer has good electrical conductivity, and setting the metal layer in contact between the electrode 51 and the epitaxial layer 30 as the Au layer can improve the ohmic contact effect between the electrode 51 and the epitaxial layer 30 .
[0105] Illustratively, the Au layer has a thickness of 100 angstroms.
[0106] Optionally, the thickness of the AuGe layer is 800 angstroms to 1500 angstroms. The AuGe layer also has good conductivity, and due to the addition of Ge metal, the ohmic contact can be improved, and the amount of Au metal used can be reduced, thereby reducing the preparation cost of the electrode 51.
[0107] Illustratively, the AuGe layer has a thickness of 1000 angstroms.
[0108] Optionally, the Pt layer has a thickness of 450 angstroms to 600 angstroms.
[0109] The last metal layer of the electrode 51 is set as a Pt layer, and the Pt layer covers the AuGe layer. In this way, the Pt layer can effectively prevent the Ge element from diffusing upward during annealing, thereby ensuring the total amount of elements diffused into the semiconductor, so that the electrode 51 can achieve a better ohmic contact effect.
[0110] Illustratively, the thickness of the Pt layer is 500 angstroms.
[0111] In the eighth step, a passivation layer 60 is formed on the surface of the epitaxial layer 30 and the surface of the electrode 51 .
[0112] The manufactured passivation layer 60 is at least located in the second semiconductor layer 33 , the electrode 51 and the groove.
[0113] Optionally, the passivation layer 60 includes a silicon oxide layer.
[0114] When preparing the passivation layer 60, the deposition temperature of the passivation layer 60 is controlled to be 150°C to 250°C, and the deposition rate of the passivation layer 60 is controlled to be 15 angstroms / second to 25 angstroms / second. The passivation layer 60 prepared according to this process can release stress and improve the preparation quality of the light-emitting diode.
[0115] Exemplarily, the deposition temperature of the passivation layer 60 is 200° C., and the deposition rate of the passivation layer 60 is 20 angstroms / second.
[0116] In the ninth step, two via holes are made on the passivation layer 60 to expose the two electrodes 51 respectively.
[0117] Specifically, the method may include: forming a photoresist layer on the surface of the passivation layer 60 , opening a hole in the photoresist layer in a region corresponding to the via hole, and then etching the passivation layer 60 with a buffered oxide etching solution to form the via hole on the passivation layer 60 .
[0118] The buffered oxide etching solution is a mixture of hydrofluoric acid and water, or a mixture of ammonium fluoride and water.
[0119] In the tenth step, solder joints 52 are formed on the surface of the passivation layer 60 away from the product to be evaporated.
[0120] The soldering point block 52 is connected to the electrode 51 through a via hole.
[0121] Specifically, it may include: sequentially evaporating a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au alloy layer on the surface of the passivation layer 60 to form the solder joint block 52 on the surface of the passivation layer 60 .
[0122] The soldering point block 52 is connected to the electrode 51 through a via hole.
[0123] Exemplarily, the thickness of the Cr layer is 50 angstroms to 150 angstroms. For example, the thickness of the Cr layer is 100 angstroms.
[0124] Exemplarily, the thickness of the Al layer is 2500 angstroms to 3500 angstroms. For example, the thickness of the Al layer is 3000 angstroms.
[0125] Exemplarily, the thickness of the Ti layer is 400 angstroms to 600 angstroms. For example, the thickness of the Ti layer is 500 angstroms.
[0126] Exemplarily, the thickness of the Ni layer is 1000 angstroms to 3000 angstroms. For example, the thickness of the Ni layer is 2000 angstroms.
[0127] Exemplarily, the thickness of the Au alloy layer is 15000 angstroms to 25000 angstroms. For example, the thickness of the Au layer is 20000 angstroms.
[0128] In the fourth step, a protection layer is formed on the surface of the passivation layer 60 , and the protection layer extends from the surface of the passivation layer 60 to the substrate.
[0129] Illustratively, in the embodiment of the present disclosure, the protective layer may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.
[0130] It should be noted that after the protective layer is grown on the surface of the passivation layer 60 , a through hole exposing the soldering point block 52 can be etched on the surface of the protective layer using photolithography technology to facilitate electrical connection.
[0131] Finally, the sapphire can be cut and scratched invisible, which can effectively reduce the loss of brightness. Then, the light-emitting diode is obtained by testing.
[0132] The present disclosure provides a light emitting diode, which is prepared by the light emitting diode preparation method as described above. Figure 2 As shown, the light emitting diode includes a substrate, a bonding layer 20 and an epitaxial layer 30 which are stacked in sequence.
[0133] Optionally, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.
[0134] Optionally, the bonding layer 20 includes a silicon oxide layer and a support column 21 located in the silicon oxide layer, and the hardness of the support column 21 is greater than the hardness of the silicon oxide layer.
[0135] As an example, a plurality of support pillars 21 may be disposed in the silicon oxide layer, and the plurality of support pillars 21 may be arranged at intervals.
[0136] By embedding the support pillars 21 in the silicon oxide layer, the hardness of the bonding layer 20 can be improved, and the bonding layer 20 can be prevented from collapsing and affecting the epitaxial layer 30 formed on the bonding layer 20 .
[0137] Exemplarily, the support column 21 may be a columnar structure made of high borosilicate glass.
[0138] Optionally, the epitaxial layer 30 includes a first semiconductor layer 31 , an active layer 32 , and a second semiconductor layer 33 sequentially stacked on the substrate.
[0139] In the embodiment of the present disclosure, one of the first semiconductor layer 31 and the second semiconductor layer 33 is a p-type layer, and the other of the first semiconductor layer 31 and the second semiconductor layer 33 is an n-type layer.
[0140] As an example, the first semiconductor layer 31 is a p-type layer, and the second semiconductor layer 33 is an n-type layer.
[0141] Optionally, the first semiconductor layer 31 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0142] Optionally, the active layer 32 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The active layer 32 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
[0143] As an example, in the embodiment of the present disclosure, the active layer 32 includes five periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
[0144] Optionally, the thickness of the active layer 32 may be 150 nm to 200 nm.
[0145] Optionally, the second semiconductor layer 33 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0146] Alternatively, if Figure 2 As shown, the light emitting diode includes two electrodes 51. The surface of the second semiconductor layer 33 has a groove exposing the first semiconductor layer 31, one of the two electrodes 51 is located in the groove, and the other of the two electrodes 51 is located on the surface of the second semiconductor layer 33 away from the substrate.
[0147] Alternatively, the electrode 51 includes an Au layer, an AuGe layer, and a Pt layer sequentially stacked on the surface of the epitaxial layer 30 .
[0148] The last metal layer of the electrode 51 is set as a Pt layer, and the Pt layer covers the AuGe layer. In this way, the Pt layer can effectively prevent the Ge element from diffusing upward during annealing, thereby ensuring the total amount of elements diffused into the semiconductor, so that the electrode 51 can achieve a better ohmic contact effect.
[0149] Optionally, the thickness of the Au layer is 80 angstroms to 150 angstroms. The Au layer has good electrical conductivity and can improve the ohmic contact effect between the electrode 51 and the epitaxial layer 30 .
[0150] Illustratively, the Au layer has a thickness of 100 angstroms.
[0151] Optionally, the thickness of the AuGe layer is 800 angstroms to 1500 angstroms. The AuGe layer also has good electrical conductivity, and can reduce the amount of Au metal used, thereby reducing the preparation cost of the electrode 51.
[0152] Illustratively, the AuGe layer has a thickness of 1000 angstroms.
[0153] Optionally, the thickness of the Pt layer is 450 angstroms to 600 angstroms. The last metal layer of the electrode 51 is set as a Pt layer, and the Pt layer covers the AuGe layer, so that the AuGe layer can be guaranteed.
[0154] Illustratively, the thickness of the Pt layer is 500 angstroms.
[0155] Alternatively, if Figure 2 As shown, the light emitting diode further includes a passivation layer 60 , which is located at least on the surface of the second semiconductor layer 33 , the bottom surface of the groove and the surfaces of the two electrodes 51 .
[0156] Exemplarily, the passivation layer 60 has via holes respectively exposing the two electrodes 51 .
[0157] Alternatively, the passivation layer 60 may include a DBR layer or a silicon oxide layer.
[0158] The electrode 51 located in the groove is an n-electrode 51 , and the electrode 51 located on the second semiconductor layer 33 is a p-electrode 51 .
[0159] Alternatively, if Figure 2 As shown, the light emitting diode further includes: two soldering blocks 52, the two soldering blocks 52 are located on the passivation layer 60, and the two soldering blocks 52 are connected to the two electrodes 51 through two via holes respectively.
[0160] Optionally, a protective layer is further provided on the surface of the passivation layer 60 and the improvement layer, and the protective layer extends from the surface of the passivation layer 60 and the improvement layer to the substrate, and the protective layer has through holes exposing the solder joints 52 for electrical connection.
[0161] Illustratively, in the embodiment of the present disclosure, the protective layer may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.
[0162] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. The data therein only represent illustrative examples. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A bonding detection method, characterized in that: The bonding detection method comprises: A product is provided, the product comprising a substrate (10), a bonding layer (20) and an epitaxial layer (30) stacked in sequence, the surface of the substrate (10) comprising an active region (11) and an inactive region (12) surrounding the active region (11), at least part of the orthographic projection of the bonding layer (20) on the substrate (10) being located in the inactive region (12); A detection groove (300) is formed on the surface of the epitaxial layer (30) and sequentially penetrates the epitaxial layer (30) and the bonding layer (20), and the thickness of the bonding layer (20) is detected through the detection groove (300), and the orthographic projection of the detection groove (300) on the substrate (10) is located in the invalid area (12).
2. The bonding detection method according to claim 1, characterized in that: Forming a detection groove (300) on the surface of the epitaxial layer (30) and sequentially penetrating the epitaxial layer (30) and the bonding layer (20) comprises: A mask (41) is formed on the surface of the epitaxial layer (30), wherein the mask (41) has an etching opening (42) exposing the epitaxial layer (30), and the orthographic projection of the etching opening (42) on the substrate (10) is located within the ineffective area (12); The detection groove (300) is formed by etching on the surface of the epitaxial layer (30) through the etching opening (42).
3. The bonding detection method according to claim 2, characterized in that: Etching the detection groove (300) on the surface of the epitaxial layer (30) through the etching opening comprises: A first etching stage and a second etching stage are sequentially performed on the surface of the epitaxial layer (30), wherein the etching power of the etching equipment during the first etching stage is greater than the etching power of the etching equipment during the second etching stage.
4. The bonding detection method according to claim 3, characterized in that: When performing the first stage of etching on the surface of the epitaxial layer (30), controlling the upper power of the etching equipment to be 450W to 550W and the lower power to be 200W to 300W; When performing the second etching step, the upper power of the etching equipment is controlled to be 0W, and the lower power is controlled to be 50W to 150W.
5. The bonding detection method according to claim 4, characterized in that: The duration of the first etching stage is 450s to 550s, and the duration of the second etching stage is 250s to 350s.
6. The bonding detection method according to claim 3, characterized in that: The depth of the first etching is less than or equal to 80% of the first thickness, the first thickness being the sum of the thickness of the epitaxial layer (30) and the thickness of the bonding layer (20); The depth of the second etching section is greater than or equal to 20% of the first thickness, and the sum of the depth of the first etching section and the depth of the second etching section is equal to the first thickness.
7. The bonding detection method according to any one of claims 1 to 6, characterized in that: Forming a detection groove (300) on the surface of the epitaxial layer (30) and sequentially penetrating the epitaxial layer (30) and the bonding layer (20) comprises: A plurality of the detection grooves (300) are formed on the surface of the epitaxial layer (30), and the plurality of the detection grooves (300) are arranged at intervals in the circumferential direction around the effective area (11).
8. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a temporary substrate; forming an epitaxial layer (30) and a bonding layer (20) on the temporary substrate; Bonding a substrate (10) to the bonding layer (20), and removing the temporary substrate; Adopting the bonding detection method according to any one of claims 1 to 7 to detect the thickness of the bonding layer (20); If the thickness of the bonding layer (20) meets the designed thickness, an electrode (51) is formed on the epitaxial layer (30).
9. A light emitting diode, characterized in that: The light-emitting diode is manufactured by the method for manufacturing a light-emitting diode according to claim 8, and comprises a substrate (10), a bonding layer (20) and an epitaxial layer (30) which are stacked in sequence.
10. The light emitting diode according to claim 9, characterized in that: The bonding layer (20) comprises a silicon oxide layer and a support column (21) located in the silicon oxide layer, and the hardness of the support column (21) is greater than the hardness of the silicon oxide layer.