Semiconductor devices and methods of making and using preformed bridge die

Abstract

A semiconductor device has a first interconnect structure. A preformed bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the preformed bridge die. A second interconnect structure is disposed over the encapsulant and the preformed bridge die. A first semiconductor die is disposed over the second interconnect structure within a footprint of the preformed bridge die. A second semiconductor die is disposed over the second interconnect structure within the footprint of the preformed bridge die.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices and methods of making and using preformed bridge dies. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices may include multiple electrical components, such as one or more semiconductor dies and numerous discrete components to support the semiconductor dies, disposed on one or more substrates to perform the necessary electrical functions. A highly integrated package with several components is often referred to as a system-in-package (SiP) module. SiP modules often have multiple semiconductor dies that must communicate with each other at very high bandwidths. Conductive traces formed at the packaging level may not be sufficient to support the necessary bandwidth.

[0004] Many SiP packages utilize bridge dies to facilitate high-bandwidth communications between components in a SiP device. A bridge die is a semiconductor die that may have no circuitry formed in its active surface, but has fine-pitch interconnects formed on them. A bridge die may be deployed between two other semiconductor dies, which are then interconnected via the bridge die to increase the available data bandwidth between them.

[0005] Bridge dies are helpful for advanced SiP modules, but introduce additional design constraints due to the additional components required.Therefore, there is a need for improved bridge die structures and topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1a-1d illustrates a semiconductor wafer having a plurality of bridge dies separated by saw streets;

[0007] Figure 2a-2e The figure shows the forming of the bridge die;

[0008] Figure 3a-3m The diagram illustrates forming a system-in-package module using a preformed bridge die;

[0009] Figure 4 illustrates a system-in-package module with a bridge die that has not been preformed;

[0010] Figure 5a-5hillustrates forming a fan-out interconnect structure over a preformed bridge die;

[0011] Figure 6a and 6b illustrates an additional protective layer formed over the bridge die; and

[0012] Figure 7a and 7b An electronic device having a system-in-package module is illustrated. DETAILED DESCRIPTION

[0013] The present invention is described in one or more embodiments in the following description with reference to the figures, in which the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have functions similar to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0014] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current that is necessary to perform the circuit function.

[0015] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and encapsulating the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scribed and broken along the non-functional area of ​​the wafer (referred to as saw road or scribing line). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die is disposed on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved using a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0016] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor die, bridge die, or other components 104 are formed on the wafer 100, separated by a passive inter-die wafer region or saw road 106. The saw road 106 provides a cutting area to singulate the semiconductor wafer 100 into individual bridge die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). The wafer 100 may include hundreds or thousands of die 104.

[0017] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each bridge die 104 has a back surface or inactive surface 108 and an active surface 110, which optionally contains analog or digital circuits, which are implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuits or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The bridge die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0018] Alternatively, the bridge die 104 has no circuitry formed in the active surface 110 and is used only for an interconnect structure 112 formed above the active surface 110. The interconnect structure 112 includes fine pitch conductive traces, for example, both the line width and the spacing between the lines are less than 2 microns (μm). The interconnect structure 112 can have one or more layers of conductive traces, with insulating layers formed between the layers. The interconnect structure 112 is illustrated only as a region because the pitch of the interconnect is too fine to be illustrated except conceptually. The area identified as the interconnect structure 112 in the figure is occupied by any appropriately configured fine pitch interconnect structure, for example, so that the contact pads 114 pairs are electrically coupled to each other on opposite sides of the bridge die 104.

[0019] The interconnect structure 112 includes a contact pad 114 formed at the top of the interconnect structure for external connection to the interconnect structure 112. The contact pad 114 is larger than 2 microns to allow a conductive via or other conductive structure to contact or be formed on the contact pad and thereby electrically connect to the underlying fine pitch conductive trace of the interconnect structure 112.

[0020] Conductive traces and contact pads 114 of interconnect structure 112 are formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive traces and contact pads 114 of interconnect structure 112 may be one or more layers of conductive materials such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. In some embodiments, contact pads 114 include under-bump metallization (UBM).

[0021] The interconnect structure 112 includes an insulating layer formed on and between the conductive traces. The insulating layer of the interconnect structure 112 includes one or more layers of the following materials: silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. The interconnect structure 112 may include any number of interlaced conductive layers and insulating layers.

[0022] Conductive micro-columns (micropost), micro-bumps or micro-columns 116 are formed on the contact pads 114 of each bridge die 104 to provide external interconnection. Conductive micro-columns 116 are typically formed by depositing conductive material into the openings of the photolithographic layer and then removing the photolithographic layer. The metal can be any of the materials mentioned above for the conductive layer. In one embodiment, the micro-columns 116 have a copper core with a Ti / Cu coating of 30 microns thick. Micro-columns 116 represent only one possible interconnection method. Other embodiments use bonding wires, conductive pastes, columnar bumps, solder bumps or any other suitable type of electrical interconnection.

[0023] An insulating or passivation layer 117 is deposited over the interconnect structure 112 and the micropillars 116. The insulating layer 117 is formed as described above for the insulating layer and is formed of any of the insulating materials mentioned above. The insulating layer 117 is formed to a thickness such that the micropillars 116 extend above the top surface of the insulating layer, i.e., the thickness of the insulating layer is less than the height of the micropillars.

[0024] Figure 1c A detailed view of a micropillar 116 in one embodiment is shown. Prior to forming the micropillar 116, an optional passivation layer 119 is formed on the bridge die 104. The micropillar 116 may include a UBM 116a formed in the same mask opening as the micropillar itself. The insulating layer 117 is a polyimide layer. The interconnect structure 112 exists only as a conductive trace extending between the contact pads 114 above the active surface 110.

[0025] exist Figure 1d , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested for identification of known good dies (KGD) or known good units (KGU) after singulation.

[0026] Figure 2a-2e The process of preforming the bridge die 104 is illustrated. Figure 2a A cross-sectional view of a portion of a carrier or temporary substrate 120 is shown, which includes a sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. An interface layer or double-sided tape 122 is formed or disposed on the carrier 120 as a temporary adhesive bonding film, etch stop layer, thermal release layer, or UV release layer. The carrier 120 can be a circular or rectangular panel with the ability to process multiple bridge tube dies 104 at one time. Although only three bridge tube dies 104 are shown, tens, hundreds, or thousands of modules can be processed together on a common carrier 120.

[0027] The bridge die 104 is disposed on a carrier 120, wherein the back surface 108 of the bridge die is oriented toward the carrier. The micropillars 116 extend upwardly away from the carrier 120. Figure 2b In the process, the sealant or molding compound 124 is deposited on and around the carrier 120, the bridge die 104 and the micropillars 116 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or another suitable applicator. The sealant 124 can be a liquid or particulate polymer composite material, such as an epoxy resin, epoxy acrylate or polymer, with or without added fillers. In another embodiment, the sealant 124 is a laminated sheet or film with or without fillers. The sealant 124 is non-conductive, provides structural support, and environmentally protects the bridge die 104 from external elements and contaminants. The sealant 124 completely covers the top and side surfaces of the micropillars 116. In another embodiment, the sealant 124 is deposited to have a top surface that is coplanar with the top surface of the micropillars 116, for example by using film-assisted molding.

[0028] exist Figure 2c In the embodiment, carrier 120 is debonded and removed from the panel of bridge die 104 and encapsulant 124. In some embodiments, the adhesion properties of interface layer 122 are reduced by heat, UV light, laser or other energy application prior to mechanically removing carrier 120 from the bridge die panel.

[0029] exist Figure 2d 1, a die attach film (DAF) tape 125 is mounted to the encapsulant 124 and the now exposed back surface 108 of the bridge die 104, which are coplanar. The DAF tape 125 is a double-sided adhesive tape that adheres to the panel of encapsulant 125 and bridge die 104 due to its adhesive properties. The side of the DAF tape 125 opposite the bridge die 104 will typically be covered by a non-adhesive film until the manufacturer peels off the non-adhesive film to mount one of the bridge dies into the package.

[0030] exist Figure 2e , the bridge dies 104 are singulated from one another through the encapsulant 124 and the DAF tape 125 to form separate preformed bridge dies 126. Singulation through the encapsulant 124 may occur using the same saw blade or laser cutting tool 118 as used above for singulating the wafers, or any other suitable means may be used. The preformed bridge dies 126 are referred to as preformed because the bridge dies 104 are molded within the encapsulant 124 before the bridge dies are incorporated into a system-in-package (SiP) module or other semiconductor package. In some embodiments, the preformed bridge dies 126 may have additional alignment mark features for die attach, such as attached copper balls or dummy dies.

[0031] As an alternative molding process, the encapsulant 124 may be deposited prior to fully singulating the semiconductor wafer 100. Grooves may be formed into the saw streets 106 to create side surfaces of the bridge die 104 exposed within the grooves. The encapsulant 124 is deposited over the active surface 110 and into the grooves in the saw streets 106. The wafer 100 is back ground to remove the remaining semiconductor material within the saw streets 106. The bridge die 104 are then singulated from one another through the encapsulant 124, which has been made the same thickness as the bridge die by back grinding the wafer 100.

[0032] Figure 3a-3m 1 shows a process for forming a SiP module incorporating a preformed bridge die 126. Figure 3a , interconnect structure 130 is formed or disposed on a carrier 127 having an interface layer 128. Carrier 127 may be the same or different than carrier 120. Carrier 127 may be the same type or size as carrier 120, or another type of carrier mentioned above may be used. Interface layer 128 may be any suitable type of interface layer as mentioned above for interface layer 122. Carrier 127 may be a circular or rectangular panel with the ability to form multiple SiP modules at once. Although only one unit is shown being formed, dozens, hundreds, thousands, or more modules may be formed together on a common carrier 120 using the steps shown and described below that are performed together.

[0033] The interconnect structure 130 includes one or more conductive layers 132 and one or more insulating layers 134. The particular illustrated embodiment shows insulating layer pairs 134a and 134b and conductive layer pairs 132a and 132b constructed as a stack, but any suitable number of layers may be used to accomplish the desired signal routing. The conductive layer 132 may be formed using the materials and methods described above for the conductive layers of the interconnect structure 112. The conductive layer 132 provides conductive traces for horizontal electrical interconnection across the interconnect structure 130 and provides conductive vias for vertical electrical interconnection between the surfaces and layers of the interconnect structure. Portions of the conductive layer 132 may be electrically common or electrically isolated, depending on the design and function of the package being formed.

[0034] In some embodiments, interconnect structure 130 is a preformed interposer or substrate that is fully formed before the interconnect structure is deployed on carrier 127. In another embodiment, interconnect structure 130 is formed directly on carrier 127 by successively forming a plurality of insulating layers 134 and conductive layers 132 on the carrier. Interconnect structure 130 is typically large enough to accommodate all SiP modules that are formed on carrier 120 at one time and then singulated with the final modules. In other embodiments, a separate interconnect structure 130 is provided or formed for each SiP module.

[0035] Openings are formed through bottom insulating layer 134a to allow conductive vias of conductive layer 132a to extend downward to the bottom of interconnect structure 130 for external interconnection. Similarly, top insulating layer 134b has openings formed above contact pads of conductive layer 132b for subsequent interconnection. In other embodiments, conductive layer 132a, conductive layer 132b, or both are formed on the outermost surface of interconnect structure 130, so that openings or vias through insulating layer 134 are not necessary for interconnection. Conductive traces of conductive layer 132a or 132b interconnect the vias of conductive layer 132a and the contact pads of conductive layer 134b to achieve desired signal routing. In other embodiments, any type of package substrate or lead frame is used for interconnect structure 130.

[0036] exist Figure 3b In the embodiment, the conductive pillars 140 are formed on the interconnect structure 130 at multiple points where the conductive layer 132b is exposed as contact pads through the openings of the insulating layer 134b. In one embodiment, the conductive pillars 140 are formed by depositing a conductive material into the photolithographic mask openings. In another embodiment, the conductive pillars 140 are preformed and then picked up and placed onto the interconnect structure 130. Solder or solder paste can be used to connect the pillars 140 to the interconnect structure 130. The conductive pillars 140 can be formed of any of the conductive materials mentioned above and using any suitable manufacturing process.

[0037] The preformed bridge die 126 is picked up and placed in Figure 3c 130 and then mounted to the interconnect structure 130. Encapsulant 124 protects bridge die 104 during the physical handling of the pick and place process. DAF tape 125 has an exposed adhesive surface that adheres to insulating layer 134. If a protective non-adhesive film is used, it is peeled off before mounting. In other embodiments, instead of using DAF tape 125, a separate die attach adhesive is spread onto the interconnect structure 130. The height of the conductive pillar 140 is selected so that the top of the conductive pillar will be approximately the same height above the interconnect structure 130 as the top of the micro pillar 116. In other embodiments, the heights are different and a subsequent planarization step can be used to make them equal.

[0038] exist Figure 3d In the embodiment of the present invention, encapsulant 150 is deposited over and around interconnect structure 130, preformed bridge die 126, and conductive pillars 140. Encapsulant 150 is deposited using any of the materials and methods described above for encapsulant 124. Encapsulant 150 completely covers the top of conductive pillars 140 and preformed bridge die 126.

[0039] Figure 3eThe encapsulant 150, the conductive pillars 140, and the preformed bridge die 126 are shown being planarized using a mechanical grinder 152. In other embodiments, chemical mechanical planarization or another suitable method is used. Figure 3f Encapsulant 150 is shown after planarization. Planarization removes the top portion of encapsulant 124 from preformed bridge die 126 to expose the top surface of micropillars 116. A small portion of conductive pillars 140 and micropillars 116 may be removed to ensure that all conductive pillars and micropillars are exposed from encapsulant 150 for electrical interconnection. Planarization makes the top surfaces of conductive pillars 140 and micropillars 116 coplanar with each other and with the top surface of encapsulant 150.

[0040] In other embodiments, film-assisted molding or another suitable molding technique is used to expose the conductive pillars 140 and micropillars 116 without a separate planarization step. Pre-molding of the bridge die 104 within the encapsulant 124 reduces the possibility of delamination during grinding. In another embodiment, instead of planarization, laser, mechanical or chemical etching is used to form openings through the encapsulant 150 down to the micropillars 116 and conductive pillars 140.

[0041] exist Figure 3g , an interconnect structure 160 is formed or disposed over the encapsulant 150. The interconnect structure 160 is formed and constructed on the opposite side of the encapsulant 150 similarly to the interconnect structure 130, with conductive layers 162 interleaved between insulating layers 164. Two conductive layers 162a and 162b and two insulating layers 164a and 164b are illustrated. However, any suitable number of insulating layers and conductive layers may be interleaved to achieve the desired signal routing. The interconnect structure 160 may be formed directly on top of the encapsulant 150 and the preformed bridge die 126, or may be formed separately and disposed over the encapsulant and preformed bridge die.

[0042] Conductive layer 162 includes conductive vias that extend down to the bottom surface of interconnect structure 160 to physically and electrically contact conductive pillars 140 and micropillars 116. Contact pads or conductive vias of conductive layer 162b are exposed at the top surface of interconnect structure 160 to allow electrical components to be mounted thereto.

[0043] Interconnect structure 130, conductive pillars 140, preformed bridge die 126, encapsulant 150, and interconnect structure 160 combine to form fan-out interposer 170. Interposer 170 may operate as a package substrate for a semiconductor package and have bridge die 104 embedded within the interposer as part of preformed bridge die 126.

[0044] exist Figure 3h16, the SiP module is formed by mounting additional semiconductor die 180 and any other desired components onto the interconnect structure 160, with the interposer 170 serving as the package substrate. The semiconductor die 180 is formed similarly to the bridge die 104, but may not have such a fine pitch interconnect structure 112. The semiconductor die 180 still has conductive and insulating layers stacked on its active surface, with final contact pads 114 exposed above the active surface of each die.

[0045] Conductive bump material is typically deposited on the contact pad 114 of the semiconductor die 180 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes at the wafer level. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), copper, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the contact pad 114 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a bump 182. The bump 182 can also be compression bonded or thermocompressed bonded to the contact pad 114. After the semiconductor die 180 is disposed on the interposer 170, the bump 182 is reflowed to mechanically couple and electrically couple the semiconductor die 180 to the interconnect structure 160.

[0046] As just a simplified example of the nearly infinite possibilities, Figure 3h The formation of a SiP module is shown, in which one bridge die 104 is embedded in an interposer 170, and two main dies 180 on the interposer are connected together through the bridge die. The main die 180 can be any type of die that serves the primary function of the package being formed, such as an ASIC, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an accelerator, a logic die, a high bandwidth memory (HBM), an I / O die, or a NAND flash memory. The main die 180 can be the same or different from each other, such as a CPU and a GPU. In other embodiments, more than two dies are coupled together through a bridge die 104. More than one bridge die can also be used. If it is convenient for the package layout, the additional bridge die 104 can be placed on top of the interposer 170 with or without preforming. Any other suitable components, such as other semiconductor dies or discrete active or passive electrical components, can be mounted to the interconnect structure 130 with the preformed bridge die 126, or mounted to the interconnect structure 160 with the main die 180.

[0047] The main die 180 are each separately coupled to the bridge die 104 through the interconnect structure 160, and then coupled to each other through the bridge die. In a plan view, each main die 180 overlaps the bridge die 104 within the interposer 170, which allows a direct vertical connection between the main die and the bridge die. The bridge die 104 provides a faster and higher density interconnection than the interconnection available through the interconnect structure 160. Only a small part of the interconnection between the main die 180 appears in the interconnect structure 160, and most of the interconnection distance is through the bridge die 104. The components are not proportional, and the proportion of the distance covered by the bridge die 104 in reality will be much greater than that shown. In some embodiments, the main die 180 are also directly coupled to each other through the interconnect structure 160. For example, a high bandwidth data line between two main die can utilize the bridge die 104, while the slower control signal is directly connected without a bridge die.

[0048] exist Figure 3i In the embodiment, the molded underfill 186 is dispersed between the interposer 170 and the main die 180. Capillary action draws the molded underfill 186 under the die to completely fill the gap between each die and the interposer 170. In some embodiments, the molded underfill 186 also flows upward between adjacent die 180. Figure 3j In the embodiment of the present invention, a second encapsulant 188 is deposited over interposer 170 and main die 180. Encapsulant 188 is deposited using similar methods and materials as disclosed above for encapsulant 150. In some embodiments, film-assisted molding is used to expose the back surface of die 180 from encapsulant 188. Figure 3k As shown in , encapsulant 188 may alternatively be back ground using back grinder 189 or another suitable method to expose the die. In other embodiments, encapsulant 188 is provided to cover semiconductor die 180 . Figure 3l Encapsulant 188 is illustrated as being coplanar with the back surface of semiconductor die 180 .

[0049] exist Figure 3m 1, SiP module 190 is completed by removing interposer 170 from carrier 127 and forming UBMs 192 and solder bumps 194 on the newly exposed surface of interconnect structure 130. UBMs 192 are formed from a plurality of conductive layers, including, in some embodiments, a wetting layer, a barrier layer, and an adhesion layer. Each UBM 192 is formed directly on an exposed conductive via of conductive layer 132 to provide an electrical connection from an external system to a component within SiP module 190. Bumps 194 are formed on UBMs 192 as described for bumps 182 on contact pads 114.

[0050] The panel is singulated through the interposer 170 and encapsulant 188 to separate the individual SiP modules 192 from each other and then picked up and placed into a tape-and-reel or other container for delivery. The SiP module 192 has the bridge die 104 included as part of the preformed bridge die 126. The additional molding layer provided by the encapsulant 124 reduces the Figure 3e The possibility of dielectric layer delamination during the grinding step shown. In addition, encapsulant 124 can be made of a different material than encapsulant 150 to provide better warpage and structural rigidity. Encapsulant 124 is also Figure 3c The bridge die 104 is protected during the die attach process.

[0051] Figure 4 An embodiment similar to SiP module 192 is illustrated, but SiP module 200 is shown with a non-preformed bridge die 104. SiP module 200 is shown as Figure 3a-3m is formed as shown in Figure 1d After singulation in the embodiment, the bridge die 104 is included, and there is no Figure 2a-2e The DAF tape 202 can be disposed on the interconnect structure 130 before mounting the bridge die 104, or first disposed on the bridge die 104. Alternatively, a liquid adhesive can be spread between the bridge die 104 and the interconnect structure 130.

[0052] Figure 5a-5h The diagram shows the formation of a redistribution layer or fan-out interconnect structure on top of the preformed die. Figure 2c Continuing, the panel of encapsulant 124 and bridge die 104 is planarized over micropillars 116 to expose the micropillars from the encapsulant. Figure 5b As shown, the top surfaces of micropillars 116 are made coplanar with the top surface of encapsulant 124 .

[0053] exist Figure 5c In the embodiment of the present invention, an insulating layer 210 is formed on the coplanar surfaces of the encapsulant 124 and the micropillars 116. The insulating layer 210 is formed using any of the processes and materials mentioned above for other insulating or passivation layers. Openings 212 are formed through the insulating layer 210 using photolithography, mechanical or chemical etching, laser ablation, or another suitable method to expose the micropillars 116 for subsequent electrical interconnection with the micropillars.

[0054] exist Figure 5dIn the embodiment, a conductive layer 218 is formed over the insulating layer 210 and into the openings 212 to contact the micropillars 116. The conductive layer 218 is formed using any of the processes and materials mentioned above for the conductive layer. The conductive layer 218 is patterned to include a fan-out pattern of conductive traces and optional contact pads where the overlying interconnect structures will be formed or deployed. Figure 5e In the embodiment of the present invention, insulating layer 220 is formed over conductive layer 218, as mentioned above for insulating layer 210. Openings 222 are formed through insulating layer 220 to expose portions of conductive layer 218 for subsequent electrical interconnection.

[0055] exist Figure 5f In FIG. 2 , contact pads or UBMs 228 are formed in openings 222 to provide external interconnect to bridge die 104 through conductive layer 218 and micropillars 116 .

[0056] exist Figure 5g In the embodiment described above, DAF tape 125 is disposed on the encapsulant 124 and the back surface of the bridge die 104. Figure 5h In the embodiment, the bridge dies 104 are singulated from each other through the insulating layer 220, the insulating layer 210, the encapsulant 124, the DAF tape 125, and the optional conductive layer 218 to separate the bridge dies into separate units of preformed bridge dies 230. The preformed bridge dies 230 have the bridge dies 104 preformed in the encapsulant 124, wherein the fan-out interconnect structure is formed over the bridge dies and the encapsulant. As described above, the preformed bridge dies 230 can be incorporated into a SiP device.

[0057] Figure 6a and 6b A preformed bridge die 240 is shown with an additional protective layer 242 used on the bridge die 104. The bridge die 104 is formed with the protective layer 242 formed on the upper surface of the bridge die 104 at the wafer 100 level. Figure 1b . The material for the protective layer 242 can be a molded sheet film with SiO2 filler and polymer resin, such as Ajinomoto ABF material. Alternatively, a molding process is used to apply a molding compound, such as Nagase liquid molding compound. In other embodiments, any of the materials and processes for the sealant or insulating layer described above can be used to form the protective layer 242. If necessary, after applying the film or molding compound, a thermal curing process is used.

[0058] In addition to having a protective function during processing of the bridge die 104, the protective layer 242 also helps to mitigate the coefficient of thermal expansion (CTE) mismatch between the bridge die 104 and the main die 180 disposed on the interposer 170. In one embodiment, the CTE of the protective layer 242 is between 4-30 ppm / K. In another embodiment, the CTE of the protective layer 242 is between 5 and 10 ppm / K. In some embodiments, the top surface of the protective layer 242 is equal to the micropillars 116 or extends above the micropillars 116. The protective layer 242 optionally has an inclined surface around each micropillar 116.

[0059] Figure 6b A SiP module 250 is shown formed using the preformed bridge die 240. The SiP module 250 is formed as described above for the SiP module 190, but the preformed bridge die 240 is used in place of the preformed bridge die 126. A protective layer 242 may also be added to the bridge die 104 without requiring the preformed bridge die 126. Figure 4 The preform shown in , or any other bridge die embodiment disclosed above or below.

[0060] Figure 7a and 7b Integration of the above-described semiconductor package (eg, SiP module 190 ) into a larger electronic device 300 is illustrated. Figure 7a A partial cross section of a SiP module 190 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is illustrated. Bumps 194 are reflowed onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the SiP module 190 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the SiP module 190 and the PCB 302. The semiconductor die 180 is electrically coupled to the conductive layer 304 via the bumps 194, the interconnect structure 130, the conductive pillars 140, and the interconnect structure 160.

[0061] Figure 7b An electronic device 300 is illustrated having a chip carrier substrate or PCB 302 with multiple semiconductor packages disposed on a surface of the PCB 302, including a SiP module 190. The electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0062] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to facilitate installation in a more ergonomic and smaller device housing.

[0063] exist Figure 7b In the embodiment of the present invention, PCB 302 provides a common substrate for structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 304 are formed on the surface or in layers of PCB 302 using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 304 also provide power and ground connections for each of the semiconductor packages.

[0064] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level of packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0065] For illustration purposes, several types of first level packages are shown on PCB 302, including a wire bond package 346 and a flip chip 348. In addition, several types of second level packages, including a ball grid array (BGA) 350, a bump chip carrier (BCC) 352, a land grid array (LGA) 356, a multi-chip module (MCM) or SIP module 358, a quad flat no-lead package (QFN) 360, a quad flat package 362, and an embedded wafer level ball grid array (eWLB) 364 are shown deployed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0066] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package types, as well as other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using cheaper components and assembly line manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, resulting in lower costs for consumers.

[0067] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a first interconnect structure; disposing a preformed bridge die over the first interconnect structure; depositing an encapsulant over the preformed bridge die; disposing a second interconnect structure over the encapsulant and the preformed bridge die; disposing a first semiconductor die over the second interconnect structure and within a footprint of the preformed bridge die; and A second semiconductor die is disposed over the second interconnect structure within the footprint of the preformed bridge die.

2. The method according to claim 1, further comprising forming the preformed bridge die by: providing a bridge die; and A second encapsulant is deposited over the bridge die. 3 . The method of claim 2 , further comprising forming a plurality of micro-pillars over the bridge die before depositing the second encapsulant. 4 . The method of claim 2 , further comprising forming the preformed bridge die by forming a protective layer over the bridge die before depositing the second encapsulant. 5 . The method of claim 1 , further comprising planarizing the encapsulant and the preformed bridge die to expose an interconnect structure of the preformed bridge die before disposing the second interconnect structure. 6 . The method of claim 1 , further comprising forming a conductive pillar through the encapsulant from the first interconnect structure to the second interconnect structure.

7. A semiconductor device comprising: a first interconnect structure; a preformed bridge die disposed over the first interconnect structure; an encapsulant deposited over the preformed bridge die; a second interconnect structure disposed over the encapsulant and the preformed bridge die; a first semiconductor die disposed over the second interconnect structure and within a footprint of the preformed bridge die; and A second semiconductor die is disposed over the second interconnect structure within the footprint of the preformed bridge die.

8. The semiconductor device of claim 7, wherein the preformed bridge die comprises: Bridge die; and A second encapsulant is deposited over the bridge die. 9 . The semiconductor device of claim 8 , wherein the preformed bridge die further comprises a plurality of micro-pillars formed over the bridge die. 10 . The semiconductor device of claim 8 , wherein the preformed bridge die comprises a protection layer formed over the bridge die.

11. A semiconductor device comprising: a first interconnect structure; a preformed bridge die disposed over the first interconnect structure; an encapsulant deposited over the preformed bridge die; and A second interconnect structure is disposed over the encapsulant and the preformed bridge die.

12. The semiconductor device of claim 11, wherein the preformed bridge die comprises: Bridge die; and A second encapsulant is deposited over the bridge die. 13 . The semiconductor device of claim 12 , wherein the preformed bridge die further comprises a plurality of micro-pillars formed over the bridge die. 14 . The semiconductor device of claim 12 , wherein the preformed bridge die comprises a protection layer formed over the bridge die. 15 . The semiconductor device of claim 11 , further comprising a conductive pillar extending through the encapsulant from the first interconnect structure to the second interconnect structure.

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