Package and method of forming same

Abstract

A method of forming a package includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding the first semiconductor device to the first conductive pillar through a first bonding region, the first bonding region including more intermetallic compounds than the solder; and bonding the first semiconductor device to the second conductive pillar through a second bonding region, the second bonding region including more solder than the intermetallic compound. The embodiment of the invention also provides a package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, the increase in integration density stems from the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the need for smaller and more creative semiconductor die packaging technologies has emerged. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for forming a package, the method comprising: forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar comprises a barrier layer; joining a first semiconductor device to the first conductive pillar via a first joining region, the first joining region comprising more intermetallic compounds than solder; and joining the first semiconductor device to the second conductive pillar via a second joining region, the second joining region comprising more solder than the intermetallic compounds.

[0004] Other embodiments of the present disclosure provide a method for forming a package, the method comprising: performing a first deposition process to form a plurality of first metal pillars above a substrate; performing a second deposition process to form a plurality of second metal pillars above the substrate; performing a third deposition process to form a barrier layer on the plurality of second metal pillars; depositing solder material on the plurality of first metal pillars and on the plurality of second metal pillars; and bonding a plurality of tube cores to the plurality of first metal pillars and to the plurality of second metal pillars, comprising: placing the plurality of tube cores on the solder material; and performing a reflow process, wherein, after performing the reflow process, the solder material on the plurality of first metal pillars includes more intermetallic compounds than the solder material on the plurality of second metal pillars.

[0005] Another embodiment of the present disclosure provides a package, comprising: an interposer; and a semiconductor device attached to the interposer via a first connector and a second connector, wherein the first connector comprises a complete intermetallic compound region sandwiched between first conductive components, wherein the second connector comprises a solder region sandwiched between second conductive components, and wherein the second conductive components comprise a barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 Cross-sectional views are shown of intermediate steps in forming an interposer in accordance with some embodiments.

[0008] Fig.11 and Fig.12 Cross-sectional views are shown of intermediate steps in forming a package in accordance with some embodiments.

[0009] Fig.13 An enlarged cross-sectional view is shown of an intermediate step in forming a package in accordance with some embodiments.

[0010] Fig.14 Plan views are shown of intermediate steps in forming a package in accordance with some embodiments.

[0011] Fig.15 An enlarged cross-sectional view is shown of an intermediate step in forming a package in accordance with some embodiments.

[0012] Fig.16 An enlarged cross-sectional view is shown of an intermediate step in forming a package in accordance with some embodiments.

[0013] Fig.17 Cross-sectional views are shown of intermediate steps in forming a package in accordance with some embodiments.

[0014] Fig.18 and Fig.19 Cross-sectional views are shown of intermediate steps in forming a package in accordance with some embodiments.

[0015] Fig. 20 A cross-sectional view of a package attached to a packaging substrate is shown in accordance with some embodiments.

[0016] Fig.21 A cross-sectional view of a package according to some embodiments is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] A package and a method for forming the same are provided. According to some embodiments of the present disclosure, multiple types of connectors are used to physically and electrically connect the components of the package. For example, different types of connectors include connectors in which components are joined by complete intermetallic compound (IMC) regions and connectors in which components are joined by partial IMC regions. In some cases, a single component (e.g., a die, a semiconductor device, etc.) is connected by a majority of IMC connectors and a majority of solder connectors. In some cases, a majority of IMC connectors can provide increased tolerance to current density, while a majority of solder connectors can provide increased tolerance to stress. In this way, using these two types of connectors at appropriate locations within the package can improve the performance and reliability of the package.

[0020] The embodiments discussed herein are intended to provide examples so that the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily understand the modifications that may be made within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0021] Figures 1 to 19 The package 200 is manufactured according to some embodiments (see Fig.19). Specifically, by bonding the semiconductor device 250 to the interposer 100 (see Figure 11 to Figure 12 ) to form package 200. In some embodiments, two types of connectors are used to join semiconductor device 250: a first connector 120 includes a full intermetallic compound (IMC) bonding area 121, and a second connector 130 includes a partial IMC bonding area 131. Using different types of connectors as described herein in the same package can allow for improved stress tolerance, improved thermal performance, and improved high current operability. In an embodiment, package 200 is a chip on wafer (CoW) package, however it should be understood that embodiments can be applied to other three-dimensional integrated circuit (3DIC) packages. In an embodiment, package 200 can be part of a larger package, such as a chip on wafer on substrate (CoWoS) package, etc., however it should be understood that embodiments can be applied to other 3DIC packages. The background of using interposer 100 describes Figures 1 to 20 However, it should be understood that the embodiments herein may be applied to another structure, such as a silicon wafer, a carrier substrate, an organic core substrate, a die, a chip, a package, or any other suitable structure.

[0022] Figures 1 to 10 The interposer 100 (see FIG. Fig.10 ). According to some embodiments, the interposer 100 includes an interconnect structure 54 located on a substrate 50. In some embodiments, the substrate 50 may be a wafer, such as a silicon wafer. Other substrates, such as a silicon-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate may also be used. The substrate 50 may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. In other embodiments, the substrate 50 may be a dielectric material, such as silicon oxide, glass, ceramic, plastic, or any other suitable material that allows structural support for the above device. In some embodiments, multiple interposers 100 may be formed on a single substrate 50, and then may be subsequently singulated into individual interposers 100 or individual packages. In some embodiments, active devices (eg, transistors, diodes, etc.), passive devices (eg, capacitors, resistors, etc.), integrated circuits, etc. may be formed in substrate 50. In other embodiments, substrate 50 may not contain passive devices or active devices.

[0023] In some embodiments, the interposer 100 includes a through hole 52 extending into the substrate 50. The through hole 52 is electrically connected to the interconnect structure 54. The through hole 52 can be formed, for example, by forming an opening extending into the substrate 50. The opening can be formed using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process. Then, a conductive material may be formed in the opening to form the through hole 52. In some embodiments, a liner (not shown) may be deposited in the opening before forming the conductive material. The conductive material may include, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, their alloys, and the like. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the surface of the substrate 50 so that the through hole 52 and the surface of the substrate 50 are flush. In other embodiments, the through hole 52 may protrude from the substrate 50 and protrude into the interconnect structure 54. Other materials or techniques are also possible.

[0024] In some embodiments, the interconnect structure 54 includes one or more layers of conductive features 56 formed in one or more dielectric layers 58 (not shown separately). The conductive features 56 may include wires, conductive vias, conductive pads, metallization patterns, redistribution layers, etc. that provide electrical interconnection and electrical routing. In some embodiments, the conductive features 56 include conductive pads (not shown) located at the top surface of the interconnect structure 54 (such as located in the top dielectric layer 58). The conductive pads may be conductive pads, under-bump metallization (UBM), etc. In some embodiments, the interconnect structure 54 may have multiple layers of conductive features 56, but the exact number of layers of the conductive features 56 may depend on the design of the interconnect structure 54. The conductive features 56 may be formed using any suitable technique (such as deposition, damascene, dual damascene, etc.). The conductive features 56 may include, for example, metals or metal alloys such as copper, silver, gold, tungsten, cobalt, ruthenium, aluminum, alloys thereof, combinations thereof, etc. Other materials are also possible.

[0025] Acceptable dielectric materials for dielectric layer 58 include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. Dielectric layer 58 may be formed using any suitable technique. In some embodiments, interconnect structure 54 may have multiple dielectric layers 58, but the exact number of dielectric layers 58 may depend on the design of interconnect structure 54.

[0026] exist Figure 2In some embodiments, a seed layer 60 is formed over the interconnect structure 54. The seed layer 60 may be formed on the top dielectric layer 58 and may be formed on the exposed surface of the conductive component 56. For example, in some embodiments, before forming the seed layer 60, the conductive component 56 (not shown separately) of the interconnect structure 54 is exposed by patterning the upper dielectric layer 58. The upper dielectric layer 58 may be patterned using suitable photolithography and etching processes. In some cases, the exposed conductive component 56 is a conductive pad, a UBM, etc. In some embodiments, the seed layer 60 is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 60 includes a titanium layer and a copper layer located above the titanium layer. The seed layer 60 may be formed using, for example, PVD.

[0027] Figures 3 to 5 The formation of the first pillar 64 according to some embodiments is shown (see Figure 4 ).exist Figure 3 In some embodiments, a first plating mask 62 is formed over the seed layer 60. In some embodiments, the first plating mask 62 may be formed of a patterned photoresist. The photoresist may be formed by spin coating or the like, and the photoresist may be exposed to light for patterning. The pattern of the photoresist corresponds to the first pillar 64 (see Figure 4 ). The pattern forms openings 63 through the photoresist to expose seed layer 60. In some cases, openings 63 can expose portions of seed layer 60 that are deposited on conductive features 56.

[0028] exist Figure 4 In some embodiments, a conductive material is deposited in the opening 63 to form a first column 64. The conductive material may be formed on the portion of the seed layer 60 exposed by the opening 63. The conductive material may be formed by plating, such as electroplating or chemical plating. The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. The conductive material and the portion of the seed layer 60 below form the first column 64. In some embodiments, the first column 64 is formed to have a height in the range of about 10 μm to about 40 μm, however other heights are possible. In some embodiments, the first column 64 has a substantially vertical sidewall.

[0029] exist Figure 5 In some embodiments, the first plating mask 62 is removed. As an example, for embodiments where the first plating mask 62 is a photoresist, the photoresist can be removed using an acceptable ashing or stripping process (such as using oxygen plasma, etc.). In some embodiments, after the first plating mask 62 is removed, the portion of the seed layer 60 covered by the first plating mask 62 remains, such as Figure 5In other embodiments, after removing the first plating mask 62, the portion of the seed layer 60 covered by the first plating mask 62 is removed. In such embodiments, a suitable etching process (such as a wet etching process and / or a dry etching process) can be used to remove the exposed portion of the seed layer 60.

[0030] Figures 6 to 9 The formation of the barrier pillar 72 according to some embodiments is shown (see Figure 8 In other embodiments, the blocking column 72 is formed before the first column 64. Figure 6 In some embodiments, a second plating mask 66 is formed over the seed layer 60. In some embodiments, the second plating mask 66 may be formed of a patterned photoresist. The photoresist may be formed by spin coating or the like, and the photoresist may be exposed to light for patterning. The pattern of the photoresist corresponds to the subsequently formed blocking pillars 72 (see Figure 8 ) of the second column 68 (see Figure 7 ). The pattern forms openings 67 through the photoresist to expose the seed layer 60. In some cases, the openings 67 can expose a portion of the seed layer 60 deposited on the conductive features 56. In other embodiments, such as embodiments where the exposed portion of the seed layer 60 is removed, a second seed layer can be deposited over the interconnect structure 54 before forming the second plating mask 66. In such embodiments, the second seed layer can be similar to the first seed layer 60.

[0031] exist Figure 7 In some embodiments, a conductive material is deposited in the opening 67 to form a second pillar 68. The conductive material may be formed on the portion of the seed layer 60 exposed by the opening 67. The conductive material may be formed by plating, such as electroplating or chemical plating. The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. In some cases, the conductive material may be similar to the conductive material of the first pillar 64. In some embodiments, the second pillar 68 is formed to have a height in the range of about 5 μm to about 30 μm, but other heights are possible. In some embodiments, the second pillar 68 has substantially vertical sidewalls. In some embodiments, the height of the second pillar 68 is less than the height of the first pillar 64. In other embodiments, the first pillar 64 and the second pillar 68 are formed using the same deposition process using the same patterned plating mask.

[0032] exist Figure 8 In accordance with some embodiments, a barrier layer 70 is formed on the second pillar 68 to form a barrier pillar 72 . Figure 8An enlarged cross-sectional view of a portion of the structure is included. The barrier layer 70, the second column 68, and the portion of the seed layer 60 below form a barrier column 72. The barrier layer 70 includes a conductive material that inhibits intermetallic diffusion, and thus can inhibit the subsequent formation of an intermetallic compound (IMC) on the second column 68. In some embodiments, the barrier layer 70 includes a conductive material such as cobalt, nickel, etc., or a combination thereof. In other embodiments, barrier layers of different materials can be deposited on different second columns 68. The barrier layer 70 can be deposited using a suitable technique, such as plating (e.g., electroplating or chemical plating) or another technique. In some embodiments, the thickness of the barrier layer 70 is in the range of about 5 μm to about 20 μm, but other thicknesses are also possible. In some embodiments, the height of the barrier column 72 is approximately the same as the height of the first column 64. In other embodiments, the height of the barrier column 72 is greater than or less than the height of the first column 64.

[0033] exist Fig. 9 In some embodiments, the second plating mask 66 is removed. As an example, for embodiments where the second plating mask 66 is a photoresist, the photoresist can be removed using an acceptable ashing or stripping process (such as using oxygen plasma, etc.). In addition, after the second plating mask 66 is removed, the portion of the seed layer 60 covered by the second plating mask 66 is removed. In such embodiments, a suitable etching process (such as a wet etching process and / or a dry etching process) can be used to remove the exposed portion of the seed layer 60. In some cases, when etching the seed layer 60, the etching process uses the first pillar 64 and the blocking pillar 72 as an etching mask.

[0034] exist Fig.10In some embodiments, a solder material 74 is formed on the first column 64 to form a first connector 76, and a solder material 74 is formed on the blocking column 72 to form a blocking connector 78. The solder material 74 may include a solder layer, a solder ball, a solder bump, etc. The solder material 74 may include a conductive material such as solder, silver, tin, etc., or a combination thereof. In some embodiments, the solder material 74 is formed by forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, stencil printing, etc. In some embodiments, once the solder material 74 is formed on the first column 64 and the blocking column 72, a reflow process may be performed to shape the solder material 74 into a desired bump shape. In some embodiments, the reflow process causes the solder material 74 and the first column 64 to diffuse into each other and form an intermetallic compound (IMC) in the first connector 76. For example, in an embodiment where the first column 64 includes copper and the solder material 74 includes tin, the IMC may include CuSn (e.g., Cu3Sn, Cu6Sn5, etc.). In such embodiments, the presence of barrier layer 70 reduces or prevents interdiffusion between solder material 74 and second pillar 68, and thus little or no IMC is formed within barrier connector 78. In some cases, first connector 76 and barrier connector 78 may be microbumps, etc. In some embodiments, because no barrier layer is formed on first pillar 64, first connector 76 may be considered a "non-barrier" connector.

[0035] Figures 11 to 19 The package 200 is manufactured according to some embodiments (see Fig.19 ) in various views of the intermediate stages. Figure 11 to Figure 12 In accordance with some embodiments, semiconductor devices 250 (eg, semiconductor devices 250A and 250B) are bonded to interposer 100 . Fig.11 shows a semiconductor device 250 before bonding, and Fig.12 The semiconductor device 250 is shown after bonding. Figure 11 to Figure 12 The semiconductor devices 250 shown in are examples, and the semiconductor devices 250 may have different numbers, arrangements, types, sizes, or other characteristics than described herein.

[0036] The semiconductor device 250 may include, for example, a chip, a die, a system on chip (SoC) device, a system on integrated circuit (SoIC) device, a package, etc., or a combination thereof. In some embodiments, the semiconductor device 250 includes a logic die, a memory die, an input output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, the semiconductor device 250 may include a logic die, such as a central processing unit (xPU or CPU) die, a graphics processing unit (GPU) die, a mobile application die, a micro control unit (MCU) die, a baseband (BB) die, an application processor (AP) die, an application specific integrated circuit (ASIC) die, a high performance computing (HPC) die, etc. The semiconductor device 250 may include a memory die, such as a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a high performance memory (HBM) die, etc. Other types of semiconductor devices 250 are also possible. Figure 11 to Figure 12 Two types of semiconductor devices 250 are shown, represented by semiconductor device 250A and semiconductor device 250B. For example, in some embodiments, semiconductor device 250A may be a logic die and semiconductor device 250B may be a memory die. This is an example, and other numbers, types, arrangements, configurations, or combinations are possible.

[0037] According to some embodiments, the semiconductor device 250 includes a first connector 256 and / or a barrier connector 258. In some embodiments, the first connector 256 can be similar to the first connector 76 described for the interposer 100, and the barrier connector 258 can be similar to the barrier connector 78 described for the interposer 100. For example, the first connector 256 can include a solder material 254 located on the conductive pillar 244, and the solder material 254 and the conductive pillar 244 can be similar to the solder material 74 and the first pillar 64 of the first connector 76. Accordingly, the first connector 256 can be "unblocked", similar to the first connector 76. The barrier connector 258 can include a barrier layer 248 located between the conductive pillar 246 and the solder material 254, and the barrier layer 248, the conductive pillar 246, and the solder material 254 can be similar to the barrier layer 70, the second pillar 68, and the solder material 74 of the barrier connector 78. For example, in some embodiments, the barrier layer 248 can include cobalt, nickel, etc. The conductive pillar 246 and the barrier layer 248 form a barrier pillar 249. In other embodiments, solder material 254 is not formed on first connector 256 and / or barrier connector 258. First connector 256 and barrier connector 258 may be formed using suitable materials and techniques, including those previously described for forming first connector 76 or barrier connector 78.

[0038] A single semiconductor device 250 may have a first connector 256, a blocking connector 258, or a combination thereof. Fig.11 , semiconductor device 250B has only barrier connector 258, but semiconductor device 250A has both first connector 256 and barrier connector 258. In some cases, semiconductor device 250 may have only first connector 256. In some embodiments, first connector 256 of semiconductor device 250 is subsequently bonded to corresponding first connector 76 of interposer 100, and barrier connector 258 of semiconductor device 250 is subsequently bonded to corresponding barrier connector 78 of interposer 100. As described below, using different types of connectors (76, 78, 256, and / or 258) within the same package may improve stress tolerance.

[0039] According to some embodiments, Fig.12 In the process, the semiconductor device 250 is bonded to the interposer 100 . Fig.13 It shows that Fig.12 1. An enlarged portion of the structure shown. The first connector 256 of the semiconductor device 250 is aligned with and placed in contact with the corresponding first connector 76 of the interposer 100, and the barrier connector 258 of the semiconductor device 250 is aligned with and placed in contact with the corresponding barrier connector 78 of the interposer 100. A reflow process may then be performed to bond the first connector 256 to the first connector 76 and the barrier connector 258 to the barrier connector 78. The reflow process melts the solder material (e.g., solder material 74 / 254), thereby forming a bonding area 121 that bonds the first connector 76 to the first connector 256 and a bonding area 131 that bonds the barrier connector 78 to the barrier connector 258. The first connector 76, the first connector 256, and the bonding area 121 collectively form the first connector 120, and the barrier connector 78, the barrier connector 258, and the bonding area 131 collectively form the second connector 130. In other embodiments, the first connector 76 and / or the barrier connector 78 are part of a local silicon interconnect (LSI) or a chiplet within the interposer 100 .

[0040] In some embodiments, the intermetallic diffusion between the solder material 74 / 254 and the pillar 76 / 256 forms a joint region 121 that substantially includes an intermetallic compound (IMC). For example, in some embodiments, the joint region 121 may include an IMC, such as Cu3Sn, Cu6Sn5, etc., or a combination thereof. In some embodiments, all of the solder material 74 / 254 may react so that the joint region 121 of the first connector 120 is completely formed by IMC. Accordingly, the joint region 121 may also be referred to herein as an IMC joint region 121 or an IMC region 121. Therefore, in some cases, the first connector 120 may also be referred to herein as an IMC connector 120, a "mostly IMC" connector 120, or a "completely IMC" connector 120. In some embodiments, the joint region 121 includes an IMC region between about 90% and about 100%.

[0041] In some embodiments, the barrier layer 70 / 248 of the barrier connector 78 / 258 inhibits intermetallic diffusion so that little or no IMC is formed in the bonding area 131 of the second connector 130. In this way, the bonding area 131 can be a solder-rich area that substantially includes unreacted solder material 74 / 254 with little or no IMC present. In some embodiments, the bonding area 131 includes between about 90% and about 100% IMC-free solder. In other words, in some embodiments, the bonding area 131 includes less than about 10% IMC. For example, in some embodiments, the atomic composition of the bonding area 131 is between about 90% tin and about 100% tin. Other compositions or ratios are also possible. Accordingly, in some cases, the bonding area 131 may also be referred to herein as a solder area 131, a "mostly solder" bonding area 131, or a "partial IMC" bonding area 131. Therefore, in some cases, the second connector 130 may also be referred to herein as a solder connector 130 , a “mostly solder” connector 130 , or a “partial IMC” connector 130 .

[0042] In some embodiments, the first connector 120 and / or the second connector 130 have a height in the range of about 35 μm to about 60 μm. Accordingly, the average height of all connectors 120 / 130 on the interposer 100 is in the range of about 35 μm to about 60 μm. In some embodiments, the height of each connector 120 / 130 differs from the average height by no more than about 15% of the average height. In other words, in some embodiments, the height of each connector 120 / 130 is between about 85% and about 115% of the average height. In some embodiments, the sum of the height of the first pillar 64 and the height of the corresponding first pillar 244 is between about 35% and about 60% of the total height of the connector 120. In some embodiments, the sum of the height of the blocking pillar 72 and the height of the corresponding blocking pillar 244 is between about 35% and about 60% of the total height of the connector 120. Other heights or ratios are also possible.

[0043] Fig.14 shows a method similar to that of Fig.12 Schematic plan view of the structure shown. Accordingly, Fig.14 The plan view may also correspond to the subsequently formed package 200 (see Fig.18 ). Fig.12 shows a similar Fig.14 The reference cross section represented in Fig.12 Cross-sectional view of a cross section. Fig.17 shows a similar Fig.14 The reference cross section represented in Fig.17 In addition, Fig.15 The reference cross sections A-A' and B-B' are shown. Fig.14 For clarity, Fig.14 For example, for ease of illustration, Fig.14 Representative connectors 120 and 130 are shown in FIG. 1 , but it should be understood that more connectors 120 / 130 may be present in the structure. Fig.14 A structure including two adjacent semiconductor devices 250A is shown, where each semiconductor device 250A is adjacent to two semiconductor devices 250B. For example, in some embodiments, the semiconductor device 250A may be a SoC die, and the semiconductor device 250B may be a memory die. Fig.14 The structures shown are examples, and other types, arrangements, numbers, configurations, or sizes of semiconductor devices 250 are possible.

[0044] like Fig.14As shown, an electrical connection between adjacent semiconductor devices 250A is made through interposer 100 using IMC connectors 120, and an electrical connection between adjacent semiconductor devices 250A and semiconductor devices 250B is made through interposer 100 using solder connectors 130. In some embodiments, solder connectors 130 are used in relatively high stress regions of the structure, and an approximate example of a relatively high stress region is shown as high stress region 230. In some cases, high stress region 230 may include regions adjacent to two semiconductor devices 250, such as a region between semiconductor device 250A and adjacent semiconductor device 250B, such as Fig.14 In some cases, high stress region 230 can include an area relatively close to an edge of the structure. Fig.14 The high stress regions 230 shown are examples, and other numbers, locations, sizes, or shapes of high stress regions 230 are possible.

[0045] In some embodiments, solder connections 130 can be used to connect semiconductor devices 250 to interposer 100 in high stress regions 230. In some embodiments, the use of solder connections 130 in high stress regions 230 can improve stress tolerance and robustness to thermal shock in these regions. In this way, the reliability and performance of the package can be improved. In some embodiments, semiconductor devices 250 within high stress regions 230 can be connected to interposer 100 only via solder connections 130, but in other embodiments, both IMC connections 120 and solder connections 130 can be used to connect semiconductor devices 250.

[0046] In some embodiments, IMC connectors 120 may be used in relatively low stress areas of a structure. Fig.14 , low stress region 220 represents an approximate example of a relatively low stress region. In some cases, low stress region 220 may include a region adjacent to two semiconductor devices 250, such as Fig.14 In some cases, low stress region 220 can be relatively close to the center of the structure. Fig.14 The low stress regions 220 shown in FIG. 2 are examples, and other numbers, locations, sizes, or shapes of low stress regions 220 are possible.

[0047] In some embodiments, the IMC connectors 120 can be used to connect the semiconductor device 250 to the interposer 100 in the low stress region 220. Because the IMC connectors 120 include a complete IMC bonding area 121, the IMC connectors 120 can allow for higher current densities than solder connectors 130. In some embodiments, the use of the IMC connectors 120 in the low stress region 220 can allow for higher currents and improved electromagnetic properties in these regions. In this way, the reliability and performance of the package can be improved. Additionally, in some cases, the IMC connectors 120 can be used in other areas where high current density is required. In some embodiments, the semiconductor device 250 within the low stress region 220 can be connected to the interposer 100 using both the IMC connectors 120 and the solder connectors 130. For example, the semiconductor device 250 can be connected to the interposer 100 by both the IMC connectors 120 and the solder connectors 130. Fig.14 2 , wherein the electrical connection with the adjacent semiconductor device 250A is made through the IMC connector 120, and the electrical connection with the adjacent semiconductor device 250B is made through the solder connector 130. In some embodiments, the IMC connector 120 can be located near the edge of the semiconductor device 250 relatively close to the center of the structure, but the IMC connector 120 can be located at any suitable location. In other embodiments, the semiconductor device 250 can be connected only through the IMC connector 120. In some embodiments, the semiconductor device 250 can have an IMC connector 120 adjacent to one edge and a solder connector 130 adjacent to another edge.

[0048] In some embodiments, a dummy solder connection 140 may be formed in the low stress region 220 to provide additional structural support and thermal robustness. In some embodiments, the dummy solder connection 140 may be similar to the solder connection 130 described above, except that the dummy solder connection 140 is not used to make an electrical connection between the semiconductor device 250 and the interposer 100. In some cases, the dummy solder connection 140 may be electrically isolated from the functional conductive components of the semiconductor device 250 and / or the interposer 100. The dummy solder connection 140 may be formed using materials or techniques similar to the solder connection 130 described above. For example, in some embodiments, the solder connection 130 and the dummy solder connection 140 may be formed simultaneously using the same process steps. Accordingly, in some embodiments, the blocking column forming the dummy solder connection 140 may be regarded as a dummy blocking column.

[0049] Fig.16 Shows something like Fig.15 , except that dummy solder connections 140 are used instead of IMC connections 120. Fig.16140 are illustrative examples, and any suitable number of dummy solder connections 140 may be used in any suitable location. For example, in other embodiments, dummy solder connections 140 may be used with two adjacent semiconductor devices 250A, or may be used in locations that are not near the edge of semiconductor device 250A. In some embodiments, dummy solder connections 140 may be used in place of IMC connections 120 or in addition to IMC connections 120. Other arrangements of dummy solder connections 140 are also possible.

[0050] exist Fig.18 In some embodiments, the semiconductor device 250 is sealed. In some embodiments, the bottom filler 260 is dispensed into the gap between the semiconductor device 250 and the interposer 100. In some cases, the bottom filler 260 may also be dispensed between adjacent semiconductor devices 250. According to some embodiments, the bottom filler 260 includes a matrix material and filler particles mixed in the matrix material. The matrix material may be a resin, an epoxy resin, a polymer, etc., or a combination thereof. Some exemplary matrix materials include epoxy amine, epoxy anhydride, epoxy phenol, etc., or a combination thereof. The filler particles may be formed of a dielectric material and may include silicon dioxide, aluminum oxide, boron nitride, etc., or a combination thereof. The filler particles may have a spherical or other shape. In some embodiments, the bottom filler 260 is dispensed in a flowable form, and then the bottom filler 260 is cured. Other materials or deposition techniques are also possible. In other embodiments, the bottom filler 260 is not present.

[0051] Then, according to some embodiments, the semiconductor device 250 is sealed in a sealant 262. The sealant 262 may be, for example, a molding compound, a molded underfill, an epoxy resin, a resin, or the like, or a combination thereof. The sealant 262 may include a matrix material and a filler located in the matrix material. The matrix material may include a polymer material, which may be or may include a plastic, an epoxy resin (such as an epoxy cresol novolac resin (ECN), a biphenyl epoxy resin, or a multifunctional liquid epoxy resin), a polyimide, a polyethylene terephthalate (PET), a polyvinyl chloride (PVC), a polymethyl methacrylate (PMMA), or the like, or a combination thereof. The filler may include titanium dioxide, carbon black, calcium carbonate, silicon dioxide, fiber, clay, ceramics, inorganic particles, or the like, or a combination thereof, and the filler may be in the form of filler particles.

[0052] In some embodiments, a planarization process is then performed to remove excess portions of the encapsulant 262. The planarization process may include, for example, a chemical mechanical polishing (CMP) process, a mechanical grinding process, etc., or a combination thereof. In some embodiments, the planarization process exposes one or more semiconductor devices 250. In some embodiments, after the planarization process is performed, the top surfaces of the encapsulant 262 and the one or more semiconductor devices 250 are flush or coplanar.

[0053] exist Fig.19 In some embodiments, a conductive connector 270 is formed on the interposer 100. In some embodiments, a planarization process (e.g., CMP or grinding process) may be performed on the substrate 50 to expose the through-hole 52. In some embodiments, a conductive component such as a redistribution layer, a UBM, etc. (not shown) may then be formed over the substrate 50 and over the exposed through-hole 52. In some embodiments, a conductive connector 270 is formed over the substrate 50 and over the exposed through-hole 52. The conductive connector 270 may be electrically connected to the through-hole 52. The conductive connector 270 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. The conductive connector 270 may be formed of a reflowable conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 270 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 270 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and the metal capping layer can be formed by a plating process.

[0054] In this way, a package 200 including an IMC connector 120 and a solder connector 130 may be formed. In other embodiments, other processes or techniques may be used. In some embodiments, multiple packages 200 are formed on the same substrate 50 and then singulated into individual packages 200.

[0055] exist Fig. 20In some embodiments, the package 200 is attached to the package substrate 300. The package 200 can be physically connected and electrically connected to the package substrate 300 by the conductive connector 270. The package substrate 300 may include conductive pads, conductive wiring, and / or other conductive components that provide interconnection and electrical wiring. In some embodiments, the package substrate 300 may include an interposer, a semiconductor substrate (e.g., a wafer), a redistribution structure, an interconnect substrate, a core substrate, a printed circuit board (PCB), etc. In some embodiments, the package substrate 300 does not contain active devices and / or passive devices. In other embodiments, the package substrate 300 does not have active and / or passive devices. In some embodiments, a bottom filler (not shown) is formed between the package 200 and the package substrate 300. In some embodiments, a conductive connector 310 is formed on the package substrate 300, and the conductive connector 310 may be similar to the conductive connector 270 described previously.

[0056] Fig.21 A package 400 is shown in accordance with some embodiments. Package 400 is similar to package 200, except that a redistribution interposer 410 and local interconnects 450 are used instead of interposer 100. For example, semiconductor device 250 may be connected to redistribution interposer 410 and / or local interconnects 450 via IMC connectors 120 and / or solder connectors 130.

[0057] The redistribution interposer 410 may be, for example, an organic interposer, a redistribution structure, etc. The redistribution interposer 410 may include a plurality of redistribution layers formed in a plurality of dielectric layers (not shown separately). The redistribution layer may include a conductive wire, a conductive via, a conductive pad, etc. The redistribution layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, a combination thereof, etc. The redistribution interposer 410 may also include other conductive components, such as metallization patterns, through-holes, etc. In some embodiments, the dielectric layer may include a polymer, such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, etc. In other embodiments, the dielectric layer may include other suitable dielectric materials, such as silicon oxide, etc. Any suitable process may be used to form the redistribution layer, such as deposition, plating, inlay, dual inlay, etc. In some embodiments, the redistribution interposer is substantially free of active devices and passive devices. In some cases, the use of the redistribution interposer 410 may reduce manufacturing costs and package size.

[0058] The local interconnect 450 may be, for example, a chip, a chiplet, a local silicon interconnect (LSI), an interconnect structure, etc., that provides additional electrical interconnects within the redistribution interposer 410. For example, the local interconnect 450 may provide an electrical connection (e.g., a bridge connection) between adjacent semiconductor devices 250. Accordingly, in some embodiments, the IMC connector 120 and / or the solder connector 130 may be formed on the local interconnect 450. The local interconnect 450 may include a conductive feature (e.g., a wire, a via, a pad, etc.) formed in a dielectric layer. The conductive feature may be formed using suitable techniques, such as damascene, dual damascene, etc. For example, in some cases, the local interconnect 450 may include an interconnect structure located on a substrate, which may have a through substrate via (TSV) therein, however other local interconnects 450 are also possible. The local interconnect 450 may or may not include passive devices or active devices. Fig.21 The local interconnects 450 shown in FIG. 4 are illustrative examples, and the local interconnects 450 may have a different arrangement, number, configuration, or size than shown. In other embodiments, the local interconnects 450 are formed in an interposer similar to the interposer 100 described previously.

[0059] Embodiments of the present disclosure have some advantageous features. Using complete IMC connectors and partial IMC connectors to form a package between a semiconductor device and an interposer can allow the advantages of these two types of connectors to be utilized in the same package. For example, complete IMC connectors can withstand high current density, and partial IMC connectors are robust to physical and thermal stresses. Therefore, in the embodiments described herein, complete IMC connectors can be used in relatively low stress areas and / or areas where high current density is important, and partial IMC connectors can be used in relatively high stress areas and / or areas where high current density is less important. In this way, by utilizing both complete IMC connectors and partial IMC connectors, the package can have improved electrical performance, improved robustness, and improved thermal tolerance. In some embodiments, two types of connectors can be used to connect semiconductor devices.

[0060] In an embodiment of the present disclosure, a method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar through a first bonding region, the first bonding region including more intermetallic compound than solder; and bonding the first semiconductor device to the second conductive pillar through a second bonding region, the second bonding region including more solder than the intermetallic compound. In an embodiment, the first conductive pillar is copper. In an embodiment, the barrier layer is cobalt or nickel. In an embodiment, the first conductive pillar is formed before the second conductive pillar. In an embodiment, forming the second conductive pillar includes forming a copper pillar, and depositing the barrier layer on the copper pillar. In an embodiment, bonding the first semiconductor device to the second conductive pillar includes depositing a solder layer on the second conductive pillar; placing a third conductive pillar of the first semiconductor device on the solder layer, wherein the third conductive pillar includes the barrier layer; and performing a reflow process. In an embodiment, the method includes forming a fourth conductive pillar on the interposer; and bonding the second semiconductor device to the fourth conductive pillar through a third bonding region, the third bonding region including more solder than the intermetallic compound. In an embodiment, the first bonding region is free of solder. In an embodiment, less than 10% of the second bonding region is intermetallic.

[0061] In an embodiment of the present disclosure, a method includes performing a first deposition process to form a first metal pillar above a substrate; performing a second deposition process to form a second metal pillar above the substrate; performing a third deposition process to form a barrier layer on the second metal pillar; depositing a solder material on the first metal pillar and on the second metal pillar; and bonding a die to the first metal pillar and to the second metal pillar, bonding the die to the first metal pillar and to the second metal pillar including: placing the die on the solder material; and performing a reflow process, wherein after performing the reflow process, the solder material on the first metal pillar includes more intermetallic compounds than the solder material on the second metal pillar. In an embodiment, the first metal pillar does not contain a barrier layer. In an embodiment, the die is bonded to both the first metal pillar and the second metal pillar. In an embodiment, the intermetallic compound includes Cu3Sn or Cu6Sn5. In an embodiment, at least one second metal pillar is a pseudo pillar. In an embodiment, the first metal pillar is closer to the center of the substrate than the second metal pillar.

[0062] In an embodiment of the present disclosure, a method of forming a package includes: performing a first deposition process to form a plurality of first metal pillars over a substrate; performing a second deposition process to form a plurality of second metal pillars over the substrate; performing a third deposition process to form a barrier layer on the plurality of second metal pillars; depositing a solder material on the plurality of first metal pillars and on the plurality of second metal pillars; and bonding a plurality of dies to the plurality of first metal pillars and to the plurality of second metal pillars, including: placing the plurality of dies on the solder material; and performing a reflow process, wherein after performing the reflow process, the solder material on the plurality of first metal pillars includes more intermetallic compounds than the solder material on the plurality of second metal pillars. In an embodiment, the plurality of first metal pillars do not contain a barrier layer. In an embodiment, a die in the plurality of dies is bonded to both the first metal pillar and the second metal pillar. In an embodiment, the intermetallic compound includes Cu3Sn or Cu6Sn5. In an embodiment, at least one second metal pillar is a pseudo pillar. In an embodiment, the plurality of first metal pillars are closer to the center of the substrate than the plurality of second metal pillars.

[0063] In an embodiment of the present disclosure, a package includes an interposer; and a semiconductor device attached to the interposer by a first connector and a second connector, wherein the first connector includes a complete intermetallic compound region sandwiched between first conductive components, wherein the second connector includes a solder region sandwiched between second conductive components, and wherein the second conductive components include a barrier layer. In an embodiment, a total height of the first conductive component of the first connector is between 35% and 60% of the total height of the first connector. In an embodiment, an average height of the first connector and the second connector is between 35μm and 60μm. In an embodiment, the second conductive component includes a barrier layer located on a copper pillar. In an embodiment, the first connector is adjacent to a first edge of the semiconductor device, and the second connector is adjacent to a second edge of the semiconductor device.

[0064] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package, comprising: forming a first conductive pillar on the interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar comprises a barrier layer; bonding a first semiconductor device to the first conductive pillar through a first bonding region, the first bonding region including more intermetallic compound than solder; and The first semiconductor device is bonded to the second conductive pillar through a second bonding region, the second bonding region including more solder than intermetallic compound.

2. The method according to claim 1, wherein: The first conductive pillar is copper.

3. The method according to claim 1, wherein: The barrier layer is cobalt or nickel.

4. The method according to claim 1, wherein: The first conductive pillar is formed before the second conductive pillar.

5. The method according to claim 1, wherein: Forming the second conductive pillar includes: forming copper pillars; and The barrier layer is deposited on the copper pillar.

6. The method according to claim 1, wherein: Bonding the first semiconductor device to the second conductive pillar includes: depositing a solder layer on the second conductive pillar; placing a third conductive pillar of the first semiconductor device on the solder layer, wherein the third conductive pillar comprises a barrier layer; and A reflow process is performed.

7. The method according to claim 1, further comprising forming a fourth conductive pillar on the interposer; and The second semiconductor device is bonded to the fourth conductive pillar through a third bonding region, the third bonding region including more solder than intermetallic compound.

8. The method according to claim 1, wherein: The first bonding region is free of solder.

9. A method of forming a package, comprising: performing a first deposition process to form a plurality of first metal pillars over the substrate; performing a second deposition process to form a plurality of second metal pillars over the substrate; performing a third deposition process to form a barrier layer on the plurality of second metal pillars; depositing a solder material on the plurality of first metal pillars and on the plurality of second metal pillars; as well as Bonding a plurality of dies to the plurality of first metal pillars and to the plurality of second metal pillars, comprising: placing the plurality of dies on the solder material; and A reflow process is performed, wherein after performing the reflow process, the solder material on the plurality of first metal pillars includes more intermetallic compounds than the solder material on the plurality of second metal pillars.

10. A package comprising: Intermediary layer; as well as A semiconductor device is attached to the interposer via a first connector and a second connector, wherein the first connector includes a complete intermetallic compound region sandwiched between first conductive components, wherein the second connector includes a solder region sandwiched between second conductive components, and wherein the second conductive components include a barrier layer.

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