High-reliability packaging lead-out structure of high-power-consumption device
By adopting vertical interconnection and a column-gate array interconnect structure with high length and thin ratio, the problems of large on-resistance and large size of the package structure of traditional high-power consumption devices are solved, and a high performance, high reliability and miniaturization package effect is achieved.
Patent Information
- Application Number
- CN202411926560.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-05-06
AI Technical Summary
The traditional high-power device packaging structure cannot meet the development needs of high performance, high reliability and miniaturization, especially because the bonded wire structure has a large on-resistance and weak load current capacity, it cannot meet the high-performance requirements of high-power devices.
The vertical interconnection method is adopted to achieve efficient outlet of the source, gate and drain through ceramic shell, chip, ceramic cover plate and column gate interconnect structure, reduce current conduction paths, and use a high-length and thin column gate array interconnect structure and high-flexible organic underfill material to improve structural stability and reliability.
It greatly shortens the current conduction path, reduces the current on resistance, improves circuit performance, meets the requirements of larger working current and high power consumption, and greatly reduces the finished device size, solving the high performance, high reliability and miniaturization problems of traditional packaging structures.
Smart Images
Figure CN119943761A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a high-reliability packaging lead-out structure for a large-power-consumption device. Background Art
[0002] In the post-Moore's Law era, as Moore's Law approaches its physical limits, development requirements for integrated circuit packaging such as high performance, high integration, and miniaturization are put forward.
[0003] Traditional high-power devices generally use ceramic packaging, usually in the form of wire bonding. Wire-bonded devices generally occupy a large space due to the bonding wire span problem. At the same time, high-power devices generally require the device package to have an on-resistance as small as possible and a current-carrying capacity as strong as possible. Compared with the new generation of direct-connect flip-chip packaging, the bonding wire structure has a large on-resistance and a weak current-carrying capacity, which cannot meet the high-performance development needs of high-power devices.
[0004] The upper and lower direct-connected MOS packaging structure adopts a vertical interconnection method with a shorter conduction path. The drain is directly connected to the surface coating of the cover plate, and the source and gate are led out to the external electrode through electrode block welding. However, for the upper and lower direct-connected MOS packaging structure, the upper and lower surfaces of the chip are in a completely mechanically fixed state. The mismatch of the coefficient of thermal expansion (CTE) between materials such as the chip (about 2.54×10-6 / K) and the shell (about 9.042×10-6 / K), the thermal gradient and geometric constraints in the system will bring more reliability problems to the structure. Summary of the invention
[0005] In order to solve the problem that the packaging structure in the prior art cannot meet the development demand of high performance of high-power consumption devices, the present invention provides a high-reliability packaging lead-out structure for high-power consumption devices, including a ceramic housing, a chip, a ceramic cover, a column grid interconnection structure, a source pin, a gate pin, a drain pin, a chip drain solder and a cover sealing solder;
[0006] The ceramic shell and the ceramic cover plate are sealed and welded by the cover plate sealing solder, a cavity is formed between the ceramic shell and the ceramic cover plate, the chip is arranged in the cavity between the ceramic shell and the ceramic cover plate, and the back side of the chip is welded to the ceramic cover plate by the chip drain solder;
[0007] The chip front source and gate regions are welded to the ceramic housing through the column-grid interconnection structure, and the chip front source and gate are respectively led out to the source pin and the gate pin through the column-grid interconnection structure and the ceramic housing;
[0008] The back side of the chip is led out to the drain pin through the chip drain solder, the ceramic cover, the cover sealing solder and the ceramic housing.
[0009] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the ceramic shell is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, each layer of the ceramic body includes a wiring structure corresponding to the source, gate and drain, and a cavity is provided inside the ceramic shell, and a source metallization welding area and a gate metallization welding area are provided on the inner surface of the cavity;
[0010] The source pin and the gate pin are connected to the source metallization welding area and the gate metallization welding area respectively through internal wiring of the ceramic housing.
[0011] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the chip includes a chip substrate, a source PAD, a gate PAD, and a drain PAD;
[0012] The source PAD and gate PAD are located on the front side of the chip substrate and are connected to the chip source and gate respectively. The surfaces of the source PAD and gate PAD are reserved with pads that can be used for electroplating growth or preparation of the column gate interconnect structure, and are respectively connected to the source metallization welding area and the gate metallization welding area through the column gate interconnect structure, and are finally led out to the source pin and the gate pin through the ceramic housing.
[0013] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the column-gate interconnect structure is an array-arranged Cu column structure or an array-arranged PbSn solder column structure.
[0014] According to a high-power consumption device high-reliability package lead-out structure provided by some embodiments of the present application, when the column grid interconnection structure adopts an array-arranged Cu column structure, it is prepared by electroplating process, the common column diameter is 0.02mm or 0.025mm, the column aspect ratio is greater than 2, and its structure is Cu / X, Cu / Ni / X or Cu / Ni / Cu / X, wherein X is SnAg, SnAgCu or PbSn tin cap solder;
[0015] When the column grid interconnect structure adopts an array-arranged PbSn solder column structure, it is prepared by a column planting process. The column diameters include 0.89mm, 0.76mm, 0.65mm, and 0.635mm. The column aspect ratio is greater than 2. The solder column material types are 90Pb10Sn columnar solder columns and 80Pb20Sn copper-clad solder columns.
[0016] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, surfaces of the source metallization welding area and the gate metallization welding area are reserved for electroplating growth or preparation of pads for the column gate interconnect structure.
[0017] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the column grid interconnect structure is arranged in a standard array or in a staggered array.
[0018] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the solder selected for welding the upper and lower ends of the column grid interconnect structure includes: any one of: gold-based solder, tin-lead solder, indium-based solder and nano-sintered material.
[0019] According to a high-reliability package lead-out structure for a high-power consumption device provided in some embodiments of the present application, the ceramic cover material is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, and a wiring structure corresponding to the drain is arranged between each layer of the ceramic body;
[0020] The ceramic cover plate comprises a metallized adhesive sheet area, a sealing welding area, a solder resist ring and a cover plate base, wherein the metallized adhesive sheet area, the sealing welding area and the solder resist ring are arranged in different areas on the cover plate base;
[0021] The upper surface of the metallized adhesive area is welded to the drain PAD on the back of the chip substrate, and the lower surface is electrically connected to the sealing welding area and the cover sealing solder through the internal wiring of the ceramic cover, and finally led out to the drain pin through the ceramic housing;
[0022] The solder resist ring is located between the metallized die bonding area and the sealing welding area.
[0023] According to some embodiments of the present application, a high-reliability package lead-out structure for a high-power consumption device also includes a filling glue, which is a high-flexibility organic bottom filling glue material or a potting glue material. The filling glue fills the gaps between the column grid interconnect structures and covers the chip.
[0024] Beneficial effects of the present invention:
[0025] Compared with the traditional wire bonding packaging structure, the present invention adopts a vertical interconnection method, which greatly shortens the current conduction path, reduces the current conduction resistance, improves the circuit performance, and meets the requirements of larger operating current and high power consumption.
[0026] The vertical space of the package is greatly developed and utilized. Since the bonding wire structure is no longer used, the problem of the bonding wire occupying a large space is effectively avoided, the size of the finished device is greatly reduced, and the problems of high performance, high reliability, and miniaturization of wire bonding chip packaging are effectively solved.
[0027] The source and gate sides of the chip use a high aspect ratio column grid array interconnection structure, which has high deformation resistance, can absorb the large stress caused by the double-sided fixed structure, and improve structural stability.
[0028] The column grid array interconnect structure used in the present invention is a Cu column or a PbSn solder column. When the Cu column is selected, the electrical conductivity and thermal conductivity of Cu are about 10 times higher than those of tin-lead solder, and the anti-electromigration property is better, which is suitable for narrow pitch interconnection of high-power devices and greatly improves circuit performance. For large-size chips, the PbSn solder column is selected, which has higher reliability than the Cu column, and has advantages in the supply chain, and is more suitable for wide pitch interconnection.
[0029] The present invention selects a highly flexible organic bottom filling glue material or a potting glue material to fill all gaps between the column grid interconnection structures, thereby increasing the overall reliability and heat resistance of the structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0031] Figure 1 is a cross-sectional schematic diagram of the lead-out structure of some embodiments of the present application;
[0032] Figure 2 is a schematic diagram of the lead-out structure of some embodiments of the present application;
[0033] Figure 3 is a schematic diagram of the ceramic housing structure of some embodiments of the present application;
[0034] Figure 4 is a schematic diagram of the chip structure of some embodiments of the present application;
[0035] Figure 5 It is a schematic diagram of the ceramic cover plate structure of some embodiments of the present application.
[0036] In the figure: 1. Ceramic shell; 11. Source metallization welding area; 12. Gate metallization welding area; 2. Chip; 21. Chip substrate; 22. Source PAD; 23. Gate PAD; 24. Drain PAD; 3. Ceramic cover; 31. Metallization bonding area; 32. Sealing welding area; 33. Solder mask ring; 34. Cover base; 4. Column gate interconnection structure; 5. Source pin; 6. Gate pin; 7. Drain pin; 8. Chip drain solder; 9. Cover sealing solder; 10. Filling glue. DETAILED DESCRIPTION
[0037] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.
[0038] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0039] like Figure 1-2 As shown, the present invention provides a high-reliability package lead-out structure for a large power consumption device, comprising a ceramic housing 1, a chip 2, a ceramic cover plate 3, a column grid interconnection structure 4, a source pin 5, a gate pin 6, a drain pin 7, a chip drain solder 8 and a cover plate sealing solder 9;
[0040] The ceramic housing 1 and the ceramic cover plate 3 are sealed and welded by a cover plate sealing solder 9, a cavity is formed between the ceramic housing 1 and the ceramic cover plate 3, the chip 2 is arranged in the cavity between the ceramic housing 1 and the ceramic cover plate 3, and the back side of the chip 2 is welded to the ceramic cover plate 3 by a chip drain solder 8;
[0041] The source and gate regions on the front side of the chip 2 are welded to the ceramic housing 1 through a column-gate interconnection structure 4, and the source and gate regions on the front side of the chip 2 are respectively led out to the source pin 5 and the gate pin 6 through the column-gate interconnection structure 4 and the ceramic housing 1, and the back side of the chip 2 is led out to the drain pin 7 through the chip drain solder 8, the ceramic cover 3, the cover sealing solder 9 and the ceramic housing 1.
[0042] In the specific implementation, the vertical interconnection method is adopted to greatly shorten the current conduction path, reduce the current conduction resistance, improve the circuit performance, meet the requirements of larger operating current and large power consumption, and greatly develop and utilize the vertical space of the package. Since the bonding wire structure is no longer used, the problem of large space occupied by the bonding wire is effectively avoided, and the size of the finished device is greatly reduced, which effectively solves the problems of high performance, high reliability and miniaturization of wire bonding chip packaging.
[0043] like Figure 3 As shown, in some embodiments, the ceramic shell 1 is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, and each layer of the ceramic body includes a wiring structure corresponding to the source, gate and drain. A cavity is provided on the inner side of the ceramic shell 1, and a source metallization welding area 11 and a gate metallization welding area 12 are provided on the inner surface of the cavity.
[0044] In specific implementation, the ceramic shell 1 is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, generally 6-8 layers, and each layer of the ceramic body contains wiring structures corresponding to the source, gate and drain respectively according to the requirements of the chip 2. The wiring material is a highly conductive material such as W, Mo, Cu, etc. The inner side of the ceramic shell 1 is recessed to form a cavity, and a source metallization welding area 11 and a gate metallization welding area 12 are arranged in the cavity. The source pin 5 and the gate pin 6 are respectively connected to the source metallization welding area 11 and the gate metallization welding area 12 through the internal wiring of the ceramic shell 1.
[0045] like Figure 4As shown, in some embodiments, the chip 2 includes a chip substrate 21, a source PAD22, a gate PAD23 and a drain PAD24. The source PAD22 and the gate PAD23 are located on the front side of the chip substrate 21 and are respectively connected to the source and gate of the chip 2. Pads for electroplating growth or preparation of a column gate interconnect structure 4 are reserved on the surfaces of the source PAD22 and the gate PAD23, and are respectively connected to a source metallization welding area 11 and a gate metallization welding area 12 through the column gate interconnect structure 4, and are finally led out to a source pin 5 and a gate pin 6 through the ceramic housing 1.
[0046] In some embodiments, the column-gate interconnect structure 4 is an array-arranged Cu column structure or an array-arranged PbSn solder column structure.
[0047] In specific implementation, as a preferred embodiment, when the pitch of the column grid interconnect structure 4 is ≤0.5mm, the Cu column structure is arranged in an array. As another pre-selected embodiment, when the pitch of the column grid interconnect structure 4 is greater than 0.5mm, the PbSn solder column structure is arranged in an array.
[0048] In some embodiments, when the column grid interconnect structure 4 adopts an array-arranged Cu column structure, it is prepared by electroplating process, the common column diameter is 0.02mm or 0.025mm, the column aspect ratio is greater than 2, and its structure is Cu / X, Cu / Ni / X or Cu / Ni / Cu / X, where X is SnAg, SnAgCu or PbSn tin cap solder;
[0049] In specific implementation, the recommended structure for the pillar gate interconnect structure 4 with a pitch less than 50 μm is Cu / Ni / Cu / PbSn.
[0050] When the column grid interconnect structure 4 adopts an array-arranged PbSn solder column structure, it is prepared by a column planting process. The column diameters include 0.89mm, 0.76mm, 0.65mm, and 0.635mm. The column aspect ratio is greater than 2. The solder column material types are 90Pb10Sn columnar solder columns and 80Pb20Sn copper-clad solder columns.
[0051] In some embodiments, pads for electroplating growth or preparation of the column gate interconnect structure 4 are reserved on the surfaces of the source metallization welding area 11 and the gate metallization welding area 12 .
[0052] In specific implementation, pads that can be used for electroplating growth or preparation of column gate interconnect structure 4 should be reserved on the surface of source metallization welding area 11 and gate metallization welding area 12. As a preferred implementation mode, when a 0.02mm diameter Cu column structure is selected, the reserved pad diameter is 0.01mm; when a 0.025mm diameter Cu column structure is selected, the reserved pad diameter is 0.015mm; when a 0.89mm diameter solder column structure is selected, the reserved pad diameter is 0.85-0.89mm; as another preferred implementation mode, when a 0.76mm diameter solder column structure is selected, the reserved pad diameter is 0.72-0.76mm; when a 0.65mm diameter solder column structure is selected, the reserved pad diameter is 0.60-0.65mm; when a 0.635mm diameter solder column structure is selected, the reserved pad diameter is 0.58-0.63mm.
[0053] In some embodiments, the column grid interconnect structure 4 is arranged in a standard array or a staggered array.
[0054] In specific implementation, when the Cu column structure is arranged in an array, the conventionally recommended pitch is 0.07mm, 0.085mm, 0.12mm, 0.135mm, 0.18mm, 0.2mm, etc.; as another implementation method, when the solder column structure is arranged in an array, the conventionally recommended pitch is 1.00mm, 1.27mm, 1.50mm, etc.
[0055] In some embodiments, the solder selected for welding the upper and lower ends of the column grid interconnect structure 4 includes: any one of gold-based solder, tin-lead solder, indium-based solder and nano-sintered material.
[0056] like Figure 5 As shown, in some embodiments, the ceramic cover plate 3 is made of multi-layer aluminum oxide or aluminum nitride co-fired ceramic, and a wiring structure corresponding to the drain electrode is arranged between each layer of ceramic body;
[0057] The ceramic cover plate 3 includes a metallized adhesive sheet area 31, a sealing welding area 32, a solder resist ring 33 and a cover plate base 34, and the metallized adhesive sheet area 31, the sealing welding area 32 and the solder resist ring 33 are arranged in different areas on the cover plate base 34;
[0058] The upper surface of the metallized adhesive area 31 is welded to the drain PAD24 on the back side of the chip substrate 21, and the lower surface is electrically connected to the sealing welding area 32 and the cover sealing solder 9 through the internal wiring of the ceramic cover 3, and finally led out to the drain pin 7 through the ceramic housing 1; the solder resist ring 33 is located between the metallized adhesive area 31 and the sealing welding area 32.
[0059] In specific implementation, the material of the ceramic cover plate 3 is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, generally 2-4 layers. The wiring structure corresponding to the drain should be included between each layer of the ceramic body according to the requirements of the chip 2. The wiring material is a highly conductive material such as W, Mo, Cu, etc., wherein the solder resist ring 33 is located between the metallized bonding area 31 and the sealing welding area 32 to limit solder diffusion.
[0060] In some embodiments, a filling glue 10 is also included. The filling glue 10 is a high-flexibility organic bottom filling glue material or a potting glue material. The filling glue 10 fills the gaps between the column grid interconnection structures 4 and covers the chip 2.
[0061] In specific implementation, the filling glue 10 is a high-flexibility organic bottom filling glue material or potting glue material, which ensures good insulation performance and further increases the overall reliability and heat resistance of the structure.
[0062] Some embodiments of the present invention propose a high-reliability package lead-out structure for high-power consumption devices. Compared with traditional wire bonding packaging structures, it adopts a vertical interconnection method, which greatly shortens the current conduction path, reduces the current conduction resistance, improves circuit performance, and meets the requirements of larger operating current and high power consumption.
[0063] The structural design exploits the vertical space of the package. Since the bonding wire structure is no longer used, the problem of the bonding wire occupying a large space is effectively avoided, and the size of the finished device is greatly reduced. It has been verified that the original volume of the high-power MOS device with a traditional bonding structure is about 1000mm 3 After adopting the lead-out structure proposed in the present invention, the volume is reduced to 283mm 3 The reduction ratio is about 70%.
[0064] At the same time, the chip source and gate sides use a high aspect ratio columnar array interconnection structure, which has high deformation resistance, can absorb the large stress caused by the double-sided fixed structure, and improve structural stability.
[0065] Highly flexible organic bottom filling glue material or potting glue material is selected as the filling material in the gap of the column grid structure and the chip, which further increases the overall reliability and heat resistance of the structure.
[0066] In the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0067] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0068] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0069] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A high-reliability package lead-out structure for a high-power consumption device, characterized in that: It comprises a ceramic housing (1), a chip (2), a ceramic cover plate (3), a column-grid interconnection structure (4), a source pin (5), a gate pin (6), a drain pin (7), a chip drain solder (8) and a cover plate sealing solder (9); The ceramic housing (1) and the ceramic cover plate (3) are sealed and welded via the cover plate sealing solder (9), a cavity is formed between the ceramic housing (1) and the ceramic cover plate (3), the chip (2) is arranged in the cavity between the ceramic housing (1) and the ceramic cover plate (3), and the back side of the chip (2) is welded to the ceramic cover plate (3) via the chip drain solder (8); The front source and gate regions of the chip (2) are welded to the ceramic housing (1) via the column-grid interconnection structure (4), and the front source and gate of the chip (2) are respectively led out to the source pin (5) and the gate pin (6) via the column-grid interconnection structure (4) and the ceramic housing (1); The back side of the chip (2) is led out to the drain pin (7) through the chip drain solder (8), the ceramic cover plate (3), the cover plate sealing solder (9) and the ceramic housing (1).
2. A high-reliability package lead-out structure for a high-power consumption device according to claim 1, characterized in that: The ceramic shell (1) is a multi-layer aluminum oxide or aluminum nitride co-fired ceramic, each layer of the ceramic body includes a wiring structure corresponding to the source, gate and drain, and a cavity is arranged inside the ceramic shell (1), and a source metallized welding area (11) and a gate metallized welding area (12) are arranged on the inner surface of the cavity; The source pin (5) and the gate pin (6) are respectively connected to the source metallized welding area (11) and the gate metallized welding area (12) through internal wiring of the ceramic housing (1).
3. A high-reliability package lead-out structure for a high-power consumption device according to claim 2, characterized in that: The chip (2) comprises a chip substrate (21), a source PAD (22), a gate PAD (23) and a drain PAD (24); The source PAD (22) and the gate PAD (23) are located on the front side of the chip substrate (21) and are respectively connected to the source and gate of the chip (2); pads for electroplating growth or preparation of the column-gate interconnect structure (4) are reserved on the surfaces of the source PAD (22) and the gate PAD (23), and are respectively connected to the source metallization welding area (11) and the gate metallization welding area (12) through the column-gate interconnect structure (4), and are finally led out to the source pin (5) and the gate pin (6) through the ceramic housing (1).
4. A high-reliability package lead-out structure for a high-power consumption device according to claim 1, characterized in that: The column grid interconnection structure (4) is an array-arranged Cu column structure or an array-arranged PbSn solder column structure.
5. A high-reliability package lead-out structure for a high-power consumption device according to claim 4, characterized in that: When the column grid interconnect structure (4) adopts an array-type Cu column structure, it is prepared by electroplating process, the column diameter is 0.02mm or 0.025mm, the column slenderness ratio is greater than 2, and its structure is Cu / X, Cu / Ni / X or Cu / Ni / Cu / X, wherein X is SnAg, SnAgCu or PbSn tin cap solder; When the column grid interconnect structure (4) adopts an array-type PbSn solder column structure, it is prepared by a column planting process, the column diameters include 0.89mm, 0.76mm, 0.65mm, and 0.635mm, the column aspect ratio is greater than 2, and the solder column material types are 90Pb10Sn columnar solder columns and 80Pb20Sn copper-clad solder columns.
6. A high-reliability package lead-out structure for a high-power consumption device according to claim 3, characterized in that: The surfaces of the source metallization welding area (11) and the gate metallization welding area (12) are reserved for electroplating growth or preparation of welding pads for the column gate interconnection structure (4).
7. A high-reliability package lead-out structure for a high-power consumption device according to claim 1, characterized in that: The column grid interconnection structure (4) is arranged in a standard array or in a staggered array.
8. The high-reliability package lead-out structure for a high-power consumption device according to claim 1, characterized in that: The solder used for welding the upper and lower ends of the column grid interconnection structure (4) comprises any one of gold-based solder, tin-lead solder, indium-based solder and nano-sintered material.
9. A high-reliability package lead-out structure for a high-power consumption device according to claim 3, characterized in that: The ceramic cover plate (3) is made of a multi-layer co-fired ceramic of aluminum oxide or aluminum nitride, and a wiring structure corresponding to the drain electrode is arranged between each layer of the ceramic body; The ceramic cover plate (3) comprises a metallized adhesive sheet area (31), a sealing welding area (32), a solder resist ring (33) and a cover plate base (34); the metallized adhesive sheet area (31), the sealing welding area (32) and the solder resist ring (33) are arranged in zones on the cover plate base (34); The upper surface of the metallized adhesive region (31) is welded to the drain PAD (24) on the back side of the chip substrate (21), and the lower surface is electrically connected to the sealing welding region (32) and the cover sealing solder (9) through the internal wiring of the ceramic cover (3), and finally led out to the drain pin (7) through the ceramic housing (1); The solder resist ring (33) is located between the metallized bonding area (31) and the sealing welding area (32).
10. A high-reliability package lead-out structure for a high-power consumption device according to claim 1, characterized in that: It also comprises a filling glue (10), wherein the filling glue (10) fills the gaps between the column grid interconnection structures (4) and covers the chip (2).