Semiconductor package

Abstract

A semiconductor package includes: a plurality of semiconductor chips stacked in a first direction; a plurality of chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips, and electrically connecting the two adjacent semiconductor chips; and a plurality of chip support structures disposed between two adjacent semiconductor chips. The plurality of chip support structures do not electrically connect two adjacent semiconductor chips, and are spaced apart from the plurality of chip connection terminals in a second direction crossing the first direction. A thickness of each of the plurality of chip support structures is greater than a thickness of each of the plurality of chip connection terminals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0150288 filed in the Korean Intellectual Property Office on November 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to a semiconductor package, and more particularly, to a semiconductor package including a plurality of vertically stacked semiconductor chips. Background Art

[0004] With the rapid development of the electronic industry, semiconductor packages mounted on electronic products have been used to provide high performance and include various functions, and thus, semiconductor packages including a plurality of semiconductor chips have been proposed.

[0005] In addition, in order to reduce the size of a semiconductor package including a plurality of semiconductor chips, a semiconductor package in which the plurality of semiconductor chips are vertically stacked has been developed. Summary of the invention

[0006] Embodiments of the inventive concept provide a semiconductor package including a plurality of vertically stacked semiconductor chips having structural reliability.

[0007] According to an embodiment of the present invention, a semiconductor package includes: a plurality of semiconductor chips stacked in a first direction; a plurality of chip connection terminals arranged between two semiconductor chips arranged adjacent to each other in the first direction among the plurality of semiconductor chips, and electrically connecting the two adjacent semiconductor chips; and a plurality of chip support structures arranged between the two adjacent semiconductor chips. The plurality of chip support structures do not electrically connect the two adjacent semiconductor chips, and are spaced apart from the plurality of chip connection terminals in a second direction intersecting the first direction. The thickness of each of the plurality of chip support structures is greater than the thickness of each of the plurality of chip connection terminals.

[0008] According to an embodiment of the present invention, a semiconductor package includes: a package substrate, including a package base insulating layer, a lower solder resist layer covering the lower surface of the package base insulating layer, and an upper solder resist layer covering the upper surface of the package base insulating layer; and a plurality of semiconductor chips, each including a substrate, a front protective layer arranged on the lower surface of the substrate, and a rear protective layer arranged on the upper surface of the substrate. The plurality of semiconductor chips include a first semiconductor chip arranged on the package substrate, and a plurality of second semiconductor chips stacked sequentially on the first semiconductor chip in a first direction. The semiconductor package also includes a plurality of first chip connection terminals and a plurality of first chip support structures, the plurality of first chip connection terminals are arranged between the package substrate and the first semiconductor chip, and the package substrate is electrically connected to the first semiconductor chip, and the plurality of first chip support structures are arranged between the package substrate and the first semiconductor chip. The plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in the second direction and extend into the upper solder resist layer. The semiconductor package also includes a plurality of second chip connection terminals arranged between two semiconductor chips arranged adjacent to each other in the first direction among the plurality of semiconductor chips. The plurality of second chip connection terminals electrically connect the two adjacent semiconductor chips, and the second direction intersects with the first direction. The semiconductor package further includes a plurality of second chip support structures disposed between the two adjacent semiconductor chips. The plurality of second chip support structures extend into a rear protection layer included in a lower semiconductor chip among the two adjacent semiconductor chips.

[0009] According to an embodiment of the present invention, a semiconductor package includes a package substrate, the package substrate includes a package base insulating layer, a plurality of package upper pads arranged on the upper surface of the package base insulating layer, a plurality of package lower pads arranged on the lower surface of the package base insulating layer, a plurality of connection pads electrically connecting the plurality of package upper pads to the plurality of package lower pads, an upper solder resist layer covering the upper surface of the package base insulating layer but not covering at least a portion of the upper surface of each of the plurality of package upper pads, and a lower solder resist layer covering the lower surface of the package base insulating layer but not covering at least a portion of the lower surface of each of the plurality of package lower pads. The semiconductor package also includes a plurality of semiconductor chips, the plurality of semiconductor chips including a first semiconductor chip and a plurality of second semiconductor chips sequentially stacked on the package substrate in a first direction. The first semiconductor chip and the plurality of second semiconductor chips each include a substrate, a plurality of rear connection pads arranged on the upper surface of the substrate, a plurality of front connection pads arranged on the lower surface of the substrate, a plurality of through electrodes vertically penetrating at least a portion of the substrate and electrically connecting the plurality of rear connection pads to the plurality of front connection pads, a front protective layer arranged on the lower surface of the substrate and not covering at least a portion of the lower surface of each of the plurality of front connection pads, and a rear protective layer arranged on the upper surface of the substrate and not covering at least a portion of the upper surface of each of the plurality of rear connection pads. The semiconductor package also includes a plurality of first chip connection terminals arranged between the plurality of package upper pads of the package substrate and the plurality of front connection pads of the first semiconductor chip, and a plurality of first chip support structures arranged between the package substrate and the first semiconductor chip. The plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in the second direction, extend into the upper solder resist layer, and do not penetrate the upper solder resist layer. The semiconductor package also includes a plurality of second chip connection terminals, which are arranged between two semiconductor chips arranged adjacent to each other in the first direction among the plurality of semiconductor chips, and are arranged between a plurality of rear connection pads and a plurality of front connection pads facing each other included in the two adjacent semiconductor chips. The second direction intersects with the first direction. The semiconductor package also includes a plurality of second chip support structures arranged between the two adjacent semiconductor chips. The plurality of second chip support structures extend into the rear protective layer included in the lower semiconductor chip among the two adjacent semiconductor chips, and do not penetrate the rear protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment;

[0012] FIG. 2A to FIG. 2Dis an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0013] Figure 3A and Figure 3B is an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0014] Figure 4A and Figure 4B is an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0015] Figure 5A and Figure 5B is an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0016] Fig. 6A and Figure 6B is an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0017] Figure 7 is a cross-sectional view of a semiconductor package according to an embodiment;

[0018] Figure 8 is a cross-sectional view of a semiconductor package according to an embodiment;

[0019] Fig. 9A and Fig. 9B is an enlarged cross-sectional view of a semiconductor package according to an embodiment;

[0020] Fig.10 is a cross-sectional view of a semiconductor package according to an embodiment; and

[0021] Fig.11 , Fig.12 , FIG. 13A to FIG. 13D , Fig.14 as well as FIG. 15A to FIG. 15D are a cross-sectional view and an enlarged cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0022] Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may represent like elements throughout the drawings.

[0023] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, a "first" element in one embodiment may be described as a "second" element in another embodiment.

[0024] It should be understood that descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0025] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0026] For ease of description, spatially relative terms such as "below," "under," "lower," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature relative to other (one or more) elements or (one or more) features as shown in the drawings. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the exemplary terms "below" and "below" can cover both the orientations of above and below.

[0027] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, connected to, coupled to, or adjacent to the other component, or there can be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there can also be one or more intervening components. It will also be understood that when a component is referred to as "overlying" another component, it can be the only component that overlies the other component, or one or more intervening components can also overlie the other component. Other words used to describe relationships between components should be interpreted in a similar manner.

[0028] In this article, as will be understood by those of ordinary skill in the art, when two or more components or values ​​are described as being substantially the same or approximately equal to each other, it is understood that the elements or values ​​are the same as each other, the elements or values ​​are equal to each other within the measurement error, or if measured as unequal, then close enough in value to be functionally equal to each other. For example, the term "about" as used herein includes the described value, and is represented within the acceptable deviation range of the specific value determined by one of ordinary skill in the art taking into account the measurement in question and the error (e.g., the limitation of the measurement system) associated with the measurement of a specific amount. For example, "about" can be represented within one or more standard deviations understood by one of ordinary skill in the art. In addition, it will be understood that although a parameter can be described herein as having "approximately" a specific value, according to an embodiment, as will be understood by those of ordinary skill in the art, the parameter can be precisely the specific value, or approximately the specific value within the measurement error. Other uses of these terms and similar terms used to describe the relationship between components should be explained in a similar manner.

[0029] Figure 1 is a cross-sectional view of a semiconductor package 1 according to the embodiment.

[0030] refer to Figure 1 The semiconductor package 1 may include a package substrate 500 , a first semiconductor chip 100 attached to the package substrate 500 , a plurality of second semiconductor chips 200 vertically stacked on the first semiconductor chip 100 , and a mold layer 900 surrounding the first semiconductor chip 100 and the second semiconductor chip 200 on the package substrate 500 .

[0031] The package substrate 500 may be a printed circuit board (PCB). The package substrate 500 may be a double-sided PCB, but is not limited thereto. For example, the package substrate 500 may be a multi-layer PCB. The package substrate 500 may include a package base insulating layer 510, a plurality of package conductive patterns 520, and a solder resist layer 530.

[0032] The encapsulation base insulating layer 510 may include, for example, at least one of a phenolic resin, an epoxy resin, and a polyimide. The encapsulation base insulating layer 510 may include, for example, flame retardant 4 (FR-4), a tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), a thermosetting resin, a cyanate ester, a polyimide, and a liquid crystal polymer. In some embodiments, the encapsulation base insulating layer 510 may include, for example, polyester (PET), polyester terephthalate, fluorinated ethylene propylene (FEP), resin coated paper, liquid polyimide resin, polyethylene naphthalate (PEN) film, etc. In some embodiments, the encapsulation base insulating layer 510 may be formed by stacking a plurality of base layers.

[0033] The package conductive pattern 520 may include copper (Cu) or an alloy containing copper (Cu). The package conductive pattern 520 may include a plurality of package upper pads 522, a plurality of package lower pads 524, and a plurality of connection patterns 526. The package upper pads 522 may be disposed on the upper surface of the package base insulating layer 510, and the package lower pads 524 may be disposed on the lower surface of the package base insulating layer 510. The connection pattern 526 may electrically connect the package upper pads 522 to the package lower pads 524. Figure 1 , each connection pattern 526 is shown as a via pattern penetrating the package substrate insulating layer 510. However, this is an example provided for convenience of explanation, and the inventive concept is not limited thereto. For example, the connection pattern 526 may include a plurality of line patterns and a plurality of via patterns. The line pattern may extend along the upper surface and / or the lower surface of the package substrate insulating layer 510. When the package substrate insulating layer 510 includes a substrate layer, the line pattern may extend along the upper surface and / or the lower surface of the substrate layer.

[0034] The via pattern may fill at least a portion of the through hole penetrating at least one of the base layers or the package base insulating layer 510, and connect the package upper pad 522, the package lower pad 524, and two of the line patterns disposed at different vertical levels. In some embodiments, the via pattern may fill all of the through holes. In some embodiments, the via pattern may be formed to cover the inner wall of the through hole and fill a portion of the through hole, and a plurality of via filling insulating layers may cover the via pattern and fill the through hole. For example, the through hole may be completely filled with the via pattern and the via filling insulating layer.

[0035] The package upper pad 522, the package lower pad 524, and the line pattern may each include, for example, electrolytic deposition (ED) copper foil, rolled annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloy, etc. In some embodiments, each of the package upper pad 522 and the package lower pad 524 may include, for example, copper, nickel, stainless steel, or beryllium copper. For example, each of the package upper pad 522 and the package lower pad 524 may include copper plating. In some embodiments, each of the package upper pad 522 and the package lower pad 524 may include Ni / Au, etc. in the surface portion on the opposite side of the package base insulating layer 510.

[0036] Each via pattern may have the following structure: copper (Cu) or an alloy including copper (Cu) is stacked on a seed layer, the seed layer including, for example, copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), Cu / Ti in which copper (Cu) is stacked on titanium (Ti), or Cu / TiW in which copper is stacked on titanium tungsten, but is not limited thereto.

[0037] The package substrate 500 may include solder resist layers 530 disposed on the upper surface and the lower surface of the package substrate 500. The solder resist layers 530 may include an upper solder resist layer 532 disposed on the upper surface of the package substrate 500 to cover the upper surface of the package base insulating layer 510, and a lower solder resist layer 534 disposed on the lower surface of the package substrate 500 to cover the lower surface of the package base insulating layer 510. At least a portion of each package upper pad 522 disposed on the upper surface of the package base insulating layer 510 may be exposed to the upper surface of the package substrate 500 without being covered by the upper solder resist layer 532, and at least a portion of each package lower pad 524 disposed on the lower surface of the package base insulating layer 510 may be exposed to the lower surface of the package substrate 500 without being covered by the lower solder resist layer 534. In some embodiments, among the line patterns, the line patterns disposed on the upper surface of the package base insulating layer 510 may be covered by the upper solder resist layer 532 without being exposed to the upper surface of the package substrate 500, and the line patterns disposed on the lower surface of the package base insulating layer 510 may be covered by the lower solder resist layer 534 without being exposed to the lower surface of the package substrate 500. For example, each of the upper solder resist layer 532 and the lower solder resist layer 534 may have a thickness of about 15 μm to about 25 μm.

[0038] A plurality of package connection terminals 550 may be attached to the package lower pads 524 of the semiconductor package 1. The package connection terminals 550 may be used as external connection terminals of the semiconductor package 1. The package connection terminals 550 may electrically connect the semiconductor package 1 to an external device. In some embodiments, the package connection terminals 550 may include, for example, bumps, solder balls, etc. A plurality of first chip connection terminals 150 may be attached to the package upper pads 522.

[0039] exist Figure 1 , the semiconductor package 1 is shown to include one first semiconductor chip 100 and four second semiconductor chips 200, but the inventive concept is not limited thereto. For example, in some embodiments, the semiconductor package 1 may include two or more second semiconductor chips 200. In some embodiments, the semiconductor package 1 may include a number of second semiconductor chips 200 that is a multiple of 4. The second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100 in a first direction (e.g., a vertical direction).

[0040] In some embodiments, among the second semiconductor chips 200, the uppermost second semiconductor chip 200T disposed farthest from the first semiconductor chip 100 does not include the second rear connection pads 214 and the second through-electrodes 230. In some embodiments, among the second semiconductor chips 200, the uppermost second semiconductor chip 200T disposed farthest from the first semiconductor chip 100 may have a thickness greater than that of the other second semiconductor chips 200.

[0041] In this specification, the relationship between the first semiconductor chip 100 and the second semiconductor chip 200 refers to the relationship between each semiconductor chip including the first semiconductor chip 100 and the second semiconductor chip 200. That is, in this specification, the relationship between the first semiconductor chip 100 and the second semiconductor chip 200 refers to the relationship between the bottom second semiconductor chip 200 among the first semiconductor chip 100 and the second semiconductor chip 200, and the relationship between two second semiconductor chips 200 disposed adjacent to each other among the second semiconductor chips 200. The first semiconductor chip 100 and the second semiconductor chip 200 may be referred to as a plurality of semiconductor chips together. The semiconductor chips may be stacked in a vertical direction. The first semiconductor chip 100 may be the bottom semiconductor chip among the semiconductor chips, and the second semiconductor chip 200 may be other semiconductor chips except the bottom semiconductor chip among the semiconductor chips. In addition, among the semiconductor chips, two semiconductor chips disposed adjacent to each other in the vertical direction may be referred to as the first semiconductor chip and the second semiconductor chip, or may be referred to as the lower semiconductor chip and the upper semiconductor chip.

[0042] In some embodiments, the horizontal width and area of ​​the first semiconductor chip 100 may be substantially the same as the horizontal width and area of ​​each second semiconductor chip 200. For example, the edge of each second semiconductor chip 200 may be aligned with the edge of the first semiconductor chip 100 in the vertical direction. The second semiconductor chip 200 may overlap the first semiconductor chip 100 in the vertical direction. In some embodiments, the horizontal width and area of ​​the first semiconductor chip 100 may be greater than the horizontal width and area of ​​each second semiconductor chip 200. For example, in some embodiments, the edge of each second semiconductor chip 200 is not aligned with the edge of the first semiconductor chip 100 in the vertical direction, so that the edge of each second semiconductor chip 200 may be spaced apart from the edge of the first semiconductor chip 100 on a plane.

[0043] The first semiconductor chip 100 includes a first substrate 102, a first interconnection layer 120, a plurality of first through electrodes 130, a first front protective layer 142, and a first rear protective layer 144. A plurality of first front connection pads 112 may be disposed on a lower surface of the first semiconductor chip 100, and a plurality of first rear connection pads 114 may be disposed on an upper surface of the first semiconductor chip 100. The second semiconductor chip 200 includes a second substrate 202, a second interconnection layer 220, a plurality of second through electrodes 230, a second front protective layer 242, and a second rear protective layer 244. A plurality of second front connection pads 212 may be disposed on a lower surface of the second semiconductor chip 200, and a plurality of second rear connection pads 214 may be disposed on an upper surface of the second semiconductor chip 200. Each of the first front connection pads 112, the first rear connection pads 114, the second front connection pads 212, and the second rear connection pads 214 may include a metal (e.g., aluminum, copper, or tungsten).

[0044] The first substrate 102 may be referred to as a substrate of the first semiconductor chip 100 , the first front connection pads 112 may be referred to as front connection pads of the first semiconductor chip 100 , the first rear connection pads 114 may be referred to as rear connection pads of the first semiconductor chip 100 , the first interconnection layer 120 may be referred to as an interconnection layer of the first semiconductor chip 100 , the first through-electrode 130 may be referred to as a through-electrode of the first semiconductor chip 100 , the first front protective layer 142 may be referred to as a front protective layer of the first semiconductor chip 100 , and the first rear protective layer 144 may be referred to as a rear protective layer of the first semiconductor chip 100 .

[0045] The second substrate 202 may be referred to as a substrate of the second semiconductor chip 200 , the second front connection pads 212 may be referred to as front connection pads of the second semiconductor chip 200 , the second rear connection pads 214 may be referred to as rear connection pads of the second semiconductor chip 200 , the second interconnection layer 220 may be referred to as an interconnection layer of the second semiconductor chip 200 , the second through-electrode 230 may be referred to as a through-electrode of the second semiconductor chip 200 , the second front protective layer 242 may be referred to as a front protective layer of the second semiconductor chip 200 , and the second rear protective layer 244 may be referred to as a rear protective layer of the second semiconductor chip 200 .

[0046] In some embodiments, the first substrate 102 and the second substrate 202 may include Si (silicon). In some embodiments, the first substrate 102 and the second substrate 202 may include semiconductor devices, for example, germanium (Ge) and compound semiconductors (for example, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The first substrate 102 and the second substrate 202 may have an active surface and an inactive surface disposed opposite to the active surface. The active surface and the inactive surface of the first substrate 102 may be referred to as a first active surface and a first inactive surface, respectively, and the active surface and the inactive surface of the second substrate 202 may be referred to as a second active surface and a second inactive surface, respectively. The second active surface of the second substrate 202 may face the first inactive surface of the first substrate 102.

[0047] The first substrate 102 and the second substrate 202 may include a plurality of individual devices of various types disposed on an active surface. The individual devices may include various microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs) (e.g., complementary metal insulator semiconductor (CMOS) transistors), system large scale integration (LSI), image sensors (e.g., CMOS image sensors (CIS)), micro-electromechanical systems (MEMS), active devices, passive devices, etc.

[0048] The first semiconductor chip 100 and the second semiconductor chip 200 may include a first semiconductor device 105 and a second semiconductor device 205 formed of separate devices. The first semiconductor device 105 may be disposed on a first active surface of the first substrate 102 , and the second semiconductor device 205 may be disposed on a second active surface of the second substrate 202 .

[0049] In the present specification, the front surface and the rear surface of each of the first semiconductor chip 100 and the second semiconductor chip 200 refer to surfaces disposed adjacent to the active surface and the inactive surface of each of the first substrate 102 and the second substrate 202, and the upper surface and the lower surface of each of the first semiconductor chip 100 and the second semiconductor chip 200 refer to surfaces disposed on the upper side and the lower side in the drawings. For example, the front surface of each of the first semiconductor chip 100 and the second semiconductor chip 200 may be the lower surface of the first semiconductor chip 100 and the second semiconductor chip 200, and the rear surface of each of the first semiconductor chip 100 and the second semiconductor chip 200 may be the upper surface of each of the first semiconductor chip 100 and the second semiconductor chip 200.

[0050] The first semiconductor chip 100 and the second semiconductor chip 200 included in the semiconductor package 1 may be stacked in sequence in a face-down form, in which the first active surface and the second active surface face downward. For example, the first active surface of the first substrate 102 included in the first semiconductor chip 100 may face the side opposite to the second semiconductor chip 200, and the first inactive surface may face the second semiconductor chip 200. The second active surface of the second substrate 202 included in each second semiconductor chip 200 may face the first semiconductor chip 100, and the second inactive surface may face the side opposite to the first semiconductor chip 100.

[0051] The first semiconductor chip 100 and the second semiconductor chip 200 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0052] In some embodiments, the first semiconductor chip 100 does not include a memory cell. The first semiconductor device 105 included in the first semiconductor chip 100 may include, for example, a serial-to-parallel conversion circuit, a test logic circuit (e.g., a design for test (DFT), a joint test action group (JTAG), and a memory built-in self-test (MBIST)), and a signal interface circuit (e.g., a PHY). The second semiconductor device included in the second semiconductor chip 200 may include a memory cell. For example, the first semiconductor chip 100 may be a buffer chip that controls the second semiconductor chip 200.

[0053] In some embodiments, the first semiconductor chip 100 may be a buffer chip controlling a memory cell, and the second semiconductor chip 200 may be a memory cell chip having a memory cell controlled by the first semiconductor chip 100. The first semiconductor chip 100 may be referred to as, for example, a buffer chip, a master chip, or a main chip, and the second semiconductor chip 200 may be referred to as, for example, a memory cell chip, a slave chip, or a sub-chip. The first semiconductor chip 100 and the second semiconductor chip 200 stacked on the first semiconductor chip 100 may be collectively referred to as a DRAM device or a DRAM chip.

[0054] In some embodiments, the first semiconductor chip 100 may be a buffer chip controlling an HBM DRAM, and the second semiconductor chip 200 may be a memory cell chip having cells of the HBM DRAM controlled by the first semiconductor chip 100. The first semiconductor chip 100 and the second semiconductor chip 200 stacked on the first semiconductor chip 100 may be collectively referred to as an HBM DRAM device or an HBM DRAM chip.

[0055] The first interconnection layer 120 may be disposed on the first active surface of the first substrate 102. The first interconnection layer 120 may include a plurality of first interconnection patterns 122, a plurality of first interconnection vias 124, and a first inter-interconnection insulating layer 126. The first interconnection vias 124 may be connected to the upper surface and / or the lower surface of the first interconnection pattern 122. In some embodiments, the first interconnection patterns 122 may be spaced apart from each other at different vertical levels, and the first interconnection vias 124 may connect the first interconnection patterns 122 arranged at different vertical levels to each other. The first interconnection pattern 122 and the first interconnection vias 124 may be electrically connected to the first semiconductor device 105 and the first through-electrode 130. The first inter-interconnection insulating layer 126 may surround the first interconnection pattern 122 and the first interconnection vias 124.

[0056] The second interconnection layer 220 may be disposed on the second active surface of the second substrate 202. The second interconnection layer 220 may include a plurality of second interconnection patterns 222, a plurality of second interconnection vias 224, and a second inter-interconnection insulating layer 226. The second interconnection vias 224 may be connected to the upper surface and / or the lower surface of the second interconnection pattern 222. In some embodiments, the second interconnection patterns 222 may be spaced apart from each other at different vertical levels, and the second interconnection vias 224 may connect the second interconnection patterns 222 disposed at different vertical levels to each other. The second interconnection pattern 222 and the second interconnection via 224 may be electrically connected to the second semiconductor device 205 and the second through-electrode 230. The second inter-interconnection insulating layer 226 may surround the second interconnection pattern 222 and the second interconnection via 224.

[0057] The first interconnection pattern 122, the first interconnection via 124, the second interconnection pattern 222 and the second interconnection via 224 may include a metal (e.g., copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), cobalt (Co), nickel (Ni)), an alloy thereof, or a nitride of these metals. The first interconnection inter-insulating layer 126 and the second interconnection inter-insulating layer 226 may include, for example, a high density plasma (HDP) oxide film, a tetraethoxysilane (TEOS) oxide film, toner silazene (TOSZ), spin-on glass (SOG), undoped quartz glass (USG), or a low-k dielectric layer.

[0058] The first front connection pads 112 may be disposed on the lower surface of the first substrate 102, and the first rear connection pads 114 may be disposed on the upper surface of the first substrate 102. For example, the first front connection pads 112 may be disposed on the lower surface of the first interconnection layer 120. The first front connection pads 112 may be electrically connected to the first interconnection pattern 122 and the first interconnection via 124, and the first rear connection pads 114 may be electrically connected to the first through-electrode 130. The second front connection pads 212 may be disposed on the lower surface of the second substrate 202, and the second rear connection pads 214 may be disposed on the upper surface of the second substrate 202. For example, the second front connection pads 212 may be disposed on the lower surface of the second interconnection layer 220. The second front connection pads 212 may be electrically connected to the second interconnection pattern 222 and the second interconnection via 224, and the second rear connection pads 214 may be electrically connected to the second through-electrode 230. In some embodiments, among the second semiconductor chips 200 , the uppermost second semiconductor chip 200T disposed farthest from the first semiconductor chip 100 does not include the second rear connection pads 214 .

[0059] The first through-electrode 130 may vertically and electrically connect the first front connection pads 112 to the first rear connection pads 114 through at least a portion of the first substrate 102. For example, the first front connection pads 112 and the first rear connection pads 114 corresponding to each other may be electrically connected through the first through-electrode 130, the first interconnection pattern 122, and the first interconnection via 124.

[0060] The second through-electrode 230 may vertically and electrically connect the second front connection pads 212 to the second rear connection pads 214 through at least a portion of the second substrate 202. For example, the second front connection pads 212 and the second rear connection pads 214 corresponding to each other may be electrically connected through the second through-electrode 230, the second interconnection pattern 222, and the second interconnection via 224. In some embodiments, among the second semiconductor chips 200, the uppermost second semiconductor chip 200T disposed farthest from the first semiconductor chip 100 does not include the second through-electrode 230.

[0061] Each of the first through electrode 130 and the second through electrode 230 may include a conductive plug and a conductive barrier film surrounding the conductive plug. The conductive plug may include Cu or W. For example, the conductive plug may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, but is not limited thereto. For example, the conductive plug may include one or more of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr, and may include one or two or more stacked structures. The conductive barrier film may include, for example, at least one of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, and may include a single layer or multiple layers.

[0062] The first front protective layer 142 may cover the lower surface of the first interconnect layer 120. In some embodiments, the first front protective layer 142 does not cover but exposes at least a portion of the lower surface of each first front connection pad 112. In some embodiments, the first front protective layer 142 may cover the edge portion of the lower surface of each first front connection pad 112, and does not cover but exposes the central portion. The second front protective layer 242 may cover the lower surface of the second interconnect layer 220. In some embodiments, the second front protective layer 242 does not cover but exposes at least a portion of the lower surface of each second front connection pad 212. In some embodiments, the second front protective layer 242 may cover the edge portion of the lower surface of each second front connection pad 212, and does not cover but exposes the central portion. The first front protective layer 142 and the second front protective layer 242 may include nitride. In some embodiments, the first front protective layer 142 and the second front protective layer 242 may include silicon nitride.

[0063] The first rear protective layer 144 may cover the upper surface of the first substrate 102. In some embodiments, the first rear protective layer 144 does not cover but exposes at least a portion of the upper surface of each first rear connection pad 114. In some embodiments, the first rear protective layer 144 may cover at least a portion of the side surface of each first rear connection pad 114. The second rear protective layer 244 may cover the upper surface of the second substrate 202. In some embodiments, the second rear protective layer 244 does not cover but exposes at least a portion of the upper surface of each second rear connection pad 214. In some embodiments, the second rear protective layer 244 may cover at least a portion of the side surface of each second rear connection pad 214. The first rear protective layer 144 and the second rear protective layer 244 may include an oxide or a polymer. In some embodiments, the first rear protective layer 144 and the second rear protective layer 244 may include silicon oxide. For example, each of the first front protective layer 142 and the second front protective layer 242 may have a thickness of about 2 μm to about 4 μm. For example, each of the first rear protective layer 144 and the second rear protective layer 244 may have a thickness of about 2 μm to about 4 μm.

[0064] A plurality of first chip connection terminals 150 may be attached to the first front connection pads 112. The first chip connection terminals 150 may be disposed between the first semiconductor chip 100 and the package substrate 500, and electrically connect the first semiconductor chip 100 to the package substrate 500. The first chip connection terminals 150 may be disposed between the first front connection pads 112 and the package upper pads 522. A plurality of second chip connection terminals 250 may be attached to the second front connection pads 212. The second chip connection terminals 250 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 200, and electrically connect the first semiconductor chip 100 to the second semiconductor chip 200. The second chip connection terminals 250 may be disposed between the second front connection pads 212 and the first rear connection pads 114, and between the second front connection pads 212 and the second rear connection pads 214. For example, the second chip connection terminal 250 can be arranged between the second front connection pad 212 included in the bottommost second semiconductor chip 200 among the second semiconductor chips 200 and the first rear connection pad 114 included in the first semiconductor chip 100, and between the second front connection pad 212 and the second rear connection pad 214 facing each other included in two second semiconductor chips 200 arranged adjacent to each other among the second semiconductor chips 200.

[0065] The semiconductor package 1 further includes a plurality of first chip support structures 170 and a plurality of second chip support structures 270. The first chip support structure 170 may be disposed between the first semiconductor chip 100 and the package substrate 500. The first chip support structure 170 may be spaced apart from the first chip connection terminal 150 in a second direction (e.g., a horizontal direction) intersecting the first direction, and may be disposed between the first semiconductor chip 100 and the package substrate 500. The second chip support structure 270 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 200. The second chip support structure 270 may be spaced apart from the second chip connection terminal 250 in a horizontal direction, and may be disposed between the second semiconductor chips 200. In some embodiments, the number of the first chip support structures 170 disposed on the lower surface of the first semiconductor chip 100 may be equal to the number of the second chip support structures 270 disposed on the lower surface of each second semiconductor chip 200 (i.e., disposed on the lower surface of one second semiconductor chip 200). The first chip support structure 170 and the second chip support structure 270 may include metal. For example, the first chip support structure 170 and the second chip support structure 270 may include copper, nickel, stainless steel or a copper alloy (eg beryllium copper).

[0066] The first chip connection terminals 150 may be referred to as substrate connection terminals, the second chip connection terminals 250 may be referred to as chip connection terminals, the first chip support structure 170 may be referred to as a substrate support structure, and the second chip support structure 270 may be referred to as a chip support structure. In some embodiments, the first chip connection terminals 150 may electrically connect the package substrate 500 to the first semiconductor chip 100, and the first chip support structure 170 does not electrically connect the package substrate 500 to the first semiconductor chip 100. In some embodiments, the second chip connection terminals 250 may electrically connect the first semiconductor chip 100 to the second semiconductor chip 200, and the second chip support structure 270 does not electrically connect the first semiconductor chip 100 to the second semiconductor chip 200.

[0067] The molding layer 900 may surround the first semiconductor chip 100 and the second semiconductor chip 200 on the package substrate 500. The molding layer 900 may include, for example, epoxy molding compound (EMC). In some embodiments, the molding layer 900 may fill the space between the package substrate 500 and the first semiconductor chip 100, and the space between the first semiconductor chip 100 and the second semiconductor chip 200. For example, the molding layer 900 may fill the space between the package substrate 500 and the first semiconductor chip 100, and surround the first chip connection terminal 150 and the first chip support structure 170, and may fill the space between the first semiconductor chip 100 and the second semiconductor chip 200, and surround the second chip connection terminal 250 and the second chip support structure 270.

[0068] In some embodiments, the mold layer 900 may cover the side surface, the upper surface, and the lower surface of each of the first semiconductor chip 100 and the second semiconductor chip 200, and does not cover the upper surface of the uppermost second semiconductor chip 200T in the second semiconductor chips 200. For example, the upper surface of the mold layer 900 may be substantially coplanar with the upper surface of the uppermost second semiconductor chip 200T. In some embodiments, the mold layer 900 may cover the upper surface of the uppermost second semiconductor chip 200T. For example, the upper surface of the mold layer 900 may be disposed at a vertical level higher than the vertical level of the upper surface of the uppermost second semiconductor chip 200T.

[0069] In some embodiments, the package substrate 500 may be an interposer. For example, the package substrate 500 may be a silicon interposer or a redistribution interposer. When the package substrate 500 is a silicon interposer, the package substrate 500 may include an interposer substrate, an interposer upper pad, an interposer lower pad, an interposer through-electrode, an interposer upper protective layer, and an interposer lower protective layer, instead of a package base insulating layer 510, a package upper pad 522, a package lower pad 524, a connection pattern 526, an upper solder resist layer 532, and a lower solder resist layer 534. The interposer substrate may include silicon (Si). The interposer through-electrode passes through the interposer substrate to electrically connect the interposer upper pad to the interposer lower pad. The interposer upper protective layer and the interposer lower protective layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0070] FIG. 2A to FIG. 2D is an enlarged cross-sectional view of a semiconductor package 1 according to an embodiment. For example, FIG. 2A to FIG. 2D It shows Figure 1 The enlarged cross-sectional view of the portion A1, portion B1, portion C1 and portion D1 of FIG. Figure 2C Shows Figure 1The second chip connection terminals 250 disposed between the lowermost second semiconductor chip 200 and the first semiconductor chip 100 may be substantially the same. Figure 2D Shows Figure 1 The portion D1 (i.e., the second chip support structure 270 disposed between two adjacent second semiconductor chips 200 among the second semiconductor chips 200), but the second chip support structure 270 disposed between the lowermost second semiconductor chip 200 among the second semiconductor chips 200 and the first semiconductor chip 100 may be substantially the same.

[0071] refer to Figure 1 as well as FIG. 2A to FIG. 2D , the first front connection pads 112 may include first actual front connection pads 112R and first dummy front connection pads 112D, and the second front connection pads 212 may include second actual front connection pads 212R and second dummy front connection pads 212D.

[0072] The first chip connection terminal 150 may be disposed between the first actual front connection pad 112R and the package upper pad 522. The second chip connection terminal 250 may be disposed between the second actual front connection pad 212R and the first rear connection pad 114, or between the second actual front connection pad 212R and the second rear connection pad 214. For example, the second chip connection terminal 250 may be disposed between the second actual front connection pad 212R included in the lowermost second semiconductor chip 200 among the second semiconductor chips 200 and the first rear connection pad 114 included in the first semiconductor chip 100, or may be disposed between the second actual front connection pad 212R and the second rear connection pad 214 facing each other included in two second semiconductor chips 200 disposed adjacent to each other among the second semiconductor chips 200.

[0073] The first chip connection terminal 150 may include a first conductive pillar 152 attached to the lower surface of the first actual front connection pad 112R, and a first conductive cap 154 ​​covering the lower surface of the first conductive pillar 152. The second chip connection terminal 250 may include a second conductive pillar 252 attached to the lower surface of the second actual front connection pad 212R, and a second conductive cap 254 covering the lower surface of the second conductive pillar 252. In some embodiments, a first under bump metallization (UBM) layer may be provided between the lower surface of the first actual front connection pad 112R and the upper surface of the first conductive pillar 152, and a second UBM layer may be provided between the lower surface of the second actual front connection pad 212R and the upper surface of the second conductive pillar 252. The first conductive pillar 152 may be referred to as a substrate conductive pillar, the first conductive cap 154 ​​may be referred to as a substrate conductive cap, the second conductive pillar 252 may be referred to as a chip conductive pillar, and the second conductive cap 254 may be referred to as a chip conductive cap.

[0074] The first conductive pillar 152 and the second conductive pillar 252 may include, for example, copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper). For example, the first conductive pillar 152 and the second conductive pillar 252 may be formed by an electroplating process (e.g., electrolytic plating or chemical plating). In some embodiments, the first conductive pillar 152 and the second conductive pillar 252 may include the same material as the first chip support structure 170 and the second chip support structure 270. For example, the first chip support structure 170 and the second chip support structure 270 may be formed by an electroplating process (e.g., electrolytic plating or chemical plating). In some embodiments, the electroplating process for forming the first conductive pillar 152 and the second conductive pillar 252 and the electroplating process for forming the first chip support structure 170 and the second chip support structure 270 may be performed separately. In some embodiments, the upper portions of the first chip support structure 170 and the second chip support structure 270 may be formed together by the electroplating process for forming the first conductive pillar 152 and the second conductive pillar 252, and the lower portions of the first chip support structure 170 and the second chip support structure 270 may be formed by an additional electroplating process. The first conductive cap 154 ​​and the second conductive cap 254 may include, for example, silver (Ag), tin (Sn), gold (Au), or solder. In some embodiments, the first conductive cap 154 ​​and the second conductive cap 254 may include SnAg.

[0075] The first front connection pad 112 may be embedded in the first front protective layer 142. For example, the lowermost end of the first front protective layer 142 may be disposed at a vertical level lower than the vertical level of the lower surface of the first front connection pad 112. The first front protective layer 142 may cover a portion of the lower surface of the first front connection pad 112 (e.g., a portion of the lower surface adjacent to the edge) and the side surface. The second front connection pad 212 may be embedded in the second front protective layer 242. For example, the lowermost end of the second front protective layer 242 may be disposed at a vertical level lower than the vertical level of the lower surface of the second front connection pad 212. The second front protective layer 242 may cover a portion of the lower surface of the second front connection pad 212 (e.g., a portion of the lower surface adjacent to the edge) and the side surface.

[0076] An upper portion of the first conductive pillar 152 may extend into the first front protective layer 142 and may contact the first actual front connection pad 112R. An upper portion of the second conductive pillar 252 may extend into the second front protective layer 242 and may contact the second actual front connection pad 212R.

[0077] The package upper pad 522 may be embedded in the upper solder resist layer 532. For example, the uppermost end of the upper solder resist layer 532 may be disposed at a vertical level higher than the vertical level of the upper surface of the package upper pad 522. The upper solder resist layer 532 may cover a portion of the upper surface of the package upper pad 522 (e.g., a portion of the upper surface adjacent to the edge) and the side surface. A portion of the second rear connection pad 214 may protrude from the first rear protective layer 144 or the second rear protective layer 244. For example, the upper surface of the second rear connection pad 214 may be disposed at a vertical level higher than the vertical level of the uppermost end of the first rear protective layer 144 or the second rear protective layer 244. In some embodiments, each of the first rear protective layer 144 and the second rear protective layer 244 may cover a portion of the side surface of the second rear connection pad 214 (e.g., the lower portion of the side surface), but not the upper surface.

[0078] In some embodiments, the lower portion of the first conductive cap 154 ​​may extend into the upper solder resist layer 532 and contact the package upper pad 522. In some embodiments, the second conductive cap 254 does not extend into the first rear protective layer 144 or the second rear protective layer 244, but may contact the second rear connection pad 214.

[0079] An upper portion of the first chip support structure 170 may extend into the first front protective layer 142, and a lower portion of the first chip support structure 170 may extend into the upper solder resist layer 532. In some embodiments, the first chip support structure 170 does not penetrate the first front protective layer 142 and the upper solder resist layer 532. An upper portion of the first chip support structure 170 may extend into the first front protective layer 142 so that an upper surface of the first chip support structure 170 may contact the first dummy front connection pad 112D, and a lower portion of the first chip support structure 170 may extend into the upper solder resist layer 532 so that a lower surface of the first chip support structure 170 may contact the upper solder resist layer 532. For example, the upper solder resist layer 532 may have a first groove GR1 extending inwardly from an upper surface, and a lower portion of the first chip support structure 170 may fill the first groove GR1.

[0080] The upper portion of the second chip support structure 270 may extend into the second front protective layer 242, and the lower portion of the second chip support structure 270 may extend into the first rear protective layer 144 or the second rear protective layer 244. In some embodiments, the second chip support structure 270 does not penetrate the first front protective layer 142, the first rear protective layer 144, and the second rear protective layer 244. The upper portion of the second chip support structure 270 may extend into the second front protective layer 242 so that the upper surface of the second chip support structure 270 may contact the second dummy front connection pad 212D, and the lower portion of the second chip support structure 270 may extend into the first rear protective layer 144 or the second rear protective layer 244 so that the lower surface of the second chip support structure 270 may contact the first rear protective layer 144 or the second rear protective layer 244. For example, each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2 extending inward from the upper surface, and the lower portion of the second chip support structure 270 may fill the second groove GR2.

[0081] The lower portion of the first chip support structure 170 may extend from the top to the bottom and may have a tapered shape with a reduced horizontal width. Corresponding to the lower portion of the first chip support structure 170 having a tapered shape, the first groove GR1 may have a tapered shape extending from the top to the bottom and having a reduced horizontal width. The lower portion of the second chip support structure 270 may have a tapered shape extending from the top to the bottom and having a reduced horizontal width. Corresponding to the lower portion of the second chip support structure 270 having a tapered shape, the second groove GR2 may have a tapered shape extending from the top to the bottom and having a reduced horizontal width.

[0082] The first chip connection terminal 150 may have a first thickness T1, the first conductive pillar 152 may have a second thickness T2, and the first chip support structure 170 may have a third thickness T3. The third thickness T3 may have a value greater than the second thickness T2. In some embodiments, the third thickness T3 may have a value greater than the first thickness T1. The third thickness T3 may have a value greater than the gap between the upper solder resist layer 532 and the first front protective layer 142. For example, the first thickness T1 may be between about 15 μm and about 30 μm, the second thickness T2 may be less than the first thickness T1, and may be between about 10 μm and about 20 μm, and the third thickness T3 may have a value greater than the first thickness T1 by about 0.5 μm to about 3 μm. The first thickness T1, the second thickness T2, and the third thickness T3 may be referred to as a first height, a second height, and a third height, respectively. The first conductive pillar 152 may have a first horizontal width W1, and the first chip support structure 170 may have a second horizontal width W2. In some embodiments, the second horizontal width W2 may have a value greater than the first horizontal width W1. For example, the first horizontal width W1 may be between about 15 μm and about 40 μm, and the second horizontal width W2 may be about 5% to about 20% greater than the first horizontal width W1. The uppermost end of the upper solder resist layer 532 may be disposed on the package upper pad 522 and may be disposed at a first vertical level L1. A portion of the upper surface of the upper solder resist layer 532 that contacts the first chip support structure 170 may be disposed at a second vertical level L2 that is lower than the first vertical level L1.

[0083] The second chip connection terminal 250 may have a fourth thickness T4, the second conductive pillar 252 may have a fifth thickness T5, and the second chip support structure 270 may have a sixth thickness T6. The sixth thickness T6 may have a value greater than the fifth thickness T5. In some embodiments, the sixth thickness T6 may have a value greater than the fourth thickness T4. In some embodiments, the fourth thickness T4 may have a value substantially the same as the first thickness T1, the fifth thickness T5 may have a value substantially the same as the second thickness T2, and the sixth thickness T6 may have a value substantially the same as the third thickness T3. The sixth thickness T6 may have a value greater than the interval between the first rear protective layer 144 and the second front protective layer 242 facing each other, and the interval between the second rear protective layer 244 and the second front protective layer 242 facing each other. For example, the fourth thickness T4 may be between about 15 μm and about 30 μm, the fifth thickness T5 may be less than the fourth thickness T4, and between about 10 μm and about 20 μm, and the sixth thickness T6 may have a value greater than the fourth thickness T4 by about 0.5 μm to about 3 μm. The fourth thickness T4, the fifth thickness T5, and the sixth thickness T6 may be referred to as a fourth height, a fifth height, and a sixth height, respectively. The second conductive pillar 252 may have a third horizontal width W3, and the second chip support structure 270 may have a fourth horizontal width W4. In some embodiments, the fourth horizontal width W4 may have a value greater than the third horizontal width W3. In some embodiments, the first horizontal width W1 may have approximately the same value as the third horizontal width W3, and the second horizontal width W2 may have approximately the same value as the fourth horizontal width W4. For example, the third horizontal width W3 may be between about 15 μm and about 40 μm, and the fourth horizontal width W4 may have a value of about 5% to about 20% greater than the third horizontal width W3. A portion of the upper surface of the first rear protective layer 144 in contact with the first rear connection pad 114 or a portion of the upper surface of the second rear protective layer 244 in contact with the second rear connection pad 214 may be disposed at a third vertical level L3, and a portion of the upper surface of the first rear protective layer 144 in contact with the second chip support structure 280 or a portion of the upper surface of the second rear protective layer 244 in contact with the second chip support structure 280 may be disposed at a fourth vertical level L4. In some embodiments, the third vertical level L3 may be substantially the same as the fourth vertical level L4.

[0084] The first groove GR1 may have a first depth D1 from the upper surface of the upper solder resist layer 532 (i.e., the second vertical level L2), and the second groove GR2 may have a second depth D2 from the upper surface of each of the first rear protective layer 144 and the second rear protective layer 244 (i.e., the fourth vertical level L4). In some embodiments, the first depth D1 may have a value substantially the same as the second depth D2. In some embodiments, the vertical level difference between the first vertical level L1 and the upper surface of the package upper pad 522 may have a value less than the first depth D1. For example, the first depth D1 and the second depth D2 may both be between about 0.5 μm and about 2 μm.

[0085] Since the semiconductor package 1 according to the embodiment of the inventive concept includes the first chip support structure 170 and the second chip support structure 270, in the process of attaching the first semiconductor chip 100 and the second semiconductor chip 200 to the package substrate 500 and forming the mold layer 900 around the first semiconductor chip 100 and the second semiconductor chip 200, a lower clamp may be provided below the package substrate 500, an upper clamp may be provided above the uppermost second semiconductor chip 200T, and then pressure may be applied between the lower clamp and the upper clamp. As a result, warpage may be prevented from occurring in the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200 included in the semiconductor package 1, and the reliability of the structure and the reliability of the electrical connection between the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200 may be improved.

[0086] In addition, in the semiconductor package 1 according to an embodiment of the inventive concept, since the first and second chip support structures 170 and 270 are coupled to the first and second grooves GR1 and GR2, misalignment between the package substrate 500, the first and second semiconductor chips 100 and 200 can be prevented.

[0087] Figure 3A and Figure 3B is an enlarged cross-sectional view of a semiconductor package 1 according to an embodiment. For example, Figure 3A and Figure 3B It shows Figure 1 An enlarged cross-sectional view of portion B1 and portion D1.

[0088] refer to Figure 1 as well as Figure 3A and Figure 3B , the semiconductor package 1 includes a plurality of first chip support structures 170 a and a plurality of second chip support structures 270 a instead of the first chip support structure 170 and the second chip support structure 270 .

[0089] The upper solder resist layer 532 may have a first groove GR1a extending inward from the upper surface, and the lower portion of the first chip support structure 170a may fill the first groove GR1a. Each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2a extending inward from the upper surface, and the lower portion of the second chip support structure 270a may fill the second groove GR2a.

[0090] The first chip support structure 170a may extend from the top to the bottom and may have substantially the same horizontal width. Corresponding to the first chip support structure 170a having substantially the same horizontal width, the first groove GR1a may extend from the top to the bottom and may have substantially the same horizontal width. The lower portion of the second chip support structure 270a may extend from the top to the bottom and may have substantially the same horizontal width. Corresponding to the second chip support structure 270a having substantially the same horizontal width, the second groove GR2a may extend from the top to the bottom and may have substantially equal horizontal widths.

[0091] Figure 4A and Figure 4B is an enlarged cross-sectional view of a semiconductor package 1 according to an embodiment. For example, Figure 4A and Figure 4B It shows Figure 1 An enlarged cross-sectional view of portion B1 and portion D1.

[0092] refer to Figure 1 as well as Figure 4A and Figure 4B , the semiconductor package 1 includes a plurality of first chip support structures 170 b and a plurality of second chip support structures 270 b instead of the first chip support structure 170 and the second chip support structure 270 .

[0093] The upper solder resist layer 532 may have a first groove GR1b extending inward from the upper surface, and the lower portion of the first chip support structure 170b may fill the first groove GR1b. Each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2b extending inward from the upper surface, and the lower portion of the second chip support structure 270b may fill the second groove GR2b.

[0094] The lower portion of the first chip support structure 170b may be convex downward. Corresponding to the lower portion of the first chip support structure 170b having a convex shape, the first groove GR1b may be recessed inward from the upper surface of the upper solder resist layer 532. The lower portion of the second chip support structure 270b may be convex downward. Corresponding to the lower portion of the second chip support structure 270b having a convex shape, the second groove GR2b may be recessed inward from the upper surface of each of the first rear protective layer 144 and the second rear protective layer 244.

[0095] Figure 5A and Figure 5B is an enlarged cross-sectional view of a semiconductor package 1 according to an embodiment. For example, Figure 5A and Figure 5B It shows Figure 1 An enlarged cross-sectional view of portion B1 and portion D1.

[0096] refer to Figure 1 as well as Figure 5A and Figure 5B , the semiconductor package 1 includes a plurality of first chip support structures 170 c and a plurality of second chip support structures 270 c instead of the first chip support structure 170 and the second chip support structure 270 .

[0097] The upper solder resist layer 532 may have a first groove GR1c extending inward from the upper surface, and the lower portion of the first chip support structure 170c may fill the first groove GR1c. Each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2c extending inward from the upper surface, and the lower portion of the second chip support structure 270c may fill the second groove GR2c.

[0098] The first chip support structure 170c may have a third thickness T3a, and the second chip support structure 270c may have a sixth thickness T6a. The first groove GR1c may have a first depth D1a from the upper surface of the upper solder resist layer 532 (i.e., the second vertical level L2), and the second groove GR2c may have a second depth D2a from the upper surface of each of the first rear protective layer 144 and the second rear protective layer 244 (i.e., the fourth vertical level L4). In some embodiments, the first depth D1a may have a value greater than the second depth D2a, and the sixth thickness T6a may have a value greater than the third thickness T3a. For example, the first depth D1a may have a value of about 0.5 μm to about 5 μm greater than the second depth D2a, and the sixth thickness T6a may have a value of about 0.5 μm to about 5 μm greater than the third thickness T3a.

[0099] Despite Figure 5A and Figure 5B170c and 270c. The lower portion of each of the first chip support structure 170c and the second chip support structure 270c is shown to have a tapered shape extending from the top to the bottom and having a reduced horizontal width, and each of the first groove GR1c and the second groove GR2c has a corresponding shape, but the inventive concept is not limited thereto. For example, in some embodiments, each of the first chip support structure 170c and the second chip support structure 270c may extend from the top to the bottom and have substantially the same horizontal width, and each of the first groove GR1c and the second groove GR2c may have a corresponding shape, with Figure 3A and Figure 3B In some embodiments, for example, the lower portion of each of the first chip support structure 170c and the second chip support structure 270c may be convex downward, and each of the first groove GR1c and the second groove GR2c may have a corresponding shape, similar to the first chip support structure 170a and the second chip support structure 270a shown in FIG. Figure 4A and Figure 4B The first chip support structure 170 b and the second chip support structure 270 b shown in FIG. 1 are similar.

[0100] Fig. 6A and Figure 6B is an enlarged cross-sectional view of a semiconductor package 1 according to an embodiment. For example, Fig. 6A and Figure 6B It shows Figure 1 An enlarged cross-sectional view of portion B1 and portion D1.

[0101] refer to Figure 1 as well as Fig. 6A and Figure 6B , the semiconductor package 1 includes a plurality of first chip support structures 170 a and a plurality of second chip support structures 270 a instead of the first chip support structure 170 and the second chip support structure 270 .

[0102] The upper solder resist layer 532 may have a first groove GR1d extending inward from the upper surface, and the lower portion of the first chip support structure 170a may fill a portion of the first groove GR1d. Each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2d extending inward from the upper surface, and the lower portion of the second chip support structure 270a may fill a portion of the second groove GR2d.

[0103] The first chip support structure 170a may have a second width W2, and the first groove GR1d may have a fifth width W5 greater than the second width W2. For example, the fifth width W5 may have a value of about 0.5 μm to about 2 μm greater than the second width W2. The second chip support structure 270a may have a fourth width W4, and the second groove GR2d may have a sixth width W6 greater than the fourth width W4. For example, the sixth width W6 may have a value of about 0.5 μm to about 2 μm greater than the fourth width W4.

[0104] Despite Fig. 6A and Figure 6B 1 and 2 show that the first chip support structure 170a and the second chip support structure 270a each extend from the top to the bottom and have substantially the same horizontal width, and the first groove GR1d and the second groove GR2d each correspond thereto and have a larger horizontal width, but the inventive concept is not limited thereto. For example, in some embodiments, the lower portion of each of the first chip support structure 170a and the second chip support structure 270a may extend from the top to the bottom and have a tapered shape with a reduced horizontal width, and each of the first groove GR1d and the second groove GR2d may correspond thereto and have a shape with a larger horizontal width, and ... Figure 2A and Figure 2B Each of the first chip support structure 170 and the second chip support structure 270 shown in FIG. 1 is similar to each of the first chip support structure 170a and the second chip support structure 270a. In some embodiments, for example, the lower portion of each of the first chip support structure 170a and the second chip support structure 270a may be convex downward, and each of the first groove GR1d and the second groove GR2d may correspond thereto and have a larger horizontal width than the first groove GR1d and the second groove GR2d. Figure 4A and Figure 4B Each of the first chip support structure 170 b and the second chip support structure 270 b shown in FIG. 1 is similar.

[0105] Figure 7 is a cross-sectional view of a semiconductor package 1 a according to the embodiment.

[0106] refer to Figure 7 The semiconductor package 1 a may include a package substrate 500 , a first semiconductor chip 100 attached to the package substrate 500 , a second semiconductor chip 200 stacked on the first semiconductor chip 100 , and a mold layer 900 surrounding the first and second semiconductor chips 100 and 200 on the package substrate 500 .

[0107] The semiconductor package 1a further includes a first chip support structure 170 and a second chip support structure 270. In some embodiments, the number of first chip support structures 170 disposed on the lower surface of the first semiconductor chip 100 may be greater than the number of second chip support structures 270 disposed on the lower surface of each second semiconductor chip 200 (i.e., the lower surface of one second semiconductor chip 200).

[0108] Figure 8 is a cross-sectional view of a semiconductor package 1 b according to the embodiment.

[0109] refer to Figure 8 The semiconductor package 1 b may include a package substrate 500 , a first semiconductor chip 100 attached to the package substrate 500 , a second semiconductor chip 200 stacked on the first semiconductor chip 100 , and a mold layer 900 surrounding the first and second semiconductor chips 100 and 200 on the package substrate 500 .

[0110] The semiconductor package 1b further includes a plurality of first chip support structures 170d and a plurality of second chip support structures 270d. In some embodiments, the number of first chip support structures 170d disposed on the lower surface of the first semiconductor chip 100 may be substantially equal to the number of second chip support structures 270d disposed on the lower surface of each second semiconductor chip 200 (i.e., one second semiconductor chip 200).

[0111] Fig. 9A and Fig. 9B is an enlarged cross-sectional view of a semiconductor package 1b according to an embodiment. For example, Fig. 9A and Fig. 9B It shows Figure 8 An enlarged cross-sectional view of portion B2 and portion D2.

[0112] refer to Figure 8 , Fig. 9A and Fig. 9B , the first chip support structure 170d may have a second horizontal width W2a, and the second chip support structure 270d may have a fourth horizontal width W4a. In some embodiments, the second horizontal width W2a may have a value greater than the fourth horizontal width W4a. For example, the fourth horizontal width W4a may have a value greater than Figure 2A The first horizontal width W1 shown in FIG. 5 has a value of about 5% to about 20%, and the second horizontal width W2a may have a value of about 5% to about 20% greater than the fourth horizontal width W4a.

[0113] The upper solder resist layer 532 may have a first groove GR1e extending inward from the upper surface, and the lower portion of the first chip support structure 170d may fill a portion of the first groove GR1e. Each of the first rear protective layer 144 and the second rear protective layer 244 may have a second groove GR2e extending inward from the upper surface, and the lower portion of the second chip support structure 270d may fill a portion of the second groove GR2e.

[0114] Figure 8 The enlarged cross-sectional view of the portion A2 and the portion C2 may correspond to Figure 2A and Figure 2C In addition, in some embodiments, reference may be made to FIG. 3A to FIG. 6B The shape of each of the first chip supporting structure 170d, the second chip supporting structure 270d, the first groove GR1e, and the second groove GR2e is modified.

[0115] Fig.10 is a cross-sectional view of a semiconductor package 1 c according to the embodiment.

[0116] refer to Fig.10 The semiconductor package 1 c may include a package substrate 500 , a first semiconductor chip 100 attached to the package substrate 500 , a second semiconductor chip 200 stacked on the first semiconductor chip 100 , and a mold layer 900 surrounding the first and second semiconductor chips 100 and 200 on the package substrate 500 .

[0117] The semiconductor package 1c further includes a first chip support structure 170d and a second chip support structure 270d. In some embodiments, the number of first chip support structures 170d disposed on the lower surface of the first semiconductor chip 100 may be greater than the number of second chip support structures 270d disposed on the lower surface of each second semiconductor chip 200 (i.e., the lower surface of one second semiconductor chip 200).

[0118] Fig.11 , Fig.12 , FIG. 13A to FIG. 13D , Fig.14 and FIG. 15A to FIG. 15D 2 is a cross-sectional view and an enlarged cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment. FIG. 13A to FIG. 13D It shows Fig.12 an enlarged cross-sectional view of a portion A3, a portion B3, a portion C3, and a portion D3, and FIG. 15A to FIG. 15D It shows Fig.14 An enlarged cross-sectional view of portion A4, portion B4, portion C4 and portion D4.

[0119] refer to Fig.11, prepare a package substrate 500. The package substrate 500 may include a package base insulating layer 510, a package conductive pattern 520, and a solder resist layer 530. The package conductive pattern 520 may include a package upper pad 522, a package lower pad 524, and a connection pattern 526. The package upper pad 522 may be disposed on an upper surface of the package base insulating layer 510, and the package lower pad 524 may be disposed on a lower surface of the package base insulating layer 510. The connection pattern 526 may electrically connect the package upper pad 522 to the package lower pad 524.

[0120] exist Fig.11 , the package connection terminal 550 is shown as being attached to the package lower pad 524 on the lower surface of the package substrate 500. However, this is an example provided for convenience of explanation, and the inventive concept is not limited thereto. For example, in some embodiments, the package connection terminal 550 may be attached to the package lower pad 524 in a subsequent operation. For example, in the formation of Figure 1 The package connection terminal 550 is then attached to the package lower pad 524 through the molding layer 900 shown in FIG.

[0121] refer to Fig.12 , a first semiconductor chip 100 and a second semiconductor chip 200 are sequentially arranged on a package substrate 500. The first semiconductor chip 100 may be arranged on the package substrate 500 so that the first chip connection terminal 150 corresponds to the package upper pad 522 of the package substrate 500. Among the second semiconductor chips 200, the lowermost second semiconductor chip 200 may be arranged on the first semiconductor chip 100 so that the second chip connection terminal 250 corresponds to the first rear connection pad 114 of the first semiconductor chip 100, and the other second semiconductor chips 200 may be arranged on the second semiconductor chip 200 located therebelow so that the second chip connection terminal 250 corresponds to the second rear connection pad 214 of the second semiconductor chip 200 located therebelow.

[0122] In some embodiments, the first chip connection terminal 150 may be in contact with the package upper pad 522, but the first chip support structure 170 is not in contact with the upper solder resist layer 532, and the second chip connection terminal 250 may be in contact with the first rear connection pad 114 or the second rear connection pad 214, but the second chip support structure 270 is not in contact with the first rear protective layer 144 or the second rear protective layer 244.

[0123] refer to Fig.12 as well as FIG. 13A to FIG. 13D, the first semiconductor chip 100 may be disposed on the package substrate 500 so that the first chip connection terminal 150 contacts the package upper pad 522. For example, the first conductive cap 154 ​​of the first chip connection terminal 150 may contact the package upper pad 522. The first chip connection terminal 150 may have a seventh thickness T7. The seventh thickness T7 may have a thickness greater than Figure 2A The value of the first thickness T1 is shown in . The seventh thickness T7 may be referred to as a seventh height.

[0124] In some embodiments, the first chip support structure 170 does not contact the upper solder resist layer 532, but is spaced apart from the upper solder resist layer 532. In some embodiments, the vertical level of the lower end of the first chip support structure 170 may be higher than the second vertical level L2, so that the first chip support structure 170 does not fill the first groove GR1, but the inventive concept is not limited thereto. For example, in some embodiments, the first chip support structure 170 does not contact the upper solder resist layer 532, but may extend into the first groove GR1, so that the lower portion of the first chip support structure 170 may be disposed within the first groove GR1.

[0125] The lowermost second semiconductor chip 200 among the second semiconductor chips 200 may be disposed on the first semiconductor chip 100 such that the second chip connection terminal 250 contacts the first rear connection pad 114, and other second semiconductor chips 200 among the second semiconductor chips 200 may be disposed on the second semiconductor chip 200 located therebelow such that the second chip connection terminal 250 contacts the second rear connection pad 214. For example, the second conductive cap 254 of the second chip connection terminal 250 may contact the first rear connection pad 114 or the second rear connection pad 214. The second chip connection terminal 250 may have an eighth thickness T8. The eighth thickness T8 may have a thickness greater than Figure 2C The value of the fourth thickness T4 is shown in . The eighth thickness T8 may be referred to as an eighth height.

[0126] In some embodiments, the second chip support structure 270 does not contact the first rear protective layer 144 or the second rear protective layer 244, but is spaced apart from the first rear protective layer 144 or the second rear protective layer 244. In some embodiments, the vertical level of the lower end of the second chip support structure 270 may be higher than the fourth vertical level L4, so that the second chip support structure 270 does not fill the second groove GR2, but the inventive concept is not limited thereto. For example, in some embodiments, the second chip support structure 270 does not contact the first rear protective layer 144 or the second rear protective layer 244, but extends into the second groove GR2, so that the lower portion of the second rear protective layer 244 may be disposed within the second groove GR2.

[0127] refer to Fig.14, a reflow process may be performed to attach the first chip connection terminals 150 to the package upper pads 522 and to attach the second chip connection terminals 250 to the first and second rear connection pads 114 and 214 .

[0128] refer to Fig.14 and FIG. 15A to FIG. 15D By the reflow process, the first conductive cap 154 ​​of the first chip connection terminal 150 may be coupled to the package upper pad 522, and the second conductive cap 254 of the second chip connection terminal 250 may be coupled to the first rear connection pad 114 or the second rear connection pad 214. By the reflow process, the thickness of each of the first conductive cap 154 ​​of the first chip connection terminal 150 and the second conductive cap 254 of the second chip connection terminal 250 may be reduced, so that the first chip connection terminal 150 may have a first thickness T1, and the second chip connection terminal may have a fourth thickness T4. The first thickness T1 may have a thickness less than Fig.13A The value of the seventh thickness T7 shown in FIG. 1 and the fourth thickness T4 may have a value less than Fig. 13C The value of the eighth thickness T8 shown in .

[0129] As the thickness of the first chip connection terminal 150 is reduced through the reflow process, the first chip support structure 170 can extend into the first groove GR1 so that the lower portion can fill the first groove GR1 and contact the upper solder resist layer 532, and as the thickness of the second chip connection terminal 250 is reduced through the reflow process, the second chip support structure 270 can extend into the second groove GR2 so that the lower portion can fill the second groove GR2 and contact the first rear protective layer 144 or the second rear protective layer 244.

[0130] Afterwards, you can Figure 1 A mold layer 900 surrounding the first semiconductor chip 100 and the second semiconductor chip 200 is formed on the package substrate 500 shown in FIG. 1 to form the semiconductor package 1 .

[0131] refer to Figures 1 to 15DIn the semiconductor package 1 according to the embodiment of the inventive concept, in the process of performing the reflow process and forming the mold layer 900, the first chip support structure 170 may be coupled to the first groove GR1, and the second chip support structure 270 may be coupled to the second groove GR2, which can prevent misalignment between the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200. In addition, since the intervals between the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200 are maintained by the first chip support structure 170 and the second chip support structure 270, although pressure is applied between the lower jig and the upper jig after the lower jig is set below the package substrate 500 and the upper jig is set on the uppermost semiconductor chip 200T, warpage can be prevented from occurring in the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200 included in the semiconductor package 1. As a result, structural reliability and electrical connection reliability between the package substrate 500, the first semiconductor chip 100, and the second semiconductor chip 200 can be improved.

[0132] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor package, comprising: A plurality of semiconductor chips are stacked in a first direction; a plurality of chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and electrically connecting the two adjacent semiconductor chips; as well as A plurality of chip support structures are arranged between the two adjacent semiconductor chips, wherein the plurality of chip support structures do not electrically connect the two adjacent semiconductor chips and are spaced apart from the plurality of chip connection terminals in a second direction intersecting the first direction, Wherein, the thickness of each of the plurality of chip supporting structures is greater than the thickness of each of the plurality of chip connecting terminals.

2. The semiconductor package according to claim 1, wherein Each of the plurality of semiconductor chips includes a substrate, a front protective layer disposed on a lower surface of the substrate, and a rear protective layer disposed on an upper surface of the substrate, and The plurality of chip support structures extend into a rear protection layer of a semiconductor chip disposed at a lower side among the plurality of semiconductor chips.

3. The semiconductor package according to claim 2, wherein: The rear protective layer has a groove extending inwardly from an upper surface of the rear protective layer, The groove does not penetrate the rear protective layer, and A lower portion of each of the plurality of chip supporting structures fills the groove.

4. The semiconductor package according to claim 3, wherein: A lower portion of each of the plurality of chip supporting structures and the groove extends from an upper side to a lower side and has a tapered shape with a reduced horizontal width.

5. The semiconductor package according to claim 3, wherein: A lower portion of each of the plurality of chip supporting structures protrudes downward, and the groove is recessed inward from an upper surface of the rear protective layer.

6. The semiconductor package according to claim 1, wherein Each of the plurality of chip connection terminals includes a chip conductive column and a chip conductive cap covering a lower surface of the chip conductive column, and A horizontal width of each of the plurality of chip supporting structures is greater than a horizontal width of a chip conductive pillar of each of the plurality of chip connecting terminals.

7. The semiconductor package according to claim 1, further comprising: A packaging substrate, disposed below the plurality of semiconductor chips; a plurality of substrate connection terminals disposed between a lowermost semiconductor chip among the plurality of semiconductor chips and the package substrate and electrically connecting the lowermost semiconductor chip to the package substrate; as well as A plurality of substrate support structures are disposed between the lowermost semiconductor chip and the packaging substrate, wherein the plurality of substrate support structures do not electrically connect the lowermost semiconductor chip to the package substrate and are spaced apart from the plurality of substrate connection terminals in the second direction, Wherein, the thickness of each of the plurality of substrate supporting structures is greater than the thickness of each of the plurality of substrate connecting terminals.

8. The semiconductor package according to claim 7, wherein: A horizontal width of each of the plurality of substrate supporting structures is greater than a horizontal width of each of the plurality of substrate connecting terminals.

9. The semiconductor package according to claim 7, wherein: The number of the plurality of substrate supporting structures is greater than the number of the plurality of chip supporting structures disposed between the two adjacent semiconductor chips in the first direction.

10. The semiconductor package according to claim 7, wherein: A horizontal width of each of the plurality of substrate supporting structures has a value greater than a horizontal width of each of the plurality of chip supporting structures.

11. A semiconductor package, comprising: A packaging substrate, comprising a packaging base insulating layer, a lower solder resist layer covering a lower surface of the packaging base insulating layer, and an upper solder resist layer covering an upper surface of the packaging base insulating layer; A plurality of semiconductor chips, each semiconductor chip comprising a substrate, a front protective layer disposed on a lower surface of the substrate, and a rear protective layer disposed on an upper surface of the substrate, The plurality of semiconductor chips include a first semiconductor chip disposed on the packaging substrate, and a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip in a first direction; a plurality of first chip connection terminals disposed between the package substrate and the first semiconductor chip and electrically connecting the package substrate to the first semiconductor chip; a plurality of first chip support structures, arranged between the packaging substrate and the first semiconductor chip, wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in the second direction and extend into the upper solder resist layer; a plurality of second chip connection terminals arranged between two semiconductor chips arranged adjacent to each other in the first direction among the plurality of semiconductor chips; wherein the plurality of second chip connection terminals electrically connect two adjacent semiconductor chips, and the second direction intersects the first direction; and a plurality of second chip support structures, arranged between the two adjacent semiconductor chips, The plurality of second chip support structures extend into a rear protection layer included in a lower semiconductor chip among the two adjacent semiconductor chips.

12. The semiconductor package according to claim 11, wherein The plurality of first chip support structures extend into the upper solder resist layer and do not penetrate the upper solder resist layer, and The plurality of second chip support structures extend into the rear protective layer and do not penetrate the rear protective layer.

13. The semiconductor package according to claim 12, wherein: Each of the plurality of first chip support structures extends into a first groove extending inwardly from the upper surface of the upper solder resist layer, Each of the plurality of second chip support structures extends into a second groove extending inwardly from the upper surface of the rear protective layer, The horizontal width of the first groove is greater than the horizontal width of each of the plurality of first chip supporting structures, and The horizontal width of the second groove is greater than the horizontal width of each of the plurality of second chip supporting structures.

14. The semiconductor package according to claim 11, wherein Each of the plurality of first chip connection terminals includes a first chip conductive column and a first chip conductive cap covering a lower surface of the first chip conductive column, and each of the plurality of second chip connection terminals includes a second chip conductive column and a second chip conductive cap covering a lower surface of the second chip conductive column, and The horizontal width of each of the plurality of first chip supporting structures is greater than the horizontal width of the first chip conductive pillar, and the horizontal width of each of the plurality of second chip supporting structures is greater than the horizontal width of the second chip conductive pillar.

15. The semiconductor package according to claim 14, wherein: The horizontal width of the first chip conductive column is equal to the horizontal width of the second chip conductive column, and The horizontal width of the first chip supporting structure is greater than the horizontal width of the second chip supporting structure.

16. The semiconductor package according to claim 14, wherein: The number of the plurality of first chip supporting structures is greater than the number of the plurality of second chip supporting structures.

17. The semiconductor package according to claim 14, wherein: The first chip conductive pillar, the second chip conductive pillar, the first chip supporting structure and the second chip supporting structure include the same material.

18. A semiconductor package, comprising: A package substrate, comprising a package base insulating layer, a plurality of package upper pads arranged on an upper surface of the package base insulating layer, a plurality of package lower pads arranged on a lower surface of the package base insulating layer, a plurality of connection pads electrically connecting the plurality of package upper pads to the plurality of package lower pads, an upper solder resist layer covering the upper surface of the package base insulating layer but not covering at least a portion of an upper surface of each of the plurality of package upper pads, and a lower solder resist layer covering the lower surface of the package base insulating layer but not covering at least a portion of a lower surface of each of the plurality of package lower pads; a plurality of semiconductor chips, including a first semiconductor chip and a plurality of second semiconductor chips sequentially stacked on the packaging substrate in a first direction, wherein each of the first semiconductor chip and the plurality of second semiconductor chips comprises a substrate, a plurality of rear connection pads disposed on an upper surface of the substrate, a plurality of front connection pads disposed on a lower surface of the substrate, a plurality of through electrodes vertically penetrating at least a portion of the substrate and electrically connecting the plurality of rear connection pads to the plurality of front connection pads, a front protective layer disposed on the lower surface of the substrate and not covering at least a portion of a lower surface of each of the plurality of front connection pads, and a rear protective layer disposed on the upper surface of the substrate and not covering at least a portion of an upper surface of each of the plurality of rear connection pads; a plurality of first chip connection terminals, disposed between the plurality of package upper pads of the package substrate and the plurality of front connection pads of the first semiconductor chip; a plurality of first chip support structures, arranged between the packaging substrate and the first semiconductor chip, wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in the second direction, extend into the upper solder resist layer, and do not penetrate the upper solder resist layer; a plurality of second chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips, and disposed between the plurality of rear connection pads and the plurality of front connection pads included in the two adjacent semiconductor chips and facing each other, wherein the second direction intersects the first direction; and a plurality of second chip support structures, arranged between the two adjacent semiconductor chips, The plurality of second chip support structures extend into the rear protective layer included in the lower semiconductor chip among the two adjacent semiconductor chips and do not penetrate the rear protective layer.

19. The semiconductor package according to claim 18, wherein: Each of the plurality of first chip connection terminals includes a first chip conductive column and a first chip conductive cap covering a lower surface of the first chip conductive column. Each of the plurality of second chip connection terminals includes a second chip conductive column and a second chip conductive cap covering a lower surface of the second chip conductive column, and Each of the first chip conductive pillar, the second chip conductive pillar, the first chip supporting structure, and the second chip supporting structure includes metal.

20. The semiconductor package according to claim 19, wherein The horizontal width of each of the first chip conductive pillar and the second chip conductive pillar is between 15 μm and 40 μm, and The horizontal width of the first chip supporting structure is 5% to 20% greater than the horizontal width of the first chip conductive pillar, and the horizontal width of the second chip supporting structure is 5% to 20% greater than the horizontal width of the second chip conductive pillar.

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