Semiconductor packaging structure

Abstract

The invention discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a conductive substrate, a chip, a plurality of conductive spacers, a conductive support and a packaging body wrapping the conductive substrate, the chip, the conductive spacers and the conductive support. The conductive substrate is provided with a solid crystal face and a heat dissipation face which are located on the two opposite sides respectively. The chip is arranged on the solid crystal face of the conductive substrate and is provided with a plurality of connecting pads far away from the conductive substrate. The plurality of conductive spacers are respectively arranged on the plurality of connecting pads, and the tail ends of the plurality of conductive spacers are far away from the plurality of conductive substrates and are arranged in a coplanar manner. The conductive bracket is connected to the tail ends of the plurality of conductive spacers in a flip-chip manner, and the conductive bracket has an exposed surface. And the heat dissipation surface and the exposed surface are exposed out of the packaging body. Therefore, according to the semiconductor packaging structure, the conductive bracket is mounted in a flip chip manner, so that the influence caused by the height difference among a plurality of components is effectively reduced.

Description

Technical Field

[0001] The present application relates to a packaging structure, and in particular to a semiconductor packaging structure. Background Art

[0002] There are often height differences between the multiple internal components of the existing semiconductor packaging structure, which is not conducive to maintaining the connection stability of the multiple internal components. For example, after the existing semiconductor packaging structure undergoes packaging thermal cycles, cracks often occur inside it. Therefore, the applicant believes that the above defects can be improved, so he has devoted himself to research and combined with the application of scientific principles, and finally proposed an invention with a reasonable design and effective improvement of the above defects. Summary of the invention

[0003] The present application provides a semiconductor packaging structure, which can effectively improve the defects that may occur in the existing semiconductor packaging structure.

[0004] The present application discloses a semiconductor packaging structure, which includes: a conductive substrate having a crystal-bonding surface and a heat-dissipating surface respectively located on opposite sides; a first chip arranged on the crystal-bonding surface of the conductive substrate, and the first chip has a plurality of first connection pads away from the conductive substrate; a second chip arranged on a first connection pad of the first chip, and the second chip has a plurality of second connection pads away from the conductive substrate; a plurality of conductive spacers, one of which is arranged on another first connection pad and is defined as a first conductive spacer, and the remaining conductive spacers are respectively arranged on the plurality of second connection pads and are respectively defined as It means a second conductive spacer; wherein, the height of the first conductive spacer is greater than the height of each second conductive spacer, and the end of the first conductive spacer and the ends of the multiple second conductive spacers are all away from the multiple conductive substrates and are arranged in the same plane; a conductive bracket, connected to the end of the first conductive spacer and the ends of the multiple second conductive spacers by flip chip method, and the conductive bracket has an exposed surface; and a package body, covering the conductive substrate, the first chip, the second chip, the first conductive spacer, the multiple second conductive spacers and the conductive bracket; wherein the heat dissipation surface and the exposed surface are exposed outside the package body.

[0005] Optionally, the heat dissipation surface and the exposed surface are flush with the outer surface of the package body.

[0006] Optionally, each conductive spacer has a coefficient of thermal expansion less than ten.

[0007] Optionally, a thermal expansion coefficient of each conductive spacer is smaller than twice a thermal expansion coefficient of the first chip and smaller than twice a thermal expansion coefficient of the second chip.

[0008] Optionally, the semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the first chip, the second chip, the plurality of conductive spacers, and the conductive bracket that are connected to each other are connected by a conductive bonding layer.

[0009] Optionally, the semiconductor package structure does not enclose any welding structure within the package body.

[0010] Optionally, the semiconductor package structure does not enclose any wire bonding structure within the package body.

[0011] Optionally, the size of the first chip is larger than that of the second chip, and the first chip is a silicon carbide chip or a gallium nitride chip, while the second chip is a metal oxide semiconductor field effect transistor chip.

[0012] Optionally, the conductive substrate is formed with a half-etched groove surrounding the heat dissipation surface, and the half-etched groove is filled with the package body.

[0013] Optionally, the conductive support includes: a first support connected to the end of the first conductive spacer, and the first support has a partially exposed surface, which is defined as a first exposed surface; wherein the first support is formed with a first half-etched groove surrounding the first exposed surface, and the first half-etched groove is filled by the packaging body; and a plurality of second supports connected to the end of the second conductive spacer, and each second support has another partially exposed surface, which is defined as a second exposed surface; wherein each second support is formed with a second half-etched groove surrounding the second exposed surface, and each second half-etched groove is filled by the packaging body.

[0014] The present application also discloses a semiconductor packaging structure, which includes: a conductive substrate having a solid-state surface and a heat dissipation surface respectively located on opposite sides; a chip arranged on the solid-state surface of the conductive substrate, and the chip has a plurality of connection pads away from the conductive substrate; a plurality of conductive spacers respectively arranged on the plurality of connection pads, and the ends of the plurality of conductive spacers are away from the plurality of conductive substrates and arranged in a coplanar manner; a conductive bracket connected to the ends of the plurality of conductive spacers by a flip-chip method, and the conductive bracket has an exposed surface; and a packaging body covering the conductive substrate, the chip, the plurality of conductive spacers and the conductive bracket; wherein the heat dissipation surface and the exposed surface are exposed outside the packaging body.

[0015] Optionally, the heat dissipation surface and the exposed surface are flush with the outer surface of the package body.

[0016] Optionally, each conductive spacer has a thermal expansion coefficient less than 10, which is also less than twice the thermal expansion coefficient of the chip.

[0017] Optionally, the semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the chip, the plurality of conductive spacers, and the conductive bracket that are connected to each other are connected by a conductive bonding layer.

[0018] Optionally, the semiconductor package structure does not enclose any wire bonding structure within the package body.

[0019] The present application further discloses a semiconductor packaging structure, which includes: a conductive substrate having a solid crystal surface and a heat dissipation surface respectively located on opposite sides; a plurality of conductive carriers adjacent to the conductive substrate; a chip arranged on the solid crystal surface of the conductive substrate, and the chip has a plurality of connection pads away from the conductive substrate; a plurality of conductive spacers respectively arranged on at least one connection pad and at least one conductive carrier, and the ends of the plurality of conductive spacers are arranged in a coplanar manner; a conductive bracket connected to the ends of the plurality of conductive spacers by flip-chip method, and the conductive bracket has an exposed surface; and a packaging body covering the conductive substrate, the plurality of conductive carriers, the chip, the plurality of conductive spacers and the conductive bracket; wherein the heat dissipation surface, the exposed surface and a partial surface of each conductive carrier are exposed outside the packaging body.

[0020] Optionally, a plurality of conductive spacers are respectively disposed on the plurality of connection pads and the plurality of conductive carriers.

[0021] Optionally, the semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the plurality of conductive carriers, the plurality of connection pads, the plurality of conductive spacers, and the conductive bracket that are connected to each other are connected by a conductive bonding layer.

[0022] Optionally, the semiconductor package structure further includes a metal wire embedded in the package body, which connects a connection pad and a conductive carrier.

[0023] Optionally, a plurality of conductive carriers are disposed at intervals on one side of the conductive substrate, and the thickness of each conductive carrier is greater than the thickness of the conductive substrate.

[0024] Beneficial Effects

[0025] In summary, the semiconductor packaging structure disclosed in the present application effectively reduces the impact of the height difference between the multiple components by matching the multiple components (such as: the ends of the multiple conductive spacers are arranged in the same plane so that the conductive bracket can be installed by flip chip method), thereby improving the connection stability between the multiple components.

[0026] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, such description and drawings are only used to illustrate the present application and are not intended to limit the scope of protection of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a three-dimensional schematic diagram of the semiconductor packaging structure of the first embodiment of the present application.

[0028] Figure 2 It is a three-dimensional schematic diagram from another perspective of the semiconductor package structure of the first embodiment of the present application.

[0029] Figure 3 for Figure 1 Schematic cross-sectional view along section line III-III.

[0030] Figure 4 for Figure 1 A three-dimensional schematic diagram of a semiconductor packaging structure with the packaging body omitted.

[0031] Figure 5 for Figure 4 Schematic diagram of the decomposition.

[0032] Figure 6 for Figure 5 Schematic diagram of local decomposition.

[0033] Figure 7 It is a three-dimensional schematic diagram of the semiconductor packaging structure of the second embodiment of the present application.

[0034] Figure 8 for Figure 7 Schematic cross-sectional view along section line VIII-VIII.

[0035] Fig. 9 for Figure 7 A three-dimensional schematic diagram of a semiconductor packaging structure with the packaging body omitted.

[0036] Fig.10 for Fig. 9 Schematic diagram of the decomposition.

[0037] Fig.11 It is a three-dimensional schematic diagram of the semiconductor packaging structure of the third embodiment of the present application.

[0038] Fig.12 for Fig.11 A three-dimensional schematic diagram of a semiconductor packaging structure with the packaging body omitted.

[0039] Fig.13 for Fig.11 Schematic cross-sectional view along section line XIII-XIII.

[0040] Fig.14 A three-dimensional schematic diagram of another state of the semiconductor package structure of the third embodiment of the present application with the package body omitted. DETAILED DESCRIPTION

[0041] The following is an explanation of the implementation methods of the "semiconductor packaging structure" disclosed in this application through specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the contents disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical contents of this application in detail, but the disclosed contents are not intended to limit the scope of protection of this application.

[0042] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0043] Embodiment 1

[0044] See also Figures 1 to 6 As shown, it is the first embodiment of the present application. Figures 1 to 3 As shown, this embodiment discloses a semiconductor package structure 100, which is, for example, a power quad flat no-lead (Power Quad Flat No-lead, PQFN) package structure, but is not limited thereto. The semiconductor package structure 100 in this embodiment includes a conductive substrate 1, a first chip 2 disposed on the conductive substrate 1, a second chip 3 disposed on the first chip 2, a plurality of conductive spacers 4 disposed on the first chip 2 and the second chip 3, a conductive bracket 5 connected to the plurality of conductive spacers 4, and a package body 6 covering the plurality of components.

[0045] It should be noted that the semiconductor packaging structure 100 in this embodiment also includes multiple conductive bonding layers 7, and any two of the conductive substrate 1, the first chip 2, the second chip 3, the multiple conductive spacers 4, and the conductive bracket 5 that are connected to each other are preferably connected by one conductive bonding layer 7, thereby achieving the effect of electrical connection with each other and allowing the semiconductor packaging structure 100 to be free of any wire bonding structure within the packaging body 6.

[0046] Furthermore, the plurality of conductive bonding layers 7 in this embodiment are of the same type and material, but they can be adjusted and varied according to design requirements, and the present application does not limit this. For example, the plurality of conductive bonding layers 7 in this embodiment can be made of conductive paste or conductive glue, so that the semiconductor package structure 100 is not covered with any welding structure within the package body 6, thereby reducing cracks caused by the welding structure; or, in other embodiments not shown in the present application, the plurality of conductive bonding layers 7 can also be made of welding material.

[0047] like Figures 3 to 6 As shown, the conductive substrate 1 is flat and has a crystal-fixing surface 11 and a heat dissipation surface 12 located on opposite sides, and the conductive substrate 1 is preferably formed with a half-etching groove 13 surrounding the heat dissipation surface 12. In this embodiment, the conductive substrate 1 can be a copper substrate or an aluminum substrate, and the present application is not limited thereto.

[0048] In this embodiment, the size of the first chip 2 is slightly smaller than or approximately equal to the size of the die-bonding surface 11, and the size of the first chip 2 is larger than the size of the second chip 3. The first chip 2 is described as a silicon carbide (SiC) chip or a gallium nitride (GaN) chip, and the second chip 3 is described as a metal oxide semiconductor field effect transistor (MOSFET) chip, but the present application is not limited thereto.

[0049] In more detail, the first chip 2 is disposed on the bonding surface 11 of the conductive substrate 1, and the first chip 2 in this embodiment is connected and fixed to the bonding surface 11 using a conductive bonding layer 7 so as to be electrically connected to each other. The first chip 2 has a plurality of first connection pads 21 away from the conductive substrate 1, which are spaced apart from each other and are arranged substantially in a coplanar manner.

[0050] In this embodiment, the plurality of first connection pads 21 include a first inner pad body 211 and a first outer pad body 212 surrounding the first inner pad body 211. The area of ​​the first outer pad body 212 is larger than (e.g., at least ten times) the area of ​​the first inner pad body 211, and the first outer pad body 212 is provided with a first notch 2121 from one edge thereof for the first inner pad body 211 to be disposed therein. Furthermore, one edge of the first inner pad body 211 is aligned with the edge of the first outer pad body 212, and the other three edges of the first inner pad body 211 face the inner wall of the first notch 2121 of the first outer pad body 212.

[0051] The second chip 3 is disposed on one of the first connection pads 21 (e.g., the first outer pad 212) of the first chip 2, and the second chip 3 is connected and fixed to the first outer pad 212 using a conductive bonding layer 7 in this embodiment so as to be electrically connected to each other. The second chip 3 has a plurality of second connection pads 31 away from the conductive substrate 1, which are spaced apart from each other and are arranged substantially in a coplanar manner.

[0052] In this embodiment, the plurality of second connection pads 31 include a second inner pad body 311 and two second outer pad bodies 312 surrounding the second inner pad body 311. The area of ​​each second outer pad body 312 is larger than (e.g., at least six times) the area of ​​the second inner pad body 311, and the two second outer pad bodies 312 are provided with a second recess 3121 from one edge thereof for the second inner pad body 311 to be disposed therein. Furthermore, one edge of the second inner pad body 311 is aligned with the edges of the two second outer pad bodies 312, and the remaining three edges of the second inner pad body 311 face the inner wall of the second recess 3121 formed by the two second outer pad bodies 312.

[0053] Furthermore, the second chip 3 is stacked at the approximate center of the first chip 2, and the second inner pad 311 is disposed adjacent to the first inner pad 211. The area of ​​the second inner pad 311 is smaller than the area of ​​the first inner pad 211, but the present application is not limited thereto.

[0054] In this embodiment, the plurality of conductive spacers 4 are made of the same material, and the material of the plurality of conductive spacers 4 can be at least one of aluminum silicon carbide (AlSiC), aluminum silicon (Al-Si) alloy, molybdenum (Mo), tungsten (W), copper-molybdenum alloy, copper-tungsten alloy and other conductive materials. Each of the conductive spacers 4 has a coefficient of thermal expansion (CTE) less than 10, and the CTE of each of the conductive spacers 4 is preferably less than twice the CTE of the first chip 2 and less than twice the CTE of the second chip 3, but the present application is not limited to the above.

[0055] In more detail, one of the conductive spacers 4 is disposed on another of the first connection pads 21 (e.g., the first inner pad body 211) and is defined as a first conductive spacer 41, and the remaining conductive spacers 4 are respectively disposed on a plurality of the second connection pads 31 and are each defined as a second conductive spacer 42. That is, the plurality of conductive spacers 4 in this embodiment include one first conductive spacer 41 and three second conductive spacers 42.

[0056] The first conductive spacer 41 is connected and fixed to the first inner pad 211 by using one conductive bonding layer 7 so as to be electrically connected to each other. Each second conductive spacer 42 is also connected and fixed to the corresponding second connection pad 31 by using one conductive bonding layer 7. Furthermore, the height of the first conductive spacer 41 is greater than the height of each second conductive spacer 42, and the end of the first conductive spacer 41 and the ends of the plurality of second conductive spacers 42 are both away from the plurality of conductive substrates 1 and are arranged in the same plane.

[0057] The conductive support (lead frame) 5 is connected to the end of the first conductive spacer 41 and the ends of the plurality of second conductive spacers 42 by flip-chip. In other words, the above coplanar arrangement in this embodiment means that the gap between the end of the first conductive spacer 41 and the ends of the plurality of second conductive spacers 42 in a thickness direction H needs to be controlled so as not to affect the connection of the conductive support 5 by flip-chip.

[0058] Accordingly, the semiconductor packaging structure 100 in this embodiment can effectively reduce the impact caused by the height difference between the multiple components by matching the multiple components (such as: the ends of the multiple conductive spacers 4 are arranged in the same plane so that the conductive bracket 5 can be installed by flip chip method), thereby improving the connection stability between the multiple components.

[0059] Specifically, the conductive support 5 includes a first support 51 and a plurality of second supports 52 spaced apart from each other, wherein the first support 51 is connected to the end of the first conductive spacer 41, and the first support 51 has a first exposed surface 511 away from the first conductive spacer 41 and a first half-etched groove 512 surrounding the first exposed surface 511.

[0060] Furthermore, a plurality of second brackets 52 are connected to the end of the second conductive spacer 42, and each of the second brackets 52 has a second exposed surface 521 away from the second conductive spacer 42 and a second half-etched groove 522 surrounding the second exposed surface 521. That is, the first exposed surface 511 of the first bracket 51 and the second exposed surfaces 521 of the plurality of second brackets 52 can be collectively defined as an exposed surface 53 of the conductive bracket 5 in this embodiment (e.g., Figure 1 ).

[0061] The package body 6 covers the conductive substrate 1, the first chip 2, the second chip 3, the first conductive spacer 41, a plurality of second conductive spacers 42 and the conductive bracket 5. The heat dissipation surface 12 and the exposed surface 53 are exposed outside the package body 6 (e.g., Figure 1 and Figure 2 ), and the heat dissipation surface 12 and the exposed surface 53 are flush with (or coplanar with) the outer surface 61 of the package body 6. Further, the half-etched groove 13 of the conductive substrate 1 is filled with the package body 6, and the first half-etched groove 512 and each of the second half-etched grooves 522 of the conductive support 5 are also filled with the package body 6, so that the package body 6 can firmly bond the conductive substrate 1 and the conductive support 5.

[0062] Embodiment 2

[0063] See also Figures 7 to 10 As shown, it is the second embodiment of the present application. Since this embodiment is similar to the above-mentioned first embodiment, the similarities between the two embodiments will not be repeated, and the differences between this embodiment and the above-mentioned first embodiment are roughly described as follows:

[0064] In this embodiment, the semiconductor package structure 100 includes a conductive substrate 1, a chip 30 disposed on the conductive substrate 1, a plurality of conductive spacers 4 disposed on the chip 30, a conductive bracket 5 connected to the plurality of conductive spacers 4, and a package body 6 covering the plurality of components. In other words, the semiconductor package structure 100 in this embodiment is equivalent to omitting the first chip 2 or the second chip 3 in the first embodiment, and the type of the chip 30 in this embodiment can be adjusted and changed according to design requirements (e.g., the chip 30 can be a silicon carbide chip or a metal oxide semiconductor field effect transistor chip), which is not limited here.

[0065] In this embodiment, the structures of the conductive substrate 1 and the conductive bracket 5, and the material of the multiple conductive spacers 4 (e.g., each of the conductive spacers 4 has a thermal expansion coefficient less than 10, which is also less than twice the thermal expansion coefficient of the chip 30) are roughly the same as those described in Example 1 and will not be elaborated here.

[0066] Furthermore, the semiconductor packaging structure 100 in this embodiment may also include multiple conductive bonding layers 7, and any two of the conductive substrate 1, the chip 30, the multiple conductive spacers 4 and the conductive bracket 5 that are connected to each other are preferably connected by one conductive bonding layer 7, thereby achieving the effect of electrical connection with each other and allowing the semiconductor packaging structure 100 to be free of any wire bonding structure within the packaging body 6.

[0067] The structure of the chip 30 in this embodiment is similar to the second chip 3 in the first embodiment. The chip 30 is disposed on the die-bonding surface 11 of the conductive substrate 1, and the chip 30 has a plurality of connection pads 310 away from the conductive substrate 1. The plurality of conductive spacers 4 are respectively disposed on the plurality of connection pads 310, and the ends of the plurality of conductive spacers 4 are away from the plurality of conductive substrates 1 and are disposed in a coplanar manner.

[0068] Furthermore, the conductive support 5 is connected to the ends of the plurality of conductive spacers 4 by flip chip method and has an exposed surface 53. The package body 6 covers the conductive substrate 1, the chip 30, the plurality of conductive spacers 4 and the conductive support 5. The heat dissipation surface 12 and the exposed surface 53 are exposed outside the package body 6 and are flush with (or coplanar with) the outer surface 61 of the package body 6.

[0069] As described above, it can be seen from the contents of the first and second embodiments that the architecture adopted by the semiconductor package structure 100 provided in the present application is applicable to one chip 30 or at least two chips 30 stacked on each other. That is to say, in other embodiments not shown in the present application, the semiconductor package structure 100 can also be provided with more than three chips 30 stacked on each other according to design requirements.

[0070] Embodiment 3

[0071] See also Figures 11 to 14 As shown, it is the third embodiment of the present application. Since this embodiment is similar to the above-mentioned second embodiment, the similarities between the two embodiments will not be repeated, and the differences between this embodiment and the above-mentioned second embodiment are roughly described as follows:

[0072] In this embodiment, if Figures 11 to 13As shown, the semiconductor package structure 100 further includes a plurality of conductive carriers 8 adjacent to the conductive substrate 1, which are embedded in the package body 6 and only partially exposed outside the package body 6. The plurality of conductive carriers 8 are disposed at intervals on one side of the conductive substrate 1, and the thickness of each conductive carrier 8 may be greater than the thickness of the conductive substrate 1.

[0073] Furthermore, the plurality of conductive spacers 4 are respectively disposed on the plurality of connection pads 310 of the chip 30 and the plurality of conductive carriers 8, so that the ends of the plurality of conductive spacers 4 are disposed in a coplanar manner. The conductive support 5 is connected to the ends of the plurality of conductive spacers 4 by flip chip method, and the conductive support 5 is Figures 11 to 13 Two brackets are used for illustration, one of which may be formed with an exposed surface 53 exposed outside the package body 6, and the other of which may be completely buried in the package body 6, but the present application is not limited thereto. Fig.14 As shown, the conductive support 5 may also be a single component that only connects one of the connection pads 310 and one of the conductive carriers 8, and the semiconductor package structure 100 further includes a metal wire 9 embedded in the package body 6, which connects another of the connection pads 310 and another of the conductive carriers 8.

[0074] like Figures 11 to 13 As shown, the semiconductor packaging structure in this embodiment also includes multiple conductive bonding layers 7, and any two of the conductive substrate 1, the multiple conductive carriers 8, the multiple connecting pads 310, the multiple conductive spacers 4 and the conductive bracket 5 that are connected to each other are connected by one of the conductive bonding layers 7.

[0075] Technical effects of this application

[0076] In summary, the semiconductor packaging structure disclosed in the present application effectively reduces the impact of the height difference between the multiple components by matching the multiple components (such as: the ends of the multiple conductive spacers are arranged in the same plane so that the conductive bracket can be installed by flip chip method), thereby improving the connection stability between the multiple components.

[0077] The contents disclosed above are only preferred feasible embodiments of the present application, and are not intended to limit the patent scope of the present application. Therefore, all equivalent technical changes made using the description and drawings of the present application are included in the patent scope of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises: A conductive substrate having a crystal-fixing surface and a heat-dissipating surface respectively located on opposite sides; a first chip disposed on the crystal-fixing surface of the conductive substrate, and the first chip having a plurality of first connection pads away from the conductive substrate; a second chip, disposed on one of the first connection pads of the first chip, and the second chip has a plurality of second connection pads away from the conductive substrate; A plurality of the conductive spacers, one of which is disposed on another of the first connection pads and is defined as a first conductive spacer, and the remaining conductive spacers are respectively disposed on the plurality of the second connection pads and are each defined as a second conductive spacer; wherein the height of the first conductive spacer is greater than the height of each of the second conductive spacers, and the end of the first conductive spacer and the ends of the plurality of the second conductive spacers are both away from the plurality of the conductive substrates and are disposed in the same plane; a conductive support connected to the end of the first conductive spacer and the ends of the second conductive spacers by flip chip method, and the conductive support has an exposed surface; and A package body covers the conductive substrate, the first chip, the second chip, the first conductive spacer, a plurality of the second conductive spacers and the conductive bracket; wherein the heat dissipation surface and the exposed surface are exposed outside the package body.

2. The semiconductor package structure according to claim 1, wherein: The heat dissipation surface and the exposed surface are flush with the outer surface of the packaging body.

3. The semiconductor package structure according to claim 1, wherein: Each of the conductive spacers has a coefficient of thermal expansion less than 10.

4. The semiconductor package structure according to claim 1, wherein: A thermal expansion coefficient of each of the conductive spacers is smaller than twice a thermal expansion coefficient of the first chip and smaller than twice a thermal expansion coefficient of the second chip.

5. The semiconductor package structure according to claim 1, wherein: The semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the first chip, the second chip, the plurality of conductive spacers, and the conductive bracket that are connected to each other are connected by one of the conductive bonding layers.

6. The semiconductor package structure according to claim 5, characterized in that: The semiconductor package structure does not enclose any welding structure within the package body.

7. The semiconductor package structure according to claim 1, wherein: The semiconductor package structure does not enclose any wire bonding structure within the package body.

8. The semiconductor package structure according to claim 1, wherein: The size of the first chip is larger than that of the second chip, and the first chip is a silicon carbide chip or a gallium nitride chip, while the second chip is a metal oxide semiconductor field effect transistor chip.

9. The semiconductor package structure according to claim 1, wherein: The conductive substrate is formed with a half-etched groove surrounding the heat dissipation surface, and the half-etched groove is filled by the packaging body.

10. The semiconductor package structure according to claim 1, wherein: The conductive support comprises: a first bracket connected to the end of the first conductive spacer, and the first bracket has a partial exposed surface, which is defined as a first exposed surface; wherein the first bracket is formed with a first half-etched groove surrounding the first exposed surface, and the first half-etched groove is filled with the package body; and A plurality of second brackets are connected to the end of the second conductive spacer, and each of the second brackets has another partially exposed surface, which is defined as a second exposed surface; wherein each of the second brackets is formed with a second half-etched groove surrounding the second exposed surface, and each of the second half-etched grooves is filled by the packaging body.

11. A semiconductor packaging structure, characterized in that: The semiconductor package structure comprises: a conductive substrate having a die-bonding surface and a heat dissipation surface respectively located on opposite sides; a chip disposed on the die-bonding surface of the conductive substrate, and the chip having a plurality of connection pads away from the conductive substrate; A plurality of conductive spacers are respectively disposed on the plurality of connection pads, and ends of the plurality of conductive spacers are away from the plurality of conductive substrates and are disposed in a coplanar manner; a conductive support connected to the ends of the plurality of conductive spacers by flip chip method, and the conductive support has an exposed surface; and A package body covers the conductive substrate, the chip, a plurality of conductive spacers, and the conductive support; wherein the heat dissipation surface and the exposed surface are exposed outside the package body.

12. The semiconductor package structure according to claim 11, characterized in that: The heat dissipation surface and the exposed surface are flush with the outer surface of the packaging body.

13. The semiconductor package structure according to claim 11, characterized in that: Each of the conductive spacers has a thermal expansion coefficient less than 10, which is also less than twice the thermal expansion coefficient of the chip.

14. The semiconductor package structure according to claim 11, wherein: The semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the chip, the plurality of conductive spacers and the conductive support that are connected to each other are connected by one of the conductive bonding layers.

15. The semiconductor package structure according to claim 11, wherein: The semiconductor package structure does not enclose any wire bonding structure within the package body.

16. A semiconductor packaging structure, characterized in that: The semiconductor package structure comprises: a conductive substrate having a die-bonding surface and a heat dissipation surface located on opposite sides; a plurality of conductive carriers, adjacent to the conductive substrate; a chip disposed on the die-bonding surface of the conductive substrate, and the chip has a plurality of connection pads away from the conductive substrate; A plurality of conductive spacers, respectively disposed on at least one of the connection pads and at least one of the conductive carriers, and the ends of the plurality of conductive spacers are disposed in a coplanar manner; a conductive support, connected to the ends of the plurality of conductive spacers by flip chip method, and the conductive support has an exposed surface; and A package body covers the conductive substrate, a plurality of conductive carriers, the chip, a plurality of conductive spacers and the conductive bracket; wherein the heat dissipation surface, the exposed surface, and a partial surface of each conductive carrier are exposed outside the package body.

17. The semiconductor package structure according to claim 16, wherein: The plurality of conductive spacers are respectively disposed on the plurality of connection pads and the plurality of conductive carriers.

18. The semiconductor package structure according to claim 17, wherein: The semiconductor package structure includes a plurality of conductive bonding layers, and any two of the conductive substrate, the conductive carriers, the connection pads, the conductive spacers and the conductive support that are connected to each other are connected by one of the conductive bonding layers.

19. The semiconductor package structure according to claim 16, wherein: The semiconductor package structure further includes a metal wire embedded in the package body, which connects one of the connection pads and one of the conductive carriers.

20. The semiconductor package structure according to claim 16, wherein: A plurality of the conductive carriers are disposed at intervals on one side of the conductive substrate, and a thickness of each of the conductive carriers is greater than a thickness of the conductive substrate.

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