Package structure

Abstract

A package structure is provided. The package structure includes a substrate, a first electronic component, a first electrical connector, and a protective layer. The first electronic component is over the substrate. The first electrical connection is between the substrate and the first electronic component. The protective layer encapsulates the first electrical connector. The protective layer has a first curved side surface recessed toward the first electrical connector and recessed relative to a side surface of the first electronic component.

Description

Technical Field

[0001] The present disclosure relates generally to a package structure, and in particular, to a package structure including a protection layer. Background Art

[0002] In stacked structures such as multiple electronic components electrically connected to a substrate, a minimum amount of solder can be used to prevent solder bridging. However, due to the minimized space, it is difficult for underfill to flow between layers to cover and protect the solder. In addition, the underfill may overflow toward the solder ball pads, thereby reducing yield. Summary of the invention

[0003] In one or more configurations, a packaging structure includes a substrate, a first electronic component, a first electrical connector, and a protective layer. The first electronic component is above the substrate. The first electrical connector is between the substrate and the first electronic component. The protective layer encapsulates the first electrical connector. The protective layer has a first curved side surface that is recessed toward the first electrical connector and is concave relative to a side surface of the first electronic component.

[0004] In one or more configurations, a packaging structure includes a substrate, a first electronic component, a second electronic component, and a protective layer. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed above the first substrate. The second electronic component is disposed below the second surface of the substrate. The protective layer is between the first electronic component and the substrate. The protective layer has a cavity space, the cavity space at least partially overlaps with a path between the first electronic component and the second electronic component, and the cavity space is configured to reduce the transfer of heat generated by the second electronic component and transferred toward the first electronic component.

[0005] In one or more configurations, a package structure includes a substrate, an electronic component, and a protective layer. The substrate includes a first conductive pad and a second conductive pad, and the second conductive pad is exposed by a first opening of the substrate. The electronic component is electrically connected to the first conductive pad. The protective layer is between the substrate and the electronic component. The first opening of the substrate is on a first side of the protective layer. A first ratio of a distance between the protective layer and the first opening of the substrate to a distance between the substrate and the electronic component is less than 25. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various features may not be drawn to scale and that the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-section of a package structure according to some configurations of the present disclosure.

[0008] Figure 1Ais a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0009] Figure 1B is a top view of a portion of a package structure according to some configurations of the present disclosure.

[0010] Figure 2A is a cross-section of a package structure according to some configurations of the present disclosure.

[0011] Figure 2B is a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0012] Figure 2C is a cross-section of a package structure according to some configurations of the present disclosure.

[0013] Figure 2D is a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0014] Figure 3A is a cross-section of a package structure according to some configurations of the present disclosure.

[0015] Figure 3B is a cross-section of a package structure according to some configurations of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G Various stages of an illustrative method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0017] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Various stages of an illustrative method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0018] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0019] Figure 1 is a cross-section of a package structure 1 according to some configurations of the present disclosure. Figure 1A is a cross-section of a portion of a package structure 1 according to some configurations of the present disclosure. Figure 1B is a top view of a portion of a package structure 1 according to some configurations of the present disclosure. In some configurations, Figure 1A yes Figure 1 A cross section of a portion 1A of the package structure 1 is shown in FIG. In some configurations, Figure 1B yes Figure 1 The package structure 1 may include a substrate 10 , electronic components 20 and 50 , electrical connectors 30 and 60 , a protective layer 40 , an underfill 70 , and electrical contacts 80 .

[0020] The substrate 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 may include an interconnect structure, which may include a plurality of conductive traces and / or conductive vias. The interconnect structure may include a redistribution layer (RDL) and / or a grounding element. In some configurations, the substrate 10 may include an organic substrate or a lead frame. In some configurations, the substrate 10 may include a ceramic material or a metal plate. In some configurations, the substrate 10 may include a two-layer substrate, which includes a core layer and conductive materials and / or structures disposed on the upper and bottom surfaces of the substrate. The substrate 10 may include a semiconductor wafer or an electronic component. The electronic component may be a chip or a bare die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit device may include an active device such as a transistor and / or a passive device such as a resistor, a capacitor, an inductor, or a combination thereof. In some configurations, substrate 10 may include one or more conductive elements, surfaces, contacts, or pads.

[0021] In some configurations, the substrate 10 has a surface 101 and a surface 102 opposite to the surface 101. In some configurations, the reference Figure 1 , 1A 1B, the substrate 10 includes a base layer 100, a dielectric layer 120, and conductive pads 110, 130, and 140. The conductive pads 110, 130, and 140 may be exposed by the surface 101. In some configurations, the conductive pad 110 is exposed by an opening 110h of the substrate 10 (or the dielectric layer 120). In some configurations, the conductive pad 130 is exposed by an opening 130h of the substrate 10 (or the dielectric layer 120). In some configurations, the conductive pad 130 is on the side of the electronic component 20. In some configurations, the distance between the conductive pad 110 and one of the conductive pads 130 is less than the pitch of the conductive pads 130. In some configurations, the conductive pads 110 and 130 may be exposed by the surface 101. Figure 1B , the conductive pad 140 is exposed by the opening 140h of the substrate 10 (or the dielectric layer 120). In some configurations, the width of the conductive pad 130 is greater than the width of the conductive pad 110. In some configurations, the width of the conductive pad 140 is greater than the width of the conductive pad 110.

[0022] The electronic component 20 may be disposed over the substrate 10. The electronic component 20 may be disposed over the conductive pad 110. The electronic component 20 may have a surface 201, a surface 202 opposite to the surface 201, and side surfaces 203, 204, 205, and 206. The side surface 203 may be opposite to the side surface 204, and the side surface 205 may be opposite to the side surface 206. The surface 202 may face the substrate 10. The surface 202 may be referred to as an active surface or bottom surface of the electronic component 20. In some configurations, the electronic component 20 includes a conductive pad 210. The conductive pad 210 may be disposed on the surface 202 or extend out of the surface. In some configurations, the electronic component 20 is electrically connected to the conductive pad 110. For example, the conductive pad 210 may be electrically connected to the conductive pad 110. In some configurations, the conductive pad 110 and the opening 110h are directly below the electronic component 20. In some configurations, the conductive pads 130 and 140 are on adjacent sides of the electronic component 20 (e.g., adjacent side surfaces 204 and 205). In some configurations, the openings 130h and 140h are on adjacent sides of the electronic component 20 (e.g., adjacent side surfaces 204 and 205). The electronic component 20 may be or include a passive die, such as a resistor, a capacitor, an inductor, or a combination thereof, or any other type of passive die. The electronic component 20 may be or include an active die, such as an ASIC, or any other type of active die. In some configurations, the electronic component 20 may be or include an integrated passive device (IPD).

[0023] The electrical connector 30 may be disposed between the substrate 10 and the electronic component 20. In some configurations, the electrical connector 30 connects or electrically connects the conductive pad 110 to the conductive pad 210. Figure 1A , the electrical connector 30 includes a solder element 330, an intermediate layer 310 between the conductive pad 110 and the solder element 330, and an intermediate layer 320 between the conductive pad 210 and the solder element 330. The solder element 330 may include a solder material, such as Sn. The intermediate layers 310 and 320 may include one or more intermetallic compounds (IMCs). In some configurations, the intermediate layer 310 includes an IMC of metals from the conductive pad 110 and the solder element 330. In some configurations, the intermediate layer 320 includes an IMC of metals from the conductive pad 210 and the solder element 330. In some configurations, the electrical connector 30 is partially within the substrate or embedded in the substrate. In some configurations, the electrical connector 30 is partially within the opening 110h of the substrate 10 (or the dielectric layer 120). The electrical connector 30 may include a conductive bump. The conductive bump may include gold (Au), silver (Ag), copper (Cu), another metal, a solder alloy, or a combination of two or more thereof.

[0024] The protective layer 40 may be between the substrate 10 and the electronic component 20. In some configurations, the protective layer 40 is between the conductive pad 110 and the electronic component 20. In some configurations, the protective layer 40 encapsulates the electrical connector 30. In some configurations, the protective layer 40 does not contain a filler. In some configurations, the protective layer 40 is formed by or includes an epoxy flux. The epoxy flux includes an epoxy resin and a solder flux material. In some configurations, the viscosity of the protective layer 40 is equal to or greater than about 20Pa·S. In some configurations, the viscosity of the protective layer 40 is about 20Pa·S to about 35Pa·S. In some configurations, the modulus of the protective layer 40 is less than about 9GPa, 7GPa, 5GPa, or 3GPa. In some configurations, the modulus of the protective layer 40 may be about 2GPa.

[0025] In some configurations, the protective layer 40 has a surface 401, a surface 402 opposite to the surface 401, and side surfaces 403 and 404 (also referred to as "curved side surfaces") that are recessed toward the electrical connector 30. In some configurations, the side surfaces 403 and 404 are recessed or at least partially recessed toward the space between the substrate 10 and the electronic component 20. In some configurations, the side surfaces 403 and 404 are recessed or at least partially recessed toward the intermediate layer 310 of the electrical connector 30. In some configurations, the side surface 403 (or the curved side surface) is recessed or at least partially recessed relative to the side surface 203 of the electronic component 20. In some configurations, the side surface 404 (or the curved side surface) is recessed or at least partially recessed relative to the side surface 204 of the electronic component 20. In some configurations, the curvature of the side surface 403 is different from the curvature of the side surface 404.

[0026] In some configurations, the protective layer 40 has one or more cavity spaces (e.g., cavity spaces V1 and V2). One or more cavity spaces may be located at a path between the electronic component 20 and the electronic component 50 or at least partially overlap the path. In some configurations, the cavity space is configured to reduce heat transfer from the electronic component 50 to the electronic component 20. In some configurations, the cavity space is configured to reduce the transfer of heat generated by the electronic component 50 and transferred toward the electronic component 20. In some configurations, multiple voids (e.g., cavity spaces V1 and V2) are formed within the protective layer 40 and between the electrical connectors 30. In some configurations, at least two of the voids have different widths. For example, the width S1 of the cavity space V1 is different from the width S1 of the cavity space V2. The cavity space may be referred to as a voicing, an air space, a pore, etc. In some configurations, the intermediate layer 310 overlaps horizontally with the cavity space V1. In some configurations, reference Figure 1B, two or more of the cavity spaces (e.g., cavity spaces V1 and V2) are connected. In some configurations, the protective layer 40 is partially separated from one or more of the electrical connectors 30 by one or more of the cavity spaces. In some configurations, the protective layer 40 includes multiple segments separated from each other by the cavity spaces V1 and V2. In some configurations, segments of the protective layer 40 are separated from one or more of the electrical connectors 30 by one or more of the cavity spaces V1 and V2. In some configurations, an area of ​​the surface 202 (or active surface) of the electronic component 20 is exposed by the protective layer 40 and is between adjacent electrical connectors 30 in a cross-sectional perspective view. An area of ​​the surface 202 may be exposed to the cavity space. In some configurations, a corner area of ​​the surface 202 (or bottom surface) of the electronic component 20 is exposed by the protective layer 40,

[0027] refer to Figure 1A In some configurations, the protective layer 40 includes portions 410 and 420 on opposite sides (e.g., different sides) of the electrical connector 30 in a cross-sectional perspective view. In some configurations, portions 410 and 420 are geometrically different from each other. In some configurations, portions 410 and 420 have different widths at the same elevation. For example, portion 410 may have different widths t1, t2, and t3 at different elevations, and portion 420 may have different widths t4, t5, and t6 at different elevations. In some configurations, width t1 and width t4 are at the same elevation and are different. In some configurations, width t2 and width t5 are at the same elevation and are different. In some configurations, width t3 and width t6 are at the same elevation and are different.

[0028] In some configurations, width t1 is smaller than width t2 and width t3. In some configurations, ratio t1 / t2 is smaller than about 0.2, and ratio t1 / t3 is smaller than about 0.3. In some configurations, width t4 is smaller than width t5 and t6. In some configurations, ratio t4 / t5 is smaller than about 0.6. In some configurations, ratio t4 / t6 is smaller than about 0.6. In some configurations, ratio S1 / P1 of width S1 of cavity space V1 relative to pitch P1 of electrical connector 30 may be smaller than about 0.6.

[0029] refer to Figure 1AIn some configurations, the protective layer 40 is partially disposed between the substrate 10 and the electrical connector 30. In some configurations, the protective layer 40 may include one or more protrusions (e.g., protrusions 410a and 420a) disposed between the substrate 10 and the electrical connector 30. The protrusions 410a and 420a may overlap horizontally with the substrate 10. In some configurations, the protrusion 410a is different from the protrusion 420a in geometry. In some configurations, the protrusions 410a and 420a have different widths at the same height. For example, the width t2a of the protrusion 410a and the width t5a of the protrusion 420a may be at the same height and different. In some configurations, the protrusions 410a and 420a are between the substrate and the solder element 330 of the electrical connector 30. In some configurations, the intermediate layer 320 of the electrical connector 30 partially overlaps the protrusion 410a and / or the protrusion 420a.

[0030] In some configurations, reference Figure 1B , the conductive pad 130 and the conductive pad 140 are on the adjacent side of the protective layer 40. In some configurations, reference Figure 1B , the opening 130 h and the opening 140 h are on the adjacent side of the protection layer 40 .

[0031] Electronic component 50 may be disposed below surface 102 of substrate 10. In some configurations, the width of electronic component 50 is greater than the width of electronic component 20. Electronic component 50 may be or include a passive die, such as a resistor, a capacitor, an inductor, or a combination thereof, or any other type of passive die. Electronic component 50 may be or include an active die, such as an ASIC, or any other type of active die. In some configurations, electronic component 50 may be or include a processor die, such as an ASIC.

[0032] The electrical connector 60 may be disposed between the electronic component 50 and the substrate 10. In some configurations, the electronic component 50 is electrically connected to the substrate 10 through the electrical connector 60. In some configurations, the thickness of the electrical connector 30 is less than the thickness of the electrical connector 60. In some configurations, the spacing of the electrical connector 60 is greater than the distance between the conductive pad 110 and one of the conductive pads 130. The electrical connector 60 may include a conductive bump. The conductive bump may include gold (Au), silver (Ag), copper (Cu), another metal, a solder alloy, or a combination of two or more thereof.

[0033] The bottom filler 70 may be disposed between the substrate 10 and the electronic component 50. In some configurations, the bottom filler 70 encapsulates the electrical connector 60. In some configurations, the bottom filler 70 includes a resin layer 710 and a plurality of fillers 720. In some configurations, the thickness T2 of the bottom filler 70 is greater than the thickness T1 of the protective layer 40. In some configurations, the modulus of the bottom filler 70 is greater than the modulus of the protective layer 40. In some configurations, the viscosity of the bottom filler 70 is less than the viscosity of the protective layer 40. In some configurations, the viscosity of the bottom filler 70 is equal to or less than about 20 Pa·S. In some configurations, the viscosity of the bottom filler 70 is about 20 Pa·S. In some configurations, the modulus of the bottom filler 70 is greater than about 3 GPa, 7 GPa, 5 GPa, or 9 GPa. In some configurations, the modulus of the bottom filler 70 may be about 9 GPa.

[0034] The electrical contact 80 (also referred to as an "electrical connector") may be disposed on one or more sides of the protective layer 40. In some configurations, the electrical contact 80 is disposed on the conductive pad 140. In some configurations, the electrical contact 80 is electrically connected to the conductive pad 140. In some configurations, the height of the top surface 801 of the electrical contact 80 is higher than the height of the top surface (e.g., surface 401) of the protective layer 40 relative to the substrate 10. In some configurations, the height of the top surface 801 of the electrical contact 80 is higher than the height of the top surface (e.g., surface 201) of the electronic component 20 relative to the substrate 10. In some configurations, the electrical contact 80 horizontally overlaps the electronic component 20. In some configurations, the electrical contact 80 is disposed on one or more sides of the electronic component 20 and horizontally overlaps the electrical connector 30. In some configurations, the thickness T3 of the electrical contact 80 is greater than the thickness of the electrical connector 60. The electrical contact 80 may be or include a solder ball. For example, the electrical contacts 80 may include controlled collapse chip connect (C4) bumps, a ball grid array (BGA), or a land grid array (LGA).

[0035] The conductive layer, pad, guide post and / or through hole may independently include a conductive material such as a metal or a metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu) or their alloys. The dielectric layer may independently include an organic material, a solder resist, PI, ABF, one or more molding compounds, one or more pre-impregnated composite fibers (e.g., prepreg materials), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, etc. The bottom filler may independently include an epoxy resin, a molding material (e.g., an epoxy molding material or other molding material), a polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination thereof.

[0036] In some configurations, the substrate 10 may have a size of approximately 25*20 mm. 2To approximately 30*14mm 2 The size of the electronic component 20 may be approximately 0.7*0.5mm 2 To approximately 1*0.8mm 2 The distance d1 between the opening 130h and the electronic component 20 may be about 0.185 mm to about 0.205 mm, and the distance d2 between the opening 130h and the protective layer 40 may be about 0.13 mm to about 0.28 mm. In some configurations, the substrate 10 may have a size of about 55*35 mm. 2 To approximately 60*40mm 2 The size of the electronic component 20 may be approximately 2*1 mm 2 To about 3*2mm 2 The distance d1 between the opening 130h and the electronic component 20 may be about 0.21 mm to about 0.68 mm, and the distance d2 between the opening 130h and the protective layer 40 may be about 0.25 mm to about 0.52 mm.

[0037] In some cases where an electronic component is bonded to a substrate via a solder bump (e.g., electrical connector 30) and then an underfill is applied to encapsulate the solder bump, the underfill may overflow toward a conductive pad (also referred to as a "solder ball pad") for a solder ball (e.g., conductive pad 130 for electrical contact 80). Once the solder ball pad is covered by the underfill, the solder ball cannot be bonded to the solder ball pad. To prevent the aforementioned problem, a keep out zone (KOZ) is required between the solder ball pad and the solder bump. For a size of about 25*20 mm, the KOZ may be formed between the solder ball pad and the solder bump. 2 To approximately 30*14mm 2 The substrate size is about 0.7*0.5mm 2 To approximately 1*0.8mm 2 For electronic components, KOZ needs to be at least about 1*0.6mm 2 To approximately 1.5*2mm 2 . For the size of about 55*35mm 2 To approximately 60*40mm 2 The substrate size is about 2*1mm 2 To about 3*2mm 2 For electronic components, KOZ needs to be at least about 2*1mm 2 To approximately 3.5*2.5mm 2 .

[0038] In contrast, according to some configurations of the present disclosure, the electrical connector 30 is encapsulated by the protective layer 40 having one or more curved side surfaces concave toward the electrical connector 30, and the KOZ can be significantly reduced. For example, the distance d1 between the electronic component 20 and the opening 130h directly above the conductive pad 130 is about 0.185 mm to about 0.205 mm or about 0.21 mm to about 0.68 mm, which is significantly smaller than the aforementioned KOZ size. In addition, by means of the design of the protective layer 40, the relationship between various sizes of the components of the package structure 1 can have the following characteristics.

[0039] The opening 140h may have a distance d2' between the protective layer 40, and the electronic component 20 may have a distance h1 between the substrate 10. The electrical connector 30 may have a width w1. The electronic connector 30 may have a pitch P1. In some configurations, a ratio d1 / h1 of the distance d1 between the opening 130h and the electronic component 20 relative to the distance h1 is less than about 25, for example, 5 to less than 25, 10 to 20, or 11 to 14. In some configurations, a ratio d1 / P1 of the distance d1 relative to the pitch P1 is less than about 5, for example, 1 to less than 5, 1.5 to 3, or 1 to 2. In some configurations, a ratio d1 / t1 of the distance d1 relative to the width t1 is less than about 25, for example, 1 to less than 25, 3 to 20, or 5 to 10. In some configurations, a ratio d1 / w1 of the distance d1 relative to the width w1 is less than about 10, for example, 1 to less than 10, 2 to 8, or 3 to 10. In some configurations, a ratio d2 / h1 of a distance d2 between the protective layer 40 and the opening 130h of the substrate 10 relative to a distance h1 between the substrate 10 and the electronic component 20 is less than about 25, for example, 8 to less than 25, 10 to 20, or 11 to 15. In some configurations, a ratio d2' / h1 of a distance d2' between the protective layer 40 and the opening 140h of the substrate 10 relative to the distance h1 is less than about 25, for example, 8 to less than 25, 10 to 20, or 11 to 15. In some configurations, the ratio d2 / h1 may be different from the ratio d2' / h1. In some configurations, a ratio d2 / P1 of the distance d2 relative to the pitch P1 is less than about 3, for example, 1 to less than 3, 1 to 2.5, or 1.5 to 2. In some configurations, a ratio d2 / t1 of the distance d2 relative to the width t1 is less than about 45, for example, 0.5 to less than 45, 5 to 30, or 7.5 to 15. In some configurations, a ratio d2 / w1 of the distance d2 to the width w1 is less than about 8, such as 2 to less than 8, 3 to 6.5, or 3.5 to 4.5.

[0040] In some examples, the ratio d2 / h1 may be greater than 25, so that the distance d2 between the protection layer 40 and the opening 130h of the substrate 10 may be relatively large, or the distance h1 between the substrate 10 and the electronic component 20 may be relatively small. When the distance d2 is relatively large, the exclusion zone (KOZ) may also be enlarged. Therefore, the size of the package structure may increase unexpectedly. Alternatively, when the distance h1 (i.e., the gap maintained between the electronic component 20 and the substrate 10) is too small, the processing window for bonding the electronic component 20 to the substrate 10 may be relatively small, so that the difficulty and complexity of the manufacturing process increase, and the yield may be reduced.

[0041] According to some configurations of the present disclosure, the ratio d2 / h1 may be less than about 25, for example, 8 to less than 25. Therefore, the KOZ may be significantly reduced without increasing the difficulty and complexity of the manufacturing process. Therefore, the size of the package structure 1 may be reduced without reducing the yield. Similarly, a ratio d2' / h1 less than about 25 may have similar effects as described above.

[0042] In some examples, the ratio d2 / h1 may be less than 8, so that the distance d2 between the protection layer 40 and the opening 130h of the substrate 10 may be relatively small, or the distance h1 between the substrate 10 and the electronic component 20 may be relatively large. When the distance d2 is relatively small, the exclusion zone (KOZ) may be too small to prevent the material of the protection layer from overflowing toward the conductive pad 130 and / or the electrical contact 80 during the manufacturing process. Therefore, the yield may be significantly reduced. Alternatively, when the distance h1 (i.e., the gap maintained between the electronic component 20 and the substrate 10) is too large, the top surface of the electronic component 20 may be higher than the top surface of the electrical contact 80 relative to the substrate 10, which may hinder the package structure from being bonded to an external component or substrate through the electrical contact 80, and thus reduce the yield, or require a larger electrical contact 80 with a larger height, which may increase the size of the package structure.

[0043] According to some configurations of the present disclosure, the ratio d2 / h1 may be equal to or greater than about 8, for example, 8 to less than 25. Therefore, the KOZ may be significantly reduced without increasing the difficulty and complexity of the manufacturing process. Therefore, the size of the package structure 1 may be reduced without reducing the yield. Similarly, a ratio d2' / h1 less than about 25 may have similar effects as described above.

[0044] There may be a distance d3 between the electrical contact 80 and the electronic component 20, and there may be a distance d4 between the electrical contact 80 and the protective layer 40. The electrical contact 80 may have a width w2. The electrical contact 80 may have a pitch P2. In some configurations, a ratio d3 / h1 of the distance d3 relative to the distance h1 is less than about 35, for example, 5 to less than 35, 10 to 20, or 12 to 15. In some configurations, a ratio d3 / P1 of the distance d3 relative to the pitch P1 is less than about 20, for example, 0.1 to less than 3, 0.2 to 2, or 0.3 to 1. In some configurations, a ratio d3 / P2 of the distance d3 relative to the pitch P2 is less than about 1.8, for example, 0.1 to less than 1.8, 0.2 to 1.2, or 0.3 to 0.6. In some configurations, a ratio d3 / t1 of the distance d3 relative to the width t1 is less than about 35, for example, 1 to less than 35, 3 to 22, or 5 to 10. In some configurations, a ratio d3 / w1 of the distance d3 relative to the width w1 is less than about 15, such as 1 to less than 15, 2 to 10, or 3 to 5. In some configurations, a ratio d3 / w2 of the distance d3 relative to the width w2 is less than about 3, such as 0.0 to less than 3, 0.5 to 2, or 0.6 to 1. In some configurations, a ratio d4 / h1 of the distance d4 relative to the distance h1 is less than about 3.5, such as 0.05 to less than 3.5, 0.1 to 2, or 0.3 to 1. In some configurations, a ratio d4 / P1 of the distance d4 relative to the pitch P1 is less than about 0.4, such as 0.01 to less than 0.4, 0.02 to 0.2, or 0.03 to 0.1. In some configurations, the ratio d4 / P2 of the distance d4 relative to the pitch P2 is less than about 0.8, such as 0.001 to less than 0.8, 0.005 to 0.6, or 0.01 to 0.05. In some configurations, the ratio d4 / t1 of the distance d4 relative to the width t1 is less than about 8, such as 0.03 to less than 8, 0.1 to 4, or 0.3 to 2. In some configurations, the ratio d4 / w1 of the distance d4 relative to the width w1 is less than about 0.9, such as 0.01 to less than 0.9, 0.025 to 0.8, or 0.1 to 0.3. In some configurations, the ratio d4 / w2 of the distance d4 relative to the width w2 is less than about 0.2, such as 0.003 to less than 0.2, 0.005 to 0.1, or 0.01 to 0.06.

[0045] According to some configurations of the present disclosure, with the above ratio between the sizes of the elements of the package structure 1, the KOZ between the conductive pad 130 and the electrical connector 30 (or the KOZ between the electrical contact 80 and the protective layer 40) can be significantly reduced. Therefore, the package size can be significantly reduced and more space can be provided for more electrical contacts (i.e., input / output (I / O) count).

[0046] In addition, according to some configurations of the present disclosure, the protective layer is formed by or includes epoxy flux. The flux material of the epoxy flux can clean the bonding surface of the conductive pad, which is conducive to increasing the bonding strength between the solder element and the conductive pad. In addition, the epoxy resin of the epoxy flux can be cured during the reflow operation of the solder element of the electrical connector and form a protective layer for the electrical connector. Therefore, the operation step of setting the bottom filler to protect the electrical connector can be omitted, and the overflow problem of the above-mentioned bottom filler can be effectively prevented.

[0047] Furthermore, according to some configurations of the present disclosure, the solvent in the flux material may be evaporated during the reflow operation. Thus, the protective layer may be formed with a concave curved side surface that is recessed from the side surface of the electronic component. Thus, the KOZ may be reduced or even omitted, and thus the package size may be reduced. Additionally, although the bottom fill material does not form voids during the curing operation, the solvent may evaporate and be expelled from the epoxy flux, and voids may be formed in the protective layer, which is beneficial for reducing heat transfer through the substrate toward the electronic component.

[0048] In addition, according to some configurations of the present disclosure, the epoxy flux has a relatively high viscosity compared to the bottom fill material, and, for example, during the reflow operation, the viscosity of the epoxy flux may increase as the temperature increases. Therefore, the protective layer formed by the epoxy flux after the reflow operation may have an increased adhesion strength to the electrical connectors, the substrate, and the electronic components. Therefore, the protective layer may provide a relatively high encapsulation of the electrical connectors, the substrate, and the electronic components, and thus further improve the reliability of the package structure 1. In addition, the flux residue may remain in the protective layer without contaminating the surface of the substrate and the electronic components, and thus the flux cleaning operation may be omitted.

[0049] In addition, according to some configurations of the present disclosure, when the step of setting the bottom filler is omitted, the pre-plasma cleaning step for increasing the roughness of the connection surface between the bottom filler and the surface of the substrate and the electronic component can be omitted, and the step of curing the bottom filler can also be omitted. Thus, the manufacturing process can be simplified and the yield can be increased.

[0050] Figure 2A is a cross-section of a package structure 2A according to some configurations of the present disclosure. Figure 2B is a cross-section of a portion of a package structure 2A according to some configurations of the present disclosure. In some configurations, Figure 2B yes Figure 2A A cross section of a portion 2B of a package structure 2A is shown in FIG. Figure 2A The package structure 2A shown in FIG. 1 is similar to Figure 1 The packaging structure in , the differences between them are as follows.

[0051] In some configurations, the protective layer 40 includes a portion 450 having a concave curved surface (eg, the side surface 403 ) and directly contacts a portion of the electrical contact 80 .

[0052] In some configurations, the intermediate layer 310 extends over a portion of the side surface of the conductive pad 210. In some configurations, the solder element 330 extends beyond the side edge of the intermediate layer 310 and the side surface of the conductive pad 210.

[0053] Figure 2C is a cross-section of a package structure 2C according to some configurations of the present disclosure. Figure 2D is a cross-section of a portion of a package structure 2C according to some configurations of the present disclosure. In some configurations, Figure 2D yes Figure 2C A cross-section of a portion 2D of a package structure 2C is shown in FIG. Figure 2C The package structure 2C shown in FIG. 2 is similar to Figure 1 The packaging structure in , the differences between them are as follows.

[0054] In some configurations, the protective layer 40 includes a portion 420 extending above a portion of the side surface 203 of the electronic component 20. In some configurations, the side surface 403 of the portion 420 of the protective layer 40 is partially recessed relative to the side surface 203 of the electronic component 20. In some configurations, the side surface 403 of the portion 420 of the protective layer 40 is partially recessed toward the electrical connector 30. In some configurations, the width S1 of the cavity space V1 is greater than the width S2 of the cavity space V2.

[0055] Figure 3A is a cross-section of a package structure 3A according to some configurations of the present disclosure. Figure 3A The package structure 3A shown in FIG. 3 is similar to Figure 1 The packaging structure in , the differences between them are as follows.

[0056] The package structure 3A may further include a carrier 10A. The carrier 10A may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The carrier 10A may include an interconnect structure, which may include a plurality of conductive traces and / or a plurality of conductive vias. The interconnect structure may include a redistribution layer (RDL) and / or a grounding element. In some configurations, the carrier 10A may include a substrate, such as an organic substrate or a lead frame. In some configurations, the carrier 10A may include a ceramic material or a metal plate. In some configurations, the carrier 10A may include a two-layer substrate, which includes a core layer and a conductive material and / or structure disposed on the upper and bottom surfaces of the substrate. The carrier 10A may include a semiconductor wafer or an electronic component. The electronic component may be a chip or a bare die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit device may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or a combination thereof. In some configurations, carrier 10A may include one or more conductive elements, surfaces, contacts, or pads.

[0057] In some configurations, the carrier 10A is electrically connected to the substrate 10 through electrical contacts 80 . In some configurations, the carrier 10A includes a base layer 110A, a dielectric layer 120A, and a plurality of conductive pads 130A. In some configurations, the conductive pads 130A are electrically connected to the conductive pads 130 through electrical contacts 80 .

[0058] Figure 3B is a cross-section of a package structure 3B according to some configurations of the present disclosure. Figure 3B The package structure 3B shown in FIG. 3B is similar to Figure 3A The packaging structure in , the differences between them are as follows.

[0059] In some configurations, the package structure 3B further includes an underfill 90 between the substrate 10 and the carrier 10A. In some configurations, the underfill 90 includes a resin layer 910 and a plurality of second fillers 920. In some configurations, a thickness T4 of the underfill 90 is greater than a thickness T1 of the protection layer 40. In some configurations, the underfill 90 directly contacts the protection layer 40, and the cavity space V1 is spaced apart from the underfill 90.

[0060] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G Various stages of an illustrative method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0061] refer to Figure 4A, a protective material 400A may be provided, and the stamped part 1400 may be partially immersed in the protective material 400A to obtain a layer of protective material 400A on the surface 1400a of the stamped part 1400. The protective material 400A may include epoxy flux. The epoxy flux includes epoxy resin and flux material. In some configurations, the viscosity of the protective material 400A is equal to or greater than about 20 Pa·S. In some configurations, the viscosity of the protective material 400A is about 20 Pa·S to about 35 Pa·S. According to some configurations of the present disclosure, the protective material 400A has a viscosity within the above range, and therefore the viscosity is high enough to have a sufficient amount of epoxy resin that can form a protective layer in subsequent operations, and the viscosity is low enough to maintain satisfactory workability.

[0062] refer to Figure 4B , a substrate 10 may be provided. In some configurations, the substrate 10 includes a base layer 100, a dielectric layer 120 having openings 110h and 130h on the base layer 100, and conductive pads 110 and 130 exposed by the openings 110h and 130h, respectively. In some configurations, a stamping part 1400 having a layer of protective material may be moved toward the substrate 10 to apply a protective material layer 400B on the conductive pad 110. In some configurations, the stamping part 1400 is moved toward the substrate 10 to apply a protective material layer 400B in the opening 110h on the exposed conductive pad 110.

[0063] refer to Figure 4C , an electronic component 20 including a conductive pad 210 and a solder element 330A on the conductive pad 210 may be provided, and a protective material layer may be disposed over the conductive pad 210 and the solder element 330A. In some configurations, the conductive pad 210 and the solder element 330A are immersed in the protective material 400A (e.g., the conductive pad 210 and the solder element 330A are "dipped" into the protective material 400A) to obtain a layer of protective material 400A on the surface of the conductive pad 210 and the solder element 330A.

[0064] refer to Figure 4D , the electronic component 20 having the conductive pad 210 and the solder element 330A covered with the protective material layer 400C can be moved toward the substrate 10. In some configurations, the conductive pad 210 and the solder element 330A covered with the protective material layer 400C move toward the conductive pad 110 covered with the protective material layer 400B. In some other configurations, the conductive pad 210 and the solder element 330A covered with the protective material layer 400C can be omitted. Figure 4A-4B , and the electronic component 20 having the conductive pad 210 and the solder element 330A covered with the protective material layer 400C moves toward the conductive pad 110 .

[0065] refer to Figure 4E , the electrical contact 80 may be disposed on the conductive pad 130, and a reflow operation may be performed on the solder element 330A to join the conductive pad 210 to the conductive pad 110. The reflow operation may also connect or join the electrical contact 80 to the conductive pad 130. The solder element 330A may melt and form the electrical connector 30 including the solder element 330 and the intermediate layers 310 and 320. The electrical contact 80 may be solder, and the intermediate layers 310 and 320 may be IMCs. In some configurations, the electrical contact 80 may be disposed on the conductive pad 130 before the protective material layer 400B is formed on the conductive pad 110. In some configurations, the electrical contact 80 may be disposed on the conductive pad 130 before the protective material layer 400C is formed on the conductive pad 210 and the solder element 330A.

[0066] refer to Figure 4F , the electronic component 50 can be connected or bonded to the substrate 10 through the electrical connector 60. In some configurations, the bottom filler 70 can be disposed to encapsulate the electrical connector 60. Thus, a Figure 1 The packaging structure 1 shown in FIG.

[0067] refer to Figure 4G , Figure 4F The package structure 1 shown in FIG. 1 may be further connected or bonded to a carrier 10A. In some configurations, the substrate 10 is bonded to the conductive pad 130A of the carrier 10A through the electrical contact 80. Thus, a Figure 3A The package structure 3A shown in FIG.

[0068] According to some configurations of the present disclosure, the protective material is disposed by dipping the solder element 330A and stamping onto the conductive pad 110. Therefore, the amount of the protective material is sufficient to provide a satisfactory solder joint structure, and the protective material is not so much as to overflow toward the conductive pad 130.

[0069] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Various stages of an illustrative method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0070] refer to Figure 5A, a protective material 400A may be provided, and the stamping part 1400 may be partially immersed in the protective material 400A to obtain a layer of protective material 400A on the surface 1400a of the stamping part 1400. The protective material 400A may include epoxy flux. In some configurations, the stamping part 1400 includes a stamping head 1410 having a predetermined pattern. The pattern may correspond to the pattern of the conductive pad on which the protective material 400A is subsequently configured. In some configurations, the stamping head 1410 includes a plurality of protrusions. The pattern of the protrusions may correspond to the pattern of the conductive pad (e.g., conductive pad 110) on which the protective material 400A is subsequently configured.

[0071] refer to Figure 5B , a substrate 10 may be provided. In some configurations, the substrate 10 includes a base layer 100, a dielectric layer 120 having openings 110h and 130h on the base layer 100, and conductive pads 110 and 130 exposed by the openings 110h and 130h, respectively. In some configurations, a stamping member 1400 having a layer of protective material may be moved toward the substrate 10 to apply a protective material layer 400B on the conductive pad 110. In some configurations, the stamping member 1400 is moved toward the substrate 10 to apply a protective material layer 400B in the opening 110h on the exposed conductive pad 110. In some configurations, a protrusion of a stamping head 1410 of the stamping member 1400 may be moved into the opening 110h to apply a protective material layer 400B within the opening 110h on the exposed conductive pad 110. In some configurations, by allowing the protrusion of the punch head 1410 to extend within the opening 110h, the protective material layer 400B is dispensed within the opening 110h, and the recessed surface of the punch part 1400 can directly contact the top surface of the dielectric layer 120. In some configurations, the protective material layer 400B is disposed within the opening 110h and is not disposed above the top surface of the dielectric layer 120. The width of the protrusion can be substantially the same as, greater than, or less than the width of the conductive pad 110 or the width of the opening 110h.

[0072] refer to Figure 5C , the electronic component 20 having the conductive pad 210 and the solder element 330A covered with the protective material layer 400C may move toward the substrate 10. In some configurations, the conductive pad 210 and the solder element 330A covered with the protective material layer 400C move toward the conductive pad 110 covered with the protective material layer 400B.

[0073] refer to Figure 5D, the electrical contact 80 may be disposed on the conductive pad 130, and a reflow operation may be performed on the solder element 330A to join the conductive pad 210 to the conductive pad 110. The reflow operation may also connect or join the electrical contact 80 to the conductive pad 130. The solder element 330A may melt and form the electrical connector 30 including the solder element 330 and the intermediate layers 310 and 320. The electrical contact 80 may be solder, and the intermediate layers 310 and 320 may be IMCs. In some configurations, the electrical contact 80 may be disposed on the conductive pad 130 before the protective material layer 400B is formed on the conductive pad 110. In some configurations, the electrical contact 80 may be disposed on the conductive pad 130 before the protective material layer 400C is formed on the conductive pad 210 and the solder element 330A.

[0074] refer to Figure 5E , the electronic component 50 can be connected or bonded to the substrate 10 through the electrical connector 60, and the substrate 10 can be bonded to the conductive pad 130A of the carrier 10A through the electrical contact 80. In some configurations, the bottom filler 70 can be disposed to encapsulate the electrical connector 60. In some configurations, the bottom filler 90 can be disposed to encapsulate the electrical contact 80. Thus, a Figure 3B The package structure 3B shown in FIG.

[0075] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that embodiments of the structures described herein may be spatially configured in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated by such configurations.

[0076] As used herein, the terms "approximately," "substantially," "generally," "about," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, these terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical can refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0077] If the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement between the highest point and the lowest point of a surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the surface can be considered to be substantially flat.

[0078] As used herein, the singular forms "a," "an," and "the" may include plural or plural referents unless the context clearly indicates otherwise.

[0079] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials are materials that present little or no resistance to the flow of electric current. One unit of measurement for conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m, for example at least 10 5 S / m or at least 10 6 S / m of a material. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0080] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for the sake of convenience and brevity, and should be flexibly construed to include not only the values ​​explicitly specified as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0081] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be replaced without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual equipment. There may be other embodiments that are not specifically described in the present disclosure. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are deemed to be included within the scope of the appended claims. Although the disclosed method has been described herein with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A packaging structure, comprising: substrate; a first electronic component over the substrate; a first electrical connection between the substrate and the first electronic component; as well as A protection layer encapsulates the first electrical connector, wherein the protection layer has a first curved side surface that is recessed toward the first electrical connector and is concave relative to a side surface of the first electronic component.

2. The packaging structure according to claim 1 further includes a second electrical connector adjacent to the first electrical connector, the protective layer is partially separated from the second electrical connector by a cavity space, the protective layer includes a first portion at a first side of the first electrical connector and a second portion at a second side of the first electrical connector different from the first side, and the first portion and the second portion have different widths at a height. 3 . The package structure according to claim 2 , wherein the first portion and the second portion of the protection layer are different in geometry from each other.

4. The packaging structure according to claim 1 further includes a second electrical connector between the substrate and the first electronic component, wherein the first electronic component has an active surface facing the substrate, the active surface includes a first area exposed by the protective layer, and the first area is between the first electrical connector and the second electrical connector in a cross-sectional perspective view. 5 . The package structure according to claim 1 , wherein the protection layer comprises a first protrusion horizontally overlapping the substrate and a second protrusion horizontally overlapping the substrate, and the first protrusion is different in geometry from the second protrusion.

6. The packaging structure according to claim 1, wherein the substrate includes a first conductive pad electrically connected to the first electronic component and a plurality of second conductive pads at sides of the first electronic component, and a distance between the first conductive pad and one of the plurality of second conductive pads is less than a pitch between the plurality of second conductive pads.

7. The packaging structure according to claim 6 further comprises a plurality of second electrical connectors, wherein the substrate is between the first electrical connector and the plurality of second electrical connectors, and a spacing between the plurality of second electrical connectors is greater than the distance between the first conductive pad and the one of the plurality of second conductive pads. 8 . The package structure according to claim 6 , further comprising an electrical contact disposed on the one of the plurality of second conductive pads, wherein a top surface of the electrical contact has a height higher than a top surface of the protection layer relative to the substrate. 9 . The package structure according to claim 1 , further comprising a second electronic component disposed under the substrate, wherein a width of the second electronic component is greater than a width of the first electronic component.

10. A packaging structure, comprising: a substrate having a first surface and a second surface opposite to the first surface; a first electronic component disposed above the first surface; a second electronic component disposed below the second surface of the substrate; as well as A protective layer between the first electronic component and the substrate, wherein the protective layer has a cavity space, wherein the cavity space at least partially overlaps a path between the first electronic component and the second electronic component, and the cavity space is configured to reduce the transfer of heat generated by the second electronic component and transferred toward the first electronic component. The package structure according to claim 10 , wherein the protection layer does not contain filler. 12 . The package structure according to claim 11 , wherein a corner area of ​​a bottom surface of the first electronic component is exposed by the protection layer.

13. The package structure according to claim 10, further comprising: a first electrical connection between the first electronic component and the substrate; as well as A second electrical connection is between the second electronic component and the substrate, wherein a thickness of the first electrical connection is smaller than a thickness of the second electrical connection. 14 . The package structure according to claim 13 , further comprising an electrical contact disposed at a side of the first electronic component and horizontally overlapping the first electrical connector, wherein a thickness of the electrical contact is greater than the thickness of the second electrical connector.

15. A packaging structure, comprising: a substrate comprising a first conductive pad and a second conductive pad, wherein the second conductive pad is exposed by a first opening of the substrate; an electronic component electrically connected to the first conductive pad; as well as a protective layer between the substrate and the electronic component, The first opening of the substrate is located at a first side of the protection layer, and a first ratio of a distance between the protection layer and the first opening of the substrate to a distance between the substrate and the electronic component is less than 25. 16 . The package structure of claim 15 , further comprising a plurality of electrical contacts disposed at the first side of the protection layer, wherein a second ratio of a distance between the protection layer and one of the plurality of electrical contacts relative to a pitch of the plurality of electrical contacts is less than 0.

8. 17 . The package structure according to claim 15 , further comprising a plurality of electrical contacts disposed at the first side of the protection layer, wherein a second ratio of a distance between the protection layer and one of the plurality of electrical contacts relative to a width of the one of the plurality of electrical contacts is less than 0.

2.

18. The package structure of claim 15, further comprising a plurality of electrical contacts disposed at the first side of the protective layer, wherein a second ratio of a distance between the electronic component and one of the plurality of electrical contacts relative to the distance between the substrate and the electronic component is less than 35.

19. The packaging structure according to claim 15, wherein the substrate further includes a third conductive pad exposed by a second opening of the substrate, the second opening of the substrate is at a second side of the protective layer, the second side is adjacent to the first side, and a second ratio of the distance between the protective layer and the second opening of the substrate to the distance between the substrate and the electronic component is less than 25. 20 . The package structure of claim 19 , wherein the first ratio is different from the second ratio.

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