Chip packaging structure, chip inversion method and electronic equipment

Abstract

The invention provides a chip packaging structure, a chip inversion method and electronic equipment, relates to the field of semiconductors, and aims to solve the problem that a gap is difficult to form between a first retaining wall and a welding column due to the fact that the interface bonding force between the first retaining wall and the welding column is large. Therefore, the welding flux of the welding column can be prevented from diffusing to the first electronic device and the second electronic device from the gap between the first retaining wall and the welding column. The packaging structure comprises a first electronic device, a second electronic device, a plurality of welding columns, a plurality of first retaining walls and filler. The first electronic device and the second electronic device are electrically connected through a plurality of welding columns; the multiple first retaining walls cover the side walls of the multiple welding columns, and gaps among the multiple first retaining walls are filled with the filler. Wherein the first retaining walls and the filler are made of dielectric materials, and the binding force between the material of the first retaining walls and the material of the welding column is larger than the binding force between the material of the filler and the material of the welding column.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a chip packaging structure, a chip flip-chip method, and an electronic device. Background Art

[0002] With the increase of chip interconnection density and the continuous reduction of interconnection size, chip packaging technology has become more and more diversified. Since flip-chip technology can shorten the interconnection length within the package and better adapt to the development needs of high integration, it has been widely used in the field of chip packaging. Flip-chip technology is to directly make solder pillars (i.e., bumps) on the bare chip (die) as connection terminals, and solder them on the redistribution layer in a flip-chip manner, so as to achieve electrical connection between the bare chip and the redistribution layer.

[0003] Under high temperature conditions, the solder of the solder column easily diffuses along the side wall of the solder column to the bare chip and the redistribution layer. On the one hand, the diffused solder is stacked on the bare chip and the redistribution layer, causing the adjacent solder columns to short-circuit through the stacked solder; on the other hand, the solder loss in some areas of the solder column is serious, causing the width of the solder column in this area to become smaller, thereby reducing the effective flow area in the solder column, and even causing the solder column to collapse at this position, completely losing the function of connecting the metal layer in the bare chip with the metal layer in the redistribution layer. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a chip packaging structure, a chip flip-chip method, and an electronic device. Since the interface bonding force between the first retaining wall and the solder column is relatively large, it is difficult to form a gap between the first retaining wall and the solder column, thereby preventing the solder of the solder column from diffusing from the gap between the first retaining wall and the solder column to the first electronic device and the second electronic device.

[0005] In a first aspect, the present application provides a chip packaging structure, which includes a first electronic device, a second electronic device, a plurality of solder pillars, a plurality of first retaining walls, and a filler. The first electronic device and the second electronic device are electrically connected via a plurality of solder pillars; the plurality of first retaining walls cover the side walls of the plurality of solder pillars, and the filler is filled in the gaps between the plurality of first retaining walls. The plurality of first retaining walls and the filler are both made of dielectric material, and the bonding force between the material of the first retaining walls and the material of the solder pillars is greater than the bonding force between the material of the filler and the material of the solder pillars.

[0006] In this way, in a high temperature environment, the first retaining wall can be used to prevent the solder of the solder column from diffusing downward along the side wall of the solder column. The filler is filled in the gaps between the plurality of first retaining walls to support the first electronic device and the second electronic device.

[0007] On this basis, compared with the related scheme of only filling fillers between adjacent solder pillars, in the present application, the bonding force between the material of the first retaining wall and the material of the solder pillar is greater than the bonding force between the material of the filler and the material of the solder pillar. In this way, in a high temperature environment, the interface bonding force between the first retaining wall and the solder pillar of the embodiment of the present application is greater than the interface bonding force between the filler and the solder pillar in the related scheme. Since the interface bonding force between the first retaining wall and the solder pillar is large, it is difficult to form a gap between the first retaining wall and the solder pillar, thereby preventing the solder of the solder pillar from diffusing from the gap between the first retaining wall and the solder pillar to the first electronic device and the second electronic device. Further, since the solder of the solder pillar no longer diffuses to the first electronic device and the second electronic device, on the one hand, the problem of short circuit of adjacent solder pillars through stacked solder can be avoided; on the other hand, it can be avoided that the width of the solder pillar becomes smaller due to the diffusion of the solder pillar, thereby reducing the effective flow area in the solder pillar, and even causing the solder pillar to collapse, completely losing the function of connecting the first connection plate and the second connection plate.

[0008] In some possible implementations, the chip packaging structure further includes a second retaining wall located between adjacent solder pillars, and the second retaining wall and the first retaining wall can be prepared by the same semiconductor process. The second retaining wall covers the surface of the first electronic device facing the second electronic device, and the surface of the second electronic device facing the first electronic device, respectively. The second retaining wall is made of a dielectric material.

[0009] In some possible implementations, the material of the plurality of first retaining walls is a dielectric material having metal elements.

[0010] For example, the material of the solder column usually contains metal elements such as tin or copper, and the material of the first retaining wall and the material of the solder column both contain metal elements. Since the properties of metals are the same or similar, the first retaining wall and the solder column have good contact, so that the bonding force between the material of the first retaining wall and the material of the solder column is greater than the bonding force between the material of the filler and the material of the solder column.

[0011] In some possible implementations, by using the first retaining wall to cover the side wall of the welding column and selecting a material with a large interface bonding force with the welding column as the material of the first retaining wall, it is also possible to prevent the welding column from being exposed to the air for a long time, causing the welding column to be continuously oxidized and generate oxides. Since the conductivity of the oxide is much lower than the conductivity of the raw material of the welding column, after at least a part of the welding column is converted into oxides, the effective flow area in the welding column is reduced, and even the welding column fails.

[0012] Furthermore, in order to prevent air from contacting the solder pillars through the first retaining walls and reacting with the solder pillars, a dense material may be selected as the material of the plurality of first retaining walls.

[0013] In some possible implementations, in order to meet the material requirements of the above-mentioned multiple first retaining walls (the material of the first retaining wall is a dense material with metal elements, and the first retaining wall is composed of dielectric material), the material of the first retaining wall includes Al2O3. Dense Al2O3 can effectively isolate the air and the welding column, greatly reducing the probability of oxidation of the material of the welding column. In addition, the material of the first retaining wall contains the metal element aluminum. During the preparation process, the first retaining wall and the welding column, which also have metal elements, can be in good contact, so that the first retaining wall and the welding column have a strong interface bonding force. On this basis, the material of the first retaining wall can also be a material that protects against electromagnetic radiation, etc.

[0014] In some possible implementations, if the material of the solder column can undergo a metal layer reaction with the material of the first connecting pad in the first electronic device and the material of the second connecting pad in the first electronic device to form an intermetallic compound, causing a phase change between the first connecting pad and the second connecting pad, resulting in shrinkage and collapse of the first connecting pad and the second connecting pad, the soldering reliability of the solder column may be greatly reduced.

[0015] Based on this, the chip packaging structure also includes a first conductive block and a second conductive block, the first conductive block is arranged between the first connection pad and the solder column, the second conductive block is arranged between the second connection pad and the solder column, and the first retaining wall is also in contact with the side walls of the first conductive block and the second conductive block. Among them, the material of the plurality of first conductive blocks and the material of the plurality of second conductive blocks both include conductive materials. In this way, the first conductive block and the second conductive block can also be used to prevent the material of the solder column from reacting with the first connection pad and the second connection pad.

[0016] In some possible implementations, the solder column is a uBump. Since the size of the uBump is very small, at the same oxidation degree, the effective flow area retained in the uBump is greatly reduced, which may cause the uBump to fail. Therefore, the solution of the present application is used on the uBump to effectively prevent the uBump from being oxidized and prevent the uBump from failing.

[0017] In some possible implementations, the material of the filler includes at least one of polyimide, organic resin, benzocyclobutene, and epoxy resin.

[0018] In a second aspect, the present application provides a flip-chip method, comprising: forming a plurality of first solder pillars, a plurality of first sub-blocking walls, and a first filler on a first electronic device to obtain a first substrate; the plurality of first sub-blocking walls cover the side walls of the plurality of first solder pillars, and the first filler is filled in the gaps between the plurality of first sub-blocking walls; wherein the first sub-blocking walls and the first filler are both made of dielectric material, and the bonding force between the material of the first sub-blocking walls and the material of the first solder pillars is greater than the bonding force between the material of the first filler and the material of the first solder pillars. Forming a plurality of second solder pillars, a plurality of second sub-blocking walls, and a second filler on a second electronic device to obtain a second substrate; the plurality of second sub-blocking walls cover the side walls of the plurality of second solder pillars, and the second filler is filled in the gaps between adjacent second sub-blocking walls; wherein the second sub-blocking walls and the second filler are both made of dielectric material, and the bonding force between the material of the second sub-blocking walls and the material of the second solder pillars is greater than the bonding force between the material of the second filler and the material of the second solder pillars. The first substrate and the second substrate are aligned; a plurality of first solder columns are aligned with a plurality of second solder columns one by one, and the first electronic device is electrically connected to the second electronic device through the plurality of first solder columns and the plurality of second solder columns; a plurality of first sub-blocking walls are aligned with a plurality of second sub-blocking walls one by one, and a first filler is aligned with a second filler.

[0019] In some possible implementations, forming a plurality of first solder pillars, a plurality of first sub-blocking walls, and a first filler on a first electronic device includes: forming a plurality of first solder pillars on the first electronic device; forming first sub-blocking walls and a first filler between adjacent first solder pillars. Forming a plurality of second solder pillars, a plurality of second sub-blocking walls, and a second filler on a second electronic device includes: forming a plurality of second solder pillars on the second electronic device; forming second sub-blocking walls and a second filler between adjacent second solder pillars.

[0020] In some possible implementations, forming a first sub-blocking wall and a first filler between adjacent first solder pillars includes: forming a first blocking wall film layer on the first solder pillars using an atomic layer deposition process, the first blocking wall film layer covering the surfaces and sidewalls of the plurality of first solder pillars, and the surface of the first electronic device located around the plurality of first solder pillars. Forming a first supporting film layer on the first blocking wall film layer; the distance from the surface of the first supporting film layer away from the first electronic device to the first electronic device is greater than or equal to the distance from the surface of the first blocking wall film layer away from the first electronic device to the first electronic device. Partially removing the first supporting film layer and the first blocking wall film layer to expose the surfaces of the plurality of first solder pillars away from the first electronic device, thereby obtaining a first sub-blocking wall and a third sub-blocking wall, wherein the third sub-blocking wall is located between the adjacent first solder pillars and covers the surface of the first electronic device.

[0021] In some possible implementations, a second sub-blocking wall and a second filler are formed between adjacent second solder pillars, including: forming a second blocking wall film layer on the second solder pillars using an atomic layer deposition process, the second blocking wall film layer covering the surfaces and sidewalls of a plurality of second solder pillars, and the surface of a second electronic device located around the second solder pillars. Forming a second supporting film layer on the second blocking wall film layer; the distance from the surface of the second supporting film layer away from the second electronic device to the second electronic device is greater than or equal to the distance from the surface of the second blocking wall film layer away from the second electronic device to the second electronic device. Partially removing the second supporting film layer and the second blocking wall film layer to expose the surfaces of a plurality of second solder pillars away from the second electronic device, thereby obtaining a second sub-blocking wall and a fourth sub-blocking wall, wherein the fourth sub-blocking wall is located between adjacent second solder pillars and covers the surface of the second electronic device.

[0022] In some possible implementations, aligning the first substrate and the second substrate includes: aligning the first substrate and the second substrate using a thermal compression welding process.

[0023] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0024] In a third aspect, the present application provides an electronic device, which includes a circuit board, solder balls, and the chip packaging structure described in the first aspect, wherein a second electronic device of the chip packaging structure is soldered to the circuit board through the solder balls.

[0025] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a A top view of a bare chip provided in an embodiment of the present application;

[0027] Figure 1b A side view of a chip packaging structure and a circuit board provided for related technologies;

[0028] Figure 1c for Figure 1b Defect diagram of the chip packaging structure shown;

[0029] Figure 2a A top view of a chip packaging structure provided in an embodiment of the present application;

[0030] Figure 2b for Figure 2a A1-A2 sectional view;

[0031] Figure 3 It is a schematic diagram of the oxidation of the solder column in the related art;

[0032] Figure 4 A side view of another chip packaging structure provided by an embodiment of the present application;

[0033] Figure 5a A side view of another chip packaging structure provided by an embodiment of the present application;

[0034] Figure 5b A side view of another chip packaging structure provided by an embodiment of the present application;

[0035] Figure 6 A side view of another chip packaging structure provided by an embodiment of the present application;

[0036] Figure 7 A side view of another chip packaging structure provided by an embodiment of the present application;

[0037] Figure 8 A flow chart of a chip flipping method provided in an embodiment of the present application;

[0038] Figure 9a A process diagram of a chip flipping method provided in an embodiment of the present application;

[0039] Figure 9b A process diagram of a chip flipping method provided in an embodiment of the present application;

[0040] Fig.9c A process diagram of a chip flipping method provided in an embodiment of the present application;

[0041] Figure 9d A process diagram of a chip flipping method provided in an embodiment of the present application;

[0042] Fig.9e A process diagram of a chip flipping method provided in an embodiment of the present application;

[0043] Figure 9f A process diagram of a chip flipping method provided in an embodiment of the present application;

[0044] Fig.10a A process diagram of a chip flipping method provided in an embodiment of the present application;

[0045] Fig.10b A process diagram of a chip flipping method provided in an embodiment of the present application;

[0046] Fig.10cA process diagram of a chip flipping method provided in an embodiment of the present application;

[0047] Fig.10d A process diagram of a chip flipping method provided in an embodiment of the present application;

[0048] Fig.10e A process diagram of a chip flipping method provided in an embodiment of the present application;

[0049] Fig.10f A process diagram of a chip flipping method provided in an embodiment of the present application.

[0050] Reference numerals:

[0051] 10-bare chip; 20-redistribution layer; 30-solder column; 31-first solder column; 32-second solder column; 40-first retaining wall; 41-first sub-retaining wall; 42-second sub-retaining wall; 401-first retaining wall film layer; 402-second retaining wall film layer; 50-filler; 51-first filler; 52-second filler; 501-first supporting film layer; 502-second supporting film layer; 60-second retaining wall; 61-third sub-retaining wall; 62-fourth sub-retaining wall; 71-first adhesion layer; 72-second adhesion layer; 81-first conductive block; 82-second conductive block. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0054] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0055] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0056] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0057] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0058] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0059] For the convenience of explanation, the following description takes a mobile phone as an example of an electronic device. The mobile phone may include a circuit board, and a processor, a memory, etc. may be integrated on the circuit board. For example, the processor may be implemented by connecting circuits on one or more chips. Of course, the mobile phone may also include other components, and other circuit structures may be integrated on the circuit board, which is not limited in the embodiments of the present application.

[0060] With the increase of chip interconnection density and the continuous reduction of interconnection size, chip packaging technology has become more and more diversified. Since the chip flip-chip technology can shorten the interconnection length in the package and better adapt to the development needs of high integration, it has been widely used in the field of chip packaging. The chip flip-chip technology is to directly make solder pillars on the bare chip as connection terminals, and solder them on the redistribution layer (RDL) in a flip-chip manner, so as to achieve electrical connection between the bare chip and the redistribution layer.

[0061] Specifically, Figure 1a The top view of the bare chip 10 is shown. The bare chip 10 includes a first connection pad 11, which may also be called a solder pad or other. Since there are many first connection pads 11 in the bare chip 10 and the size of the solder balls is large, if the bare chip 10 is directly soldered to the circuit board using solder balls, and the bare chip 10 is electrically connected to the circuit board using solder balls, the problem of pin solder balls short circuit may occur. In addition, in addition to the first connection pads 11, the bare chip 10 may also include wiring and metal film layers constituting circuit components.

[0062] Therefore, if Figure 1b As shown, the bare chip 10 is flipped on the redistribution layer 20, and the solder pillars 30 are respectively in contact with the first connection pad 11 of the bare chip 10 and the second connection pad 21 of the redistribution layer 20, so that the first connection pad 11 is electrically connected to the second connection pad 21 through the solder pillars 30, thereby leading the first connection pad 11 in the bare chip 10 to the second connection pad 21 of the redistribution layer 20 through the solder pillars 30.

[0063] The redistribution layer 20 further includes a third connection pad 22 opposite to the second connection pad 21. The second connection pad 21 is electrically connected to the third connection pad 22 via a metal layer in the redistribution layer 20. The bare chip 10 is soldered to the circuit board via the third connection pad 22 and solder balls in the redistribution layer 20. Since the size of the solder column 30 between the redistribution layer 20 and the bare chip 10 is much smaller than the size of the solder ball, under ideal conditions, there will be no short circuit problem between adjacent solder columns 30.

[0064] Under high temperature conditions, the solder of the solder pillar 30 easily diffuses along the sidewall of the solder pillar 30 toward the bare chip 10 and the redistribution layer 20. Figure 1c As shown, on the one hand, the diffused solder is stacked on the bare chip 10 and the redistribution layer 20, causing the adjacent solder pillars 30 to short-circuit through the stacked solder; on the other hand, the solder loss in some areas of the solder pillars 30 is serious, causing the partial width of the solder pillars 30 in this area to become smaller, thereby causing the effective flow area in the solder pillars 30 to decrease, and even causing the solder pillars 30 to collapse at this position, completely losing the function of connecting the first connection pad 11 and the second connection pad 21.

[0065] The effective flow area refers to the effective area of ​​the solder column 30 that can be used to connect the first connection pad 11 and the second connection pad 21, or the effective area of ​​the solder column 30 that can be used to connect the bare chip 10 and the redistribution layer 20. The width direction of the solder column 30 is the direction from any solder column 30 to the adjacent solder column 30.

[0066] Based on this, the embodiment of the present application provides a chip packaging structure, such as Figure 2a and Figure 2b As shown, the chip packaging structure includes a first electronic device and a second electronic device, and the first electronic device and the second electronic device are electrically connected through a plurality of solder pillars 30. The embodiment of the present application does not limit the first electronic device and the second electronic device, and the first electronic device and the second electronic device can be any two electronic devices that need to be electrically connected through solder pillars 30.

[0067] For example, the first electronic device and the second electronic device may be a bare chip 10, a redistribution layer 20, an integrated passive device (IPD), etc. For the convenience of description, the following description takes the bare chip 10 as the first electronic device and the redistribution layer 20 as the second electronic device as an example.

[0068] In addition to the bare chip 10, the redistribution layer 20, and the solder pillars 30, the chip packaging structure also includes a first retaining wall 40 and a filler 50. The first retaining wall 40 covers the side walls of the plurality of solder pillars 30, so that in a high temperature environment, the first retaining wall 40 can be used to prevent the solder of the solder pillars 30 from diffusing downward along the side walls of the solder pillars 30. The filler 50 is filled in the gaps between the plurality of first retaining walls 40, so that the filler 50 supports the bare chip 10 and the redistribution layer 20.

[0069] On this basis, compared with the related solution of only filling the filler 50 between adjacent solder pillars 30, in the embodiment of the present application, the bonding force between the material of the first retaining wall 40 and the material of the solder pillar 30 is greater than the bonding force between the material of the filler 50 and the material of the solder pillar 30. In this way, in a high temperature environment, the interface bonding force between the first retaining wall 40 and the solder pillar 30 in the embodiment of the present application is greater than the interface bonding force between the filler 50 and the solder pillar 30 in the related solution. Since the interface bonding force between the first retaining wall 40 and the solder pillar 30 is large, it is difficult to form a gap between the first retaining wall 40 and the solder pillar 30, thereby preventing the solder of the solder pillar 30 from diffusing from the gap between the first retaining wall 40 and the solder pillar 30 to the bare chip 10 and the redistribution layer 20. Furthermore, since the solder of the solder column 30 no longer diffuses toward the bare chip 10 and the redistribution layer 20, on the one hand, the problem of short circuit between adjacent solder columns 30 through the stacked solder can be avoided; on the other hand, the width of the solder column 30 can be avoided from becoming smaller due to the diffusion of the solder column 30, thereby reducing the effective flow area in the solder column 30, and even causing the solder column 30 to collapse, completely losing the function of connecting the first connection plate 11 and the second connection plate 21.

[0070] It should be understood that the plurality of first retaining walls 40 cover the sidewalls of the plurality of solder pillars 30, and the filler 50 is filled in the gaps between the plurality of first retaining walls 40, that is, the first retaining walls 40 are in contact with the sidewalls of the solder pillars 30, and the filler 50 is not in direct contact with the first retaining walls 40. Therefore, the bonding force between the material of the filler 50 and the material of the solder pillar 30 is the bonding force between the material used for the filler 50 and the material used for the solder pillar 30, and is not the interface bonding force between the filler 50 and the solder pillar 30.

[0071] In some possible implementations, the first barrier wall 40 and the filler 50 are both made of dielectric material to prevent adjacent solder pillars 30 from being short-circuited by the first barrier wall 40 and the filler 50 .

[0072] The material of the filler 50 may include a material with good supporting effect, so as to use the filler 50 to support the bare chip 10 and the redistribution layer 20, so as to improve the stability of the chip packaging structure. For example, the material of the solder column 30 includes at least one of tin-silver (SnAg), tin-silver-copper (CuSnAg), tin-silver-nickel (NiSnAg), tin-silver-copper-nickel (NiCuSnAg), and copper. The material of the filler 50 includes at least one of polyimide (PI), organic resin, benzocyclobutene (BCB), and epoxy resin.

[0073] For example, the material of the first retaining wall 40 can be a dielectric material having a metal element, and the material of the solder column 30 generally has a metal element such as a tin (Sn) element or a copper element, and the material of the first retaining wall 40 and the material of the solder column 30 both include a metal element. Since the properties of metals are the same or similar to each other, the first retaining wall 40 has good contact with the solder column 30, so that the bonding force between the material of the first retaining wall 40 and the material of the solder column 30 is greater than the bonding force between the material of the filler 50 and the material of the solder column 30.

[0074] In addition, by using the first retaining wall 40 to cover the side wall of the solder column 30 and selecting a material with a large interface bonding force with the solder column 30 as the material of the first retaining wall 40, it is also possible to prevent the solder column 30 from being exposed to the air for a long time, causing the solder column 30 to be continuously oxidized and generate oxides ( Figure 3 ). Since the conductivity of the oxide is much lower than the conductivity of the raw material of the solder column 30, after at least a portion of the solder column 30 is converted into the oxide, the effective flow area of ​​the solder column 30 is reduced, and even the solder column 30 fails.

[0075] Furthermore, in order to prevent air from contacting the welding pillar 30 through the first retaining wall 40 and reacting with the welding pillar 30 , a dense material may be selected as the material of the first retaining wall 40 .

[0076] In some possible implementations, the solder column 30 of the embodiment of the present application may be a solder bump or a micro bump (uBump), etc. Optionally, when the solder column 30 is a uBump, since the size of the uBump is very small, at the same oxidation degree, the effective flow area retained in the uBump is greatly reduced, which may cause the uBump to fail. Therefore, the solution of the embodiment of the present application is used on the uBump, which can effectively prevent the uBump from being oxidized and prevent the uBump from failing.

[0077] In order to meet the material requirements of the first retaining wall 40 (the material of the first retaining wall is a dense material with metal elements, and the first retaining wall is composed of a dielectric material), the material of the first retaining wall 40 includes aluminum oxide (Al2O3). The dense Al2O3 can effectively isolate the air from the welding column, greatly reducing the probability of oxidation of the material of the welding column 30. In addition, the material of the first retaining wall 40 contains the metal element aluminum (Al). During the preparation process, the first retaining wall 40 and the welding column 30, which also have metal elements, can be in good contact, so that the first retaining wall 40 and the welding column 30 have a strong interface bonding force. On this basis, the material of the first retaining wall 40 can also be a material that prevents electromagnetic radiation.

[0078] In some possible implementations, such as Figure 4As shown, the chip packaging structure includes, in addition to the first retaining wall 40, a second retaining wall 60 between adjacent solder pillars 30. The second retaining wall 60 is in contact with the surface of the bare chip 10 facing the redistribution layer 20 and the surface of the redistribution layer 20 facing the bare chip 10, respectively, and is used to cover the surface of the bare chip 10 facing the redistribution layer 20 and the surface of the redistribution layer 20 facing the bare chip 10. It should be understood that the second retaining wall 60 is located between adjacent solder pillars 30, and therefore, the second retaining wall 60 does not affect the electrical connection between the solder pillar 30 and the first connection pad 11 of the bare chip 10, nor does it affect the electrical connection between the solder pillar 30 and the second connection pad 21 of the redistribution layer 20.

[0079] In this case, the materials of the first retaining wall 40 and the second retaining wall 50 are both made of dielectric material, thereby preventing adjacent solder columns 30 from short-circuiting through the first retaining wall 40 and the second retaining wall 60, and preventing the originally electrically isolated first connecting plate 11 and the second connecting plate 21 from short-circuiting through the first retaining wall 40 and the second retaining wall 60.

[0080] The material of the first retaining wall 40 may be the same as that of the second retaining wall 60, or the material of the first retaining wall 40 may be different from that of the second retaining wall 60. Optionally, the first retaining wall 40 and the second retaining wall 60 are prepared by the same semiconductor process, and the material of the first retaining wall 40 is the same as that of the second retaining wall 60. For the specific preparation process of the first retaining wall 40 and the second retaining wall 60, refer to the detailed introduction of the flip-chip method below.

[0081] In some possible implementations, the embodiments of the present application do not limit the width W1 of the first barrier wall 40 and the thickness D1 of the second barrier wall 60, as long as the sum of the width W2 of the filler 50 and twice the width W1 of the first barrier wall 40 is equal to the spacing distance between adjacent solder columns 30, and the sum of the thickness D2 of the filler 50 and twice the thickness D1 of the second barrier wall 60 is equal to the spacing between the bare chip 10 and the redistribution layer 20.

[0082] Optionally, when the first retaining wall 40 and the second retaining wall 60 are prepared by the same semiconductor process, the width W1 of the first retaining wall 40 and the thickness D1 of the second retaining wall are the same, and the width W1 of the first retaining wall 40 and the thickness D1 of the second retaining wall can be in the range of 10nm to 30nm. This thickness range is moderate, and the process preparation cost of the first retaining wall 40 is not increased due to a too large thickness range, and the air does not still pass through the first retaining wall 40 due to a too small thickness range, thereby causing the solder column 30 to be oxidized. For example, the width W1 of the first retaining wall 40 and the thickness D1 of the second retaining wall 60 are 10nm, 20nm, 30nm, etc.

[0083] In some possible implementations, the bare chip 10 may include active devices, capacitors, etc. in addition to the metal layer. The active devices may include transistors, for example.

[0084] In some embodiments, Figure 5a As shown, the chip packaging structure is obtained by aligning the first substrate and the second substrate. The first substrate includes a bare chip 10, and a first solder column 31, a first sub-blocking wall 41, and a first filler 51 arranged on the bare chip 10; the second substrate includes a redistribution layer 20, and a second solder column 32, a second sub-blocking wall 42, and a second filler 52 arranged on the redistribution layer 20. The first solder column 31 and the second solder column 32 are arranged opposite to each other, and the two form the solder column 30 after being aligned; the first sub-blocking wall 41 and the second sub-blocking wall 42 are arranged opposite to each other, and the two form the first block wall 40 after being aligned; the first filler 51 and the second filler 52 are arranged opposite to each other, and the two form the filler 50 after being aligned.

[0085] Optional, such as Figure 5b As shown, the first substrate further includes a third sub-blocking wall 61, which is disposed between the bare chip 10 and the first filler 51 and is adjacent to two adjacent first sub-blocking walls 41, and the third sub-blocking wall 61 covers the surface of the bare chip 10. The second substrate further includes a fourth sub-blocking wall 62, which is disposed between the redistribution layer 20 and the second filler 52 and is adjacent to two adjacent second sub-blocking walls 42, and the fourth sub-blocking wall 62 covers the surface of the redistribution layer 20. After the first substrate and the second substrate are aligned, the third sub-blocking wall 61 and the fourth sub-blocking wall 62 constitute the second blocking wall 60.

[0086] In some possible implementation methods, the embodiment of the present application does not limit the method of aligning the first substrate and the second substrate. Optionally, the first substrate and the second substrate can be aligned using a hot pressing process, and the solder of the first solder column 31 and the solder of the second solder column 32 are annealed and reflowed to achieve molten welding between the solders.

[0087] In some embodiments, if the material of the solder column 30 can react with the material of the first connecting pad 11 and the material of the second connecting pad 21 to form an intermetallic compound, it will cause the first connecting pad 11 and the second connecting pad 21 to undergo a phase change, causing the first connecting pad 11 and the second connecting pad 21 to shrink and collapse, thereby greatly reducing the welding reliability of the solder column 30.

[0088] For example, the materials of the first connection pad 11 and the second connection pad 21 are copper (Cu), and the material of the solder pillar 30 includes tin. Copper and tin react to generate a copper-tin intermetallic compound.

[0089] Based on this, Figure 6and Figure 7 As shown, the chip packaging structure further includes a plurality of first conductive blocks 81 and a plurality of second conductive blocks 82 arranged at intervals. The first conductive block 81 is arranged between the bare chip 10 and the solder column 30, the second conductive block 82 is arranged between the redistribution layer 20 and the solder column 30, and the first retaining wall 40 is also in contact with the sidewalls of the first conductive block 81 and the sidewalls of the second conductive block 82. In this way, the first conductive block 81 and the second conductive block 82 can also be used to prevent the material of the solder column 30 from reacting with the first connection pad 11 and the second connection pad 21.

[0090] Furthermore, in order to ensure that the second connection pad 21 is electrically connected to the first connection pad 11, the materials of the first conductive block 81 and the second conductive block 82 both include conductive materials, so that the second connection pad 21 is electrically connected to the first connection pad 11 through the first conductive block 81, the solder column 30, and the second conductive block 82. Optionally, the first conductive block 81 and the second conductive block 82 can be a stack of titanium (Ti) and Cu.

[0091] In another embodiment, the present application also provides a chip flipping method, such as Figure 8 As shown, this can be achieved as follows:

[0092] S110, forming a plurality of first solder pillars, a plurality of first sub-blocking walls, and a first filler on the first electronic device to obtain a first substrate; the plurality of first sub-blocking walls cover the side walls of the plurality of first solder pillars, and the first filler is filled in the gaps between the plurality of first sub-blocking walls; wherein the first sub-blocking walls and the first filler are both made of dielectric material, and the bonding force between the material of the first sub-blocking walls and the material of the first solder pillars is greater than the bonding force between the material of the first filler and the material of the first solder pillars.

[0093] Specifically, the process of forming the first substrate includes:

[0094] The bare chip 10 is prebaked and then cleaned with a scrubber to remove process residues on the bare chip 10 , improve the surface cleanliness of the bare chip 10 , and enhance the surface adhesion of the bare chip 10 .

[0095] Then, if Figure 9a As shown, a seed layer 80 is deposited on the front side of the bare chip 10. Optionally, the seed layer 80 may be deposited by physical vapor deposition (PVD), and the seed layer 80 may be a stacked layer of titanium and copper.

[0096] It should be understood that the front side of the bare chip 10 is the surface of the bare chip 10 having the first connection pad 11 .

[0097] Then, if Figure 9b As shown, the first solder column 31 is formed on the side of the seed layer 80 away from the bare chip 10. Optionally, the first photoresist can be spin-coated on the seed layer 80, and the first photoresist is soft-baked, and then the first photoresist is exposed and developed. After development, a first photoresist pattern is obtained, and the first photoresist pattern includes a hollow portion, and the hollow portion is the area where the first solder column 31 to be formed is located. Then, the first solder column 31 is filled in the hollow portion by a plating process, and the first photoresist pattern is peeled off. Afterwards, as shown in FIG. Fig.9c As shown, the first photoresist pattern is removed, and the seed layer 80 is etched under the protection of the first solder column 31 to obtain the first conductive block 81. When the seed layer 80 is etched, the etching material does not affect the pattern of the first solder column 31 because the material of the first solder column 31 is different from that of the seed layer 80, and the two have an etching selectivity ratio.

[0098] In other possible implementation methods, the first solder column 31 may be formed in other ways, which are not limited in the embodiments of the present application. For example, solder and a first photoresist are first formed on the seed layer 80 in sequence, and the first photoresist is soft-baked, and then the first photoresist is exposed and developed, and a first photoresist pattern is obtained after development, and the first photoresist pattern includes a reserved portion, and the reserved portion corresponds to the area where the first solder column 31 to be formed is located. Then, under the protection of the first photoresist pattern, the solder and the seed layer 80 are etched in sequence to obtain the first solder column 31 and the first conductive block 81, and the first photoresist pattern is peeled off.

[0099] Compared with the solution of etching the solder to obtain the first solder column 31 , the solution of filling the first solder column 31 in the hollow portion can save solder, thereby saving packaging costs.

[0100] Of course, when the first substrate does not include the first conductive block 81 , the above two processes can also be used to directly form the first solder pillar 31 on the front side of the bare chip 10 .

[0101] In some possible implementations, the material of the first solder pillar 31 includes at least one of SnAg, CuSnAg, NiSnAg, NiCuSnAg, and Cu.

[0102] Then, if Figure 9d As shown, a first barrier film layer 401 is formed on the surface of the first solder column 31 away from the bare chip 10, the side of the first solder column 31, and the surface of the bare chip 10 around the first solder column 31. Optionally, an atomic layer deposition (ALD) process may be used to deposit the first barrier film layer 401. The thickness of the first barrier film layer 401 may range from 10 nm to 30 nm.

[0103] Then, if Fig.9e As shown, the first supporting film layer 501 is covered on the first barrier film layer 401, and the distance from the surface of the first supporting film layer 501 away from the bare chip 10 to the bare chip 10 is greater than or equal to the distance from the surface of the first barrier film layer 401 away from the bare chip 10 to the bare chip 10. Optionally, the material of the first filler 501 includes at least one of PI, organic resin, BCB, and epoxy resin.

[0104] Then, if Figure 9f As shown, the first support film layer 501 and the first retaining wall film layer 401 are partially removed to expose the surface of the first solder column 31 away from the bare chip 10, thereby obtaining the first sub-retaining wall 41, the third sub-retaining wall 61, and the first filler 51. The first sub-retaining wall 41 is in contact with the side wall of the first solder column 31, and the third sub-retaining wall 61 is in contact with the bare chip 10. In other words, the first sub-retaining wall 41 covers the side wall of the first solder column 31, and the third sub-retaining wall 61 is located between adjacent first solder columns 31 and covers the surface of the bare chip 10. The first filler 51 is located in the gaps between the plurality of first sub-retaining walls 41.

[0105] Optionally, the first support film layer 501 and the first barrier film layer 401 may be partially removed by grinding, chemical mechanical polishing (CMP), wet etching, dry etching or the like to expose the surface of the first solder pillar 31 facing away from the bare chip 10 .

[0106] S120, forming a plurality of second solder pillars, a plurality of second sub-blocking walls, and a second filler on the second electronic device to obtain a second substrate; the plurality of second sub-blocking walls cover the side walls of the plurality of second solder pillars, and the second filler is filled in the gaps between adjacent second sub-blocking walls; wherein the second sub-blocking walls and the second filler are both made of dielectric material, and the bonding force between the material of the second sub-blocking walls and the material of the second solder pillars is greater than the bonding force between the material of the second filler and the material of the second solder pillars.

[0107] like Fig.10a As shown, a seed layer 80 is deposited on the redistribution layer 20 . Optionally, the seed layer 80 may be deposited by PVD, and the seed layer 80 may be a stacked layer of titanium and copper.

[0108] Then, if Fig.10bAs shown, the second solder column 32 is formed on the side of the seed layer 80 away from the redistribution layer 20. Optionally, the second photoresist can be firstly spin-coated on the seed layer 80, and the second photoresist is soft-baked, and then the second photoresist is exposed and developed. After development, a second photoresist pattern is obtained, and the second photoresist pattern includes a hollow portion, and the hollow portion is the area where the second solder column 32 to be formed is located. Then, the second solder column 32 is filled in the hollow portion by a plating process, and the second photoresist pattern is peeled off. Afterwards, as shown in FIG. Fig.10c As shown, the second photoresist pattern is removed, and the seed layer 80 is etched under the protection of the second solder column 32 to obtain the second conductive block 82. When the seed layer 80 is etched, the etching material does not affect the pattern of the second solder column 32 because the material of the second solder column 32 is different from that of the seed layer 80, and the two have an etching selectivity ratio.

[0109] In other possible implementations, the second solder column 32 may be formed in other ways, which are not limited in the embodiments of the present application. For example, solder and a second photoresist are first formed on the seed layer 80 in sequence, and the second photoresist is soft-baked, and then the second photoresist is exposed and developed, and a second photoresist pattern is obtained after development, and the second photoresist pattern includes a reserved portion, and the reserved portion corresponds to the area where the second solder column 32 to be formed is located. Then, under the protection of the second photoresist pattern, the solder and the seed layer 80 are etched in sequence to obtain the second solder column 32 and the second conductive block 82, and the second photoresist pattern is peeled off.

[0110] Compared with the solution of etching the solder to obtain the second solder pillar 32 , the solution of filling the second solder pillar 32 in the hollow portion can save solder, thereby saving packaging costs.

[0111] Of course, when the second substrate does not include the second conductive block 82 , the above two processes can also be used to directly form the second solder pillar 32 on the front surface of the redistribution layer 20 .

[0112] In some possible implementations, the material of the second solder pillar 32 includes at least one of SnAg, CuSnAg, NiSnAg, NiCuSnAg, and Cu.

[0113] Then, if Fig.10d As shown, a second barrier film layer 402 is formed on the surface of the second solder column 32 away from the redistribution layer 20, the side of the second solder column 32, and the surface of the redistribution layer 20 around the second solder column 32. Optionally, the second barrier film layer 402 may be deposited by an ALD process. The thickness of the second barrier film layer 402 may range from 10 nm to 30 nm.

[0114] Then, if Fig.10eAs shown, the second supporting film layer 502 is covered on the second retaining wall film layer 402, and the distance from the surface of the second supporting film layer 502 away from the redistribution layer 20 to the redistribution layer 20 is greater than or equal to the distance from the surface of the second retaining wall film layer 402 away from the redistribution layer 20 to the redistribution layer 20. Optionally, the material of the second filler 502 includes at least one of PI, SiO, SiO2, SiN, and SiCN.

[0115] Then, if Fig.10f As shown, the second support film layer 502 and the second retaining wall film layer 402 are partially removed to expose the surface of the second solder column 32 away from the redistribution layer 20, thereby obtaining the second sub-retaining wall 42, the fourth sub-retaining wall 62, and the second filler 52. The second sub-retaining wall 42 is in contact with the side wall of the second solder column 32, and the fourth sub-retaining wall 62 is in contact with the redistribution layer 20. In other words, the second sub-retaining wall 42 covers the side wall of the second solder column 32, and the third and fourth sub-retaining walls 62 are located between adjacent second solder columns 32 and cover the surface of the redistribution layer 20. The second filler 52 is located in the gaps between the plurality of second sub-retaining walls 42.

[0116] Optionally, the second support film layer 502 and the second barrier film layer 402 may be partially removed by rough grinding, chemical mechanical polishing, wet etching, dry etching or other processes to expose the surface of the second solder pillar 32 away from the redistribution layer 20 .

[0117] In some possible implementations, step S110 may be performed first, and then step S120; or, step S120 may be performed first, and then step S110; or, step S110 and step S120 may be performed simultaneously.

[0118] S130, aligning the first substrate and the second substrate. The plurality of first solder pillars 31 and the plurality of second solder pillars 32 are arranged opposite to each other, the bare chip 10 is electrically connected to the redistribution layer 20 through the plurality of first solder pillars 31 and the plurality of second solder pillars 32, and the plurality of first solder pillars 31 and the plurality of second solder pillars 32 are aligned to form solder pillars 30; the first sub-blocking wall 41 and the second sub-blocking wall 42 are arranged opposite to each other, and the two are aligned to form the first blocking wall 40; the first filler 51 and the second filler 52 are arranged opposite to each other, and the two are aligned to form the filler 50.

[0119] In some possible implementation methods, the embodiment of the present application does not limit the method of aligning the first substrate and the second substrate. Optionally, the first substrate and the second substrate can be aligned using a hot pressing process, and the solder of the first solder column 31 and the solder of the second solder column 32 are annealed and reflowed to achieve molten welding between the solders.

[0120] By making the first retaining wall 40 cover the side walls of the plurality of solder pillars 30, in this way, in a high temperature environment, the first retaining wall 40 can be used to prevent the solder of the solder pillar 30 from diffusing downward along the side walls of the solder pillar 30. The filler 50 is filled in the gaps between the plurality of first retaining walls 40, so that the filler 50 supports the bare chip 10 and the redistribution layer 20.

[0121] On this basis, compared with the related solution of only filling the filler 50 between adjacent solder pillars 30, in the embodiment of the present application, the bonding force between the material of the first retaining wall 40 and the material of the solder pillar 30 is greater than the bonding force between the material of the filler 50 and the material of the solder pillar 30. In this way, in a high temperature environment, the interface bonding force between the first retaining wall 40 and the solder pillar 30 in the embodiment of the present application is greater than the interface bonding force between the filler 50 and the solder pillar 30 in the related solution. Since the interface bonding force between the first retaining wall 40 and the solder pillar 30 is large, it is difficult to form a gap between the first retaining wall 40 and the solder pillar 30, thereby preventing the solder of the solder pillar 30 from diffusing from the gap between the first retaining wall 40 and the solder pillar 30 to the bare chip 10 and the redistribution layer 20. Furthermore, since the solder of the solder column 30 no longer diffuses toward the bare chip 10 and the redistribution layer 20, on the one hand, the problem of short circuit between adjacent solder columns 30 through the stacked solder can be avoided; on the other hand, the width of the solder column 30 can be avoided from becoming smaller due to the diffusion of the solder column 30, thereby reducing the effective flow area in the solder column 30, and even causing the solder column 30 to collapse, completely losing the function of connecting the first connection plate 11 and the second connection plate 21.

[0122] In some possible implementations, the first barrier wall 40 and the filler 50 are both made of dielectric material to prevent adjacent solder pillars 30 from being short-circuited by the first barrier wall 40 and the filler 50 .

[0123] For example, the material of the first retaining wall 40 can be a dielectric material having a metal element, and the material of the solder column 30 generally has a metal element such as tin or copper, and both the material of the first retaining wall 40 and the material of the solder column 30 include a metal element. Since the properties of metals are the same or similar, the first retaining wall 40 and the solder column 30 have good contact, so that the bonding force between the material of the first retaining wall 40 and the material of the solder column 30 is greater than the bonding force between the material of the filler 50 and the material of the solder column 30.

[0124] In addition, by using the first retaining wall 40 to cover the side wall of the solder column 30 and selecting a material with a large interface bonding force with the solder column 30 as the material of the first retaining wall 40, it is also possible to prevent the solder column 30 from being exposed to the air for a long time, causing the solder column 30 to be continuously oxidized and generate oxides ( Figure 3). Since the conductivity of the oxide is much lower than the conductivity of the raw material of the solder column 30, after at least a portion of the solder column 30 is converted into the oxide, the effective flow area of ​​the solder column 30 is reduced, and even the solder column 30 fails.

[0125] Furthermore, in order to prevent air from contacting the welding pillar 30 through the first retaining wall 40 and reacting with the welding pillar 30 , a dense material may be selected as the material of the first retaining wall 40 .

[0126] In some possible implementations, the solder column 30 of the embodiment of the present application may be a solder ball bump or uBump, etc. Optionally, when the solder column 30 is a uBump, since the size of the uBump is very small, at the same oxidation degree, the effective flow area retained in the uBump is greatly reduced, which may cause the uBump to fail. Therefore, the solution of the embodiment of the present application is used on the uBump, which can effectively prevent the uBump from being oxidized and prevent the uBump from failing.

[0127] In order to meet the material requirements of the first retaining wall 40 (the material of the first retaining wall is a dense material with metal elements, and the first retaining wall is composed of dielectric material), the material of the first retaining wall 40 includes Al2O3. The dense Al2O3 can effectively isolate the air and the welding column, greatly reducing the probability of oxidation of the material of the welding column 30. In addition, the material of the first retaining wall 40 contains the metal element aluminum. During the preparation process, the first retaining wall 40 and the welding column 30, which also have metal elements, can have good contact, so that the first retaining wall 40 and the welding column 30 have a strong interface bonding force. On this basis, the material of the first retaining wall 40 can also be a material that prevents electromagnetic radiation.

[0128] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiments and will not be repeated here.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip packaging structure, characterized in that: It includes a first electronic device, a second electronic device, a plurality of solder pillars, a plurality of first retaining walls, and a filler; The first electronic device and the second electronic device are electrically connected via the plurality of solder pillars; the plurality of first retaining walls cover the side walls of the plurality of solder pillars, and the filler is filled in the gaps between the plurality of first retaining walls; The plurality of first retaining walls and the filler are both made of dielectric material, and the bonding force between the material of the first retaining walls and the material of the solder column is greater than the bonding force between the material of the filler and the material of the solder column.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a second retaining wall located between adjacent solder pillars; the second retaining wall respectively covers a surface of the first electronic device facing the second electronic device, and a surface of the second electronic device facing the first electronic device; Wherein, the second retaining wall is made of the dielectric material.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The material of the first retaining walls is a dielectric material having metal elements.

4. The chip packaging structure according to claim 3, characterized in that: The material of the plurality of first retaining walls comprises a dense material.

5. The chip packaging structure according to claim 4, characterized in that: The material of the plurality of first retaining walls includes aluminum oxide.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The chip packaging structure further includes a first conductive block and a second conductive block; The first conductive block is disposed between the first electronic device and the solder column, the second conductive block is disposed between the second electronic device and the solder column, and the plurality of first retaining walls also cover the side walls of the first conductive block and the second conductive block; Wherein, the material of the plurality of first conductive blocks and the material of the plurality of second conductive blocks both include conductive materials.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The solder pillars are micro-bumps.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The material of the filler includes at least one of polyimide, organic resin, benzocyclobutene and epoxy resin.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The first electronic device is a bare chip, and the second electronic device is a redistribution layer.

10. A chip flipping method, characterized in that: include: Forming a plurality of first solder pillars, a plurality of first sub-blocking walls, and a first filler on the first electronic device to obtain a first substrate; The plurality of first sub-retaining walls cover the side walls of the plurality of first welding columns, and the first filler is filled in the gaps between the plurality of first sub-retaining walls; wherein the first sub-retaining walls and the first filler are both made of dielectric material, and the bonding force between the material of the first sub-retaining walls and the material of the first welding column is greater than the bonding force between the material of the first filler and the material of the first welding column; A plurality of second solder pillars, a plurality of second sub-blocking walls, and a second filler are formed on the second electronic device to obtain a second substrate; the plurality of second sub-blocking walls cover the side walls of the plurality of second solder pillars, and the second filler is filled in the gaps between adjacent second sub-blocking walls; wherein the second sub-blocking walls and the second filler are both made of dielectric material, and the bonding force between the material of the second sub-blocking walls and the material of the second solder pillars is greater than the bonding force between the material of the second filler and the material of the second solder pillars; The first substrate and the second substrate are aligned; the multiple first solder columns are opposite to the multiple second solder columns one by one, and the first electronic device is electrically connected to the second electronic device through the multiple first solder columns and the multiple second solder columns; the multiple first sub-blocking walls are opposite to the multiple second sub-blocking walls one by one, and the first filler is opposite to the second filler.

11. The chip flipping method according to claim 10, characterized in that: The method of forming a plurality of first solder pillars, a plurality of first sub-blocking walls, and a first filler on the first electronic device includes: forming a plurality of first solder pillars on the first electronic device; forming the first sub-blocking wall and the first filler between adjacent first welding columns; The method of forming a plurality of second solder pillars, a plurality of second sub-blocking walls, and a second filler on the second electronic device comprises: forming a plurality of second solder pillars on the second electronic device; The second sub-blocking wall and the second filler are formed between adjacent second welding columns.

12. The chip flipping method according to claim 11, characterized in that: The forming of the first sub-blocking wall and the first filler between adjacent first welding columns comprises: Forming a first barrier film layer on the first solder pillars by an atomic layer deposition process, wherein the first barrier film layer covers the surfaces and sidewalls of the plurality of first solder pillars and the surface of the first electronic device located around the plurality of first solder pillars; forming a first supporting film layer on the first retaining wall film layer; the distance from the surface of the first supporting film layer away from the first electronic device to the first electronic device is greater than or equal to the distance from the surface of the first retaining wall film layer away from the first electronic device to the first electronic device; The first supporting film layer and the first retaining wall film layer are partially removed to expose the surfaces of the multiple first solder columns facing away from the first electronic device, thereby obtaining the first sub-retaining wall and the third sub-retaining wall. The third sub-retaining wall is located between adjacent first solder columns and covers the surface of the first electronic device.

13. The chip flipping method according to claim 11 or 12, characterized in that: The forming of the second sub-blocking wall and the second filler between adjacent second welding columns comprises: Forming a second barrier film layer on the second solder pillars by an atomic layer deposition process, wherein the second barrier film layer covers the surfaces and sidewalls of the plurality of second solder pillars and the surface of the second electronic device located around the second solder pillars; forming a second supporting film layer on the second retaining wall film layer; the distance from the surface of the second supporting film layer away from the second electronic device to the second electronic device is greater than or equal to the distance from the surface of the second retaining wall film layer away from the second electronic device to the second electronic device; The second supporting film layer and the second retaining wall film layer are partially removed to expose the surfaces of the multiple second solder columns facing away from the second electronic device, thereby obtaining the second sub-retaining wall and the fourth sub-retaining wall. The fourth sub-retaining wall is located between adjacent second solder columns and covers the surface of the second electronic device.

14. The chip flipping method according to any one of claims 10 to 13, characterized in that: The step of aligning the first substrate and the second substrate comprises: The first substrate and the second substrate are aligned by using a thermal compression welding process.

15. An electronic device, characterized in that: It comprises a circuit board, solder balls, and the chip packaging structure according to any one of claims 1 to 9, wherein a second electronic device of the chip packaging structure is soldered on the circuit board through the solder balls.

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