Semiconductor device, manufacturing method thereof, and electronic apparatus
By designing a semiconductor device with concave bit lines, the problem that plane transistors cannot meet the memory density requirements after memory shrinkage is solved, and high conductivity and low contact resistance between the bit lines and the semiconductor column are achieved.
Patent Information
- Application Number
- CN202311465428.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-06
- Publication Date
- 2025-05-06
AI Technical Summary
With the shrinking of the memory, planar transistors are difficult to meet the needs of memory density, and vertical transistors have become a better choice. However, in the prior art, the bit line depth is large, the processing is difficult to process, the bit line shape is irregular, and the contact surface is difficult to achieve heavy doping, resulting in a large contact resistance.
A semiconductor device is designed, which includes an array of semiconductor pillars and a plurality of bit lines. The first sub-bit line extends in the first direction and is disposed near the bottom of the semiconductor pillar near the substrate. The second sub-bit line is disposed on both sides of the semiconductor pillar in the second direction. The shape of the bit line is concave to improve the contact area and conductivity.
By increasing the contact area between the bit line and the semiconductor column, the conductivity between the bit line and the semiconductor column is significantly improved, the contact resistance is reduced, and the manufacturing process is simplified.
Smart Images
Figure CN119943789A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof and an electronic device. Background Art
[0002] Currently, memory technology is developing in the direction of increasing integration and reducing component size. In order to improve integration capabilities, reduce unit area, and manufacture more memory cells in the same chip area, the size of memory devices needs to continue to shrink as technology develops. However, as memory shrinks, more problems will arise. Summary of the invention
[0003] The present application aims at at least one disadvantage of the existing method and proposes a semiconductor device and a manufacturing method thereof and an electronic device.
[0004] In a first aspect, an embodiment of the present application provides a semiconductor device, including:
[0005] Semiconductor pillars arranged in an array on one side of a substrate, wherein the semiconductor pillars arranged in an array are arranged in a plurality of rows at intervals along a first direction and are arranged in a plurality of columns at intervals along a second direction; the first direction and the second direction are at a designed angle and are both parallel to the substrate;
[0006] A plurality of bit lines, each of the bit lines comprises a first sub-bit line and a second sub-bit line connected to each other, the first sub-bit line extends along the first direction and is arranged at the bottom of each row of the semiconductor pillars close to the substrate, and the second sub-bit line is arranged on two side surfaces of the semiconductor pillars along the second direction.
[0007] Optionally, along the second direction, a width of a portion of the semiconductor pillar in contact with the second sub-bit line is smaller than a width of a portion of the semiconductor pillar not in contact with the second sub-bit line.
[0008] Optionally, the material of the semiconductor pillar includes in-situ doped silicon.
[0009] Optionally, it further includes a first dielectric layer, wherein the first dielectric layer is arranged between two adjacent columns of the first sub-bit lines along the second direction;
[0010] Along a direction perpendicular to the substrate, an upper surface of the first dielectric layer is located between an upper surface and a bottom surface of the first sub-bit line, and a bottom surface of the first dielectric layer is lower than a bottom surface of the first sub-bit line.
[0011] In a second aspect, an embodiment of the present application provides an electronic device, including: the semiconductor device of the first aspect.
[0012] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:
[0013] Manufacturing a plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures on one side of the substrate, so that the plurality of first sacrificial structures and the plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction, the first direction and the second direction are at a designed angle and are both parallel to the substrate;
[0014] Manufacturing sacrificial layers on both sides of the semiconductor structure facing the second direction, wherein the sacrificial layers are connected to the first sacrificial structure; protecting a side of the sacrificial layer close to the substrate, removing the remaining sacrificial layer, and obtaining a second sacrificial structure;
[0015] Patterning each of the semiconductor structures to obtain semiconductor pillars arranged in an array and first trenches extending along the second direction and arranged at intervals along the first direction, wherein the first trenches expose the upper surface of the first sacrificial structure;
[0016] While protecting the sidewall of the semiconductor column, removing the first sacrificial structure and the second sacrificial structure through the first trench to obtain a first groove and a second groove;
[0017] Metal is filled in the first groove and the second groove to obtain a first sub-bit line and a second sub-bit line respectively, and the first sub-bit line and the second sub-bit line form a bit line.
[0018] Optionally, after removing the first sacrificial structure and the second sacrificial structure to obtain the first groove and the second groove while protecting the semiconductor column, and before filling the first groove and the second groove with metal, the method further includes:
[0019] The sidewall of the semiconductor column exposed in the second groove is etched to obtain a third groove, so that along the second direction, the width of the third groove is greater than the width of the second groove.
[0020] Optionally, filling the first groove and the second groove with metal includes:
[0021] The third groove is filled with metal to obtain a second sub-bit line.
[0022] Optionally, a plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures are manufactured on one side of the substrate, comprising:
[0023] A first sacrificial layer and a semiconductor layer are sequentially manufactured on one side of the substrate;
[0024] The first sacrificial layer and the semiconductor layer are patterned to obtain the first sacrificial structure formed by the first sacrificial layer, the semiconductor structure formed by the semiconductor layer, and a plurality of second grooves extending along the first direction and arranged at intervals along the second direction, so that the bottom surface of the second groove is lower than the bottom surface of the first sacrificial layer.
[0025] Optionally, after manufacturing a plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures on one side of the substrate, and before manufacturing sacrificial layers on both sides of the first semiconductor structure facing the second direction, the method further includes:
[0026] A first dielectric layer is manufactured in the second trench to obtain a third trench formed by the second trench, wherein the third trench exposes at least a portion of the sidewall of the first sacrificial structure.
[0027] Optionally, protecting a side of the sacrificial layer close to the substrate and removing the remaining sacrificial layer to obtain a second sacrificial structure includes:
[0028] manufacturing a protective layer in the third trench;
[0029] removing a portion of the protection layer to obtain a first protection structure and a fourth trench formed by the protection layer, so that along a direction perpendicular to the substrate, a height of the first protection structure is equal to a height of the second sub-bit line;
[0030] removing the sacrificial layer not covered by the first protective structure to obtain the second sacrificial structure;
[0031] A first isolation layer is fabricated in the fourth trench.
[0032] Optionally, patterning each of the semiconductor structures to obtain semiconductor pillars arranged in an array and first trenches extending along the second direction and arranged at intervals along the first direction comprises:
[0033] The first isolation layer and each of the semiconductor structures are patterned to obtain semiconductor columns arranged in an array, first trenches extending along the second direction and arranged at intervals along the first direction, and a first isolation structure formed by the first isolation layer, wherein the first isolation structure is located between two adjacent semiconductor columns along the second direction.
[0034] Optionally, after metal is filled in the first groove and the second groove to obtain a first sub-bit line and a second sub-bit line respectively, the method further includes:
[0035] Conformally manufacturing a second isolation layer and a second dielectric layer along the first trench, wherein the second dielectric layer fills the first trench;
[0036] The second isolation layer and the second dielectric layer are etched to obtain a second isolation structure formed by the second isolation layer and a second dielectric structure formed by the second dielectric layer, and to obtain a fifth trench.
[0037] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0038] The first sub-bit line is arranged at the bottom of each semiconductor column in each row close to the substrate, and the second sub-bit line is arranged at the two side surfaces of the semiconductor column along the second direction, so that the second sub-bit line is arranged above both sides of the first sub-bit line along the second direction, so that the cross-section of the bit line along the second direction is concave. Compared with the bit line arranged only at the bottom of the semiconductor column in the related art, it is beneficial to increase the contact area between the bit line and the semiconductor column, thereby improving the conductivity between the bit line and the semiconductor column.
[0039] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0041] Figure 1 A schematic diagram of a top view structure of a semiconductor device provided in an embodiment of the present application;
[0042] Figure 2 for Figure 1 Schematic diagram of the cross section at AA;
[0043] Figure 3 for Figure 1 A schematic cross-sectional view at BB in the middle;
[0044] Figure 4 for Figure 1 Another cross-sectional schematic diagram at the middle BB;
[0045] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;
[0046] Figures 6 to 23 A schematic diagram of the structure obtained from each step in a flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
[0047] Description of reference numerals:
[0048] 1- substrate;
[0049] 2- semiconductor column;
[0050] 3-bit line; 31-first sub-bit line; 32-second sub-bit line;
[0051] 41-first sacrificial structure; 411-first sacrificial layer; 42-second sacrificial structure; 421-sacrificial layer;
[0052] 51-semiconductor structure; 511-semiconductor layer; 52-first trench; 53-second trench; 54-third trench; 55-fourth trench; 56-fifth trench;
[0053] 61-first groove; 62-second groove; 63-third groove;
[0054] 71-first dielectric layer; 72-first protective structure; 721-protective layer; 73-second dielectric structure; 731-second dielectric layer; 74-sidewall protective layer;
[0055] 81 - first isolation structure; 811 - first isolation layer; 82 - second isolation structure; 821 - second isolation layer. DETAILED DESCRIPTION
[0056] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0057] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0059] The research and development ideas of this application include: with the miniaturization of memory, planar transistors are difficult to meet the needs of storage density, and vertical transistors become a better choice. In the related art, the bit line in the memory formed by the vertical transistor is located below the vertical transistor. Due to the deep depth of the bit line, the processing is difficult. In addition, when manufacturing the bit line, the isotropic method is used to etch the semiconductor structure, and the shape of the manufactured bit line is irregular and varies greatly; and it is difficult to achieve heavy doping on the contact surface between the bit line and the semiconductor structure, and its contact resistance is also large.
[0060] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0061] The present application embodiment provides a semiconductor device. The structure diagram of the semiconductor device is as follows: Figures 1 to 3 As shown, it includes: semiconductor pillars 2 and a plurality of bit lines 3 arranged in an array on one side of a substrate 1 .
[0062] like Figure 1 As shown, the semiconductor pillars 2 arranged in an array are arranged into multiple rows at intervals along a first direction, and are arranged into multiple columns at intervals along a second direction; the first direction and the second direction are at a designed angle and are both parallel to the substrate 1.
[0063] like Figures 1 to 3 As shown, each bit line 3 includes a first sub-bit line 31 and a second sub-bit line 32 connected to each other. The first sub-bit line 31 extends along the first direction and is arranged at the bottom of each row of semiconductor pillars 2 close to the substrate 1, and the second sub-bit line 32 is arranged on both side surfaces of the semiconductor pillar 2 along the second direction.
[0064] In this embodiment, the first sub-bit line 31 is arranged at the bottom of each semiconductor column 2 in each row close to the substrate 1, and the second sub-bit line 32 is arranged on the two side surfaces of the semiconductor column 2 along the second direction, so the second sub-bit line 32 is arranged above both sides of the first sub-bit line 31 along the second direction, so that the cross-section of the bit line 3 along the second direction is concave. Compared with the bit line only arranged at the bottom of the semiconductor column in the related art, it is beneficial to increase the contact area between the bit line 3 and the semiconductor column 2, thereby improving the conductivity between the bit line 3 and the semiconductor column 2.
[0065] It should be noted that Figure 1 A schematic top view of a semiconductor device provided in an embodiment of the present application; Figure 2 for Figure 1 A schematic cross-sectional view perpendicular to the substrate 1 at AA in the middle; Figure 3 for Figure 1BB is a cross-sectional view perpendicular to the substrate 1. In order to facilitate understanding of the main structure in the top view, Figure 1 The various dielectric layers and isolation layers are omitted.
[0066] Optionally, the first bit line 31 and the second bit line 32 may each include an inner metal layer and an outer metal layer wrapping the inner metal layer. The material of the inner metal layer may be tungsten, and the material of the outer metal layer may be titanium or titanium nitride.
[0067] In this embodiment, the outer metal is made of titanium or titanium nitride, which can improve the connection performance between the first bit line 31 and the second bit line 32 and the semiconductor pillar 2. The inner metal is made of tungsten, which can enhance the conductivity between the bit line 3 and the semiconductor pillar 2.
[0068] Optionally, along the second direction, the width of a portion of the semiconductor pillar 2 that contacts the second sub-bit line 32 is smaller than the width of a portion of the semiconductor pillar 2 that does not contact the second sub-bit line 32 .
[0069] In this embodiment, the width of the portion of the semiconductor column 2 that contacts the second sub-bit line 32 is smaller than the width of the portion of the semiconductor column 2 that does not contact the second sub-bit line 32, thereby increasing the width of the second sub-bit line 32 and further facilitating increasing the conductivity between the second sub-bit line 32 and the semiconductor column 2.
[0070] Optionally, the material of the semiconductor pillar 2 includes in-situ doped silicon.
[0071] In this embodiment, the material of the semiconductor pillar 2 may include in-situ doped single crystal silicon. By performing in-situ doping in the semiconductor pillar 2 , the conductivity of the semiconductor pillar 2 can be improved, thereby reducing the contact resistance between the bit line 3 and the semiconductor pillar 2 .
[0072] Optionally, the in-situ doped element includes an N-type or P-type element. Specifically, the in-situ doped element may be at least one of boron, phosphorus and arsenic.
[0073] Optionally, the material of the semiconductor pillar 2 may further include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO) , titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.
[0074] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the dynamic semiconductor device.
[0075] The above materials only emphasize the element type of the material, not the atomic proportion of the material and the film quality of the material.
[0076] Alternatively, if Figure 3 As shown, the semiconductor device further includes a first dielectric layer 71 , and the first dielectric layer 71 is disposed between two adjacent columns of first sub-bit lines 31 along the second direction.
[0077] Along a direction perpendicular to the substrate 1 , the upper surface of the first dielectric layer 71 is located between the upper surface and the bottom surface of the first sub-bit line 31 , and the bottom surface of the first dielectric layer 71 is lower than the bottom surface of the first sub-bit line 31 .
[0078] In this embodiment, the first dielectric layer 71 cannot completely isolate the adjacent first sub-bit lines 31 , and a portion of the sidewall of the first sub-bit lines 31 needs to be exposed to facilitate connection with the manufactured second sub-bit lines 32 .
[0079] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the semiconductor structure provided by the above embodiment.
[0080] In this embodiment, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.
[0081] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.
[0082] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided by the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided by the embodiments of the present application.
[0083] Based on the same inventive concept, the present application provides a method for manufacturing a semiconductor device. The flowchart of the method is as follows: Figure 5 As shown, the method comprises steps S1 to S5:
[0084] S1: A plurality of first sacrificial structures 41 and a plurality of semiconductor structures 51 disposed above the first sacrificial structures 41 are manufactured on one side of the substrate 1, so that the plurality of first sacrificial structures 41 and the plurality of semiconductor structures 51 extend along a first direction and are arranged at intervals along a second direction, and the first direction and the second direction form a designed angle and are both parallel to the substrate 1.
[0085] Optionally, in step S1, a plurality of first sacrificial structures 41 and a plurality of semiconductor structures 51 disposed above the first sacrificial structures 41 are manufactured on one side of the substrate 1, including:
[0086] A first sacrificial layer 411 and a semiconductor layer 511 are sequentially manufactured on one side of the substrate 1 . Figure 6 and Figure 8 Schematic diagram of the structure obtained after this step.
[0087] The first sacrificial layer 411 and the semiconductor layer 511 are patterned to obtain a first sacrificial structure 41 formed by the first sacrificial layer 411, a semiconductor structure 51 formed by the semiconductor layer 511, and a plurality of second grooves 53 extending along the first direction and arranged at intervals along the second direction, so that the bottom surface of the second groove 53 is lower than the bottom surface of the first sacrificial layer 411. Figure 8 Schematic diagram of the structure obtained after this step.
[0088] In this embodiment, reference Figure 6 and Figure 7 , a first sacrificial layer 411 and a semiconductor layer 511 may be manufactured on one side of the substrate 1 by epitaxy, wherein the thickness of the first sacrificial layer 411 along a direction perpendicular to the substrate 1 is the thickness of the first sub-bit line 31 manufactured subsequently.
[0089] refer to Figure 8, the first sacrificial layer 411 and the semiconductor layer 511 are etched, and the first sacrificial layer 411 is etched through, so that the bottom surface of the second trench 53 is lower than the bottom surface of the first sacrificial layer 411. In this way, two adjacent first sacrificial layers 411 can be isolated to avoid short circuits in the first sub-bit lines 31 manufactured later.
[0090] It should be noted that when epitaxially growing the semiconductor layer 511, the semiconductor layer 511 may be in-situ doped to reduce the Schottky barrier of the contact surface with the subsequently manufactured bit line 3, thereby reducing the contact resistance. The material of the first sacrificial layer 411 and the material of the semiconductor layer 511 need to have a significant etching ratio, which can be beneficial to protecting the semiconductor layer 511 when the first sacrificial layer 411 is subsequently removed. Specifically, the material of the first sacrificial layer 411 may include silicon germanium, and the material of the semiconductor layer 511 may include silicon.
[0091] Optionally, the in-situ doped element includes an N-type or P-type element. Specifically, the in-situ doped element may be at least one of boron, phosphorus and arsenic.
[0092] Optionally, after step S1 and before step S2, the manufacturing method further includes: manufacturing a first dielectric layer 71 in the second trench 53 to obtain a third trench 54 formed by the second trench 53, wherein the third trench 54 exposes at least a portion of the sidewall of the first sacrificial structure 41. The schematic diagram of the structure obtained after this step is as shown in FIG. Fig. 9 shown.
[0093] In this embodiment, the first dielectric layer 71 cannot completely isolate the adjacent first sacrificial structure 41 , and a portion of the sidewall of the first sacrificial structure 41 needs to be exposed to facilitate connection with the subsequently manufactured second sacrificial structure 42 .
[0094] S2: manufacturing sacrificial layers 421 on both sides of the semiconductor structure 51 facing the second direction, wherein the sacrificial layers 421 are connected to the first sacrificial structure 41 ; protecting the side of the sacrificial layer 421 close to the substrate 1 , removing the remaining sacrificial layer 421 , and obtaining the second sacrificial structure 42 .
[0095] In this embodiment, Fig.10 Schematic diagram of the structure obtained after manufacturing sacrificial layers 421 on both sides of the semiconductor structure 51 facing the second direction. The sacrificial layer 421 is manufactured on the surface of the semiconductor structure 51 by epitaxy, and the material of the sacrificial layer 421 needs to have a significant etching ratio with the material of the semiconductor structure 51, so that the semiconductor structure 51 can be protected when the sacrificial layer 421 is removed.
[0096] Optionally, the material of the sacrificial layer 421 may be silicon germanium or silicon nitride.
[0097] Optionally, in step S2, the side of the sacrificial layer 421 close to the substrate 1 is protected, and the remaining sacrificial layer 421 is removed to obtain a second sacrificial structure 42, including:
[0098] A protective layer 721 is manufactured in the third groove 54. The schematic diagram of the structure obtained after this step is as follows Fig.11 shown.
[0099] Part of the protective layer 721 is removed to obtain the fourth trench 55 and the first protective structure 72 formed by the protective layer 721, so that the height of the first protective structure 72 along the direction perpendicular to the substrate 1 is equal to the height of the second sub-bit line 32. The schematic diagram of the structure obtained after this step is as follows: Fig.12 shown.
[0100] The sacrificial layer 421 not covered by the first protective structure 72 is removed to obtain the second sacrificial structure 42 and the fourth trench 55. The schematic diagram of the structure obtained after this step is as follows: Fig.13 shown.
[0101] A first isolation layer 811 is manufactured in the fourth trench 55. The schematic diagram of the structure obtained after this step is as follows Fig.14 and Fig.15 shown.
[0102] In this embodiment, the upper surface of the first protection structure 72 is higher than the upper surface of the first sacrificial structure 41, so that under the protection of the first protection structure 72, the upper surface of the second sacrificial structure 42 is higher than the upper surface of the first sacrificial structure 41. The height of the first protection structure 72 along the direction perpendicular to the substrate 1 is equal to the height of the second sacrificial structure 42, that is, the height of the first protection structure 72 along the direction perpendicular to the substrate 1 defines the height of the second sub-bit line 32 manufactured subsequently.
[0103] Specifically, the material of the protection layer 721 may be silicon dioxide.
[0104] refer to Fig.14 and Fig.15 , a first isolation layer 811 is manufactured in the fourth trench 55 , which can isolate two adjacent semiconductor structures 51 .
[0105] S3 : patterning each semiconductor structure 51 to obtain semiconductor pillars 2 arranged in an array and first trenches 52 extending along the second direction and arranged at intervals along the first direction, wherein the first trenches expose the upper surface of the first sacrificial structure 41 .
[0106] Optionally, in step S3, patterning each semiconductor structure 51 to obtain semiconductor pillars 2 arranged in an array and first trenches 52 extending along the second direction and arranged at intervals along the first direction includes: patterning the first isolation layer 811 and each semiconductor structure 51 to obtain semiconductor pillars 2 arranged in an array, first trenches 52 extending along the second direction and arranged at intervals along the first direction, and a first isolation structure 81 formed by the first isolation layer 811, wherein the first isolation structure 81 is located between two adjacent semiconductor pillars 2 along the second direction. The schematic diagram of the structure obtained after this step is as shown in FIG. Fig.16 and Fig.17 shown.
[0107] In this embodiment, the first isolation layer 811 and each semiconductor structure 51 may be patterned along the second direction by using a self-aligned double patterning (SADP) technique or a self-aligned quadruple patterning (SAQP) technique.
[0108] refer to Fig.16 The first groove 52 exposes the upper surface of the first sacrificial structure 41 , which can facilitate the subsequent removal of the first sacrificial structure 41 and the second sacrificial structure 42 .
[0109] refer to Fig.17 The first isolation structure 81 can isolate two adjacent semiconductor pillars 2 along the second direction, thereby preventing the semiconductor pillars 2 from short-circuiting and improving the working performance of the semiconductor device.
[0110] Optionally, after step S3 and before step S4, the manufacturing method further includes: manufacturing a sidewall protection layer 74 on the sidewalls of each column of semiconductor structures 51 and the sidewalls of the first isolation layer 81 along the first trench 52. The schematic diagram of the structure obtained after this step is as follows: Fig.18 shown.
[0111] In this embodiment, a protective layer material is deposited along the first trench 52, and then the protective layer material at the top of each column of semiconductor structures 51 and the bottom of the first trench 52 is removed by anisotropic etching to obtain a sidewall protective layer 74 located on the sidewalls of each column of semiconductor structures 51 and the sidewalls of the first isolation layer 81. The upper surface of the first sacrificial structure 41 is exposed to facilitate the subsequent removal of the first sacrificial structure 41 and the second sacrificial structure 42. Specifically, the material of the sidewall protective layer 74 may include silicon dioxide.
[0112] S4: While protecting the sidewalls of the semiconductor pillar 2, the first sacrificial structure 41 and the second sacrificial structure 42 are removed through the first trench 52 to obtain the first groove 61 and the second groove 62. The schematic diagram of the structure obtained after this step is as follows: Fig.19 and Fig. 20 shown.
[0113] In this embodiment, under the protection of the sidewall protection layer 74, because the materials of the first sacrificial structure 41 and the second sacrificial structure 42 have a significant etching ratio with the material of the semiconductor column 2, the first sacrificial structure 41 and the second sacrificial structure 42 can be removed by selective etching without damaging the semiconductor column 2, which can help improve the performance of the semiconductor device.
[0114] refer to Fig.19 and Fig. 20 By selectively etching and removing the first sacrificial structure 41 and the second sacrificial structure 42 , a relatively regular first groove 61 and second groove 62 can be obtained.
[0115] Optionally, after step S4 and before step S5, the manufacturing method further includes: etching the sidewall of the semiconductor column 2 exposed in the second groove 62 to obtain a third groove 63, so that along the second direction, the width of the third groove 63 is greater than the width of the second groove 62. The schematic diagram of the structure obtained after this step is as shown in FIG. Fig.21 shown.
[0116] In this embodiment, based on the second groove 62, the side wall of the semiconductor column 2 is etched in the second groove 62 by wet etching, thereby expanding the space of the second groove 62 to obtain the third groove 63, and then the thickness of the second sub-bit line 32 manufactured in the third groove 63 is larger, which can increase the conductivity.
[0117] S5: Filling metal in the first groove 61 and the second groove 62 to obtain the first sub-bit line 31 and the second sub-bit line 32 respectively, and the first sub-bit line 31 and the second sub-bit line 32 form the bit line 3. The schematic diagram of the structure along the AA direction obtained after this step is as follows Fig. 22 As shown; the schematic diagram of the structure along the BB direction is as follows Figure 3 shown.
[0118] In this embodiment, the metal is filled in the first groove 61 and the second groove 62 by ALD (Atomic Layer Deposition), PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or other methods.
[0119] refer to Fig. 22 and Figure 3The first sub-bit line 31 and the second sub-bit line 32 are manufactured after removing the first sacrificial structure 41 and the second sacrificial structure 42, and the obtained first sub-bit line 31 and the second sub-bit line 32 have regular shapes. Under the premise of protecting the semiconductor 2, a relatively regular-shaped bit line 3 can be obtained, which is beneficial to increase the conductive channel of the bit line 3 and reduce the contact resistance between the bit line 3 and the semiconductor pillar 2.
[0120] In addition, the second sub-bit lines 32 are arranged above both sides of the first sub-bit line 31 of the present application along the second direction, so that the cross-section of the bit line 3 along the second direction is concave, that is, a semi-enclosed bit line 3, which is beneficial to improve the conductivity of the bit line 3 and the semiconductor column 2 compared to the bit line arranged only below the semiconductor column in the related art. In addition, by manufacturing the first sacrificial structure 41 and the second sacrificial structure 42, the first sub-bit line 31 and the second sub-bit line 32 with relatively uniform shapes are obtained, which can reduce the difficulty of manufacturing the bit line and facilitate processing.
[0121] Optionally, in step S5, metal is filled in the first groove 61 and the second groove 62, including: filling metal in the third groove 63 to obtain the second sub-bit line 32. The schematic diagram of the structure obtained after this step is as follows: Figure 4 shown.
[0122] In this embodiment, since the width of the third groove 63 along the second direction is greater than that of the second groove 62 , the thickness of the second sub-bit line 32 along the second direction is greater, which can increase the conductivity between the second sub-bit line 32 and the semiconductor pillar 2 .
[0123] Optionally, after step S5, the manufacturing method further includes:
[0124] The second isolation layer 821 and the second dielectric layer 731 are formed along the first trench 52, and the second dielectric layer 731 fills the first trench 52. The schematic diagram of the structure obtained after this step is as follows: Fig.23 shown.
[0125] The second isolation layer 821 and the second dielectric layer 731 are etched to obtain a second isolation structure 82 formed by the second isolation layer 821 and a second dielectric structure 73 formed by the second dielectric layer 731, and to obtain a fifth trench 56. The schematic diagram of the structure obtained after this step is shown in FIG. Figure 2 shown.
[0126] In this embodiment, the material of the second isolation structure 82 may be silicon nitride, and the material of the second dielectric structure 73 may be silicon oxide. The second isolation structure 82 can isolate two adjacent semiconductor pillars 2 along the first direction.
[0127] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0128] 1. In the embodiment of the present application, the first sub-bit line is arranged at the bottom of each semiconductor column in each row close to the substrate, and the second sub-bit line is arranged at the two side surfaces of the semiconductor column along the second direction, so the second sub-bit line is arranged above both sides of the first sub-bit line along the second direction, so that the cross-section of the bit line along the second direction is concave. Compared with the bit line arranged only at the bottom of the semiconductor column in the related art, it is beneficial to increase the contact area between the bit line and the semiconductor column, thereby improving the conductivity between the bit line and the semiconductor column.
[0129] 2. In the embodiment of the present application, by manufacturing the first sacrificial structure and the second sacrificial structure, the first sub-bit line and the second sub-bit line with relatively uniform shapes are obtained, which can reduce the difficulty of manufacturing the bit line and facilitate processing.
[0130] 3. In the embodiment of the present application, a bit line with a relatively regular shape can be obtained while protecting the semiconductor, which is beneficial to increase the conductive channel of the bit line and reduce the contact resistance between the bit line and the semiconductor column.
[0131] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0132] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0133] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0134] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0135] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0136] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.
[0137] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that: include: Semiconductor pillars arranged in an array on one side of the substrate, wherein the semiconductor pillars arranged in the array are arranged in a plurality of rows at intervals along a first direction and are arranged in a plurality of columns at intervals along a second direction; The first direction and the second direction are at a designed angle and are both parallel to the substrate; A plurality of bit lines, each of the bit lines comprises a first sub-bit line and a second sub-bit line connected to each other, the first sub-bit line extends along the first direction and is arranged at the bottom of each row of the semiconductor pillars close to the substrate, and the second sub-bit line is arranged on two side surfaces of the semiconductor pillars along the second direction.
2. The semiconductor device according to claim 1, wherein: Along the second direction, a width of a portion of the semiconductor pillar in contact with the second sub-bit line is smaller than a width of a portion of the semiconductor pillar not in contact with the second sub-bit line.
3. The semiconductor device according to claim 1, wherein: The material of the semiconductor pillar includes in-situ doped silicon.
4. The semiconductor device according to claim 3, characterized in that It also includes a first dielectric layer, wherein the first dielectric layer is disposed between two adjacent columns of the first sub-bit lines along the second direction; Along a direction perpendicular to the substrate, an upper surface of the first dielectric layer is located between an upper surface and a bottom surface of the first sub-bit line, and a bottom surface of the first dielectric layer is lower than a bottom surface of the first sub-bit line.
5. An electronic device, characterized in that: Comprising the semiconductor device as claimed in any one of claims 1 to 4.
6. A method for manufacturing a semiconductor device, characterized in that: include: Manufacturing a plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures on one side of the substrate, so that the plurality of first sacrificial structures and the plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction, the first direction and the second direction are at a designed angle and are both parallel to the substrate; Manufacturing a sacrificial layer on both sides of the semiconductor structure facing the second direction, wherein the sacrificial layer is connected to the first sacrificial structure; Protecting a side of the sacrificial layer close to the substrate, and removing the remaining sacrificial layer to obtain a second sacrificial structure; Patterning each of the semiconductor structures to obtain semiconductor pillars arranged in an array and first trenches extending along the second direction and arranged at intervals along the first direction, wherein the first trenches expose the upper surface of the first sacrificial structure; While protecting the sidewall of the semiconductor column, removing the first sacrificial structure and the second sacrificial structure through the first trench to obtain a first groove and a second groove; Metal is filled in the first groove and the second groove to obtain a first sub-bit line and a second sub-bit line respectively, and the first sub-bit line and the second sub-bit line form a bit line.
7. The manufacturing method according to claim 6, characterized in that: Under the protection of the semiconductor column, after removing the first sacrificial structure and the second sacrificial structure to obtain the first groove and the second groove, and before filling the first groove and the second groove with metal, the method further includes: The sidewall of the semiconductor column exposed in the second groove is etched to obtain a third groove, so that along the second direction, the width of the third groove is greater than the width of the second groove.
8. The manufacturing method according to claim 7, characterized in that: Filling metal in the first groove and the second groove comprises: The third groove is filled with metal to obtain a second sub-bit line.
9. The manufacturing method according to claim 7, characterized in that: A plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures are manufactured on one side of a substrate, comprising: A first sacrificial layer and a semiconductor layer are sequentially manufactured on one side of the substrate; The first sacrificial layer and the semiconductor layer are patterned to obtain the first sacrificial structure formed by the first sacrificial layer, the semiconductor structure formed by the semiconductor layer, and a plurality of second grooves extending along the first direction and arranged at intervals along the second direction, so that the bottom surface of the second groove is lower than the bottom surface of the first sacrificial layer.
10. The manufacturing method according to claim 9, characterized in that: After manufacturing a plurality of first sacrificial structures and a plurality of semiconductor structures disposed above the first sacrificial structures on one side of the substrate, and before manufacturing sacrificial layers on both sides of the semiconductor structures facing the second direction, the method further includes: A first dielectric layer is manufactured in the second trench to obtain a third trench formed by the second trench, wherein the third trench exposes at least a portion of the sidewall of the first sacrificial structure.
11. The manufacturing method according to claim 10, characterized in that: Protecting a side of the sacrificial layer close to the substrate and removing the remaining sacrificial layer to obtain a second sacrificial structure, comprising: manufacturing a protective layer in the third trench; removing a portion of the protection layer to obtain a fourth trench and a first protection structure formed by the protection layer, so that along a direction perpendicular to the substrate, a height of the first protection structure is equal to a height of the second sub-bit line; removing the sacrificial layer not covered by the first protective structure to obtain the second sacrificial structure; A first isolation layer is fabricated in the fourth trench.
12. The manufacturing method according to claim 11, characterized in that: Each of the semiconductor structures is patterned to obtain semiconductor pillars arranged in an array and first trenches extending along the second direction and arranged at intervals along the first direction, including: The first isolation layer and each of the semiconductor structures are patterned to obtain semiconductor columns arranged in an array, first trenches extending along the second direction and arranged at intervals along the first direction, and a first isolation structure formed by the first isolation layer, wherein the first isolation structure is located between two adjacent semiconductor columns along the second direction.
13. The manufacturing method according to claim 6, characterized in that: After metal is filled in the first groove and the second groove to obtain a first sub-bit line and a second sub-bit line respectively, the method further includes: Conformally manufacturing a second isolation layer and a second dielectric layer along the first trench, wherein the second dielectric layer fills the first trench; The second isolation layer and the second dielectric layer are etched to obtain a second isolation structure formed by the second isolation layer and a second dielectric structure formed by the second dielectric layer, and to obtain a fifth trench.