Semiconductor package

Abstract

There is provided a semiconductor package including: a first semiconductor chip including a substrate, an interconnect, an insulating layer on the interconnect, a first lower pad on the interconnect, and a first passivation layer on the first lower pad; and a second semiconductor chip including a second upper pad in contact with the first lower pad, a second passivation layer on the second upper pad and in contact with the first passivation layer, a second lower pad opposite to the second upper pad, and a through electrode, the first semiconductor chip has a first long side extending in a first direction and a first short side extending in a second direction, and the interconnect includes an intermediate conductor and a connection conductor between the intermediate conductor and the first lower pad, the connection conductor having a thickness greater than that of the intermediate conductor, and the number of the connecting conductors in the first direction is greater than the number of the connecting conductors in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0150218 filed in the Korean Intellectual Property Office on November 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor package. Background Art

[0004] Semiconductor devices installed in electronic devices require high performance and large capacity as well as miniaturization. For this reason, semiconductor packages that interconnect vertically stacked semiconductor chips using through electrodes (eg, through silicon vias) are being developed. Summary of the invention

[0005] One or more embodiments provide a semiconductor package with improved reliability.

[0006] According to one aspect of the embodiment, a semiconductor package is provided, comprising: a first semiconductor chip, comprising a substrate, an interconnection on a first surface of the substrate, an insulating layer on at least a portion of the interconnection, a first lower pad on the interconnection, and a first passivation layer on at least a portion of each first lower pad; and a second semiconductor chip, comprising a second upper pad in contact with the first lower pad, a second passivation layer on at least a portion of each second upper pad and in contact with the first passivation layer, a second lower pad opposite to the second upper pad, and a through electrode electrically connecting the second upper pad and the second lower pad, wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction, and a first short side extending in a second direction intersecting the first direction, wherein the interconnection comprises an intermediate conductor, and a connecting conductor between the intermediate conductor and the first lower pad, the thickness of each connecting conductor being greater than the thickness of each intermediate conductor, and wherein the connecting conductors are arranged along the first direction and the second direction, and the number of connecting conductors in the first direction is greater than the number of connecting conductors in the second direction.

[0007] According to another aspect of the embodiment, a semiconductor package is provided, comprising: a first semiconductor chip, comprising an interconnect, a first lower pad on the interconnect, and a first passivation layer on at least a portion of each first lower pad; and a second semiconductor chip, comprising a second upper pad in contact with the first lower pad, a second passivation layer on at least a portion of each second upper pad and in contact with the first passivation layer, a second lower pad opposite to the second upper pad, and a through electrode electrically connecting the second upper pad and the second lower pad, wherein the interconnect comprises an intermediate conductor, and a top conductor between the intermediate conductor and the first lower pad, wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction, and a first short side extending in a second direction intersecting the first direction, and wherein, in a plan view, the top conductor comprises a first side having a first length in the first direction, and a second side having a second length longer than the first length in the second direction.

[0008] According to another aspect of the embodiment, a semiconductor package is provided, comprising: a first semiconductor chip, comprising an interconnect, a first lower pad on the interconnect, and a first passivation layer on at least a portion of each first lower pad; a second semiconductor chip, comprising a second upper pad in contact with the first lower pad, and a second passivation layer in contact with the first passivation layer on at least a portion of each second upper pad; and a molding layer on the second semiconductor chip and adjacent to at least a side surface of the first semiconductor chip, wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction, and a first short side extending in a second direction intersecting the first direction, wherein, in a plan view, the second semiconductor chip has a second long side longer than the first long side in the first direction, and a second short side longer than the first short side in the second direction, wherein the interconnect comprises an intermediate conductor, and a top conductor connecting the intermediate conductor and the first lower pad, and wherein each top conductor has a rectangular shape elongated in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a perspective view of a semiconductor package according to one or more embodiments;

[0011] Figure 2A is along Figure 1 A cross-sectional view taken along line II' of Figure 2B yes Figure 2A A partial enlarged view of area "A";

[0012] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a plan view showing a plan shape of a first top conductor according to one or more other embodiments;

[0013] Figure 4A , Figure 4B and Figure 4C is a diagram showing a manufacturing process of a semiconductor package according to one or more embodiments;

[0014] Figure 5A is a perspective view of a semiconductor package according to one or more embodiments, Figure 5B is along Figure 5A A cross-sectional view taken along line II-II', Figure 5C yes Figure 5B A partial enlarged view of area "B" and Figure 5D is a plan view showing a plan shape of a first top conductor according to one or more embodiments;

[0015] Fig. 6A , Figure 6B and Figure 6C It shows Figure 5B A diagram of a manufacturing process of a semiconductor package shown;

[0016] Fig. 7A is a perspective view of a semiconductor package according to one or more embodiments, and Figure 7B It shows Fig. 7A a plan view of a plan shape of a first top conductor of each of the plurality of first semiconductor chips;

[0017] Fig. 8A is a plan view of a semiconductor package according to one or more embodiments, and Figure 8B is along Fig. 8A A cross-sectional view taken along line III-III';

[0018] Fig. 9 is a cross-sectional view of a semiconductor package according to one or more embodiments;

[0019] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D It shows Fig. 9 A diagram showing a manufacturing process of a semiconductor package; and

[0020] Fig.11A is a cross-sectional view of a semiconductor package according to one or more embodiments, and Fig. 11B yes Fig.11A A partial enlarged view of area "C". DETAILED DESCRIPTION

[0021] Hereinafter, an exemplary embodiment of the present invention will be described as follows with reference to the accompanying drawings. Unless otherwise specified, in this specification, terms such as "upper", "upper surface", "lower", "lower surface", "side" and the like are based on the accompanying drawings and may actually vary depending on the direction in which the components are arranged.

[0022] In addition, ordinals such as "first", "second", "third", etc. can be used as labels for specific elements, step parts, directions, etc. to distinguish various elements, step parts, directions, etc. from each other. Terms that are not described using "first", "second", etc. in the specification can still be referred to as "first" or "second" in the claims. In addition, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) can be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0023] Figure 1 is a perspective view of a semiconductor package 10A according to one or more embodiments.

[0024] Figure 2A is along Figure 1 A cross-sectional view taken along line II of Figure 2B yes Figure 2A A partial enlarged view of area "A" in FIG.

[0025] refer to Figure 1 , Figure 2A and Figure 2B , a semiconductor package 10A according to one or more embodiments may include two or more semiconductor chips facing each other in a vertical direction D3, for example, a first semiconductor chip 100 and a second semiconductor chip 200. Two or more first semiconductor chips 100 may be disposed on the second semiconductor chip 200. The first semiconductor chip 100 and the second semiconductor chip 200 may include a chiplet included in a multi-chip module (MCM). According to example embodiments, the semiconductor package 10A may further include a molding layer 260 that seals at least a portion of each of the semiconductor chips 100 and 200. The molding layer 260 may include, for example, an epoxy molding compound (EMC), but the material of the molding layer 260 is not particularly limited.

[0026] The first semiconductor chip 100 and the second semiconductor chip 200 may be bonded and coupled to each other through metal-to-metal bonding and dielectric-to-dielectric bonding. The semiconductor package 10A may have a bonding surface BS where the first lower pad PD1 and the first passivation layer PSV1 of the first semiconductor chip 100 are bonded and combined with the second upper pad PD22 and the second passivation layer PSV2 of the second semiconductor chip 200.

[0027] In example embodiments, the first semiconductor chip 100 may be a chip that is picked up and placed on the temporarily supported second semiconductor chip 200. Hereinafter, the second semiconductor chip 200 may be referred to as a substrate chip or a substrate wafer.

[0028] Since the first top conductors TC1 of one or more embodiments are spaced apart in the long side (LS1) direction (D1 direction) of the first semiconductor chip 100, the first semiconductor chip 100 can be bent more easily in the long side (LS1) direction. In addition, since the first top conductor TC1 of the example embodiments has a shorter length in the short side (SS1) direction (D2 direction) of the first semiconductor chip 100, the first semiconductor chip 100 can also be bent more easily in the short side SS1 direction. Accordingly, since the first semiconductor chip 100 is attached to the substrate chip 200 in a bent state along the long side (LS1) direction D1 and the short side SS1 direction (D2 direction), the attachment area of ​​the first semiconductor chip 100 and the substrate chip 200 can expand outward from the center of the first semiconductor chip 100. Accordingly, the voids generated during the placement of the first semiconductor chip 100 can be reduced, and the voids (discharged in the extension direction of the top conductor TC1) generated during the hot pressing process and the discharge path of moisture can be significantly reduced (see FIG. 4A to FIG. 4C ). Hereinafter, the long side (LS1) direction refers to a direction in which the long side (LS1) extends, and the short side SS1 direction (D2 direction) refers to a direction in which the short side SS1 extends.

[0029] The first semiconductor chip 100 may include a first substrate 110 , a first circuit layer 120 , a first passivation layer PSV1 , and a plurality of first lower pads PD1 .

[0030] The first substrate 110 may be a semiconductor wafer. For example, the first substrate 110 may include a semiconductor element (e.g., silicon or germanium), or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The first substrate 110 may include a conductive region 112 and an isolation region 111 formed on one surface 110S. The conductive region 112 may be, for example, a well doped with impurities, or a structure doped with impurities. The isolation region 111 is a device isolation structure having a shallow trench isolation (STI) structure, and may include silicon oxide.

[0031] The first circuit layer 120 may be disposed on the first surface 110S of the first substrate 110 in which the conductive region 112 is formed. The first circuit layer 120 may include a separate element ID, a first insulating layer IL1, and a first interconnect IC1. Hereinafter, the first insulating layer IL1 may be referred to as a front insulating layer or an interlayer insulating layer 121. The first interconnect IC1 may be referred to as an interconnect structure 125.

[0032] The individual element ID may be disposed on the first surface 110S of the first substrate 110. The individual element ID may be electrically connected to the conductive region 112. The individual element ID may include, for example, FETs (e.g., planar FETs, FinFETs, etc.), memory devices (e.g., flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM), logic elements (e.g., AND, OR, NOT, etc.), and various active and / or passive elements (e.g., system LSI, CIS, and MEMS).

[0033] The interlayer insulating layer 121 is formed to cover the individual element ID and the interconnection structure 125, and can electrically separate the individual element ID disposed on the first substrate 110. The interlayer insulating layer 121 may include flowable oxide (FOX), eastern burning silazane (TOSZ), undoped silicon glass (USG), borosilicate glass (BSG), phosphorus silicon glass (PSG), borophosphorus silicon glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer 121 surrounding the interconnection structure 125 may be composed of a low dielectric layer. The interlayer insulating layer 121 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process.

[0034] The interconnection structure 125 may be formed as a multilayer structure including a plurality of interconnection patterns and a plurality of vias formed of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W) or a combination thereof. A barrier film (not shown) containing titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN) may be disposed between the interconnection pattern or / and the via and the interlayer insulating layer 121. The interconnection structure 125 may be electrically connected to a separate element ID through an interconnector 123 (e.g., a contact plug). The interconnection structure 125 may include a signal interconnection, a power interconnection, and a ground interconnection.

[0035] The first interconnect IC1 may include a first intermediate conductor MC1 and a first top conductor TC1. Hereinafter, the first top conductor TC1 may be referred to as a connecting conductor. The first intermediate conductor MC1 may be disposed in the first insulating layer IL1. The first intermediate conductor MC1 may be located between the first surface 110S of the first substrate 110 and the first top conductor TC1. The first top conductor TC1 may be located between the first intermediate conductor MC1 and the plurality of first lower pads PD1 in the vertical direction D3. The thickness T1 of the first top conductor TC1 may be greater than the thickness t1 of the first intermediate conductor MC1. The thickness T1 of the first top conductor TC1 may be greater than or equal to about 1 μm, for example, may be in a range from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, from about 1 μm to about 10 μm, from about 1 μm to about 5 μm, etc., but the embodiment is not limited thereto. The first top conductor TC1 may include aluminum (Al) or an alloy thereof, but the embodiment is not limited thereto. According to example embodiments, the first top conductor TC1 may include a material similar to the first intermediate conductor MC1, for example, copper (Cu) or an alloy thereof.

[0036] In one or more embodiments, the first top conductor TC1 may extend longitudinally in the short side (SS1) direction (D2 direction) of the first semiconductor chip 100. For example, on a plane, the first semiconductor chip 100 may include a first long side LS1 extending in the first direction D1, and a first short side SS1 extending in a second direction D2 intersecting the first direction D1, and the first top conductor TC1 may have a rectangular shape elongated in the second direction D2. FIG. 3A to FIG. 3D The planar shape of the first top conductor TC1 is described in more detail.

[0037] A plurality of first lower pads PD1 may be disposed on the first interconnect IC1. The plurality of first lower pads PD1 may be electrically connected to the first interconnect IC1 through a first top conductor TC1. The plurality of first lower pads PD1 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the plurality of first lower pads PD1 may include at least one of copper (Cu) or its alloy. In order to distinguish the positions of the components within the first semiconductor chip 100, the plurality of first lower pads PD1 may be referred to as front pads 132. At least some of the plurality of first lower pads PD1 may be in direct contact with the second upper pad PD22 of the second semiconductor chip 200.

[0038] A plurality of second upper pads PD22 may be disposed on the through electrode 240. The plurality of second upper pads PD22 may be electrically connected to the second interconnect IC2 through the through electrode 240. The plurality of second upper pads PD22 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the plurality of second upper pads PD22 may include at least one of copper (Cu) or its alloy. In order to distinguish the positions of the components within the second semiconductor chip 200, the plurality of second upper pads PD22 may be referred to as rear pads 252. The rear pads 252 may be electrically connected to the second interconnect IC2 and / or the second front pads 232 through the through electrode 240.

[0039] The first passivation layer PSV1 may be formed to surround the side surfaces of the plurality of first lower pads PD1. The first passivation layer PSV1 may form a bonding surface BS provided for dielectric bonding between the plurality of first lower pads PD1. The first passivation layer PSV1 may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN). The first passivation layer PSV1 may be in direct contact with the second passivation layer PSV2 of the second semiconductor chip 200.

[0040] The second passivation layer PSV2 may be formed to surround the side surfaces of the plurality of second upper pads PD22. The second passivation layer PSV2 may form a bonding surface BS provided for dielectric bonding between the plurality of second upper pads PD22. The second passivation layer PSV2 may include, for example, silicon oxide (SiO) and / or silicon carbon nitride (SiCN).

[0041] The second semiconductor chip 200 may be disposed on the first surface of the first semiconductor chip 100. The second semiconductor chip 200 may be disposed in a direction in which the plurality of second upper pads PD22 face the front pads 132 of the first semiconductor chip 100.

[0042] The second semiconductor chip 200 may have a rectangular shape with a long side in the first direction D1 or the second direction D2. For example, the second semiconductor chip 200 may have a second long side LS2 extending in the first direction D1 or the second direction D2. The length of the second long side LS2 of the second semiconductor chip 200 may be greater than the length of the first long side LS1 of the first semiconductor chip 100. For example, the second semiconductor chip 200 may include a second long side LS2 longer than the first long side LS1 of the first semiconductor chip 100 in the first direction D1, and a second short side SS2 longer than the first short side SS1 of the first semiconductor chip 100 in the second direction D2. For example, the second long side LS2 of the second semiconductor chip 200 extends in the first direction D1, and the second short side SS2 may extend in the second direction D2. However, the embodiment is not limited thereto, and for example, the second semiconductor chip 200 may have a square shape.

[0043] The second semiconductor chip 200 may include a second substrate 210, a second circuit layer 220, a second passivation layer PSV2, a plurality of second upper pads PD22, a plurality of through electrodes 240, and a plurality of second lower pads PD21. The second semiconductor chip 200 may include components substantially similar to those of the first semiconductor chip 100, and, for example, may include a second substrate 210, a second circuit layer 220, a second passivation layer PSV2, and a plurality of second lower pads PD21. Therefore, the same or similar components are represented by the same or similar terms and / or reference numerals, and redundant descriptions are omitted below. The second insulating layer IL2 may be referred to as a front insulating layer or an interlayer insulating layer 221, and the second interconnect IC2 may be referred to as an interconnect structure 225.

[0044] The through electrode 240 may penetrate the first surface 210S1 and the second surface 210S2 of the second substrate 210 to electrically connect the second interconnect IC2 and the plurality of second upper pads PD22. The first surface 210S1 of the second substrate 210 may be referred to as a front surface or a rear surface depending on whether the conductive region 112 is formed. For example, the first surface 210S1 of the second substrate 210 in the present embodiment may be referred to as a rear surface, and Fig. 11BThe first surface 210S1 of the second substrate 210 in the example embodiment may be referred to as a front surface. The through electrode 240 may include a via plug 245 and a side barrier layer 241 surrounding its side. The via plug 245 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by an electroplating process, a PVD process, or a CVD process. The side barrier layer 241 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by an electroplating process, a PVD process, or a CVD process. A side insulating film containing an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., a high aspect ratio process (HARP) oxide) may be formed between the side barrier layer 241 and the second substrate 210.

[0045] The through electrode 240 may penetrate the insulating protective layer 213 formed on the first surface 210S1 of the second substrate 210. The insulating protective layer 213 may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 214 such as a polishing stop layer or a barrier layer may be provided on the insulating protective layer 213. For example, the buffer film may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0046] A plurality of second lower pads PD21 may be disposed on the second surface 210S2 of the second substrate 210. The plurality of second lower pads PD21 may be referred to as front pads 232. The plurality of second lower pads PD21 may be connected to a connection bump 236. The connection bump 236 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or an alloy thereof. According to example embodiments, the connection bump 236 may have a combination form of a metal column and a solder ball (see Fig. 9 ).

[0047] In the following, reference will be made to FIG. 3A to FIG. 3D The planar shape of the first top conductor TC1 is described.

[0048] FIG. 3A to FIG. 3D is a plan view showing a plan shape of the first top conductor TC1 according to an exemplary modification.

[0049] refer to Figure 3A, the first semiconductor chip 100a of one or more other embodiments may have a first long side LS1 extending in the first direction D1 and a first short side SS1 extending in the second direction D2. The first top conductor TC1 may be disposed in the circuit region R1 of the first semiconductor chip 100a. The first top conductor TC1 may be formed to facilitate bending of the first semiconductor chip 100a in the first long side (LS1) and the first short side (SS1) directions.

[0050] In a plan view, the first top conductor (which may be referred to as a connecting conductor) TC1 may have a first side s1 extending in a first direction D1, and a second side s2 extending in a second direction D2. The length of the first side s1 may be shorter than the length of the second side s2. The length of the first side s1 may correspond to the line width of the first top conductor TC1. For example, the length of the first side s1 may be in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but is not limited thereto.

[0051] The distribution of the first side s1 relative to the first long side LS1 may be smaller than the distribution of the second side s2 relative to the first short side SS1. On a plane, a first ratio (s1 / LS1) of the sum of the lengths of the first sides (s1) adjacent to the first long side (LS1) of the first semiconductor chip 100a to the length of the first long side (LS1) may be smaller than a second ratio (s2 / SS1) of the sum of the lengths of the second sides (s2) adjacent to the first short side (SS1) to the length of the first short side (SS1).

[0052] The number of the first top conductors TC1 arranged in the first direction D1 may be greater than the number of the first top conductors TC1 arranged in the second direction D2. Figure 3A As shown, the number of the first top conductors TC1 arranged in the first direction D1 is 16, and the number of the first top conductors TC1 arranged in the second direction D2 may be 2 or 8. In addition, the number of first intervals sp1 between the first top conductors TC1 arranged in the first direction D1 may be greater than the number of second intervals sp2 between the first top conductors TC1 arranged in the second direction D2. Figure 3AAs shown, the number of first intervals sp1 arranged in the first direction D1 is 15, and the number of second intervals sp2 arranged in the second direction D2 may be 1 or 7. The first interval sp1 may extend in the second direction D2, and may be an area that does not overlap with the first top conductor TC1. The width of the first interval sp1 in the first direction D1 may be less than or equal to about 50 μm, and, for example, may be in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but the embodiment is not limited thereto.

[0053] The first sides s1 of the first top conductors TC1 may have the same length. According to example embodiments, the second sides s2 of the first top conductors TC1 may include conductors of different lengths. For example, the first top conductor TC1 may include a first group of top conductors TC11 and a second group of top conductors TC12 having second sides s2 of different lengths. The length of the second side s21 of the first group of top conductors TC11 may be greater than the length of the second side s22 of the second group of top conductors TC12. The first group of top conductors TC11 may be connected to a greater number of first lower pads PD1 than the second group of top conductors TC12. For example, the first group of top conductors TC11 may be connected to two or more first lower pads PD1 arranged in the second direction D2, and the second group of top conductors TC12 may be connected to the first lower pads PD1 in a 1:1 manner. According to example embodiments, the first group of top conductors TC11 is connected to at least one of a power interconnect and a ground interconnect, and the second group of top conductors TC12 may be connected to a signal interconnect, but embodiments are not limited thereto.

[0054] refer to Figure 3B , the first semiconductor chip 100b of the example variation may include a first group of top conductors TC11 that are not segmented in the second direction D2. The length of the second side s21 of the first group of top conductors TC11 may exceed 1 / 2 of the length of the first short side SS1 of the first semiconductor chip 100b. The length of the second side s21 of the first group of top conductors TC11 may be greater than the length of the second side s22 of the second group of top conductors TC12. The first group of top conductors TC11 may be connected to a greater number of first lower pads PD1 than the second group of top conductors TC12. For example, the first group of top conductors TC11 may be connected to at least one of a power interconnect and a ground interconnect, but the embodiment is not limited thereto.

[0055] refer to Figure 3C, the first semiconductor chip 100c of the example variation may include a first group of top conductors TC11 segmented twice or more in the second direction D2. The length of the second side s21 of the first group of top conductors TC11 may be less than half the length of the first short side SS1 of the first semiconductor chip 100c. The length of the second side s21 of the first group of top conductors TC11 may be greater than the length of the second side s22 of the second group of top conductors TC12. The first group of top conductors TC11 may be connected to a greater number of first lower pads PD1 than the second group of top conductors TC12. For example, the first group of top conductors TC11 may be connected to at least one of a power interconnect and a ground interconnect, but the embodiment is not limited thereto.

[0056] refer to Figure 3D , the first semiconductor chip 100d of one or more other example embodiments may further include a third group of top conductors TC13. The third group of top conductors TC13 may not be electrically connected to the first lower pad PD1. The length of the second side s23 of the third group of top conductors TC13 may exceed 1 / 2 of the length of the first short side SS1 of the first semiconductor chip 100d. For example, a non-functional pad may be provided on the third group of top conductors TC13. For example, the third group of top conductors TC13 may be connected to at least one of a power interconnect and a ground interconnect, but the embodiment is not limited thereto.

[0057] FIG. 4A to FIG. 4C is a diagram illustrating a manufacturing process of a semiconductor package according to one or more embodiments.

[0058] refer to Figure 4A , the first semiconductor chip 100 is pre-bonded on the base wafer 200W. The base wafer 200W may include a plurality of base chips (eg, Figure 1 In one or more embodiments, the pick-and-place device applies stress to the first semiconductor chip 100 so that the first semiconductor chip 100 can be placed on the base wafer 200W in a bent state along the long side direction and the short side direction. Therefore, the area of ​​the attachment region TR of the first semiconductor chip 100 and the base wafer 200W can be significantly reduced. In this case, pre-bonding refers to a process of simply placing the first semiconductor chip 100 on the base wafer 200W without applying pressure or heat.

[0059] refer to Figure 4B, the first semiconductor chip 100 is attached to the base wafer 200W in a bent state along the long side direction D1 and the short side direction D2, and the attachment region TR of the first semiconductor chip 100 and the base wafer 200 may expand outward from the center of the first semiconductor chip 100. Therefore, a gap generated at the interface between the first semiconductor chip 100 and the base wafer 200W may be reduced.

[0060] refer to Figure 4C , a hot pressing process may be performed to bond the first semiconductor chip 100 and the base wafer 200W. The hot pressing process may be performed in a hot atmosphere in a range of about 100° C. to about 300° C. However, the temperature of the hot atmosphere is not limited to the above range and may vary. The top conductor TC1 of the first semiconductor chip 100 adjacent to the base wafer 200W may form a discharge path dp extending in the short side direction D2 of the first semiconductor chip 100. Therefore, moisture and voids generated during the hot pressing process may be more easily removed, and the quality of the bonding surface may be improved.

[0061] Figure 5A is a perspective view of a semiconductor package 10B according to one or more embodiments, Figure 5B is along Figure 5A A cross-sectional view taken along line II-II of Figure 5C yes Figure 5B A partial enlarged view of area "B" and Figure 5D is a plan view illustrating a plan shape of a first top conductor TC1 according to one or more other example embodiments.

[0062] refer to Figure 5A , Figure 5B and Figure 5C , the semiconductor package 10B of one or more embodiments may have the same Figures 1 to 4C The features described are the same or similar features except that they include a plurality of first semiconductor chips 100A, 100B, 100C, and 100D stacked on the second semiconductor chip 200 in the vertical direction D3 .

[0063] The plurality of first semiconductor chips 100A, 100B, 100C, and 100D may include a top first semiconductor chip 100D, and first semiconductor chips 100A, 100B, and 100C between the top first semiconductor chip 100D and the second semiconductor chip 200. The plurality of first semiconductor chips 100A, 100B, 100C, and 100D may include Figure 2A and Figure 2B100A, 100B, and 100C except the top first semiconductor chip 100D may further include a first through electrode 140, a first upper pad PD12, and a first upper passivation layer PSV12. The upper surface of the top first semiconductor chip 100D may not be covered by the mold layer 260, but may also be covered by the mold layer 260.

[0064] The first through electrode 140 may penetrate the first surface 110S1 and the second surface 110S2 of the first substrate 110 to electrically connect the first interconnect IC1 and the first upper pad PD12. The first through electrode 140 may include a via plug 145 and a side barrier layer 141 surrounding the side of the via plug 145. The via plug 145 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by an electroplating process, a PVD process, or a CVD process. The side barrier layer 141 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by an electroplating process, a PVD process, or a CVD process. A side insulating film (not shown) containing an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP oxide) may be formed between the side barrier layer 141 and the first substrate 110. The first through electrode 140 may penetrate the insulating protection layer 113. The insulating protective layer 113 may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 114 such as a polish stop layer or a barrier layer may be disposed on the insulating protective layer 113 .

[0065] The first upper pad PD12 may be disposed on the first through electrode 140. The first upper pad PD12 may be electrically connected to the first interconnect IC1 through the first through electrode 140. The first upper pad PD12 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Tj), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the first upper pad PD12 may include at least one of copper (Cu) or an alloy thereof. In order to distinguish the position of the components within the first semiconductor chip 100, the first upper pad PD12 may be referred to as a rear pad 152. The first upper pad PD12 may contact the first lower pad PD11 adjacent thereto in the vertical direction D3.

[0066] The first upper passivation layer PSV12 may be formed to surround the side surface of the second upper pad PD12. The first upper passivation layer PSV12 may form a bonding surface provided for dielectric bonding between the second upper pads PD12. The first upper passivation layer PSV12 may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN). The first upper passivation layer PSV12 may contact the first lower passivation layer PSV11 adjacent thereto in the vertical direction D3.

[0067] For example, the second semiconductor chip 200 may be a buffer chip or a control chip including a plurality of logic elements and / or storage elements. The second semiconductor chip 200 may transmit signals from the first semiconductor chips 100A, 100B, 100C, and 100D stacked on the second semiconductor chip 200 to the outside, and may also transmit signals and power from the outside to the first semiconductor chips 100A, 100B, 100C, and 100D. The first semiconductor chips 100A, 100B, 100C, and 100D may be memory chips including volatile memory devices (e.g., DRAM and SRAM) or nonvolatile memory devices (e.g., PRAM, MRAM, FeRAM, or RRAM).

[0068] Reference together Figure 5D , the first semiconductor chip 100e of one or more other example embodiments may include at least one first circuit region R1 extending in the long side direction D1, and a second circuit region R2 adjacent to at least one side of the at least one first circuit region R1 in the short side direction D2. The first top conductor TC1 may include a fourth group of top conductors TC14 disposed in the first circuit region R1, and a fifth group of top conductors TC15 disposed in the second circuit region R2. The width of the first circuit region R1 in the second direction D2 may be greater than the width of the second circuit region R2 in the second direction D2. The length of the second side s24 of the fourth group of top conductors TC14 in the second direction D2 may be greater than the length of the second side s25 of the fifth group of top conductors TC15 in the second direction D2. The first circuit region R1 may include a storage circuit (or storage block) including a storage cell. For example, the first circuit region R1 may include a plurality of storage cells, a plurality of word lines, and a plurality of bit lines. The second circuit region R2 may include an input / output circuit for a storage circuit.

[0069] FIG. 6A to FIG. 6C It shows Figure 5B FIG. 2 is a diagram showing a manufacturing process of the semiconductor package 10B.

[0070] refer to Fig. 6A , the first semiconductor chip 100A may be placed on a base wafer 200W.

[0071] The base wafer 200W may be temporarily supported on the carrier wafer CR by a bonding material layer RL such as glue. The base wafer 200W may include components for a plurality of base chips. For example, the base wafer 200W may include a second substrate 210, a second circuit layer 220, a second lower pad PD21, a second upper pad PD22, a second passivation layer PSV2, a through electrode 240, etc. In addition, a connection bump 236 buried in the bonding material layer RL may be provided on the lower portion of the base wafer 200W.

[0072] The first semiconductor chip 100A may be arranged so that the first lower pad PD11 and the first lower passivation layer PSV11 are in contact with the upper surface of the base wafer 200W. Thereafter, a hot pressing process may be performed to bond the first lower passivation layer PSV11 and the second passivation layer PSV2 and the first lower pad PD11 and the second upper pad PD22. Since the first semiconductor chip 100A is attached to the base wafer 200W in a bent state along the long side direction D1 and the short side direction D2, the void generated at the interface between the first semiconductor chip 100 and the base wafer 200W may be reduced. In addition, in the subsequent hot pressing process, moisture and voids may be more easily discharged in the short side direction D2 of the first semiconductor chip 100.

[0073] refer to Figure 6B , additional first semiconductor chips 100B, 100C, and 100D may be stacked on the first semiconductor chip 100A. Fig. 6A The other first semiconductor chips 100B, 100C and 100D are stacked by the process of FIG. 4A to FIG. 4C The described manner performs the pre-bonding and the thermocompression bonding of the plurality of first semiconductor chips 100A, 100B, 100C, and 100D, and thus a bonding interface of excellent quality can be formed.

[0074] refer to Figure 6C A mold layer 260 is formed to cover the plurality of first semiconductor chips 100A, 100B, 100C, and 100D, and the semiconductor packages may be separated by cutting along scribe lines SL.

[0075] Fig. 7A is a perspective view of a semiconductor package 10C according to one or more embodiments, and Figure 7B It is shown separately Fig. 7A FIG. 1 is a plan view of plan shapes of first top conductors TC1a, TC1b, and TC1c of a plurality of first semiconductor chips 100A, 100B, and 100C.

[0076] refer to Fig. 7A and Figure 7B , the semiconductor package 10C of one or more embodiments may have the same Figures 1 to 5D The features described are the same or similar features except that they include a plurality of first semiconductor chips 100A, 100B, and 100C disposed on the second semiconductor chip 200 in the horizontal directions ( D1 and D2 ).

[0077] The plurality of first semiconductor chips 100A, 100B, and 100C and the second semiconductor chip 200 may be chiplets included in a multi-chip module (MCM). The plurality of first semiconductor chips 100A, 100B, and 100C may include a first chiplet 100A, a second chiplet 100B, and a third chiplet 100C. For example, the first chiplet 100A may be a central processing unit (CPU), the second chiplet 100B may be a graphics processing unit (GPU), the third chiplet 100C may be a field programmable gate array (FPGA) chip, and the second semiconductor chip 200 may be an I / O chip or an active interposer. For example, the second semiconductor chip 200 may include therein I / O elements, DC / DC converters, sensors, test circuits, and the like.

[0078] like Figure 7B As shown, the first chiplet 100A, the second chiplet 100B, and the third chiplet 100C may be bonded on the second semiconductor chip 200. The second semiconductor chip 200 may have a second long side LS2 extending in the first direction, and a second short side SS2 extending in the second direction D2.

[0079] The first chiplet 100A may have a 1-1 long side LS11 extending in the first direction D1, and a 1-1 short side SS11 extending in the second direction D2. The first chiplet 100A may be arranged so that the 1-1 long side LS11 corresponds to the second long side LS2, and the 1-1 short side SS11 corresponds to the second short side SS2. The 1-1 top conductor TC1a of the first chiplet 100A may be formed in a rectangular shape extending in the direction of the 1-1 short side SS11.

[0080] The second chiplet 100B may have a 1-2 long side LS12 extending in the first direction D1, and a 1-2 short side SS12 extending in the second direction D2. The second chiplet 100B may be arranged so that the 1-2 long side LS12 corresponds to the second long side LS2, and the 1-2 short side SS12 corresponds to the second short side SS2. The 1-2 top conductor TC1b of the second chiplet 100B may be formed in a rectangular shape extending in the direction of the 1-2 short side SS12.

[0081] The third chiplet 100C may have a 1-3 long side LS13 extending in the second direction D2, and a 1-3 short side SS13 extending in the first direction D1. The third chiplet 100C may be arranged so that the 1-3 long side LS13 corresponds to the second short side SS2, and the 1-3 short side SS13 corresponds to the second long side LS2. The 1-3 top conductor TC1c of the third chiplet 100C may be formed in a rectangular shape extending in the direction of the 1-3 short side SS13. For example, the 1-3 top conductor TC1c may be formed in a direction intersecting the extending direction of the 1-1 top conductor TC1a and the 1-2 top conductor TC1b.

[0082] Fig. 8A is a plan view of a semiconductor package 10D according to one or more embodiments, and Figure 8B is along Fig. 8A A cross-sectional view taken along line III-III'.

[0083] refer to Fig. 8A and Figure 8B , the semiconductor package 10D of one or more embodiments may include a package substrate 600, an interposer substrate 700, and at least one package structure (PS1, PS2). The at least one package structure (PS1, PS2) may be provided in greater or lesser numbers than shown in the drawings.

[0084] At least one package structure ( PS1 , PS2 ) may include a first package structure PS1 and a second package structure PS2 connected to each other through the interposer substrate 700 .

[0085] The first package structure PS1 may be a high-performance memory device (eg, a high bandwidth memory (HBM) or a hybrid memory cube (HMC)). For example, the first package structure PS1 may be a memory device having the same FIG. 5A to FIG. 6C The first package structure PS1 may be connected to the interposer substrate 700 through metal bumps BP.

[0086] The second package structure PS2 may be a bare chip or a packaged chip on which a logic circuit or a storage circuit is formed. Fig. 7A and Figure 7B The second package structure PS2 may be connected to the interposer substrate 700 through the metal bumps BP. The second package structure PS2 may include semiconductor chips of different types from the first package structure PS1. For example, the first package structure PS1 may include a logic chip, and the second package structure PS2 may include a memory chip.

[0087] The package substrate 600 may be a support substrate on which the interposer substrate 700 is mounted, and may be a substrate for semiconductor packaging, including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape interconnect substrate, etc. The package substrate 600 may include a lower pad 612, an upper pad 611, and an interconnect circuit 613. External connection bumps 620 connected to the lower pads 612 may be provided on the lower surface of the package substrate 600. The external connection bumps 620 may include, for example, solder balls.

[0088] The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower terminal 705, an interconnection structure 710, a conductive bump 720, and a via 730. The first package structure PS1 and the second package structure PS2 may be electrically connected to each other via the interposer substrate 700.

[0089] The substrate 701 may be formed of any one of, for example, a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. For example, when the substrate 701 is a silicon substrate, the interposer substrate 700 may be referred to as a silicon interposer. Unlike shown in the drawings, when the substrate 701 is an organic substrate, the interposer substrate 700 may be referred to as a panel interposer.

[0090] The lower terminal 705 may be connected to the through-hole 730. The lower terminal 705 may be electrically connected to the package substrate 600 through the conductive bump 720.

[0091] The interconnection structure 710 is disposed on the upper surface of the substrate 701 and may include an interlayer insulating layer 711 and a single-layer or multi-layer interconnection 712. When the interconnection structure 710 has a multi-layer interconnection structure, interconnection patterns of different layers may be connected to each other through contact vias. An upper terminal 704 connected to the interconnection structure 710 may be disposed on the interconnection structure 710.

[0092] The via 730 may extend from the top to the bottom of the substrate 701 and penetrate the substrate 701. In an example, the via 730 extends to the inside of the interconnect structure 710 and may also be electrically connected to the interconnect 712. In the case where the substrate 701 is silicon, the via 730 may be referred to as a TSV.

[0093] Fig. 9 is a cross-sectional view of a semiconductor package 10E according to one or more embodiments.

[0094] refer to Fig. 9 , the semiconductor package 10E of one or more embodiments may have the same Figures 1 to 4C The features described are the same or similar features, except that both the first semiconductor chip 100 and the second semiconductor chip 200 include top conductors extending in the respective short-side directions D2 .

[0095] The connection bump 236 may include a column portion PL and a solder portion SD. The column portion PL includes copper (Cu) or an alloy of copper (Cu), and the solder portion SD may include a low melting point metal, such as tin (Sn) or an alloy containing tin (Sn) (e.g., Sn-Ag or Sn-Ag-Cu). For example, the connection bump 236 may include only the column portion PL, or only the solder portion (SD).

[0096] The semiconductor package 10E of one or more embodiments may include a first mold layer 261 and a second mold layer 262. The first mold layer 261 and the second mold layer 262 may be layers of an inorganic material such as silicon oxide (SiO), silicon nitride (SiN), or silicon carbonitride (SiCN), and may also be polymer resin layers according to one or more embodiments.

[0097] The first mold layer 261 may cover the first surface 210S1 and side surfaces of the second substrate 210, and a portion of the side surface (referring to a portion protruding onto the first surface 210S1) of each second through electrode 240. The second upper pad PD22 and the second upper passivation layer PSV22 may be disposed on the first mold layer 261. The second mold layer 262 may cover the side surfaces and the upper surface of the first semiconductor chip 100 on the second upper passivation layer PSV22.

[0098] As will be described later, the first and second semiconductor chips 100 and 200 of the present embodiment are bent during a manufacturing process and pre-bonded, and thus may include top conductors contacting the first and second lower pads PD1 and PD21 , respectively, and extending in the short-side direction D2 .

[0099] FIG. 10A to FIG. 10D It shows Fig. 9 FIG. 1 is a diagram showing a manufacturing process of a semiconductor package 10E.

[0100] refer to Fig. 10A , the second preliminary semiconductor chip 200 ′ may be disposed on the temporary bonding layer TML of the recombinant carrier RECR.

[0101] To illustrate Fig. 9 The manufacturing process of the semiconductor package 10E shown in the figure only shows one unit of the recombinant carrier RECR. For example, the recombinant carrier RECR can be a 6-inch, 8-inch, 12-inch silicon wafer containing dozens or more of the units shown in the figure. In the following, for ease of explanation, the manufacturing process of the semiconductor package will be described focusing on one unit shown in the figure. The temporary bonding layer TML may include silicon oxide (SiO). The temporary bonding layer TML may be formed using a PVD or CVD process.

[0102] The second preliminary semiconductor chip 200' may be a known good die (KGD) for which testing has been completed. The second preliminary semiconductor chip 200' may include a second preliminary substrate 210', a second preliminary through electrode 240', a second circuit layer 220, a second lower pad PD21, and a second lower passivation layer PSV21. The second preliminary substrate 210' may be a silicon die whose thickness is not adjusted by a back grinding process. The second preliminary semiconductor chip 200' may be arranged so that the second lower pad PD21 and the second lower passivation layer PSV21 are in contact with the temporary bonding layer TML. Thereafter, a hot pressing process may be performed to bond the second lower passivation layer PSV21 and the temporary bonding layer TML. Since the second preliminary semiconductor chip 200' is attached in a bent state along the long side direction D1 and the short side direction D2, the void generated at the interface with the temporary bonding layer TML may be reduced. In addition, in the subsequent hot pressing process, moisture and voids may be more easily discharged in the short side direction D2 of the second preliminary semiconductor chip 200'.

[0103] Thereafter, a back grinding process and an etch-back process are applied to the second preliminary substrate 210 ′, so that the thickness of the second preliminary substrate 210 ′ is reduced and the second preliminary through electrode 240 ′ may protrude to one surface of the second substrate 210 .

[0104] refer to Fig. 10B , a first mold layer 261, a second upper passivation layer PSV22, and a second upper pad PD22 may be formed. The first mold layer 261 may be formed to completely cover the second semiconductor chip 200 and the second through electrode 240. Thereafter, a CMP process is applied to the first mold layer 261 so that the second through electrode 240 may be exposed to the upper surface of the first mold layer 261.

[0105] The second upper passivation layer PSV22 includes silicon oxide (SiO) and can be formed using a PVD or CVD process. The second upper pad PD22 can be formed in the second upper passivation layer PSV22 patterned using a photosensitive material layer and a photolithography process. The second upper pad PD22 includes a metal such as copper (Cu), titanium (Ti), etc., and can be formed by an electroplating process. The second upper passivation layer PSV22 and the second upper pad PD22 can be planarized by a CMP process.

[0106] refer to Fig. 10C, the first semiconductor chip 100 may be placed on the first mold layer 261. The first semiconductor chip 100 may be a tested KGD. The first semiconductor chip 100 may include a first substrate 110, a first circuit layer 120, a first passivation layer PSV1, and a first lower pad PD1. The first semiconductor chip 100 may be placed so that the first lower pad PD1 is aligned with the second upper pad PD22. Thereafter, a hot pressing process may be performed to bond the first passivation layer PSV1 and the second upper passivation layer PSV22. Since the first semiconductor chip 100 is attached in a bent state along the long side direction D1 and the short side direction D2, the gap generated at the interface with the second upper passivation layer PSV22 may be reduced. In addition, in the subsequent hot pressing process, moisture and gaps may be more easily discharged in the short side direction D2 of the first semiconductor chip 100.

[0107] refer to Fig. 10D , a second mold layer 262 may be formed. The second mold layer 262 may be formed to cover the upper surface of the first semiconductor chip 100. The second mold layer 262 may include, for example, silicon oxide (SiO), and may be formed using a PVD or CVD process. Then, the reconstructed carrier RECR and the temporary bonding layer TML may be removed. The reconstructed carrier RECR and the temporary bonding layer TML may be removed using a combination of grinding and etching processes. For example, a portion of the temporary bonding layer TML may be retained and used as a protective layer covering the second lower pad PD21. Thereafter, the unit package may be separated by forming a connection bump on the second lower pad PD21 and then performing a cutting process.

[0108] Fig.11A is a cross-sectional view of a semiconductor package 10F according to one or more embodiments, and Fig. 11B yes Fig.11A A partial enlarged view of area "C".

[0109] refer to Fig.11A and Fig. 11B , the semiconductor package 10F of one or more embodiments may have the same Figures 1 to 4C The features described are the same or similar features except that the second circuit layer 220 is disposed on the first surface 210S1 of the second substrate 210. In the present embodiment, the first surface 210S1 of the second substrate 210 may be referred to as a front surface, and the second surface 210S2 of the second substrate 210 may be referred to as a rear surface.

[0110] The second circuit layer 220 may be disposed on the first surface 210S1 of the second substrate 210 on which the conductive region 112 is formed. The second circuit layer 220 may include a separate element ID, a second insulating layer IL2, and a second interconnect IC2. Hereinafter, the second insulating layer IL2 may be referred to as a front insulating layer or an interlayer insulating layer 221. The second interconnect IC2 may be referred to as an interconnect structure 225.

[0111] The second interconnect IC2 may include a second intermediate conductor MC2 and a second top conductor TC2. The second top conductor TC2 may be referred to as a connecting conductor. The second intermediate conductor MC2 may be disposed in the second insulating layer IL2. The second intermediate conductor MC2 may be located between the first surface 210S1 of the second substrate 210 and the second top conductor TC2. The thickness T2 of the second top conductor TC2 may be greater than the thickness t2 of the second intermediate conductor MC2. The thickness T2 of the second top conductor TC2 may be greater than or equal to about 1 μm, for example, in a range from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, from about 1 μm to about 10 μm, from about 1 μm to about 5 μm, etc., but the embodiment is not limited thereto. The second top conductor TC2 may include aluminum (Al) or an alloy thereof, but the embodiment is not limited thereto.

[0112] In one or more embodiments, the second top conductor TC2 may extend longitudinally in the long side direction (D1 direction) of the second semiconductor chip 200. For example, when the second semiconductor chip 200 is a substrate wafer or a substrate chip, the second top conductor TC2 may be formed into a long rectangular shape in the long side direction D1 of the second semiconductor chip 200. On a plane, the second top conductor TC2 may intersect with the first top conductor TC1, but the embodiment is not limited thereto. According to the design of the second semiconductor chip 200, the second top conductor TC2 may be formed into a long rectangular shape in the short side direction D2 of the second semiconductor chip 200.

[0113] As described above, according to example embodiments, since a top conductor of a semiconductor chip attached to a substrate chip extends in a short side direction of the semiconductor chip, a semiconductor package having improved bonding surface quality and reliability may be provided.

[0114] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims and their equivalents.

Claims

1. A semiconductor package, comprising: A first semiconductor chip comprising a substrate, an interconnect on a first surface of the substrate, an insulating layer on at least a portion of the interconnect, a first lower pad on the interconnect, and a first passivation layer on at least a portion of each of the first lower pads; as well as a second semiconductor chip including a second upper pad in contact with the first lower pad, a second passivation layer on at least a portion of each of the second upper pads and in contact with the first passivation layer, a second lower pad opposite to the second upper pad, and a through electrode electrically connecting the second upper pad and the second lower pad, Wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction, and a first short side extending in a second direction intersecting the first direction, wherein the interconnect comprises an intermediate conductor and a connecting conductor between the intermediate conductor and the first lower pad, the thickness of each of the connecting conductors being greater than the thickness of each of the intermediate conductors, and The connecting conductors are arranged along the first direction and the second direction, and the number of the connecting conductors in the first direction is greater than the number of the connecting conductors in the second direction.

2. The semiconductor package according to claim 1, wherein Each of the connecting conductors has a first side extending in the first direction and a second side extending in the second direction, and The length of each of the first sides is shorter than the length of each of the second sides.

3. The semiconductor package according to claim 2, wherein: A first ratio of a sum of lengths of the first sides adjacent to the first long side to the length of the first long side is lower than a second ratio of a sum of lengths of the second sides adjacent to the first short side to the length of the first short side.

4. The semiconductor package according to claim 2, wherein: The length of the first side ranges from 1 μm to 50 μm.

5. The semiconductor package according to claim 1, wherein The number of first intervals between the connection conductors in the first direction is greater than the number of second intervals between the connection conductors in the second direction.

6. The semiconductor package according to claim 5, wherein: The first space does not overlap with the connecting conductor in the second direction.

7. The semiconductor package according to claim 1, wherein: The thickness of the connecting conductor is greater than or equal to 1 μm.

8. The semiconductor package according to claim 1, wherein The connection conductors include a first group of connection conductors connected to two or more of the first lower pads disposed in the second direction.

9. The semiconductor package according to claim 1, wherein: The connection conductors include a second group of connection conductors connected to the first lower pad in a 1:1 manner.

10. The semiconductor package according to claim 1, wherein The connection conductors include a third group of connection conductors spaced apart from the first lower pad.

11. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a plurality of first semiconductor chips stacked on the second semiconductor chip in a vertical direction, and Among them, at least some of the multiple first semiconductor chips are on the second surface of the substrate and include a first upper pad in contact with the first lower pad in the vertical direction, an upper passivation layer on at least a portion of each of the first upper pads and in contact with the first passivation layer in the vertical direction, and a through electrode that penetrates the substrate and electrically connects the first upper pad to the first lower pad.

12. A semiconductor package, comprising: a first semiconductor chip comprising an interconnect, first lower pads on the interconnect, and a first passivation layer on at least a portion of each of the first lower pads; as well as a second semiconductor chip including a second upper pad in contact with the first lower pad, a second passivation layer on at least a portion of each of the second upper pads and in contact with the first passivation layer, a second lower pad opposite to the second upper pad, and a through electrode electrically connecting the second upper pad and the second lower pad, wherein the interconnect comprises an intermediate conductor and a top conductor between the intermediate conductor and the first lower pad, wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction and a first short side extending in a second direction intersecting the first direction, and In a plan view, the top conductor includes a first side having a first length in the first direction, and a second side having a second length longer than the first length in the second direction.

13. The semiconductor package according to claim 12, wherein: The first lengths of the first sides are equal to each other.

14. The semiconductor package according to claim 12, wherein: The top conductors include a first set of top conductors and a second set of top conductors, and The length of the second side of the first group of top conductors is different from the length of the second side of the second group of top conductors.

15. The semiconductor package according to claim 14, wherein: The length of the second side of the first set of top conductors is greater than the length of the second side of the second set of top conductors.

16. The semiconductor package according to claim 15, wherein: The intermediate conductor includes a signal interconnect, a power interconnect and a ground interconnect, wherein the first set of top conductors are connected to at least one of the power interconnect and the ground interconnect, and Wherein, the second set of top conductors are connected to the signal interconnect.

17. A semiconductor package, comprising: a first semiconductor chip comprising an interconnect, first lower pads on the interconnect, and a first passivation layer on at least a portion of each of the first lower pads; a second semiconductor chip including second upper pads contacting the first lower pads, and a second passivation layer on at least a portion of each of the second upper pads and contacting the first passivation layer; as well as a molding layer on the second semiconductor chip and adjacent to at least a side surface of the first semiconductor chip, Wherein, in a plan view, the first semiconductor chip has a first long side extending in a first direction, and a first short side extending in a second direction intersecting the first direction, wherein, in a plan view, the second semiconductor chip has a second long side longer than the first long side in the first direction, and a second short side longer than the first short side in the second direction, The interconnector comprises a middle conductor and a top conductor connecting the middle conductor and the first lower pad, and Wherein, each of the top conductors has a rectangular shape elongated in the second direction.

18. The semiconductor package according to claim 17, wherein: In a plan view, the first semiconductor chip includes a first circuit region extending in the first direction, and a second circuit region adjacent to at least one side of the first circuit region in the second direction, and The top conductors include a first group of top conductors in the first circuit region and a second group of top conductors in the second circuit region.

19. The semiconductor package according to claim 18, wherein: The length of each of the first set of top conductors in the second direction is greater than the length of each of the second set of top conductors in the second direction.

20. The semiconductor package according to claim 18, wherein The first circuit area includes a storage circuit, and The second circuit area includes an input / output circuit for the storage circuit.

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