Semiconductor device including bumps and manufacturing method thereof

Abstract

The invention relates to a semiconductor device including a bump and a method of manufacturing the same. The semiconductor device may include: a first pillar and a second pillar formed over a substrate; a first solder layer configured to cover a first surface of the first pillar; and a second solder layer configured to cover a second surface of the second pillar. The first surface of the first pillar has a height lower than a height of the second surface of the second pillar. The second solder layer has a thickness smaller than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packaging technology, and more particularly to a semiconductor device including a bump and a method for manufacturing the same. Background Art

[0002] For semiconductor devices or technologies for packaging semiconductor devices, a conductive bump structure is used. In order to electrically connect an integrated circuit integrated in a semiconductor substrate to a device outside the semiconductor device, a semiconductor device is known in which a conductive bump is formed in a connection pad of the semiconductor substrate. Because it is advantageous for semiconductor devices to operate at high speeds and have a smaller form factor, for many semiconductor devices, an electrical connection method through a bump is used. The conductive bump structure can connect a semiconductor device and a packaging substrate or can connect a semiconductor device and another semiconductor device. Summary of the invention

[0003] In an embodiment, a semiconductor device may include: a first column and a second column formed above a substrate; a first solder layer configured to cover a first surface of the first column; and a second solder layer configured to cover a second surface of the second column. The first surface of the first column has a height lower than a height of a second surface of the second column, and the second solder layer has a thickness smaller than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface, wherein the first surface of the first column is a surface of the first column farthest from a surface of the substrate, and the second surface of the second column is a surface of the second column farthest from the surface of the substrate.

[0004] In an embodiment, a semiconductor device may include: a first substrate and a second substrate disposed above the first substrate and including a first conductive trace and a second conductive trace; a first column and a second column disposed between the first substrate and the second substrate; a first solder layer configured to cover a first surface of the first column; and a second solder layer configured to cover a second surface of the second column. The first surface of the first column may be disposed at a height lower than a height of a second surface of the second column. The first surface of the first column may be a surface of the first column that is farthest from a surface of the substrate, and the second surface of the second column may be a surface of the second column that is farthest from a surface of the substrate. The first solder layer may be connected to the first conductive trace. The second solder layer may be connected to the second conductive trace. The distance between the first surface and the first conductive trace may be greater than the distance between the second surface and the second conductive trace.

[0005] In an embodiment, a method for manufacturing a semiconductor device may include: forming a first column and a second column above a substrate; forming a first resist pattern including a first opening exposing a first surface of the first column and including a second opening exposing a second surface of the second column and having a width smaller than a width of the first opening, wherein the first surface of the first column is a surface of the first column farthest from a surface of the substrate, and the second surface of the second column is a surface of the second column farthest from the surface of the substrate; forming a first solder pattern within the first opening and forming a second solder pattern within the second opening; removing the first resist pattern; and forming a first solder layer by reflowing the first solder pattern, and forming a second solder layer by reflowing the second solder pattern.

[0006] A semiconductor device includes: a first column and a second column formed above a substrate; a first solder layer configured to cover a first surface of the first column; and a second solder layer configured to cover a second surface of the second column. The second solder layer may have a thickness smaller than that of the first solder layer to compensate for the difference between the height of the second surface and the height of the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 4 is a cross-sectional view illustrating a semiconductor device according to an embodiment.

[0008] Figures 5 to 13 is a cross-sectional view illustrating a semiconductor device formed using a method of manufacturing a semiconductor device according to an embodiment.

[0009] Fig.14 is a cross-sectional view illustrating a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0010] The terms used in the description of the present disclosure are selected in consideration of the functions in the proposed embodiments, and the meanings of these terms may differ depending on the intention of the user, operator, or practice in the technical field. If a term is specifically defined in this specification, the meaning of the term is included in the definition of the term, and if a term is not specifically defined, the meaning of the term may be the meaning generally recognized by those skilled in the art.

[0011] In the description of the present disclosure, terms such as "first", "second", "bottom", "top", "topmost", "side", and "lower" are used to distinguish components from each other for the convenience of description, and are not intended to limit the components themselves or indicate a specific order or relationship. In the description of the present disclosure, terms such as "upper or above" or "lower or below" indicate relative positional relationships, and are not limited to specific cases where one component is in direct contact with another component or a third component is located between the two components. The same explanation can be applied to other expressions describing the positional relationship between components.

[0012] Throughout this specification, the same reference numerals represent the same or similar components. Although not mentioned or described in the corresponding drawings, the same reference numerals or similar reference numerals may be described with reference to other drawings. In addition, although a reference numeral is not indicated in a portion of a corresponding drawing, the reference numeral may be described with reference to another drawing. Cross-hatching throughout the drawings illustrates corresponding or similar areas between the drawings, rather than indicating the material of these areas.

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor device 10 according to an embodiment. Figure 1 , the semiconductor device 10 includes a substrate 100, a first column 210A, a second column 210B, a first solder layer 220A, and a second solder layer 220B. The substrate 100 may be a semiconductor chip or a semiconductor wafer. The substrate 100 may include a semiconductor substrate integrated with an integrated circuit (not shown). The integrated circuit may include electronic components such as transistors and interconnect wiring structures connecting the electronic components. The integrated circuit may include a memory device such as a DRAM or a NAND flash memory.

[0014] The substrate 100 includes a conductive pad 110 located at a surface 100S. The conductive pad 110 may include a metal layer. The metal layer may include aluminum (Al). The conductive pad 110 may be electrically connected to an integrated circuit. The conductive pad 110 may be a connection terminal that electrically connects the integrated circuit of the semiconductor device 10 to an external device. The conductive pad 110 may be an input / output (I / O) terminal. The semiconductor device 10 includes a dielectric layer 130 that covers the surface 100S of the substrate 100 and exposes the conductive pad 110. The dielectric layer 130 may be a passivation layer or a protective layer. The dielectric layer 130 may include a polymer layer. The polymer layer may include a polyimide such as polyimide isoindolequinoline (PIQ).

[0015] The first column 210A and the second column 210B are spaced apart from each other and are arranged above the substrate 100. The first column 210A is electrically connected to the conductive pad 110 of the substrate 100. The first bottom layer 230A is arranged between the first column 210A and the conductive pad 110. The second column 210B is connected to the dielectric layer 130. The second bottom layer 230B is arranged between the second column 210B and the dielectric layer 130. The first bottom layer 230A and the second bottom layer 230B can be metal layers with substantially the same thickness. The first bottom layer 230A and the second bottom layer 230B can each be an under bump metallization (UBM) layer. The second column 210B and the second bottom layer 230B overlap with the dielectric layer 130. The second column 210B is electrically isolated from the substrate 100 by the dielectric layer 130. The second column 210B is electrically isolated from the integrated circuit of the substrate 100 by the dielectric layer 130.

[0016] The first column 210A and the second column 210B may include substantially the same conductive material. The first column 210A and the second column 210B may include the same material formed simultaneously by a single process. The first column 210A and the second column 210B may each include a metal material formed by a plating process. The first column 210A and the second column 210B may each be a metal layer including copper (Cu). The first column 210A and the second column 210B may each have a cylindrical shape. In another embodiment, the first column 210A and the second column 210B may each have a different shape such as a square column.

[0017] The first solder layer 220A covers the first top surface 210AS of the first column 210A. The second solder layer 220B covers the second top surface 210BS of the second column 210B. For example, the first top surface 210AS of the first column 210A is the surface of the first column 210A that is farthest from the surface 100S of the substrate 100, and the second top surface 210BS of the second column 210B is the surface of the second column 210B that is farthest from the surface 100S of the substrate 100. The first solder layer 220A and the second solder layer 220B may include the same solder material. The solder material may include tin (Sn) and / or silver (Ag). The first solder layer 220A and the second solder layer 220B may be formed simultaneously by a single process, and may each include a material having the same composition. The first solder layer 220A and the second solder layer 220B may each include a metal material formed by a plating process.

[0018] The first solder layer 220A is thicker than the second solder layer 220B. The first solder layer 220A has a first thickness T1. The second solder layer 220B has a second thickness T2 that is less than the first thickness T1. The thickness of the first solder layer 220A (first thickness T1) represents the distance from the first top surface 210AS of the first column 210A to the topmost end 220AE of the first solder layer 220A. The thickness of the second solder layer 220B (second thickness T2) represents the distance from the second top surface 210BS of the second column 210B to the topmost end 220BE of the second solder layer 220B. For example, the topmost end 220AE of the first solder layer 220A is the end of the first solder layer 220A that is farthest from the first column 210A, and the topmost end 220BE of the second solder layer 220B is the end of the second solder layer 220B that is farthest from the second column 210B.

[0019] The first bump 200A includes a first column 210A and a first solder layer 220A. The first bump 200A may also include a first bottom layer 230A. The second bump 200B includes a second column 210B and a second solder layer 220B. The second bump 200B may also include a second bottom layer 230B. The second bump 200B overlaps with the dielectric layer 130 and is coupled or connected to the dielectric layer 130. Because the second bump 200B is electrically isolated from the substrate 100 and the integrated circuit of the substrate 100 by the dielectric layer 130, the second bump 200B is a dummy bump. The dummy bump is not electrically connected to the substrate 100 or the integrated circuit, but has a bump-shaped element.

[0020] The first column 210A has a first lateral width W1 and a third longitudinal thickness T3. The second column 210B has a second lateral width W2 and a fourth longitudinal thickness T4. When the first column 210A and the second column 210B are each cylindrical, the first lateral width W1 and the second lateral width W2 represent the diameters of the first column 210A and the second column 210B, respectively. The first column 210A and the second column 210B may have substantially the same features. The first lateral width W1 of the first column 210A and the second lateral width W2 of the second column 210B may have substantially the same measurement. The third thickness T3 of the first column 210A and the fourth thickness T4 of the second column 210B may have substantially the same size. In another embodiment, the size of the first column 210A and the second column 210B is not limited to the aforementioned size.

[0021] The first top surface 210AS of the first pillar 210A is disposed at a height H1 lower than the height H2 of the second top surface 210BS of the second pillar 210B. The first pillar 210A is disposed to overlap the conductive pad 110, while the second pillar 210B is disposed to overlap the dielectric layer 130. Unlike the second pillar 210B, the first pillar 210A is disposed in an opening of the dielectric layer 130. Therefore, although the third thickness T3 of the first pillar 210A and the fourth thickness T4 of the second pillar 210B are substantially the same, the second top surface 210BS of the second pillar 210B may be disposed higher than the first top surface 210AS of the first pillar 210A by the thickness of the dielectric layer 130. Due to the thickness of the dielectric layer 130, the second top surface 210BS of the second pillar 210B is disposed farther from the substrate 100 than the first top surface 210AS of the first pillar 210A.

[0022] The first height H1 of the first top surface 210AS of the first pillar 210A is the distance from the surface 100S of the substrate 100 to the first top surface 210AS. The second height H2 of the second top surface 210BS of the second pillar 210B is the distance from the surface 100S of the substrate 100 to the second top surface 210BS. The first height H1 of the first top surface 210AS of the first pillar 210A may be less than the second height H2 of the second top surface 210BS of the second pillar 210B. When the first solder layer 220A has a thickness T1 different from the thickness T2 of the second solder layer 220B, the difference HD between the height H1 of the first top surface 210AS of the first pillar 210A and the height H2 of the second top surface 210BS of the second pillar 210B may be compensated. Therefore, the third height HB1 of the first topmost end 220AE of the first solder layer 220A and the fourth height HB2 of the second topmost end 220BE of the second solder layer 220B are substantially the same.

[0023] The third height HB1 of the first topmost end 220AE of the first solder layer 220A is the distance from the surface 100S of the substrate 100 to the first topmost end 220AE. The third height HB1 of the first topmost end 220AE of the first solder layer 220A is the height of the first bump 200A. The fourth height HB2 of the second topmost end 220BE of the second solder layer 220B is the distance from the surface 100S of the substrate 100 to the second topmost end 220BE. The fourth height HB2 of the second topmost end 220BE of the second solder layer 220B is the height of the second bump 200B. As described above, although the positions at which the first bump 200A and the second bump 200B are arranged on the substrate 100 are different from each other and the bottom structures arranged under the first bump 200A and the second bump 200B are different from each other, the height HB1 of the first bump 200A is substantially the same as the height HB2 of the second bump 200B.

[0024] If the height HB1 of the first bump 200A is different from the height HB2 of the second bump 200B, when the first bump 200A and the second bump 200B are connected to another substrate or other element, the following failure may occur: due to the difference between the heights of the first bump 200A and the second bump 200B, the first bump 200A or the second bump 200B does not contact the other substrate or other element and cannot be connected to the other substrate or other element. According to the present disclosure, since the height HB1 of the first bump 200A is substantially the same as the height HB2 of the second bump 200B, the failure of the first bump 200A and the second bump 200B to be connected to another substrate or other element because the first bump 200A and the second bump 200B do not contact the other substrate or other element can be reduced.

[0025] The first bottom layer 230A has substantially the same width W1 as the first column 210A. The second bottom layer 230B has substantially the same width W2 as the second column 210B. Because the first bottom layer 230A and the second bottom layer 230B are formed when the first column 210A and the second column 210B having the same width are formed, the second bottom layer 230B can have substantially the same width as the first bottom layer 230A. Therefore, the second bottom layer 230B can have a bonding surface with substantially the same area as the bonding surface of the first bottom layer 230A. Although there is a difference between the heights of the bottom structure due to the dielectric layer 130, the first bump 200A and the second bump 200B according to the present embodiment can have substantially the same heights HB1 and HB2. In addition, the area of ​​the first bump 200A and the second bump 200B bonded to the bottom structure can remain substantially the same. According to the present disclosure, regardless of the bottom structure of the first bump 200A and the second bump 200B, another substrate or element and the substrate 100 can be stably connected. The first bump 200A and the second bump 200B may cover the same size of area where the first bump 200A and the second bump 200B are bonded to the bottom structure, and may each maintain the ability to connect to another substrate or component. A plurality of first bumps 200A and a plurality of second bumps 200B may be implemented.

[0026] Figure 2 is a cross-sectional view illustrating a semiconductor device 11 according to an embodiment. Figure 2 In, with Figure 1 The same reference numerals used in the drawings represent the same elements or dimensions. Figure 2, the semiconductor device 11 includes a substrate 100, a first bump 200A and a second bump 200B-1. The first bump 200A includes a first column 210A, a first solder layer 220A and a first bottom layer 230A. The first bump 200A is connected to the conductive pad 110 of the substrate 100 and is electrically connected to the integrated circuit integrated in the substrate 100. The second bump 200B-1 is a dummy bump connected to the dielectric layer 130. The second bump 200B-1 includes a second column 210B-1, a second solder layer 220B-1 and a second bottom layer 230B-1.

[0027] The second column 210B-1 has a second lateral width W2-1 greater than the first lateral width W1 of the first column 210A, and has a fourth thickness T4-1 greater than the third thickness T3 of the first column 210A. The second solder layer 220B-1 has a second thickness T2-1, which is a distance from the second top surface 210BS-1 of the second column 210B-1 to the second topmost end 220BE-1 of the second solder layer 220B-1. The second thickness T2-1 is less than the first thickness T1 of the first solder layer 220A. Due to the difference between the thickness of the dielectric layer 130 and the difference between the thickness of the first column 210A and the thickness of the second column 210B-1, the first height H1 of the first top surface 210AS of the first column 210A and the second height H2-1 of the second top surface 210BS-1 of the second column 210B-1 are different. The difference between the second thickness T2-1 of the second solder layer 220B-1 and the first thickness T1 of the first solder layer 220A may be compensated by the difference HD-1 between the first height H1 and the second height H2-1. Therefore, the first bump 200A may have the same height as the second bump 200B-1.

[0028] The height HB2-1 of the second bump 200B-1 is substantially the same as the height HB1 of the first bump 200A, but the second lateral width W2-1 of the second column 210B-1 of the second bump 200B-1 is greater than the first lateral width W1 of the first column 210A. The width W2-1 of the second bottom layer 230B-1 having substantially the same width W2-1 as the second column 210 is greater than the width W1 of the first bottom layer 230A having substantially the same width W1 as the first column 210A. Therefore, the area where the second bottom layer 230B-1 and the dielectric layer 130 are connected is greater than the area where the first bottom layer 230A and the conductive pad 110 are connected. Because the second bottom layer 230B-1 includes a metal material and the dielectric layer 130 includes a dielectric material or a polymer material, the coupling force between the second bottom layer 230B-1 and the dielectric layer 130 may be smaller than the coupling force between the conductive pad 110 and the metal sheet of the first bottom layer 230A. Because the area where the second bottom layer 230B-1 and the dielectric layer 130 are connected is larger than the area where the first bottom layer 230A and the conductive pad 110 are connected, the weak connection force between the metal material and the non-metal material can be compensated. Therefore, because the second bump 200B-1 can be more strongly connected to the dielectric layer 130 over a larger area, the failure in which the second bump 200B-1 is separated or broken from the dielectric layer 130 can be reduced.

[0029] Figure 3 and Figure 4 is a cross-sectional view illustrating the semiconductor device 12 during a process of forming the semiconductor device 12 according to an embodiment. Figure 4 Examples of which Figure 3 The solder layers 220A and 220B in the bump fastening structure are connected by a reflow process. Figure 3 and Figure 4 In, with Figure 1 and Figure 2 The same reference numerals in the drawings represent the same elements or dimensions. Figure 3 and Figure 4 In the embodiment, the first substrate 100 is Figure 1 and Figure 2 The substrate 100 is basically the same element.

[0030] Reference Figure 3 The second substrate 1100 is stacked on or above the first substrate 100, or the first substrate 100 is stacked on or above the second substrate 1100, to obtain the semiconductor device 12. The semiconductor device 12 is a semiconductor package in which the first substrate 100 and the second substrate 1100 are connected through the first bump 200A and the second bump 200B. Figure 3 and Figure 4 In the implementation method, it can be used Figure 1 The second bump 200B or Figure 2The second bump 200B-1 in FIG.

[0031] The second substrate 1100 may be a semiconductor substrate in which an integrated circuit is integrated. Alternatively, the second substrate 1100 may be a package substrate. The package substrate may be a printed circuit board (PCB) on which a semiconductor substrate, a semiconductor chip and / or other electronic devices are mounted. The second substrate 1100 may be an interconnect structure in which wiring is stacked. The second substrate 1100 may be an interposer. When the second substrate 1100 is an element connected to the first bump 200A and the second bump 200B of the first substrate 100, the second substrate 1100 may not be limited to a specific form or specific element. The second substrate 1100 includes a first conductive trace 1111 and a second conductive trace 1112 spaced apart from each other. The second substrate 1100 is disposed above the first substrate 100 so that the first conductive trace 1111 and the second conductive trace 1112 face the first substrate 100. The first conductive trace 1111 is connected to the first solder layer 220A. The second conductive trace 1112 is connected to the second solder layer 220B. A protective layer 1130 may be additionally formed to protect the surface of the second substrate 1100 by covering the surface of the second substrate 1100 while exposing the first and second conductive traces 1111 and 1112 to the second substrate 1100. The protective layer 1130 may include a dielectric material or a polymer material.

[0032] Figure 3 The state in which the second substrate 1100 is disposed on the first bump 200A and the second bump 200B of the first substrate 100 is illustrated, or the state in which the first substrate 100 is disposed on the second substrate 1100 so that the first bump 200A and the second bump 200B of the first substrate 100 make contact with the second substrate 1100 is illustrated. When the first top surface 210AS of the first pillar 210A of the first bump 200A is disposed at a lower height than the second top surface 210BS of the second pillar 210B of the second bump 200B, when the second solder layer 220B has a thickness less than that of the first solder layer 220A, the difference between the height of the first top surface 210AS and the height of the second top surface 210BS can be compensated. Because the first bump 200A and the second bump 200B have substantially the same height, both the first solder layer 220A and the second solder layer 220B are in contact with the first conductive trace 1111 and the second conductive trace 1112 disposed on the second substrate 1100, respectively. When a reflow process is performed such that the solder materials of the first solder layer 220A and the second solder layer 220B are melted by applying heat to the first solder layer 220A and the second solder layer 220B, the first solder layer 220A and the second solder layer 220B are connected to the conductive traces 1111 and 1112 by covering the conductive traces 1111 and 1112 with the solder material, as shown in FIG. Figure 4shown.

[0033] Reference Figure 4 , when the first bump 200A and the second bump 200B are connected to the first conductive trace 1111 and the second conductive trace 1112, respectively, the first spacing distance G1 between the first conductive trace 1111 and the first top surface 210AS of the first pillar 210A may be greater than the second spacing distance G2 between the second conductive trace 1112 and the second top surface 210BS of the second pillar 210B. Figure 3 As shown, because the first solder layer 220A is thicker than the second solder layer 220B, the first solder layer 220A can have a larger volume than the second solder layer 220B. The first solder layer 220A can be reflowed to cover the first conductive trace 1111 while filling the gap having the first spacing distance G1 between the first conductive trace 1111 and the first pillar 210A. Therefore, if the first top surface 210AS of the first pillar 210A is set at a lower height than the second top surface 210BS of the second pillar 210B, the first solder layer 220A can be stably connected to the first conductive trace 1111.

[0034] Figures 5 to 12 is a cross-sectional view illustrating a semiconductor device formed by a method of manufacturing a semiconductor device according to an embodiment. Figures 5 to 12 In, with Figure 1 and Figure 2 The same reference numerals as used in the drawings represent the same elements or dimensions.

[0035] Reference Figure 5 , a dielectric layer 130 is formed on the substrate 100. In this example, the substrate 100 includes a conductive pad 110 formed at a surface 100S of the substrate 100. The dielectric layer 130 may be formed to cover the surface 100S of the substrate 100 while exposing a portion of the conductive pad 110.

[0036] Reference Figure 6 , a bottom layer 230 is formed on the substrate 100. The bottom layer 230 may be formed of an under bump metallization (UBM) layer. The bottom layer 230 may be a seed layer for plating that grows a plating layer in a plating process. The seed layer for plating may cover the conductive pad 110 and may extend to cover the dielectric layer 130.

[0037] Reference Figure 7, a first resist pattern 310 is formed on the bottom layer 230 of the substrate 100. The first resist pattern 310 may be formed as a template or a plating resist pattern in a plating process. The first resist pattern 310 is formed as a pattern including a first opening 312A and a second opening 312B. The first resist pattern 310 may be formed by a process of forming a layer including a resist material on the substrate 100 and exposing and developing the layer of the resist material.

[0038] The first opening 312A of the first resist pattern 310 overlaps the conductive pad 110. The second opening 312B of the first resist pattern 310 overlaps the dielectric layer 130. The first opening 312A and the second opening 312B of the first resist pattern 310 are through holes that each expose a portion of the bottom layer 230. The first opening 312A and the second opening 312B of the first resist pattern 310 may have substantially the same width or diameter. The second opening 312B of the first resist pattern 310 may have a width or diameter greater than the width or diameter of the first opening 312A. The second lateral width W2 of the second opening 312B of the first resist pattern 310 may have the same size as the first lateral width W1 of the first opening 312A, or may have a size greater than the first lateral width W1 of the first opening 312A.

[0039] Reference Figure 8 , a plating process including growing a metal layer in the first opening 312A and the second opening 312B of the first resist pattern 310 is performed. The metal material is plated starting from the portion of the bottom layer 230 exposed to the bottom of the first opening 312A and the second opening 312B of the first resist pattern 310. By growing the metal layer in the openings 312A and 312B, the first pillar 210A may be formed in the first opening 312A of the first resist pattern 310 and the second pillar 210B may be formed in the second opening 312B of the first resist pattern 310. When the second lateral width W2 of the second opening 312B of the first resist pattern 310 has the same size as the first lateral width W1 of the first opening 312A, the third thickness T3 of the first pillar 210A may be formed to be substantially the same as the fourth thickness T4 of the second pillar 210B. When the second lateral width W2 of the second opening 312B of the first resist pattern 310 is greater than the first lateral width W1 of the first opening 312A, the fourth thickness T4 of the second pillar 210B may be formed to have a thickness thicker or greater than the third thickness T3 of the first pillar 210A. Because the dielectric layer 130 overlaps the second pillar 210B but does not overlap the first pillar 210A, the second top surface 210BS of the second pillar 210B is set higher than the first top surface 210AS of the first pillar 210A by the thickness of the dielectric layer 130. After forming the first pillar 210A and the second pillar 210B, the first resist pattern 310 is removed.

[0040] Reference Fig. 9 , a second resist pattern 320 is formed over the substrate 100. The second resist pattern 320 is formed to cover the bottom layer 230 and include a third opening 322A and a fourth opening 322B. The third opening 322A of the second resist pattern 320 is a through hole that exposes a portion of the top surface 210AS of the first pillar 210A. The fourth opening 322B of the second resist pattern 320 is a through hole that exposes a portion of the top surface 210BS of the second pillar 210B. The fourth opening 322B may be formed to have a width smaller than that of the third opening 322A. Fig. 9 In the example of FIG. 5 , the fourth width W4 of the fourth opening 322B has a smaller value than the third width W3 of the third opening 322A.

[0041] Reference Fig.10 , a first solder pattern 220AP is formed within the third opening 322A of the second resist pattern 320. A second solder pattern 220BP is formed within the fourth opening 322B of the second resist pattern 320. A layer of solder material may be grown by a plating process from the first top surface 210AS of the first pillar 210A exposed through the third opening 322A of the second resist pattern 320 and the second top surface 210BS of the second pillar 210B exposed through the fourth opening 322B. Because the third width W3 of the third opening 322A is greater than the fourth width W4 of the fourth opening 322B, the plated first solder pattern 220AP may be formed to have a larger volume than the volume of the second solder pattern 220BP.

[0042] Reference Fig.11 After forming the first solder pattern 220AP and the second solder pattern 220BP, the second resist pattern ( Fig.10 320 in ).

[0043] Reference Fig.11 and Fig.12 , the exposed portions of the bottom layer 230 that do not overlap with the first pillar 210A and the second pillar 210B are removed, leaving the first bottom layer 230A between the first pillar 210A and the conductive pad 110 and the second bottom layer 230B between the second pillar 210B and the dielectric layer 130. As described above, the first bottom layer 230A overlapping with the first pillar 210A and the second bottom layer 230B overlapping with the second pillar 210B are formed.

[0044] Reference Fig.12 and Fig.13, the first solder layer 220A and the second solder layer 220B are formed by reflowing the first solder pattern 220AP and the second solder pattern 220BP, respectively. In the present embodiment, as the solder material of the first solder pattern 220AP melts and deforms into the first solder layer 220A having an elliptical shape, the exposed first top surface 210AS of the first column 210A may be covered. In the present embodiment, as the solder material of the second solder pattern 220BP melts and deforms into the second solder layer 220B having an elliptical shape, the exposed second top surface 210BS of the second column 210B may be covered. The second solder layer 220B is formed to have a thickness smaller than that of the first solder layer 220A. Because the area of ​​the second top surface 210BS of the second pillar 210B is substantially the same as the area of ​​the first top surface 210AS of the first pillar 210A when the width / diameter of the first pillar 210A and the second pillar 210B are the same, the volume of the second solder pattern 220BP is smaller than the volume of the first solder pattern 220AP.

[0045] Fig.14 is a cross-sectional view illustrating a semiconductor device according to an embodiment. Fig.14 , the semiconductor device includes a first substrate 100E, a conductive pad 110E and a dielectric layer 130E. A plurality of conductive vias 111E are connected to the conductive pad 110E while supporting the conductive pad 110E. A conductive pattern 112E is disposed on the bottom layer 101E. The conductive patterns 112E can each be a metal wiring. The conductive vias 111E are connected to the conductive patterns 112E and electrically connect the conductive patterns 112E and the conductive pad 110E.

[0046] The bottom layer 101E may include a semiconductor substrate in which an integrated circuit (not shown) is integrated. An insulating layer 102E that insulates the conductive pattern 112E and the conductive via 111E is disposed between the bottom layer 101E and the conductive pad 110E. An additional insulating layer may be further disposed between the insulating layer 102E and the bottom layer 101E. Additional conductive patterns may be included in the interconnect wiring structure.

[0047] The dielectric layer 130E is disposed on the insulating layer 102E so that a portion of the conductive pad 110E is exposed. The dielectric layer 130E may include a first dielectric layer 131E and a second dielectric layer 132E. The first dielectric layer 131E may be an inorganic insulating layer including a passivation material such as silicon oxide or silicon nitride. The first dielectric layer 131E is formed so that a portion of the conductive pad 110E is exposed. The second dielectric layer 132E may include a carbon polymer insulating layer such as PIQ. A step SH is formed between a top surface of the dielectric layer 130E (132E) and a top surface of the conductive pad 110E. By forming a dielectric layer 131E on the conductive pad 110E, a step SH is formed between the top surface of the dielectric layer 130E (132E) and the top surface of the conductive pad 110E. Figure 1The second bump 200B is formed on the dielectric layer 130E. Figure 1 The second bump 200B can compensate for the deviation between the bump heights caused by the step SH.

[0048] Embodiments of the present disclosure are described herein. One of ordinary skill in the art to which the present disclosure belongs will appreciate that the present disclosure may be implemented in a modified form without departing from the essential features of the present disclosure. Therefore, the disclosed embodiments should be considered from a descriptive perspective rather than from a restrictive perspective. The scope of the present disclosure is described in the claims rather than in the foregoing description, and all differences within their equivalent ranges should be interpreted as being included in the present disclosure.

[0049] CROSS-REFERENCE TO RELATED APPLICATIONS

[0050] This application claims the priority of Korean Patent Application No. 10-2023-0150350 filed on November 2, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first pillar and a second pillar, the first pillar and the second pillar being formed over a substrate; a first solder layer covering a first surface of the first column; as well as a second solder layer covering a second surface of the second column; wherein the first surface of the first column has a height lower than the height of the second surface of the second column, and the second solder layer has a thickness smaller than the thickness of the first solder layer to compensate for the difference between the height of the second surface and the height of the first surface, wherein the first surface of the first column is the surface of the first column farthest from the surface of the substrate, and the second surface of the second column is the surface of the second column farthest from the surface of the substrate.

2. The semiconductor device according to claim 1, wherein A first height of the first surface of the first pillar is a first distance from a surface of the substrate, and a second height of the second surface of the second pillar is a second distance from the surface of the substrate, and The first thickness of the first solder layer is the distance from the first surface to the first end of the first solder layer, and the second thickness of the second solder layer is the distance from the second surface to the second end of the second solder layer, wherein the first end of the first solder layer is the end of the first solder layer farthest from the first column, and the second end of the second solder layer is the end of the second solder layer farthest from the second column.

3. The semiconductor device according to claim 1, wherein The substrate includes a conductive pad connected to the first pillar.

4. The semiconductor device according to claim 3, further comprising a dielectric layer on the substrate exposing the conductive pad, in, The second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height higher than that of the first surface of the first pillar by the thickness of the dielectric layer.

5. The semiconductor device according to claim 4, further comprising: a first bottom layer formed between the first pillar and the conductive pad; as well as A second bottom layer is formed between the second pillar and the dielectric layer.

6. The semiconductor device according to claim 1, wherein The second pillar has the same thickness as that of the first pillar or has a thickness greater than that of the first pillar.

7. The semiconductor device according to claim 1, wherein The second pillar has a width that is the same as or greater than a width of the first pillar.

8. A semiconductor device, comprising: a first substrate; a second substrate disposed over the first substrate and comprising a first conductive trace and a second conductive trace; a first column and a second column, wherein the first column and the second column are disposed between the first substrate and the second substrate; a first solder layer covering a first surface of the first column; as well as a second solder layer covering a second surface of the second column, wherein the first surface of the first column has a height lower than a height of the second surface of the second column, wherein the first surface of the first column is a surface of the first column farthest from a surface of the substrate, and the second surface of the second column is a surface of the second column farthest from the surface of the substrate, wherein the first solder layer is connected to the first conductive trace, wherein the second solder layer is connected to the second conductive trace, and The distance between the first surface and the first conductive trace is greater than the distance between the second surface and the second conductive trace.

9. The semiconductor device according to claim 8, wherein: The first substrate includes a conductive pad connected to the first column, The semiconductor device further comprises a dielectric layer located on the substrate and exposing the conductive pad, and The second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height higher than that of the first surface of the first pillar by the thickness of the dielectric layer.

10. The semiconductor device according to claim 9, wherein: The first substrate further comprises: a conductive via supporting the conductive pad; a conductive pattern connected to the conductive pad through the conductive via; and an insulating layer, the insulating layer insulating the conductive via from the conductive pattern, Wherein, the dielectric layer comprises: a first dielectric layer exposing a portion of the conductive pad and comprising an inorganic insulating layer; and A second dielectric layer is disposed on the first dielectric layer and includes a carbon polymer insulating layer.

11. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first pillar and a second pillar over a substrate; forming a first resist pattern including a first opening exposing a first surface of the first pillar and including a second opening exposing a second surface of the second pillar and having a width smaller than a width of the first opening, wherein the first surface of the first pillar is a surface of the first pillar farthest from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar farthest from the surface of the substrate; forming a first solder pattern in the first opening and forming a second solder pattern in the second opening; removing the first resist pattern; and A first solder layer is formed by reflowing the first solder pattern, and a second solder layer is formed by reflowing the second solder pattern.

12. The method according to claim 11, wherein: The first pillar and the second pillar are formed such that the first surface of the first pillar has a lower height than the second surface of the second pillar.

13. The method according to claim 12, wherein: The second solder layer is formed to have a smaller thickness than the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.

14. The method according to claim 11, wherein: Due to the difference between the width of the first opening and the width of the second opening, the second solder pattern is formed to have a smaller volume than the first solder pattern.

15. The method according to claim 11, wherein: The substrate includes a conductive pad, and The first pillar is connected to the conductive pad.

16. The method according to claim 15, further comprising the steps of: forming a dielectric layer over the substrate to expose the conductive pad, The second pillar is connected to the dielectric layer and is formed such that the second surface of the second pillar has a height higher than the first surface of the first pillar by the thickness of the dielectric layer.

17. The method according to claim 16, wherein: The step of forming the first column and the second column comprises the following steps: forming a seed layer for plating, the seed layer for plating covering the conductive pad and extending to cover the dielectric layer; forming a second resist pattern including a third opening overlapping the conductive pad and a fourth opening overlapping the dielectric layer; and The first pillar is plated within the third opening, and the second pillar is plated within the fourth opening.

18. The method according to claim 11, wherein: The first solder pattern is formed by plating a solder material in the first opening, and the second solder pattern is formed by plating a solder material in the second opening.

19. The method according to claim 11, wherein: The second pillar is formed to have the same thickness as that of the first pillar or to have a thickness greater than that of the first pillar.

20. The method according to claim 11, wherein: The second pillar is formed to have the same width as that of the first pillar or to have a width greater than that of the first pillar.

21. A semiconductor device, comprising: a first pillar and a second pillar, the first pillar and the second pillar being formed over a substrate; a first solder layer covering a first surface of the first column; as well as a second solder layer covering a second surface of the second column; The second solder layer has a thickness smaller than that of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.

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