Semiconductor stacked structure and manufacturing method thereof

Abstract

A stack structure is provided. The stacked structure includes a first die and a second die stacked on the first die. The first die includes a first substrate and a first bonding structure over the first substrate. The second die includes a second substrate and a second bonding structure over the second substrate. The first and second dies are bonded through bonded first and second bonding structures. The bonded first and second bonding structures include a fused bonding pad having a homogeneous core pad and a catch pattern surrounding the homogeneous core pad.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor stacking structure and a method for manufacturing the same. Background Art

[0002] As semiconductor manufacturing technology advances, complex semiconductor structures combining different types of semiconductor dies are manufactured and further integrated with integrated circuits (ICs) and electronic components. In order to achieve reliable and durable integration, it is essential to establish reliable electrical connections between semiconductor dies and / or other components. Summary of the invention

[0003] An embodiment of the present invention provides a stacking structure. The stacking structure includes a first tube core and a second tube core stacked on the first tube core. The first tube core includes a first substrate and a first bonding structure located above the first substrate. The second tube core includes a second substrate and a second bonding structure located above the second substrate. The first and second tube cores are bonded through the bonded first and second bonding structures. The bonded first and second bonding structures include a fusion bonding pad having a homogeneous core pad and a locking pattern surrounding the homogeneous core pad.

[0004] An embodiment of the present invention provides a stacking structure. The stacking structure includes a first tube core and a second tube core stacked on the first tube core and bonded to the first tube core. The first tube core has a first bonding structure, the first bonding structure includes a first bonding pad embedded in a first dielectric material, and the first bonding pad includes a first auxiliary pattern and a first metal material. The second tube core has a second bonding structure, the second bonding structure includes a second bonding pad embedded in a second dielectric material, and the second bonding pad includes a second auxiliary pattern and a second metal material. The first and second tube cores are bonded through bonded first and second bonding structures, and the bonded first and second bonding structures have bonded first and second bonding pads embedded in bonded first and second dielectric materials. The bonded first and second bonding pads include bonded first and second auxiliary patterns and a fusion core pad, and the fusion core pad includes first and second metal materials and is surrounded by the bonded first and second auxiliary patterns.

[0005] An embodiment of the present invention provides a method for manufacturing a stacked structure. A first wafer having a plurality of first tube cores is provided. Each first tube core has a first bonding structure, the first bonding structure includes a first bonding pad embedded in a first dielectric material, and the first bonding pad includes a first inner metal pattern, a first outer metal pattern, and a first auxiliary pattern sandwiched between the first inner and outer metal patterns. A plurality of second tube cores are provided. Each second tube core has a second bonding structure, the second bonding structure includes a second bonding pad embedded in a second dielectric material, and the second bonding pad includes a second inner metal pattern, a second outer metal pattern, and a second auxiliary pattern sandwiched between the second inner and outer metal patterns. The second bonding pad of the second tube core is aligned with the first bonding pad of the first tube core. The second tube core is bonded to the first tube core by bonding the first and second dielectric materials of the first and second bonding structures and bonding the first and second bonding pads, wherein the first and second bonding pads are bonded to form a fusion core pad by merging the first and second inner metal patterns, and the first and second auxiliary patterns are retained and located around the fusion core pad. A singulation process is performed to form individual stacked structures.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a schematic top view of an exemplary structure having a plurality of semiconductor die units according to some embodiments of the present disclosure.

[0009] Figure 2-6 are cross-sectional views showing various stages of a manufacturing method for forming a semiconductor stacked structure according to some embodiments of the present disclosure.

[0010] Figures 7 to 9 is a schematic enlarged cross-sectional view showing the joint structure relative to the multiple components thereunder.

[0011] Fig.10 is a schematic diagram of a joint portion according to some embodiments of the present disclosure.

[0012] Figure 11-14 are cross-sectional views showing various stages of a manufacturing method for forming a semiconductor stacked structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a second feature on or on a first feature may include an embodiment in which the second feature and the first feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature and the first feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "on," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, for the convenience of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different components or features as illustrated, and may be used interchangeably according to the order of appearance or the context of description.

[0016] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) component. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, which enables the 3D package or 3DIC to be tested, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0017] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed herein are merely illustrative and relate to three-dimensional (3D) integrated structures or assemblies, and do not limit the scope of the present disclosure. The embodiments of the present disclosure describe exemplary manufacturing processes for 3D stacked structures and 3D stacked structures made by the exemplary manufacturing processes. Certain embodiments of the present disclosure relate to 3D stacked structures formed by wafer bonding structures and stacked wafers and / or dies. Other embodiments relate to 3D integrated structures or assemblies including post-passivation interconnect (PPI) structures or interposers with other electrically connected components, including wafer-to-wafer assembly structures, die-to-wafer assembly structures, package-on-package assembly structures, die-to-die assembly structures, and die-to-substrate assembly structures. The wafer or die may include one or more types of integrated circuits or electronic components located on a bulk semiconductor substrate or a silicon / germanium on insulator substrate. The embodiments are intended to provide further explanation, but are not intended to limit the scope of the present disclosure.

[0018] Figure 1 is a schematic top view of an exemplary structure having a plurality of semiconductor die units according to some embodiments of the present disclosure.

[0019] exist Figure 1 In the present invention, a wafer structure 100 is provided and can be used to form a semiconductor stack structure or a package structure in a packaging process. In some embodiments, the wafer structure 100 has a plurality of die units 10D formed therein. In some embodiments, the wafer structure 100 is a semiconductor bulk wafer having active devices and optionally passive devices formed therein. In some embodiments, the wafer structure 100 can be a reconstructed wafer. Figure 1 As can be seen in FIG. 1 , the node lines represent the dicing lanes DL, and the wafer structure 100 will be cut in a subsequent singulation process to obtain separate dies 10D. In some embodiments, the dies 10D are semiconductor dies having the same design and performing the same functions. In some embodiments, the dies 10D include semiconductor dies having different designs and performing different functions.

[0020] Figure 2-6 2 is a cross-sectional view showing various stages of a method for forming a semiconductor stack structure according to some embodiments of the present disclosure. In the drawings, the same components or elements or similar or identical structures may be marked with the same reference numerals. Figures 7 to 9 is a schematic enlarged cross-sectional view showing the joint structure relative to the multiple components thereunder. Fig.10 is a schematic diagram of a joint portion according to some embodiments of the present disclosure.

[0021] exist Figure 2 In some embodiments, a wafer 100A is provided, and the wafer 100A is similar to the wafer structure 100 described in the previous paragraph. In some embodiments, the wafer 100A is a semiconductor wafer, and the wafer 100A includes a semiconductor substrate 102 having a component layer 103, a metallization structure 104 formed on the semiconductor substrate 102 and the component layer 103, and a bonding structure 106 formed on the metallization structure 104 and the semiconductor substrate 102. In some embodiments, the wafer 100A is a silicon wafer or a bulk wafer made of other semiconductor materials such as III-V semiconductor materials such as gallium nitride (GaN) or gallium arsenide (GaAs). In some embodiments, the substrate 102 can be a single crystal semiconductor substrate (e.g., a silicon substrate), a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the component layer 103 includes a semiconductor component formed in or on the semiconductor substrate 102 of the wafer 100A during a front-end-of-line (FEOL) manufacturing step. In some embodiments, the semiconductor components are active devices or include transistors, memory, or power components. In some embodiments, the semiconductor components are or include capacitors, resistors, diodes, photodiodes, sensors, inductors, or fuses. In an exemplary embodiment, some of the semiconductor components are electrically connected to the metallization structure 104, and some of the semiconductor components are electrically interconnected to each other through the metallization structure 104.

[0022] In some embodiments, wafer 100A can be considered to have multiple die units or semiconductor dies before dicing or singulation. Figure 2 10A, including at least two die units 10D1 and 10D2 defined by a dicing line DL (dashed line). It should be understood that the number of die units or semiconductor dies is merely exemplary. In some embodiments, die units (or semiconductor dies) 10D1 and 10D2 are or include different types of dies with different functions. In some embodiments, die units (or semiconductor dies) 10D1 and 10D2 are or include the same type of dies or dies with the same function.

[0023] like Figure 2As shown, in some embodiments, the metallization structure 104 is embedded in a dielectric material 105 formed on the semiconductor substrate 102. In some embodiments, the metallization structure 104 includes a plurality of metallization layers or interconnection line structures, including interconnected metal lines, vias, and contact pads (certain details of the architecture and intermediate layers are omitted and indicated by ellipses). In some embodiments, the metallization structure 104 includes at least an electrically connected top metallization layer 1042 and a bottom metallization layer 1046, and the bottom metallization layer 1046 is electrically connected to the component layer 103. In some embodiments, the top metallization layer 1042 includes a contact 1043 and a top metal line 1044, and the bottom metallization layer 1046 includes a bottom metal line 1047 and a via 1048 connected to the bottom metal line 1047. The metallization structure 104 shown herein is for illustration purposes only, and the metallization structure 104 may include other architectures and may include one or more vias and / or damascene structures. The present disclosure does not limit the number of sublayers and metallization layers included in the dielectric material 105, and the number of layers or sublayers shown in the drawings is only exemplary. Additional layers such as barrier layers and etch stop layers may also be formed between each layer or its sublayers / sublayers.

[0024] In some embodiments, the material of the metallization structure 104 includes aluminum (Al), aluminum alloy, copper (Cu), copper alloy, titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), tungsten (W), nitrides thereof, or combinations thereof. In some embodiments, the contact 1043 includes an aluminum pad, a copper pad, or a copper alloy pad. In some embodiments, the top metallization layer 1042 and the bottom metallization layer 1046 and each metal layer formed therebetween (including metal lines 1044, 1047, and vias 1048) are formed by the same metallization process and are made of the same metal material. In some embodiments, the top metallization layer 1042 and the bottom metallization layer 1046 and each metal layer formed therebetween (including metal lines 1044, 1047, and vias 1048) are made of copper or copper alloy. In some embodiments, the dielectric material 105 includes silicon oxide, a spin-on dielectric material, a low dielectric constant dielectric material, or combinations thereof. In some embodiments, the insulating dielectric material 105 includes one or more low dielectric constant dielectric layers. Examples include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), amorphous fluorinated carbon, polyparaxylene, benzocyclobutene (BCB), polyimide, Flare, xerogel, aerogel, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), or a combination thereof.

[0025] In an exemplary embodiment, the semiconductor components in the component layer 103 are electrically connected to the metallization structure 1046 through the bottom metal line 1047 and the through hole 1048. In some embodiments, the wafer 100A may also include through semiconductor vias (TSVs) for additional electrical connection. In some embodiments, the wafer 100A may include a non-electrically connected seal ring structure embedded in the dielectric material 105 as a structural reinforcement component.

[0026] refer to Figure 3 In some embodiments, a bonding structure 106 including a dielectric material 1061 and a bonding pad 1069 embedded in the dielectric material 1061 is formed over the dielectric material 105 and the metallization structure 104. In some embodiments, the metallization structure 104 electrically connects some semiconductor components in the component layer 103 to the bonding structure 106. The formation of the bonding structure 106 will be described in further detail in the subsequent paragraphs.

[0027] For illustration purposes, portions of the engagement structure 106 are shown in FIG. Figure 7 , Figure 8 and Fig. 9 An enlarged schematic diagram of the embodiment is shown to show the exemplary architecture in more detail. Figure 7 In some embodiments, a dielectric material 1061 is formed on the dielectric material 105, covering the contact 1043 and the top metal line 1044 of the metallization structure 104 and covering the substrate 102. Afterwards, a dual damascene opening DD1 is formed in the dielectric material 1061 through a dual damascene formation process, and a metal substrate pattern 1065 is formed inside the dual damascene opening DD1.

[0028] In some embodiments, the formation of the dual damascene opening DD1 involves sequentially forming an etch stop layer E21 and a dielectric sublayer 1061L, an etch stop layer E22, a dielectric sublayer 1061H, and a shield layer 1062, patterning the shield layer 1062, etching the dielectric sublayer 1061H through the patterned shield layer 1062 to form a trench opening TC1 in the dielectric sublayer 1061H (etching stops at the etch stop layer E22), and etching the dielectric sublayer 1061L to form a via opening VC1 in the dielectric sublayer 1061L (etching stops at the etch stop layer E21). Therefore, the trench opening TC1 and the via opening VC1 together form the dual damascene opening DD1, as shown in FIG. Figure 7 shown.

[0029] In some embodiments, dielectric material 1061 (including dielectric sublayers 1061L, 1061B) comprises silicon oxide, silicon oxynitride (SiON), silicon carbonitride (SiCN), or an oxide-based dielectric material. In some embodiments, individual dielectric sublayers such as 1061L, 1061H can be fabricated to a suitable thickness by chemical vapor deposition such as flowable CVD (FCVD), HDPCVD, sub-atmospheric pressure chemical vapor deposition, spin coating, sputtering, or other suitable methods. In some embodiments, the material of etching stop layers E21 and E22 comprises silicon nitride or silicon carbide. In some embodiments, the material of shielding layer 1062 comprises silicon nitride or silicon carbide.

[0030] In some embodiments, reference Figure 7 The formation of the metal substrate pattern 1065 includes forming a barrier layer (not shown) on the dielectric material 1061 to conformally cover the dual damascene opening DD1, forming a metal layer (not shown) on the barrier layer to fill the dual damascene opening DD1 (at least partially fill or fill up the dual damascene opening DD1), and partially removing (etching back process) the barrier layer outside the dual damascene opening DD1 to form a barrier pattern 1063, and partially removing the metal layer to form a metal pattern 1064 inside the dual damascene opening DD1. In some embodiments, the etching back process removes the barrier layer and the metal layer outside the dual damascene opening DD1, and partially removes the metal layer without exposing the barrier layer inside the dual damascene opening DD1 (the metal layer still covers the barrier layer inside the dual damascene opening DD1).

[0031] In the dual damascene opening DD1, the barrier pattern 1063 and the metal pattern 1064 together form a metal substrate pattern 1065. Figure 7 Since the barrier layer and the metal layer outside the dual metal damascene opening DD1 or above the top surface of the shielding layer 1062 are removed, the tops of the metal pattern 1064 and the barrier pattern 1063 are flush with or slightly below the top surface of the shielding layer 1062. In other words, the metal substrate pattern 1065 does not fill the dual metal damascene opening DD1, so there is a hollow space (or cavity) in the dual metal damascene opening DD1, such as Figure 7 shown.

[0032] In some embodiments, the material of the barrier layer or barrier pattern 1063 includes titanium (Ti), tantalum (Ta), ruthenium (Ru), nitrides thereof, or combinations thereof. In some embodiments, the thickness of the barrier layer is in the range of about 200 angstroms to about 1000 angstroms. In some embodiments, the barrier pattern 1063 includes a composite layer of titanium / titanium nitride (Ti / TiN), a composite layer of tantalum / tantalum nitride (Ta / TaN), or a ruthenium layer. In some embodiments, the material of the metal pattern 1064 includes copper or a copper alloy. The formation of the metal layer involves plating (e.g., electrochemical plating), deposition, or other appropriate processes. It should be understood that the dual-pass metal damascene process described herein is merely exemplary, and trenches, damascene openings, through-hole openings, or other openings may be formed through appropriate architectures and processes to form openings and bonding structures within the openings.

[0033] refer to Figure 8 In some embodiments, after forming the metal substrate pattern 1065, a latching assisting layer 1066 is formed over the patterned shielding layer 1062 and conformally covers the exposed surface of the metal substrate pattern 1065 without filling the dual metal damascene opening DD1. Subsequently, a metal layer 1067 is formed on the latching assisting layer 1066 and over the patterned shielding layer 1062 and fills the dual metal damascene opening DD1.

[0034] In some embodiments, the latching assist layer 1066 is formed as a layer with a specific orientation (a layer with a particularly preferred crystal orientation or a strong grain orientation), and serves as an orientation layer for the subsequently formed metal layer 1067. Due to the presence of the latching assist layer 1066, the subsequently formed metal layer 1067 is also a layer with a specific orientation with a similar preferred crystal orientation (i.e., a similar strong grain orientation). In some embodiments, the material of the latching assist layer 1066 includes Ti, Ta, silver (Ag), gold (Au), Ru, or a combination thereof. In some embodiments, the latching assist layer 1066 with a specific preferred crystal orientation is formed by physical vapor deposition (PVD) with a thickness ranging from about 200 angstroms to about 1500 angstroms. In one embodiment, the latching assist layer 1066 is or includes a titanium layer formed by PVD, which has a higher purity (lower contamination). In one embodiment, the latching assist layer 1066 is or includes a tantalum layer formed by PVD. In one embodiment, the thickness of the latching assist layer 1066 is about 250 angstroms to about 350 angstroms. Although the latching assist layer 1066 shown in the figure has a uniform thickness, the thickness of the latching assist layer 1066 may also vary depending on the underlying profile. As shown in the figure for example, the latching assist layer 1066 can be formed to be thicker at the bottom portion of the opening, but thinner at the sidewalls of the opening. In some embodiments, the material of the metal layer 1067 includes copper or a copper alloy. In the figure for example, the metal layer 1067 is formed by deposition (e.g., CVD, PVD, atomic layer deposition (ALD)), plating, or other appropriate material formation processes. In some embodiments, the material of the latching assist layer 1066 is different from the material of the metal layer 1067. In some embodiments, the material of the latching assist layer 1066 is different from the material of the barrier layer.

[0035] refer to Fig. 9 The latching auxiliary layer 1066 and the metal layer 1067 are planarized to remove the redundant portions of the latching auxiliary layer 1066 and the metal layer 1067 located outside the double-track metal damascene opening DD1 and on the patterned shielding layer 1062, thereby forming a latching auxiliary pattern 1066P and a metal pattern 1067P. Fig. 9 As can be seen, the latching auxiliary pattern 1066P completely covers the sidewalls and bottom surface of the metal pattern 1067P. However, depending on whether the latching auxiliary layer is formed with a uniform thickness, the latching auxiliary pattern 1066P may partially cover the sidewalls and / or partially or completely cover the bottom surface of the metal pattern 1067P. In some embodiments, the latching auxiliary pattern 1066P and the metal pattern 1067P together form the main pad 1068. Fig. 9 It can be seen that the metal substrate pattern 1065 and the main pad 1068 together form a bonding pad 1069 located in the respective opening DD1 , and the bonding pad 1069 is embedded in the dielectric material 1061 .

[0036] refer to Fig. 9 , the main pad 1068 and the barrier pattern 1063 are separated by the metal pattern 1064. In addition, the metal pattern 1067P is separated from the metal pattern 1064 by the latch auxiliary pattern 1066P. Fig. 9 As seen in FIG. 1 , the latching auxiliary pattern 1066P having a U-shaped cross-section (or a bowl shape) surrounds and encloses the metal pattern 1067P therein. In some embodiments, the metal pattern 1067P and the metal pattern 1064 separated by the latching auxiliary pattern 1066P can be regarded as an inner metal pattern (e.g., a pad shape) and an outer metal pattern (e.g., a ring shell shape).

[0037] refer to Figure 4 , another wafer 100B is provided, and the wafer 100B is similar to the wafer structure 100 or the wafer 100A described in the previous paragraph. In some embodiments, the wafer 100B is a semiconductor wafer, and the wafer 100B includes a semiconductor substrate 102B having a component layer 103B, a metallization structure 104B formed on the semiconductor substrate 102B and the component layer 103B, and a bonding structure 106B formed on the metallization structure 104B and the semiconductor substrate 102B. Specifically, for the wafer 100B, the bonding structure 106B including the dielectric material 1061B and the bonding pad 1069B embedded in the dielectric material 1061B is substantially the same as the bonding structure 106 of the wafer 100A.

[0038] Then, refer to Figure 4 and Figure 5After the wafer 100B and the wafer 100A are mounted and aligned, a bonding process is performed to bond the wafers 100A and 100B through the bonding of the bonding structures 106 and 106B. In some embodiments, the bonding process is or includes a hybrid bonding process. In some embodiments, the bonding process involves performing a low temperature heating process performed at a temperature below about 300 degrees. Due to the presence of the locking auxiliary pattern 1066P embedded in the bonding pad, the bonding process can be performed at a lower bonding temperature because the formed metal pattern 1067 has a specific preferred crystalline orientation. In one embodiment, the bonding process is performed in two stages, firstly performing a first temperature heating process at a temperature of about 100 degrees to about 200 degrees to heat and bond the dielectric materials 1061 and 1061B (dielectric-to-dielectric bonding), and then performing a second temperature heating process at a temperature of about 200 degrees to about 250 degrees to bond the bonding pads 1069 and 1069B (metal-to-metal bonding). In one embodiment, the bonding process involves a low temperature heating process at a temperature of about 150 degrees to about 250 degrees to heat and bond the dielectric materials 1061 and 1061B (dielectric-to-dielectric bonding) and the bonding pads 1069 and 1069B (metal-to-metal bonding). In some embodiments, the wafers 100A and 100B are bonded by a hybrid interface to form a wafer-to-wafer structure 100WB.

[0039] Although the steps of the method are illustrated and described as a series of actions or events, it should be understood that the order in which these actions or events are depicted is not limiting. In addition, further processes or steps may be performed, such as a singulation process, to implement one or more embodiments of the present disclosure. The above-described process is a wafer-to-wafer (WoW) process and can be further made into a 3D stacked package or a chip-to-wafer-to-substrate (CoWoS) package.

[0040] refer to Figure 5 , the wafers 100A and 100B are bonded through dielectric-to-dielectric bonding between dielectric materials 1061 and 1061B and metal-to-metal bonding between bonding pads 1069 and 1069B. After wafer 100B is placed on wafer 100A, bonding structures 106 and 106B, especially corresponding bonding pads 1069 and 1069B, are aligned with each other, and during a low temperature heating process, the aligned bonding pads 1069 and 1069B are heated and bonded to form a bonded bonding pad 107 having a fused core pad 1072 without a distinct interface. According to an embodiment of the present disclosure, the fused core pad 1072 without a distinct interface (or pores or defects) can be described as a homogeneous core pad of the bonded bonding pad 107.

[0041] According to some embodiments of the present disclosure, Figure 6 show Figure 5 A schematic enlarged view of the bonding portion of the bonding pads of the wafer-to-wafer bonding structure. Fig.10 is a schematic diagram showing a joint portion according to an embodiment of the present disclosure. Figure 6 After the bonding process, the aligned bonding pads 1069 and 1069B are bonded to form a fused bonding pad 107. Figure 6 And refer to Figure 4 , Figure 5 and Fig. 9 In some embodiments, through the heating of the bonding process, in the presence of the locking auxiliary pattern 1066P, the metal materials of the metal pattern 1067P from the respective bonding pads 1069 and 1069B are fused together, and the metal atoms in the metal pattern 1067P of the respective bonding pads 1069 and 1069B diffuse, fuse, and merge into a complete fusion core pad 1072 without a distinct interface. After the thermal process, most of the locking auxiliary pattern 1066P is retained and merged into the locking pattern 1070, and the metal material of the metal pattern 1067P, which was originally formed with a specific grain orientation, will fuse and re-grow large grains on the contact interface (represented by the node line in the figure), forming a complete, integrated and homogeneous fusion core pad 1072, with almost no (or no) bonding interface, which will result in a stronger bonding strength of the bonded bonding pads 107. Compared with a conventional bonding pad without a locking auxiliary pattern, the bonding pad with the fusion core pad has a bonding strength increased by at least 20%-30%.

[0042] In some embodiments, when aligning the bonding pads 1069 and 1069B, it is preferred to precisely align the locking auxiliary patterns 1066P of the corresponding bonding pads. Figure 6 Compared to the precise alignment shown in FIG. 1 , it can be seen that the barrier patterns 1063 and 1063B are aligned, and the metal patterns 1064 and 1064B of the respective bonding pads 1069 and 1069B are aligned and bonded to each other. In some embodiments, the bonded metal substrate patterns 1065 and 1065B of the corresponding bonding pads 1069 and 1069B are aligned and bonded to each other to form a combined metal shell. In some embodiments, the latching auxiliary pattern 1066P ( Fig. 9 ) are aligned and combined to form a locking pattern 1070, which can enhance the bonding quality of the fused bonding pad 107. In some embodiments, under the condition of acceptable alignment, the locking pattern 1070 can be formed into a cage or box shape, the fusion core pad 1072 is a homogeneous metal block, most of which is formed within the span defined by the locking pattern 1070 (locked and confined within the locking pattern 1070), and the merged metal shell is located outside the locking pattern 1070 and surrounds the locking pattern 1070.

[0043] refer to Figure 5 and Figure 6 , the wafer-to-wafer structure 100WB includes wafers 100A and 100B bonded through bonding pads 107 embedded in fusion-bonded dielectric materials 1061 and 1061B. In some embodiments, the bonded bonding pads 107 include fusion core pads 1072 surrounded by latch patterns 1070 (remaining auxiliary patterns 1066P).

[0044] from Fig.10 It can be seen that after the thermal process of the bonding process, the bonding pads BP1 and BP2 are bonded, and the latching auxiliary patterns LAP1 and LAP2 remain in the bonding pads BP1 and BP2. Fig.10 It can be seen that the span range of the bonding pad BP1 and BP2 mostly overlap but not completely overlap (or it can be said that they are not completely aligned). Fig.10 The butt joints with each other may not be perfect, but the metal patterns of the main pads of the bonding pads BP1 and BP2 are bonded and fused to form a fusion core bonding portion FC, in which large grains (indicated by dotted lines) grow across the bonding interface (shown as node lines) and are located within the span defined by the remaining latching auxiliary patterns LAP1 and LAP2. Due to the formation of a directional crystalline microstructure (large grains), the fusion core bonding portion FC forms an integral metal block with large grains and no clear interfaces. It can be seen that the fusion core pad FC is surrounded by the remaining latching auxiliary patterns LAP1 and LAP2, and the remaining latching auxiliary patterns LAP1 and LAP2 may not be completely connected. Therefore, the bonded bonding pad has a fusion core pad, providing excellent bonding strength and reliability.

[0045] Figure 11-14 is a cross-sectional view showing various stages of a manufacturing method for forming a semiconductor stack structure according to some embodiments of the present disclosure. Fig.11 In some embodiments, a wafer 100C is provided, and the wafer 100C is similar to the wafer structure 100 and the wafer 100A described in the previous paragraphs. In some embodiments, the wafer 100C is a semiconductor wafer, and the wafer 100C includes a semiconductor substrate 102C having a component layer 103C, a metallization structure 104C formed on the semiconductor substrate 102C and the component layer 103C, and a bonding structure 106C formed on the metallization structure 104C and the semiconductor substrate 102C. Specifically, for the wafer 100C, the bonding structure 106C including the dielectric material 1061C and the bonding pad 1069C embedded in the dielectric material 1061C is substantially the same as the bonding structure 106 of the wafer 100A.

[0046] refer to Fig.11 , multiple dies 200 (only two are shown) are provided and stacked on the wafer 100C. For example, Fig.11As shown, a plurality of dies 200 are arranged side by side on a wafer 100C. In certain embodiments, each die 200 includes a semiconductor substrate 202, a component layer 203, a metallization structure 204 embedded in an insulating material 205 formed on the semiconductor substrate 202, and a bonding structure 206 formed on the second metallization structure 204 (from top to bottom because the die 200 faces downward). In an embodiment, each die 200 includes a semiconductor component formed in the component layer 203 and an isolation structure (not shown) formed in the semiconductor substrate 202. In certain embodiments, the metallization structure 204 includes a through-semiconductor via (TSV) 2041 and interconnected metal lines and vias (certain details of the architecture and intermediate layers are omitted and indicated by ellipses). In some embodiments, the bonding structure 206 includes a dielectric material 2061 and a bonding pad 2069 in the dielectric material 2061. In some embodiments, as Fig.11 As shown in the enlarged view of the lower part, Figure 3 and Fig. 9 Similar to the bonding pad 1069 of the embodiment, the bonding pad 2069 includes a main pad 2068 and a metal substrate pattern 2065 surrounding and covering the main pad 2068, and the metal substrate pattern 2065 and the main pad 2068 are separated by a latching auxiliary pattern 2066 sandwiched therebetween. In some embodiments, some of the bonding pads 2069 are electrically connected to the semiconductor device and the metallization structure 204 in the device layer 203.

[0047] In some embodiments, die 200 may be the same die with the same function or the same size, or may be a die with different functions or different sizes. In some embodiments, die 200 includes a logic die, such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a microcontroller unit (MCU) die, a baseband (BB) die, or an application processor (AP) die, or a memory die, such as a high bandwidth memory (HBM) die, a dynamic random access memory (DRAM) die, or a static random access memory (SRAM) die. In some embodiments, die 200 includes an application specific integrated circuit (ASIC) die, an analog die, a sensor die, a wireless application die (including a Bluetooth chip and / or a radio frequency chip), or a voltage regulator die.

[0048] In some embodiments, die 200 is a semiconductor die manufactured from a semiconductor wafer having an architectural design similar to that shown in die unit of wafer structure 100 or wafer 100A. In some embodiments, the material of metallization structure 204 can be similar or identical to the material of metallization structure 104. In some embodiments, the dielectric material 2061 of bonding pad 2069 and the material of bonding structure 206 can be similar or identical to the material of bonding structure 106. In the process of placing die 200, die 200 is arranged in such a way that bonding structure 206 is aligned with corresponding bonding structure 106C of wafer 100C, respectively, so that bonding pads 1069C and 2069 are substantially vertically aligned (along the stacking direction).

[0049] Then, in some embodiments, Fig.12 As shown, a bonding process is performed to bond the bonding structures 106C and 206 so as to bond the die 200 to the wafer 100C. In some embodiments, the bonding process includes a low temperature heating process at a temperature of about 150 degrees Celsius to about 250 degrees Celsius to bond the dielectric materials 1061C, 2061 (dielectric to dielectric bonding) and the bonding pads 1069C, 2069 (metal to metal bonding). In some embodiments, the die 200 is bonded to the wafer 100C through hybrid interface bonding to form a die stacked on wafer structure.

[0050] refer to Fig.12 After the die 200 stack is bonded to the wafer 100C, a filling material 250 is formed above the structure of the die stack to the wafer, in particular, the gaps between the die 200 on the wafer 100C are filled to form a molding structure 300. In some embodiments, the filling material 250 is an insulating material. In one embodiment, the filling material 250 is formed by chemical vapor deposition (CVD), spin coating or molding. In some embodiments, the material of the filling material 250 includes silicon oxide, silicon nitride, epoxy resin, phenol resin or silicone resin. In some embodiments, the filling material 250 covers at least the top surface of the wafer 100C, fills the gaps between the die 200 and covers the sidewalls of the die 200. In some embodiments, the filling material 250 completely covers the die 200 on the wafer 100C, and a planarization process is performed to partially remove the filling material 250 and a portion of the die 200. For example, the planarization process includes performing a grinding process (grinding) or a polishing process (polishing), such as a chemical mechanical polishing process. After planarization, the backside of the die 200 is ground and exposes the TSVs 204. In some embodiments, the planarized fill material 250 at least laterally covers the sidewalls of the die 200 bonded to the wafer 100C.

[0051] refer to Fig.12After the bonding process, the aligned bonding pads 1069C and 2069 are heated and bonded to form a bonding pad 207 having a fused core pad 2072 without a distinct interface. In some embodiments, through the heating of the bonding process, in the presence of the locking auxiliary patterns 2066 and 1066C, the main pads 2068 and 1068C are fused and merged into a complete fused core pad 2072 without a distinct interface. Fig.12 In the enlarged view at the bottom, it can be seen that for the bonded bonding pad 207, the metal substrate patterns 2065 and 1065C are bonded to form a combined metal shell 2074, and the remaining locking auxiliary patterns 2066 and 1066C (see Fig.11 ) into a locking pattern 2070, and as the large grains grow across the previous contact surface, the resulting molten and homogeneous fused core pad 2072 has little (or no) bonding interface, which results in a molten bonding pad 207 having a stronger bonding strength. By forming a bonding pad 207 fused with a homogeneous fused core pad 2072, a stronger and more reliable bond is established between the die 200 and the wafer 100C. It is understood that the area / size of the bonding pad 1069C of the wafer 100C may be larger than the area / size of the bonding pad 2069 of the die 200. The span range of the main pads 1068C and 2068 may also be different but matched (i.e., mostly overlap but not exactly the same or completely overlap).

[0052] By forming a locking assist pattern inside the bonding pad of the bonding structure, a high-quality bond is established for a semiconductor structure manufactured using a die-to-wafer process or a wafer-to-wafer process. In addition, a stronger bond is achieved between different types of dies in a semiconductor stacking structure (such as a multiple die stacking structure, a system integrated chip or a 3D integrated chiplet).

[0053] refer to Fig.13In some embodiments, a redistribution layer (RDL) 240 is formed over the molding structure 300 and on the filling material 250 and the die 200. The redistribution layer (RDL) 240 is electrically connected to the die 200 through at least the TSV 2041. In some embodiments, the RDL 240 includes a redistribution metal pattern 242 embedded in the dielectric material layer 241. The redistribution metal pattern or the structural configuration is not limited by the present disclosure, and the dielectric material layer may include more than one layer or dielectric material. For example, the redistribution metal pattern 242 includes a wiring metal pattern, a via, and a metal pad. In some embodiments, the dielectric material layer 241 exposes some of the underlying redistribution metal pattern 242, and forms a conductive terminal 260 on the exposed redistribution metal pattern 242. In some embodiments, the conductive terminal 260 includes a metal pillar 261 and a bump 262. In some embodiments, the material of dielectric material layer 241 includes silicon oxide, silicon nitride, low dielectric constant dielectric material, benzocyclobutene (BCB), epoxy resin, polyimide (PI) or polybenzoxazole (PBO). In some embodiments, the material of metal pillar 261 includes copper or copper alloy, and the material of bump 262 includes solder. In one embodiment, metal pillar 261 and bump 262 located on metal pillar 261 constitute micro bumps. In some embodiments, conductive terminal 260 includes copper pillar bumps.

[0054] Subsequently, in some embodiments, reference Fig.13 and Fig.14 , a singulation process is performed to cut the molded structure 300 and cut through the RDL 240 along the scribe line DL into individual three-dimensional (3D) stacked structures 30. In an exemplary embodiment, referring to FIG. Fig.13 As shown in FIG. 1 , an exemplary configuration including at least one die 200 in one die unit (defined by dicing lines DL) is provided. After singulation, each singulated 3D stacked structure 30 includes at least one die 200 stacked on a semiconductor die 10D, and a filling material 250 surrounds the die 200. In some embodiments, the singulation process includes a wafer cutting process or a sawing process.

[0055] Although the steps or methods are illustrated and described as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted as limiting. In addition, not all of the processes or steps shown are required to implement one or more embodiments of the present disclosure. In addition, although the process shown belongs to a chip-to-wafer (CoW) process, it can be further manufactured into a 3D stacked package or a chip-to-wafer-to-substrate (CoWoS) package.

[0056] In some embodiments, an electrical connection path is established between the semiconductor dies 10D and 200 of the 3D stacked structure 30 via the metallization structures 104C and 204 and the bonding structures 106C and 206. For the obtained 3D stacked structure 30, a strong bond is established between the dies 10D and 200 through the fusion bonding pad 207 including the homogeneous fusion core pad 2072 without a distinct interface, and better reliability and satisfactory electrical performance are provided.

[0057] According to the embodiments of the present disclosure, forming an additional locking assist pattern in the bonding pad enhances the bonding strength and reduces poor bonding due to voids occurring at the bonding interface.

[0058] In some embodiments of the present disclosure, a stacked structure is provided. The stacked structure includes a first tube core and a second tube core stacked on the first tube core. The first tube core includes a first substrate and a first bonding structure located above the first substrate. The second tube core includes a second substrate and a second bonding structure located above the second substrate. The first and second tube cores are bonded through the bonded first and second bonding structures. The bonded first and second bonding structures include a fusion bonding pad having a homogeneous core pad and a locking pattern surrounding the homogeneous core pad.

[0059] In some embodiments of the present disclosure, a stacking structure is provided. The stacking structure includes a first die and a second die stacked on the first die and bonded to the first die. The first die has a first bonding structure, the first bonding structure includes a first bonding pad embedded in a first dielectric material, and the first bonding pad includes a first auxiliary pattern and a first metal material. The second die has a second bonding structure, the second bonding structure includes a second bonding pad embedded in a second dielectric material, and the second bonding pad includes a second auxiliary pattern and a second metal material. The first and second dies are bonded through bonded first and second bonding structures, the bonded first and second bonding structures have bonded first and second bonding pads embedded in bonded first and second dielectric materials. The bonded first and second bonding pads include bonded first and second auxiliary patterns and a fusion core pad, the fusion core pad includes first and second metal materials and is surrounded by the bonded first and second auxiliary patterns.

[0060] In some embodiments of the present disclosure, a manufacturing method for forming a stacked structure is described. A first wafer having a plurality of first tube cores is provided. Each first tube core has a first bonding structure, the first bonding structure includes a first bonding pad embedded in a first dielectric material, and the first bonding pad includes a first inner metal pattern, a first outer metal pattern, and a first auxiliary pattern sandwiched between the first inner and outer metal patterns. A plurality of second tube cores are provided. Each second tube core has a second bonding structure, the second bonding structure includes a second bonding pad embedded in a second dielectric material, and the second bonding pad includes a second inner metal pattern, a second outer metal pattern, and a second auxiliary pattern sandwiched between the second inner and outer metal patterns. The second bonding pad of the second tube core is aligned with the first bonding pad of the first tube core. The second tube core is bonded to the first tube core by bonding the first and second dielectric materials of the first and second bonding structures and bonding the first and second bonding pads, wherein the first and second bonding pads are bonded to form a fusion core pad by merging the first and second inner metal patterns, and the first and second auxiliary patterns are retained and located around the fusion core pad. A singulation process is performed to form individual stacked structures.

[0061] It will be apparent to those skilled in the art that various modifications and changes may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover the modifications and changes provided within the scope of the above claims and their equivalents.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A stacking structure, characterized in that: include: a first die, wherein the first die comprises a first substrate and a first bonding structure located on the first substrate; as well as a second tube die stacked on the first tube die, wherein the second tube die comprises a second substrate and a second bonding structure located above the second substrate, The first and second dies are bonded through the bonded first and second bonding structures, and the bonded first and second bonding structures include a fusion bonding pad having a homogeneous core pad and a locking pattern surrounding the homogeneous core pad.

2. The stacking structure according to claim 1, characterized in that: The material of the homogeneous core pad is different from the material of the locking pattern.

3. The stacking structure according to claim 2, characterized in that: The fusion bonding pad includes a metal substrate pattern surrounding and covering the locking pattern.

4. The stacking structure according to claim 3, characterized in that: The metal substrate pattern includes a metal pattern and a barrier pattern surrounding and covering the metal pattern.

5. The stacking structure according to claim 1, characterized in that: The first bonding structure includes a first metallization structure located above the first substrate, the second bonding structure includes a second metallization structure located above the second substrate, and the first and second dies are electrically connected through the fusion bonding pad and the first and second metallization structures connected to the fusion bonding pad.

6. The stacking structure according to claim 5, characterized in that: It also includes a redistribution wiring structure formed on the second tube core, the second metallization structure includes a through-semiconductor via, and the redistribution wiring structure is electrically connected to the second tube core through the through-semiconductor via.

7. A stacking structure, characterized in that: include: The first die has a first bonding structure, the first bonding structure includes a first bonding pad embedded in a first dielectric material, and the first bonding pad includes a first auxiliary pattern and a first metal material; as well as a second die stacked on the first die and bonded to the first die, wherein the second die has a second bonding structure, the second bonding structure includes a second bonding pad embedded in a second dielectric material, and the second bonding pad includes a second auxiliary pattern and a second metal material, The first and second dies are bonded through the bonded first and second bonding structures, the bonded first and second bonding structures have the first and second bonding pads embedded in the bonded first and second dielectric materials, the bonded first and second bonding pads include the bonded first and second auxiliary patterns and a fusion core pad, the fusion core pad includes the first and second metal materials, and is surrounded by the bonded first and second auxiliary patterns.

8. The stacking structure according to claim 7, characterized in that: The fusion core pad includes a homogeneous metal block having large grains therein.

9. The stacking structure according to claim 7, characterized in that: A material of the fusion core pad is different from a material of the first auxiliary pattern and a material of the second auxiliary pattern, and the bonded first and second bonding pads include a metal shell surrounding the bonded first and second auxiliary patterns and the fusion core pad.

10. A method for manufacturing a stacked structure, characterized in that: include: providing a first wafer having a plurality of first dies, each first die having a first bonding structure including a first bonding pad embedded in a first dielectric material, and the first bonding pad including a first inner metal pattern, a first outer metal pattern, and a first auxiliary pattern sandwiched between the first inner and outer metal patterns; providing a plurality of second dies, wherein each second die has a second bonding structure including a second bonding pad embedded in a second dielectric material, the second bonding pad including a second inner metal pattern, a second outer metal pattern, and a second auxiliary pattern sandwiched between the second inner and outer metal patterns; aligning the second bond pad of the second die with the first bond pad of the first die; Bonding the second die to the first die by bonding the first and second dielectric materials of the first and second bonding structures and bonding the first and second bonding pads, wherein the first and second bonding pads are bonded to form a fusion core pad by merging the first and second inner metal patterns, and the first and second auxiliary patterns are retained and located around the fusion core pad; And a singulation process is performed to form individual stacked structures.

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