Semiconductor device

Abstract

The present disclosure provides a semiconductor device in which the efficiency of an amplifier is less likely to decrease. A semiconductor device includes: a transistor provided on a main surface of a substrate having the main surface and having a first electrode including an ohmic electrode; the MIM capacitor is formed on the transistor and is provided with a second electrode, a first insulating layer arranged on the second electrode and a third electrode arranged on the first insulating layer; the second insulating layer is arranged between the first electrode and the second electrode; and a plurality of vias penetrating the second insulating layer and electrically connecting the first electrode and the second electrode to each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a technology related to a semiconductor element having a MIM capacitor. The technology includes a MIM capacitor, which is formed on a semiconductor substrate and is composed of a lower electrode, a dielectric film, and an upper electrode. On the upper electrode of the MIM capacitor, there are formed: a first interlayer insulating film having a first via hole; and a second interlayer insulating film having a second via hole. On the second interlayer insulating film, there is formed a wiring layer connected to the upper electrode through the first via hole and the second via hole, and the vertical distance between the lower electrode of the MIM capacitor and the wiring layer becomes larger.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-193563

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2011-165931

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2004-022773

[0008] Patent Document 4: Japanese Patent Application Laid-Open No. 2017-059621

[0009] In the past, in amplifiers, transistors such as HEMT (High Electron Mobility Transistor) and MIM (Metal-Insulator-Metal) capacitors were arranged on a substrate in a direction along the substrate surface and connected via routing wiring. As the routing wiring becomes longer, the inductance component of the circuit becomes larger. Due to the influence of this inductance component, the impedance adjustment becomes complicated and the wiring length tends to become longer. As the wiring length becomes longer, the loss increases and the efficiency of the amplifier tends to decrease. Summary of the invention

[0010] An object of the present disclosure is to provide a semiconductor device in which the efficiency of an amplifier is unlikely to decrease.

[0011] A semiconductor device of one embodiment of the present disclosure comprises: a transistor, which is arranged on a main surface of a substrate having a main surface, and has a first electrode including an ohmic electrode; a MIM capacitor, which is formed on the transistor, and has a second electrode, a first insulating layer arranged on the second electrode, and a third electrode arranged on the first insulating layer; a second insulating layer, which is arranged between the first electrode and the second electrode; and a plurality of vias, which penetrate the second insulating layer and electrically connect the first electrode and the second electrode to each other.

[0012] Effects of the Invention

[0013] According to the present disclosure, it is possible to provide a semiconductor device in which the efficiency of an amplifier is unlikely to decrease. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment of the present disclosure.

[0015] Figure 2 This is a circuit diagram of the semiconductor device according to the first embodiment.

[0016] Figure 3 It is along Figure 1 A cross-sectional view taken along line III-III is shown.

[0017] Figure 4 is a top view showing a transistor.

[0018] Figure 5 It is along Figure 1 A cross-sectional view taken along line V-V is shown.

[0019] Figure 6 It is along Figure 1 A cross-sectional view taken along line VI-VI is shown.

[0020] Figure 7 It is a plan view showing a semiconductor device according to a second embodiment.

[0021] Figure 8 This is a circuit diagram of a semiconductor device according to a second embodiment.

[0022] Fig. 9 It is along Figure 7 A cross-sectional view taken along line IX-IX is shown.

[0023] Fig.10 It is a plan view showing an amplifier of the semiconductor device according to the third embodiment.

[0024] Fig.11 It is along Fig.10 A cross-sectional view taken along line XI-XI is shown.

[0025] Fig.12is a plan view showing a semiconductor device as a comparative example.

[0026] Fig.13 is a circuit diagram of a semiconductor device as a comparative example.

[0027] Fig.14 It is a Smith chart showing the impedance characteristics of the semiconductor device according to the first embodiment and a semiconductor device as a comparative example.

[0028] Fig.15 This is a circuit diagram of an amplifier circuit used as a verification example.

[0029] Fig.16 It is a diagram showing the characteristics of an amplifier circuit as a verification example.

[0030] Fig.17 This is a circuit diagram of a Doherty amplifier circuit as a verification example.

[0031] Fig.18 : is a graph showing the characteristics of a Doherty amplifier circuit as a verification example.

[0032] Description of Reference Numerals

[0033] 1, 1B, 1C, 1D: amplifier;

[0034] 2: Bias circuit;

[0035] 3: Ground potential line;

[0036] 4: Filter circuit;

[0037] 5: splitter;

[0038] 6: Wiring;

[0039] 7: Gate bias circuit;

[0040] 8: Substrate;

[0041] 9: Main side;

[0042] 10: Transistor;

[0043] 11: drain electrode;

[0044] 12: source electrode;

[0045] 13: gate electrode;

[0046] 14: Field plate;

[0047] 15: Input terminal;

[0048] 16: Wiring;

[0049] 17: vias;

[0050] 20, 20A, 20D: MIM capacitors;

[0051] 21, 21B: lower electrode;

[0052] 22, 22B: dielectric layer;

[0053] 23, 23B: upper electrode;

[0054] 24: Part I;

[0055] 25: Part II;

[0056] 32, 33, 34: Wiring;

[0057] 35: Ohm electrode;

[0058] 37: back electrode;

[0059] 38, 39: insulation layer;

[0060] 39a: Opening;

[0061] 40: Inductor;

[0062] 51: soldering pad;

[0063] 52: external power supply;

[0064] 60: MIM capacitor;

[0065] 72, 74, 76: output terminals;

[0066] 73, 75: input terminals;

[0067] 81, 82: vias;

[0068] 100: wiring portion;

[0069] A, B, C, D: semiconductor devices;

[0070] E: amplifier circuit;

[0071] F: Doherty amplifier circuit;

[0072] F1, F2: amplifier circuit;

[0073] L1, L2, L3, L4: curve;

[0074] S1: design value;

[0075] S2: relay value;

[0076] S3: Target value. DETAILED DESCRIPTION

[0077] [Description of Embodiments of the Present Disclosure]

[0078] First, the contents of the embodiments of the present disclosure are listed for explanation. [1] A semiconductor device of one embodiment of the present disclosure comprises: a transistor, which is provided on a main surface of a substrate having a main surface, and has a first electrode including an ohmic electrode; a MIM capacitor, which is formed on the transistor, and has a second electrode, a first insulating layer provided on the second electrode, and a third electrode provided on the first insulating layer; a second insulating layer, which is provided between the first electrode and the second electrode; and a plurality of vias, which penetrate the second insulating layer and electrically connect the first electrode and the second electrode to each other.

[0079] In the semiconductor device of [1] above, the MIM capacitor is formed on the transistor, and the transistor and the MIM capacitor are electrically connected through a plurality of vias. Thus, the distance between the transistor and the MIM capacitor is shorter than the distance between the transistor and the MIM capacitor when the MIM capacitor and the transistor are arranged in a direction along the main surface and the transistor and the MIM capacitor are connected by routing wiring. Therefore, compared with the case where the transistor and the MIM capacitor are connected by routing wiring, the size of the inductance component between the transistor and the MIM capacitor in the configuration of the semiconductor device of [1] becomes smaller. Therefore, the loss can be reduced, and thus a semiconductor device in which the efficiency of the amplifier is not easily reduced can be realized.

[0080] In addition, the surface of the ohmic electrode becomes rough due to annealing during manufacturing, so the surface of the first electrode also becomes rough, but in the film formation process of the second insulating layer provided between the first electrode and the second electrode, the surface of the second insulating layer is not easy to inherit the state of the surface of the first electrode. That is, even if the surface of the first electrode is uneven, the surface of the second insulating layer can be made nearly flat. Thus, the surface of the second electrode formed on the second insulating layer can also be made flat. Therefore, the local increase of the electric field can be suppressed, and the reliability of the MIM capacitor can be improved.

[0081] Furthermore, by sandwiching a plurality of vias between the first electrode and the second electrode, the total cross-sectional area of ​​the plurality of vias along the main surface becomes larger than that of a single via, so that current can flow easily between the first electrode and the second electrode. Therefore, the loss can be reduced and the efficiency of the amplifier can be suppressed from decreasing.

[0082] [2] In the semiconductor device of [1] above, the MIM capacitor may be arranged in a manner avoiding the gate electrode of the transistor. Thus, the parasitic capacitance generated between the MIM capacitor and the gate electrode can be reduced. Therefore, by reducing the inductance component and the parasitic capacitance at the same time, the efficiency reduction of the amplifier can be further suppressed.

[0083] [3] In the semiconductor device of [1] above, the MIM capacitor may be accommodated on the first electrode when viewed from a direction perpendicular to the main surface. Thus, the portion forming the MIM capacitor is limited to the first electrode, thereby reducing the parasitic capacitance generated between the MIM capacitor and the area other than the first electrode. Therefore, by reducing the inductance component and the parasitic capacitance, the efficiency of the amplifier can be further suppressed.

[0084] [4] In the semiconductor device of [1] above, the MIM capacitor may include: a first portion, which is accommodated on the first electrode when viewed from a direction perpendicular to the main surface; and a second portion, which is continuous with the first portion and is arranged outside the transistor when viewed from a direction perpendicular to the main surface. Thus, in both the first portion and the second portion, the parasitic capacitance generated between the MIM capacitor and the area outside the first electrode can be reduced. In addition, by having the second portion in addition to the first portion, the area of ​​the electrode of the MIM capacitor is increased, and the capacitance of the MIM capacitor can be increased. In the semiconductor device of [4], the MIM capacitor is provided, for example, for the purpose of DC cut. By increasing the capacitance of the MIM capacitor, the cut-off frequency becomes lower. Therefore, DC cut-off can be performed at a lower frequency, and DC cut-off can be performed within a wider frequency band.

[0085] [5] In the semiconductor devices of [1] to [4] above, the transistor may be a high electron mobility transistor (HEMT) including a III-V semiconductor. Generally speaking, a HEMT can withstand high voltages and can handle large currents, thereby enabling high output power amplification. Therefore, by using a HEMT as the transistor, the efficiency of the amplifier can be further improved.

[0086] [6] In the semiconductor devices of [1] to [5] above, the dielectric constant of the first insulating layer may be greater than the dielectric constant of the second insulating layer. Thus, the capacitance of the MIM capacitor can be further increased. In the semiconductor device of [6], the MIM capacitor is provided, for example, for the purpose of DC cutoff. As the capacitance of the MIM capacitor increases, the cutoff frequency becomes lower. Therefore, DC cutoff can be performed at a lower frequency, and DC cutoff can be performed within a wider frequency band.

[0087] [7] In the semiconductor devices of [1] to [6] above, the thickness of the first insulating layer in the direction perpendicular to the main surface may be thinner than the thickness of the second insulating layer in the direction perpendicular to the main surface. By reducing the thickness of the first insulating layer, the capacitance of the MIM capacitor can be increased. In the semiconductor device of [7], the MIM capacitor is provided, for example, for the purpose of DC cutoff. As the capacitance of the MIM capacitor increases, the cutoff frequency becomes lower. Therefore, DC cutoff can be performed at a lower frequency, and DC cutoff can be performed within a wider frequency band.

[0088] [8] In the semiconductor devices of [1] to [7] above, the thickness of the second electrode in the direction perpendicular to the main surface may be thinner than the thickness of the first electrode in the direction perpendicular to the main surface. By reducing the thickness of the second electrode, the film formation time of the insulating layer in which the second electrode is buried can be shortened.

[0089] [9] In the semiconductor devices of [1] to [8] above, the length of the plurality of vias in the direction perpendicular to the main surface may be greater than 0.1 μm and less than 10 μm. When the transistor and the MIM capacitor are connected by routing wiring, the distance between the transistor and the MIM capacitor is likely to be a long distance such as several hundred μm or more. In contrast, according to the semiconductor device of [1] above, the distance of the wiring (via) between the transistor and the MIM capacitor can be shortened, for example, as in [9] above. Thus, a semiconductor device in which the efficiency of the amplifier is not easily reduced can be realized.

[0090] [Details of the embodiments of the present disclosure]

[0091] Hereinafter, specific examples of the semiconductor device disclosed in the present invention will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, in the description of the drawings, the same reference numerals are marked on the same elements, and repeated descriptions are omitted.

[0092] (First Embodiment)

[0093] Figure 1 It is a plan view showing a semiconductor device A according to the first embodiment of the present disclosure. Figure 2 1 is a circuit diagram of a semiconductor device A according to a first embodiment of the present disclosure. The semiconductor device A includes an amplifier 1, a bias circuit 2, an input terminal 15, and an output terminal 72. The input terminal 15 is provided on the input side of the amplifier 1, and the output terminal 72 is provided on the output side of the amplifier 1.

[0094] The amplifier 1 includes a transistor 10 and a plurality of (two in the example shown) MIM capacitors 20. The bias circuit 2 includes an inductor 40, a MIM capacitor 60, an external power supply 52 (see Figure 2 ) and a pad 51 for connecting to an external power source 52 (see Figure 1 ). In the transistor 10, the gate is connected to the input terminal 15. The source is connected to the ground potential line 3 (see Figure 2 ). The drain is connected to the first electrode of each MIM capacitor 20, and is connected to one end of the inductor 40 of the bias circuit 2 via the wiring 33. The second electrode of each MIM capacitor 20 is connected to the output terminal 72 via the wiring 32. The other end of the inductor 40 is connected to the first electrode of the MIM capacitor 60, and is connected to the positive electrode of the external power supply 52 via the pad 51. The inductor 40 is, for example, a spiral inductor. The second electrode of the MIM capacitor 60 and the negative electrode of the external power supply 52 are connected to the ground potential line 3.

[0095] Figure 3 It is along Figure 1 The amplifier 1 includes a substrate 8 having a main surface 9 and a back surface 18. The transistor 10 is provided on the main surface 9 of the substrate 8. The transistor 10 includes a plurality of (two in the example shown in the figure) drain electrodes 11, a plurality of (three in the example shown in the figure) source electrodes 12, a plurality of (four in the example shown in the figure) gate electrodes 13, and a semiconductor layer 19. The plurality of drain electrodes 11 and the plurality of source electrodes 12 are alternately arranged in a predetermined direction y, and a gap is provided between each drain electrode 11 and each source electrode 12. Each gate electrode 13 is arranged in the gap between the drain electrode 11 and the source electrode 12. The drain electrode 11 (first electrode) and the source electrode 12 are respectively configured to include an ohmic electrode 35 and a wiring 16. The transistor 10 is, for example, a high electron mobility transistor HEMT including a III-V semiconductor in the semiconductor layer 19. The semiconductor layer 19 is composed of, for example, a semiconductor such as GaAs, InGaAs, AlGaAs, and GaN.

[0096] The ohmic electrode 35 is provided on the semiconductor layer 19. The ohmic electrode 35 is in a film shape. The material of the ohmic electrode 35 is, for example, titanium (Ti) or nickel (Ni). The wiring 16 is provided on the ohmic electrode 35 and is connected to the ohmic electrode 35. The material of the wiring 16 is, for example, gold (Au). The thickness of the wiring 16 in the direction perpendicular to the main surface 9 is, for example, greater than 0.1 μm and less than 10 μm. The width W of the wiring 16 along the y direction, which is the arrangement direction of the drain electrode 11, the source electrode 12, and the gate electrode 13, is, for example, greater than 1 μm and less than 1000 μm. The area of ​​the wiring 16 when observed from the direction perpendicular to the main surface 9 is, for example, 1 μm 2 Above and 1000000μm 2 the following.

[0097] The amplifier 1 further includes a field plate 14, a back electrode 37, and a via 17. The field plate 14 is provided on the gate electrode 13 and between the gate electrode 13 and the drain electrode 11. The field plate 14 is set as a reference potential to control the distribution of the electric field. The back electrode 37 is provided to cover the entire surface on the back surface 18 of the substrate 8. The back electrode 37 is connected to Figure 2 The ground potential line 3 shown is thus defined as a reference potential. The via 17 is provided to penetrate the substrate 8 and the semiconductor layer 19 from the back surface 18 of the substrate 8 toward the source electrode 12. The via 17 is connected to the back surface electrode 37 and the ohmic electrode 35 of the source electrode 12. That is, the source electrode 12 is connected to the ground potential line 3 via the via 17 and the back surface electrode 37.

[0098] Figure 4 1 is a top view showing the transistor 10. Each drain electrode 11 and each source electrode 12 is in the form of a rectangular shape that is long in the x direction and intersects the y direction and is along the main surface 9. One end in the x direction of the wiring 16 of the plurality of source electrodes 12 is connected to each other through a wiring 91 that is long in the y direction and is provided in a region outside the ohmic electrode 35. One end in the x direction of the plurality of gate electrodes 13 is connected to each other through a wiring 92 that is long in the y direction. The input terminal 15 (see Figure 1 and Figure 2 ) is connected to the gate electrode 13 via the wiring 92.

[0099] Refer again Figure 3. The amplifier 1 also has a plurality of vias 81, an insulating layer 38, and an insulating layer 39. The insulating layer 38 (second insulating layer) is provided between the wiring 16 and the lower electrode 21 (described later) of the MIM capacitor 20. That is, the insulating layer 38 is provided on the drain electrode 11 and the source electrode 12. Moreover, the insulating layer 38 is also provided on the gate electrode 13 and is provided to extend over the entire semiconductor layer 19. The material of the insulating layer 38 is, for example, an insulating material containing Si such as SiO2, SiN, SiON, or a resin material such as polyimide. The insulating layer 39 is provided on the insulating layer 38. The insulating layer 39 is provided to extend over the entire insulating layer 38. The material of the insulating layer 39 is, for example, an insulating material containing Si such as SiO2, SiN, SiON, or a resin material such as polyimide. The plurality of vias 81 penetrate the insulating layer 38 to electrically connect the wiring 16 to the lower electrode 21. That is, the plurality of vias 81 are sandwiched between the wiring 16 and the lower electrode 21. When viewed from a direction perpendicular to the main surface 9, a plurality of vias 81 are accommodated on the drain electrode 11. The length of the via 81 in the direction perpendicular to the main surface 9 is, for example, greater than 0.1 μm and less than 10 μm. In addition, the diameter of each via 81 is, for example, greater than 0.5 μm and less than 10 μm. The number of vias 81 is, for example, greater than 1 and less than 1,000,000. The material of the member constituting the via 81 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, Cr, Co, and Ru.

[0100] Each MIM capacitor 20 includes a lower electrode 21 (second electrode), a dielectric layer 22 (first insulating layer), and an upper electrode 23 (third electrode). Each MIM capacitor 20 is formed on each drain electrode 11. When viewed from a direction perpendicular to the main surface 9, the MIM capacitor 20 is a rectangular shape that is long along the x direction (see Figure 1 ) Each MIM capacitor 20 of the present embodiment is provided in the amplifier 1 for the purpose of direct current blocking.

[0101] Each MIM capacitor 20 is arranged in a manner avoiding the gate electrode 13 of the transistor 10. As in the present embodiment, in one example, when viewed from a direction perpendicular to the main surface 9, each MIM capacitor 20 is accommodated on the drain electrode 11 of the transistor 10. The lower electrode 21 is provided between the insulating layer 38 and the insulating layer 39. The material of the lower electrode 21 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd and Cr. In the y direction, the width of the lower electrode 21 is the same as the width of the drain electrode 11 or is less than the width of the drain electrode 11. The width of the lower electrode 21 along the y direction is, for example, greater than 1 μm and less than 1000 μm. The area of ​​the lower electrode 21 when viewed from a direction perpendicular to the main surface 9 is, for example, 1 μm 2 Above and 1000000μm 2The thickness of the lower electrode 21 in the direction perpendicular to the main surface 9 is thinner than the thickness of the wiring 16 in the direction. The thickness of the lower electrode 21 in the direction is, for example, 0.1 μm or more and 10 μm or less.

[0102] The dielectric layer 22 is provided between the insulating layer 38 and the insulating layer 39, and is formed so as to extend over the insulating layer 38 and the lower electrode 21, and the dielectric layer 22 is in contact with the entire area of ​​the surface of the lower electrode 21 that is opposite to the upper electrode 23. In other words, the lower electrode 21 is in contact with the insulating layer 38 on the surface connected to the plurality of vias 81, and is in contact with the dielectric layer 22 on all surfaces along the x direction other than the surface. The material of the dielectric layer 22 is, for example, an insulating material containing Si such as SiO2, SiN, and SiON, or a resin material such as polyimide, or a metal oxide such as hafnium oxide (HfO2) and aluminum oxide (Al2O3).

[0103] The upper electrode 23 is provided on the lower electrode 21 and on the dielectric layer 22. The upper electrode 23 has a portion provided on the insulating layer 39 and a portion provided along the surface of the opening 39a formed in the insulating layer 39. In addition, the upper electrode 23 also has a portion in contact with the dielectric layer 22 at the bottom of the opening 39a. When viewed from a direction perpendicular to the main surface 9, the opening 39a is accommodated on the lower electrode 21. The material of the upper electrode 23 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd and Cr.

[0104] The thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 is thinner than the thickness of the insulating layers 38 and 39 in the direction. The thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the insulating layer 38 in the direction is, for example, 0.2 μm or more and 10 μm or less. The thickness of the insulating layer 39 in the direction is, for example, 0.1 μm or more and 10 μm or less. In addition, the dielectric constant of the dielectric layer 22 is greater than the dielectric constants of the insulating layers 38 and 39. The dielectric constant of the dielectric layer 22 is, for example, 20 p(pico)F / m or more and 500 p(pico)F / m or less. The dielectric constant of the insulating layer 38 is, for example, 10 p(pico)F / m or more and 200 p(pico)F / m or less. The dielectric constant of the insulating layer 39 is, for example, 10 p(pico)F / m or more and 200 p(pico)F / m or less.

[0105] Figure 5 It is along Figure 1 A cross-sectional view taken along line V-V is shown. Figure 6 It is along Figure 1A cross-sectional view along the line VI-VI is shown. In addition to the aforementioned wiring 32 and wiring 33, the amplifier 1 further includes a plurality of vias 82 and a wiring 34. The wiring 34, the plurality of vias 82, the wiring 33, and the wiring 32 are provided between the transistor 10 and the MIM capacitor 20 and the output terminal 72. The wiring 34 is formed integrally with the wiring 16 in the same wiring layer as the wiring 16, and extends from the wiring 16 toward the outside of the transistor 10. The wiring 33 is provided on the wiring 34. The wiring 33 is formed integrally with the lower electrode 21 in the same wiring layer as the lower electrode 21, and extends from the lower electrode 21 toward the outside of the transistor 10. One end of the wiring 33 is connected to the lower electrode 21. The other ends of the wiring 33 and the wiring 34 are connected to the inductor 40 of the bias circuit 2 (see Figure 1 ) at one end. Wiring 33 functions as a transmission line for direct current. A plurality of vias 82 are sandwiched between wiring 34 and wiring 33 and are dispersed throughout the wiring 34 and wiring 33. A plurality of vias 82 are provided to penetrate insulating layer 38 (see Figure 3 ), interconnecting the wiring 34 and the wiring 33. The wiring 32 is provided on the wiring 33. The wiring 32 is formed integrally with the upper electrode 23 in the same wiring layer as the upper electrode 23, and extends from the upper electrode 23 toward the outside of the transistor 10. Figure 1 One end of the wiring 32 is connected to the upper electrode 23 of each MIM capacitor 20. The other end of the wiring 32 is connected via the inductor 90 (at Figure 1 The wiring 32 is connected to the output terminal 72. The wiring 32 functions as a transmission path for the signal amplified in the transistor 10 (RF (Radio Frequency) signal).

[0106] Effects obtained by the semiconductor device A having the above configuration will be described. Fig.12 1 is a plan view showing a semiconductor device D as a comparative example. Fig.13 : is a circuit diagram of a semiconductor device D as a comparative example. The semiconductor device D is different from the semiconductor device A in the following points. The semiconductor device D includes an amplifier 1D instead of the amplifier 1. The amplifier 1D includes a MIM capacitor 20D instead of the MIM capacitor 20. The MIM capacitor 20D is not provided on the transistor 10 but is provided outside the transistor 10. In addition, the amplifier 1D includes a routing wiring portion 100 that connects the transistor 10 and the MIM capacitor 20D. In the semiconductor device D, the routing wiring portion 100 is longer, so the inductance component (at Fig.12 The inductor symbol in the figure increases. Due to the influence of this inductance component, the impedance adjustment becomes complicated and the wiring length tends to be longer. As the wiring length becomes longer, the loss increases and the efficiency of the amplifier 1D tends to decrease.

[0107] In contrast, in the semiconductor device A described above, the MIM capacitor 20 is formed on the transistor 10, and the drain electrode 11 of the transistor 10 and the lower electrode 21 of the MIM capacitor 20 are electrically connected through a plurality of vias 81. Thus, the distance between the transistor 10 and the MIM capacitor 20 is shorter than the distance between the transistor 10 and the MIM capacitor 20D in the case where the drain electrode 11 and the lower electrode 21 are connected through the routing wiring portion 100. Therefore, the magnitude of the inductance component between the transistor 10 and the MIM capacitor 20 in the configuration of the semiconductor device A becomes smaller than in the case where the transistor 10 and the MIM capacitor 20D are connected through the routing wiring portion 100. Therefore, the loss can be reduced, and thus the semiconductor device A in which the efficiency of the amplifier is not easily reduced can be realized.

[0108] In addition, the surface of the ohmic electrode 35 becomes rough due to annealing during manufacturing, so the surface of the wiring 16 also becomes rough, but in the film formation process of the insulating layer 38 provided between the wiring 16 and the lower electrode 21, the surface of the insulating layer 38 is not easy to inherit the state of the surface of the wiring 16. That is, even if the surface of the wiring 16 has unevenness, the surface of the insulating layer 38 can be made nearly flat. As a result, the surface of the lower electrode 21 formed on the insulating layer 38 can also be made flat. Therefore, it is possible to suppress the local increase of the electric field and improve the reliability of the MIM capacitor 20.

[0109] Furthermore, by sandwiching a plurality of via holes 81 between the drain electrode 11 and the lower electrode 21, the total cross-sectional area of ​​the plurality of via holes 81 along the plane of the main surface 9 becomes larger than that of a single via hole, so that current easily flows between the wiring 16 and the lower electrode 21. Therefore, the loss can be reduced, and the reduction in the efficiency of the amplifier 1 can be suppressed.

[0110] Fig.14 : is a Smith chart showing the impedance characteristics of the semiconductor device A according to the first embodiment and the semiconductor device D as a comparative example. Fig.14 , the design value S1, the intermediate value S2, and the target value S3 are shown. In the semiconductor device D, due to the influence of the inductance component generated by the routing wiring portion 100, the impedance follows a moving path from the design value S1 via the intermediate value S2 and finally reaches the target value S3. Therefore, the moving path of the impedance is likely to become longer. In contrast, in the semiconductor device A, a plurality of vias 81 are provided instead of the routing wiring portion 100, so the impedance follows a moving path directly from the design value S1 to the target value S3. Therefore, the moving path of the impedance becomes shorter, so the wiring length can be shortened. Since the wiring length is short, the loss can be reduced. Therefore, according to this embodiment, a semiconductor device A in which the efficiency of the amplifier 1 is not easily reduced can be realized.

[0111] Fig.152 is a circuit diagram of an amplifier circuit E as a verification example. The amplifier circuit E includes an input terminal 73 , an output terminal 74 , a filter circuit 4 , a bias circuit 2 , an amplifier 1D of a comparative example, and a gate bias circuit 7 . Fig.16 It is a diagram showing the characteristics (relationship between output power and efficiency) of an amplifier circuit E as a verification example. Fig.16 The curve L1 and the curve L2 are shown in FIG. The curve L2 represents Fig.15 The characteristic of the amplifier circuit E shown in FIG. 1 is a curve L1 showing the characteristic of the amplifier circuit E when the amplifier 1 of this embodiment is provided instead of the amplifier 1D. Fig.16 In the curve L1 of FIG. 1 , since a plurality of vias 81 are provided instead of the routing wiring portion 100 , the inductance component is reduced and the loss is reduced. Therefore, the efficiency of the amplifier circuit is improved.

[0112] Fig.17 : is a circuit diagram of a Doherty amplifier circuit F as a verification example. The Doherty amplifier circuit F includes an input terminal 75, an output terminal 76, a branching device 5, a wiring 6, and two amplifier circuits F1 and F2. The amplifier circuits F1 and F2 each include a filter circuit 4, a bias circuit 2, an amplifier 1D of a comparative example, and a gate bias circuit 7. Fig.18 : is a graph showing the characteristics (relationship between output power and efficiency) of a Doherty amplifier circuit F as a verification example. Fig.18 Curve L3 and curve L4 are shown in FIG. Curve L4 represents Fig.17 The curve L3 shows the characteristics of the Doherty amplifier circuit F when the amplifier 1 of this embodiment is provided instead of the amplifier 1D. Fig.18 In the curve L3 of FIG. 1 , since a plurality of vias 81 are provided instead of the routing wiring portion 100 , the inductance component is reduced and the loss is reduced. Therefore, the efficiency of the Doherty amplifier circuit is improved.

[0113] As in this embodiment, the MIM capacitor 20 may be provided so as to avoid being on the gate electrode 13 of the transistor 10. This can reduce the parasitic capacitance generated between the MIM capacitor 20 and the gate electrode 13. Therefore, by reducing the inductance component and the parasitic capacitance, the efficiency of the amplifier 1 can be further suppressed from decreasing.

[0114] As in the present embodiment, the MIM capacitor 20 may be accommodated on the drain electrode 11 of the transistor 10 when viewed from a direction perpendicular to the main surface 9. Thus, the portion where the MIM capacitor 20 is formed is limited to the drain electrode 11, so that it is possible to reduce the parasitic capacitance generated between the MIM capacitor 20 and the area other than the drain electrode 11. Therefore, by reducing the inductance component and the parasitic capacitance, it is possible to further suppress the reduction in efficiency of the amplifier 1.

[0115] As in the present embodiment, the transistor 10 may be a high electron mobility transistor (HEMT) including a III-V semiconductor. Generally speaking, a HEMT can withstand high voltages and can handle large currents, so that high output power can be amplified. Therefore, by using a HEMT as the transistor 10, the efficiency of the amplifier 1 can be further improved.

[0116] As in the present embodiment, the dielectric constant of the dielectric layer 22 may be greater than the dielectric constant of the insulating layers 38 and 39. Thus, the capacitance of the MIM capacitor 20 can be further increased. Therefore, the cutoff frequency becomes lower. Therefore, the DC cutoff can be performed at a lower frequency, and the DC cutoff can be performed in a wider frequency band.

[0117] As in the present embodiment, the thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 may be thinner than the thickness of the insulating layers 38 and 39 in the direction. By reducing the thickness of the dielectric layer 22, the capacitance of the MIM capacitor 20 can be increased. Therefore, the cutoff frequency becomes lower. Therefore, DC cutoff can be performed at a lower frequency, and DC cutoff can be performed in a wider frequency band.

[0118] As in this embodiment, the thickness of lower electrode 21 in the direction perpendicular to main surface 9 may be thinner than the thickness of wiring 16 in the direction. By reducing the thickness of lower electrode 21, the film formation time of insulating layer 39 in which lower electrode 21 is buried can be shortened.

[0119] As in the present embodiment, the length of the via 81 in the direction perpendicular to the main surface 9 may be greater than 0.1 μm and less than 10 μm. In the case where the routing wiring portion 100 is provided between the transistor 10 and the MIM capacitor 20D as in the above-mentioned comparative example, the distance between the transistor 10 and the MIM capacitor 20D is likely to be a long distance such as several hundred μm or more. In contrast, according to the above-mentioned semiconductor device A, the distance of the wiring (via 81) between the transistor 10 and the MIM capacitor 20 can be shortened in this way. Thus, a semiconductor device in which the efficiency of the amplifier 1 is not easily reduced can be realized.

[0120] (Second Embodiment)

[0121] Figure 7 is a top view showing a semiconductor device B according to the second embodiment. Figure 8: is a circuit diagram of a semiconductor device B according to a second embodiment. The semiconductor device B is different from the semiconductor device A in the following points, and is the same as the semiconductor device A in other points. The semiconductor device B includes an amplifier 1B instead of the amplifier 1. The amplifier 1B includes a MIM capacitor 20A instead of the MIM capacitor 20. The other configurations of the amplifier 1B are the same as those of the amplifier 1. The MIM capacitor 20A includes a second portion 25 and two first portions 24. When viewed from a direction perpendicular to the main surface 9, each first portion 24 is accommodated on the drain electrode 11. Each first portion 24 has the same configuration as the MIM capacitor 20 of the above-described embodiment. The second portion 25 is continuous with the first portion 24, and when viewed from a direction perpendicular to the main surface 9, the second portion 25 is provided outside the transistor 10 (specifically, between the transistor 10 and the wiring 32).

[0122] Fig. 9 It is along Figure 7 The cross-sectional view of the line IX-IX is shown. Fig. 9 As shown, the second portion 25 includes a lower electrode 21B, a dielectric layer 22B provided on the lower electrode 21B, and an upper electrode 23B provided on the dielectric layer 22B. The lower electrode 21B of the second portion 25 is formed integrally with the lower electrode 21 of the first portion 24 in the same wiring layer. The lower electrode 21B is connected to the wiring 34 via a plurality of vias 81. The dielectric layer 22B of the second portion 25 is a common dielectric layer with the dielectric layer 22 of the first portion 24. The upper electrode 23B of the second portion 25 is formed integrally with the upper electrode 23 of the first portion 24 in the same wiring layer. When viewed from a direction perpendicular to the main surface 9, the second portion 25 is a rectangular shape that is long in a direction (y direction) intersecting the extension direction (x direction) of the first portion 24.

[0123] In the present embodiment, one end of the wiring 32 is connected to the upper electrode 23B. The other end of the wiring 32 is connected to the output terminal 72. The wiring 32 functions as a transmission line for the signal (RF signal) amplified in the transistor 10.

[0124] The effect obtained by the semiconductor device B having the above structure is described. In the semiconductor device B, in both the first part 24 and the second part 25, the parasitic capacitance generated between the MIM capacitor 20A and the area other than the drain electrode 11 can be reduced. In addition, since the MIM capacitor 20A has the second part 25 in addition to the first part 24, the area of ​​the electrode of the MIM capacitor 20A is increased, and the capacitance of the MIM capacitor 20A can be increased. As a result, the cutoff frequency becomes lower. Therefore, DC cutoff can be performed at a lower frequency, and DC cutoff can be performed within a wider frequency band.

[0125] (Third Embodiment)

[0126] Fig.10 1 is a top view of an amplifier 1C of a semiconductor device C according to the third embodiment. The amplifier 1C has a transistor 10 and a plurality of MIM capacitors 20. The transistor 10 of the amplifier 1C has six drain electrodes 11, seven source electrodes 12, and twelve gate electrodes 13. The drain electrodes 11 and the source electrodes 12 are alternately arranged in the y direction, and the gate electrode 13 is arranged between the drain electrodes 11 and the source electrodes 12. In addition, each MIM capacitor 20 is provided on each drain electrode 11. It should be noted that Fig.11 It is along Fig.10 A cross-sectional view taken along line XI-XI is shown. In the present embodiment, the configurations of the wiring 32 , the wiring 33 , and the wiring 34 are the same as those of the first embodiment.

[0127] The semiconductor device C having the above configuration can also obtain the same effect as the semiconductor device A. Moreover, in the semiconductor device C, the overall electrode area of ​​the MIM capacitor 20 is larger than that of the semiconductor device A. Thus, the capacitance of the MIM capacitor 20 can be increased. Therefore, the cutoff frequency becomes lower. Therefore, the DC cutoff can be performed at a lower frequency, and the DC cutoff can be performed within a wider frequency band.

[0128] The semiconductor device of the present disclosure is not limited to the above-mentioned embodiments, and various other modifications are possible. For example, in the first embodiment, the MIM capacitor 20 is provided on the drain electrode 11, but depending on the configuration of the circuit using the semiconductor device, the MIM capacitor 20 may also be provided on the source electrode 12. In addition, in the above-mentioned embodiments, the manner of providing two or six MIM capacitors 20 on the transistor 10 is exemplified, but the number of the MIM capacitors 20 is not limited thereto.

Claims

1. A semiconductor device comprising: A transistor, provided on a main surface of a substrate having a main surface, and having a first electrode including an ohmic electrode; A MIM capacitor formed on the transistor, comprising a second electrode, a first insulating layer disposed on the second electrode, and a third electrode disposed on the first insulating layer; A second insulating layer is provided between the first electrode and the second electrode; as well as A plurality of via holes penetrates the second insulating layer to electrically connect the first electrode and the second electrode to each other.

2. The semiconductor device according to claim 1, wherein The MIM capacitor is disposed so as to avoid being on the gate electrode of the transistor.

3. The semiconductor device according to claim 1, wherein The MIM capacitor is housed on the first electrode when viewed from a direction perpendicular to the main surface.

4. The semiconductor device according to claim 1, wherein The MIM capacitor has: a first portion, when viewed from a direction perpendicular to the main surface, received on the first electrode; as well as The second portion is continuous with the first portion and is provided outside the transistor when viewed from a direction perpendicular to the main surface.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The transistor is a high electron mobility transistor (HEMT) including a group III-V semiconductor.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The thickness of the first insulating layer in a direction perpendicular to the main surface is thinner than the thickness of the second insulating layer in a direction perpendicular to the main surface.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The thickness of the second electrode in a direction perpendicular to the main surface is thinner than the thickness of the first electrode in a direction perpendicular to the main surface.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The length of the plurality of via holes in a direction perpendicular to the main surface is greater than or equal to 0.1 μm and less than or equal to 10 μm.

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