Semiconductor device

Abstract

This semiconductor device is provided with: a substrate having a main surface and a back surface facing the opposite direction from the main surface; a first metal film provided on the main surface of the substrate; the first insulating layer is arranged on the first metal film and is connected with the first metal film; the second metal film is arranged on the first insulating layer and is connected with the first insulating layer; a plurality of first via holes penetrating through the first insulating layer and connecting the first metal film and the second metal film; the second insulating layer is arranged on the second metal film and is connected with the second metal film; a third metal film which is provided on the second insulating layer, is in contact with the second insulating layer, and is insulated from the second metal film through the second insulating layer; the fourth metal film is arranged on the back surface of the substrate; and a second via hole that penetrates the substrate, connects the first metal film and the fourth metal film, and is provided at a position overlapping the second metal film when viewed from a normal direction of the main surface. The second metal film, the second insulating layer and the third metal film form an MIM capacitor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a wiring substrate with a built-in capacitor element. The wiring substrate has two capacitor element electrode layers. The outer periphery of one capacitor element electrode layer is located outside the outer periphery of the other capacitor element electrode layer. A frame-shaped auxiliary capacitor element electrode layer connected to one capacitor element electrode layer surrounds the other capacitor element electrode layer. The inner periphery of the auxiliary capacitor element electrode layer is located inside the outer periphery of one capacitor element electrode layer.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-283070

[0006] Patent Document 2: Japanese Patent Application Publication No. 2018-37497

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2004-193563

[0008] Patent Document 4: Japanese Patent Application Laid-Open No. 2004-6958

[0009] For example, in semiconductor devices such as monolithic microwave integrated circuits (MMICs), MIM (Metal-Insulator-Metal) capacitors are sometimes provided in the wiring layer. The capacitance of a MIM capacitor is proportional to the area, so the area of ​​the MIM capacitor sometimes becomes larger depending on the capacitance of the MIM capacitor. On the other hand, in semiconductor devices such as MMICs, miniaturization is required by reducing the wiring area. Summary of the invention

[0010] The present disclosure has been made in view of such problems, and an object of the present disclosure is to enable miniaturization by reducing the wiring area in a semiconductor device having a MIM capacitor.

[0011] In order to solve the above problems, the semiconductor device disclosed in the present invention comprises: a substrate having a main surface and a back surface facing opposite to the main surface; a first metal film disposed on the main surface of the substrate; a first insulating layer disposed on the first metal film and connected to the first metal film; a second metal film disposed on the first insulating layer and connected to the first insulating layer; a plurality of first vias penetrating the first insulating layer to connect the first metal film to the second metal film; a second insulating layer disposed on the second metal film and connected to the second metal film; a third metal film disposed on the second insulating layer, connected to the second insulating layer, and insulated from the second metal film by the second insulating layer; a fourth metal film disposed on the back surface of the substrate; and a second via penetrating the substrate to connect the first metal film to the fourth metal film. The second metal film, the second insulating layer and the third metal film constitute a MIM capacitor. The plurality of first vias, the first metal film and the second vias are arranged in the normal direction of the main surface with the MIM capacitor.

[0012] Effects of the Invention

[0013] According to the present disclosure, it is possible to achieve miniaturization by reducing the wiring area in a semiconductor device having a MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure.

[0015] Figure 2 It is along Figure 1 A cross-sectional view of the semiconductor device taken along line II-II is shown.

[0016] Figure 3 As an example, a case where each of the plurality of first via holes has a polygonal cross-sectional shape is shown.

[0017] Figure 4 is a cross-sectional view showing a semiconductor device according to a modified example.

[0018] Figure 5 It is a top view showing a semiconductor device according to another modified example of the present disclosure.

[0019] Figure 6 It is along Figure 5 A cross-sectional view of the semiconductor device taken along line VI-VI is shown.

[0020] Description of Reference Numerals

[0021] 10, 11, 12: semiconductor devices;

[0022] 20: substrate;

[0023] 21: semiconductor layer;

[0024] 31: second metal film;

[0025] 33: third metal film;

[0026] 41: first metal film;

[0027] 42: first via;

[0028] 51: first insulating layer;

[0029] 52: second insulating layer;

[0030] 61: fourth metal film;

[0031] 62: second via;

[0032] 70: MIM capacitor;

[0033] 201: Main side;

[0034] 202: back;

[0035] 421: Depression. DETAILED DESCRIPTION

[0036] [Description of Embodiments of the Present Disclosure]

[0037] First, the contents of the embodiments of the present disclosure are listed for explanation. [1] A semiconductor device according to one aspect of the present disclosure comprises: a substrate having a main surface and a back surface facing opposite to the main surface; a first metal film disposed on the main surface of the substrate; a first insulating layer disposed on the first metal film and in contact with the first metal film; a second metal film disposed on the first insulating layer and in contact with the first insulating layer; a plurality of first vias penetrating the first insulating layer and connecting the first metal film to the second metal film; a second insulating layer disposed on the second metal film and in contact with the second metal film; a third metal film disposed on the second insulating layer and in contact with the second insulating layer and insulated from the second metal film by the second insulating layer; a fourth metal film disposed on the back surface of the substrate; and a second via penetrating the substrate and connecting the first metal film to the fourth metal film. The second metal film, the second insulating layer, and the third metal film constitute a MIM capacitor. The plurality of first vias, the first metal film, and the second vias are arranged in the normal direction of the main surface with the MIM capacitor.

[0038] In the semiconductor device of [1] above, the plurality of first vias, the first metal film, and the second vias are arranged in a direction perpendicular to the main surface of the substrate (i.e., in the thickness direction of the substrate) with the MIM capacitor. Thus, compared with the case where the lead wiring (e.g., ground wiring) from one electrode of the MIM capacitor is arranged side by side with the MIM capacitor as in the structure described in Patent Document 2, the wiring area can be reduced. Therefore, the miniaturization of the semiconductor device having the MIM capacitor can be achieved.

[0039] [2] In the semiconductor device of [1] above, the third metal film may be arranged in a manner avoiding the area above each of the plurality of first vias. The plurality of first vias are formed respectively by forming a hole in the first insulating layer and burying the hole with a metal material. When the hole in the first insulating layer is buried with a metal material, bumps and depressions may sometimes be generated on the upper surface of the first via. In this case, the upper surface of the second metal film formed on the first via and the upper surface of the second insulating layer formed on the second metal film also inherit the bumps and depressions. When the third metal film is formed on such bumps and depressions, the withstand voltage of the MIM capacitor may decrease. By arranging the third metal film in a manner avoiding the area above each of the plurality of first vias, a decrease in the withstand voltage of the MIM capacitor can be avoided.

[0040] [3] In the semiconductor device of [1] or [2] above, the substrate may be a silicon carbide substrate.

[0041] [4] In the semiconductor device of [1] or [3] above, the cross-sectional shape of each of the plurality of first vias when the plurality of first vias are cut along the cross section of the main surface of the substrate is a polygon, and the plurality of corners of the polygon are respectively greater than 90 degrees. In the case where the cross-sectional shape of each of the plurality of first vias is a polygon, the smaller the angle of each of the plurality of corners of the polygon is, the slower the accumulation speed of the metal material is at the plurality of corners when the hole of the first insulating layer is buried with the metal material, and unevenness will be generated on the upper surface of the first via. In addition, the unevenness of the upper surface of the first via is significant when the plurality of corners of the polygon are respectively less than 90 degrees. Therefore, if the plurality of corners of the polygon are respectively greater than 90 degrees, the unevenness of the upper surface of the first via can be suppressed to be small. Therefore, the unevenness of the upper surface of the second metal film formed on the first via and the unevenness of the upper surface of the second insulating layer formed on the second metal film can also be suppressed to be small, and the reduction in the withstand voltage of the MIM capacitor can be suppressed.

[0042] [5] In the semiconductor device of [4] above, the polygon may be a regular polygon. In this case, when the hole of the first insulating layer is buried with a metal material, the growth rate of the metal material can be made nearly uniform along the circumference of the hole, and the unevenness of the upper surface of the first via hole can be further suppressed.

[0043] [6] In the semiconductor devices of [1] to [5] above, the plurality of first via holes may include at least one metal material selected from the group consisting of Au, Cu, W, Ti, Al, Ru, and Co. In this case, it is easy to form a film of the material of the first via holes on the sidewalls of the holes having a high aspect ratio by a CVD (Chemical Vapor Deposition) process or a plating process.

[0044] [Details of the embodiments of the present disclosure]

[0045] Hereinafter, specific examples of the semiconductor device disclosed in the present invention will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are marked on the same elements in the description of the drawings, and repeated descriptions are omitted.

[0046] Figure 1 1 is a plan view showing a semiconductor device 10 according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the semiconductor device 10 taken along line II-II. Figure 1 and Figure 2 As shown, the semiconductor device 10 of this embodiment includes a substrate 20, a semiconductor layer 21, a first metal film 41, a plurality of first vias 42, a second metal film 31, a third metal film 33, a first insulating layer 51, a second insulating layer 52, a fourth metal film 61 and a second via 62.

[0047] The substrate 20 has a main surface 201 and a back surface 202 facing opposite to the main surface 201. The main surface 201 and the back surface 202 are both flat and parallel to each other. The substrate 20 is an insulating substrate such as a silicon carbide (SiC) substrate or a sapphire substrate.

[0048] The semiconductor layer 21 is a semiconductor layer provided on the main surface 201 of the substrate 20 by epitaxial growth. The semiconductor layer 21 includes, for example, a III-V compound semiconductor as its component. In one embodiment, the semiconductor layer 21 includes a GaN-based semiconductor as its component. The semiconductor layer 21 may also include a channel layer and a barrier layer for a high electron mobility transistor (HEMT: High Electron Mobility Transition). The channel layer and the barrier layer may also be a GaN layer and an AlGaN layer, respectively. The thickness of the substrate 20 and the semiconductor layer 21 added together is, for example, 10 μm.

[0049] The first metal film 41 is a metal film provided on the main surface 201 of the substrate 20. In one example, the first metal film 41 is provided on the semiconductor layer 21 and is in contact with the semiconductor layer 21. The first metal film 41 has conductivity. The first metal film 41 is formed, for example, by stacking a nickel (Ni) layer and a gold (Au) layer in sequence. The thickness of the first metal film 41 is, for example, greater than 0.1 μm and less than 10 μm. When observed from the normal direction of the main surface 201 (hereinafter, also referred to as a top view), the first metal film 41 has, for example, a planar shape such as a rectangle. Hereinafter, when referred to as a planar shape, it means the shape when viewed from above. The length of the short side of the first metal film 41 is, for example, greater than 1 μm and less than 1000 μm. The length of the long side of the first metal film 41 is, for example, greater than 1 μm and less than 1000 μm. It should be noted that the planar shape of the first metal film 41 is not limited to a rectangle.

[0050] The first insulating layer 51 is an insulating layer provided on the first metal film 41 and on the region of the main surface 201 where the first metal film 41 is not provided. The first insulating layer 51 is in contact with the other surfaces (upper surface and side surfaces) of the first metal film 41 except the surface in contact with the main surface 201 and the region of the main surface 201. In other words, the first insulating layer 51 covers the first metal film 41 on the main surface 201. The first insulating layer 51 is provided over the entire surface on the main surface 201. The first insulating layer 51 has insulating properties. The first insulating layer 51 is, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon oxynitride film (SiON). The thickness of the first insulating layer 51 on the first metal film 41 is, for example, not less than 0.2 μm and not more than 10 μm.

[0051] The second metal film 31 is a metal film provided on the first insulating layer 51 and is in contact with the first insulating layer 51. When viewed from the normal direction of the main surface 201 of the substrate 20, the second metal film 31 includes a portion overlapping with the first metal film 41. In the illustrated example, the entire second metal film 31 overlaps with the first metal film 41 when viewed from above. The second metal film 31 is conductive. The second metal film 31 is, for example, formed by stacking a first titanium (Ti) layer, a gold (Au) layer, and a second titanium (Ti) layer in sequence. The thickness of the second metal film 31 is, for example, greater than 0.1 μm and less than 10 μm. The second metal film 31 has a planar shape such as a rectangle. The range of the length of the short side and the range of the length of the long side of the second metal film 31 are, for example, the same as the range of the length of the short side and the range of the length of the long side of the above-mentioned first metal film 41. The planar shape of the second metal film 31 is not limited to a rectangle.

[0052] A plurality of first vias 42 are arranged in a one-dimensional or two-dimensional manner on the first metal film 41 in a plane along the main surface 201. The plane may be parallel to the main surface 201. In the illustrated example, the plurality of first vias 42 are arranged in two rows along the long side direction of the first metal film 41, but the arrangement of the plurality of first vias 42 is not limited thereto. The plurality of first vias 42 may also be arbitrarily arranged in a manner of being spaced apart from each other at appropriate intervals in a plane along the main surface 201. The plane may be parallel to the main surface 201. The plurality of first vias 42 penetrate the first insulating layer 51, connecting the first metal film 41 and the second metal film 31 to each other. Each first via 42, for example, includes at least one metal material selected from the group consisting of gold (Au), copper (Cu), tungsten (W), titanium (Ti), aluminum (Al), ruthenium (Ru) and cobalt (Co). The second metal film 31 is electrically connected to the first metal film 41 through the plurality of first vias 42. Assuming that the second metal film 31 is insulated from the first metal film 41 by the first insulating layer 51 when the plurality of first vias 42 are not provided. The number of the plurality of first vias 42 is at least two. By increasing the number of the plurality of first vias 42, the second metal film 31 can be more stably electrically connected to the first metal film 41. For example, with respect to the plurality of first vias 42, more than four first vias 42 can also be provided. For example, when the MIM capacitor 70 is used in a high-frequency circuit, by providing the plurality of first vias 42 to more than four, the influence of the parasitic inductance of one first via 42 on the high-frequency circuit can be reduced.

[0053] In the illustrated example, the cross-sectional shape of each first via hole 42 when each first via hole 42 is cut along the cross section of the main surface 201 is circular. The cross section may be parallel to the main surface 201. The diameter of each first via hole 42 is, for example, not less than 0.5 μm and not more than 10 μm. Each first via hole 42 is not limited to a circle, and may have various cross-sectional shapes. Figure 3 As an example, the cross-sectional shape of each first via hole 42 is a polygon. The angles of the polygon are larger than 90 degrees. As shown in the example in the figure, the polygon may be a regular polygon such as a regular hexagon or a regular octagon.

[0054] The second insulating layer 52 is an insulating layer provided on the second metal film 31 and on the region of the first insulating layer 51 where the second metal film 31 is not provided. The second insulating layer 52 is in contact with the other surfaces (upper surface and side surface) of the second metal film 31 except the surface in contact with the first insulating layer 51 and the above-mentioned region of the first insulating layer 51. In other words, the second insulating layer 52 covers the second metal film 31 on the first insulating layer 51. The second insulating layer 52 is provided over the entire surface on the first insulating layer 51, that is, the entire surface on the main surface 201. The second insulating layer 52 has insulating properties. The dielectric constant of the second insulating layer 52 is greater than the dielectric constant of the first insulating layer 51. The second insulating layer 52 is, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon oxynitride film (SiON). The thickness of the second insulating layer 52 on the second metal film 31 is smaller than the thickness of the first insulating layer 51 on the first metal film 41, for example, 0.01 μm or more and 0.5 μm or less.

[0055] The third metal film 33 is a metal film provided on the second metal film 31 and on the second insulating layer 52, and is in contact with the second insulating layer 52. When viewed from the normal direction of the main surface 201, the third metal film 33 includes a portion overlapping with both the first metal film 41 and the second metal film 31. In the illustrated example, the entire third metal film 33 overlaps with both the first metal film 41 and the second metal film 31. In addition, in the present embodiment, when viewed from the normal direction of the main surface 201, the third metal film 33 overlaps with the plurality of first vias 42. The third metal film 33 is conductive. The third metal film 33 is insulated from the second metal film 31 by the second insulating layer 52. The second metal film 31, the second insulating layer 52, and the third metal film 33 constitute a MIM capacitor 70. That is, the MIM capacitor 70 is arranged in the normal direction of the main surface 201 with the first metal film 41 and the plurality of first vias 42. The MIM capacitor 70 can also be used as a coupling capacitor or a filter capacitor in the semiconductor device 10. The third metal film 33 is formed by, for example, sequentially stacking a first titanium (Ti) layer, a gold (Au) layer, and a second titanium (Ti) layer, similarly to the second metal film 31. The thickness of the third metal film 33 is, for example, greater than 0.1 μm and less than 10 μm. The third metal film 33 has, for example, a planar shape such as a rectangle. The range of the length of the short side and the range of the length of the long side of the third metal film 33 are, for example, the same as the range of the length of the short side and the range of the length of the long side of the first metal film 41 described above. The planar shape of the third metal film 33 is not limited to a rectangle.

[0056] The fourth metal film 61 is a metal film provided on the back surface 202 of the substrate 20 and is in contact with the back surface 202. The fourth metal film 61 is provided over the entire surface of the back surface 202. The fourth metal film 61 has conductivity. When the semiconductor device 10 is mounted on a metal base (not shown) that is defined as a reference potential, the fourth metal film 61 is bonded to the metal base, for example, by a conductive adhesive such as silver paste. Thus, the fourth metal film 61 is defined as a reference potential. The fourth metal film 61 is formed by, for example, a nickel (Ni) layer and a gold (Au) layer stacked in sequence on the back surface 202.

[0057] The second via 62 is a via that penetrates the substrate 20 and the semiconductor layer 21 and connects the first metal film 41 and the fourth metal film 61 to each other. When viewed from the normal direction of the main surface 201, the second via 62 is arranged at a position overlapping the second metal film 31 and the third metal film 33. That is, the second via 62 and the MIM capacitor 70 are arranged in the normal direction of the main surface 201. The second via 62 is composed of, for example, a gold (Au) layer and a copper (Cu) layer deposited on the gold (Au) layer. The maximum diameter of the second via 62 is larger than the diameter of the first via 42, for example, 100μm. The second via 62 can also be in the shape of a truncated cone that becomes thinner as it approaches the main surface 201 of the substrate 20. In this case, the maximum diameter of the portion of the second via 62 that is in contact with the first metal film 41 is, for example, 10μm.

[0058] The effects of the semiconductor device 10 of the present embodiment having the above structure are described. In the semiconductor device 10, the second metal film 31 as the lower electrode of the MIM capacitor 70 is connected to the first metal film 41 provided on the main surface 201 of the substrate 20 through a plurality of first vias 42. In addition, the first metal film 41 is connected to the fourth metal film 61 provided on the back surface 202 of the substrate 20 through the second via 62. In this way, the MIM capacitor 70, the plurality of first vias 42, the first metal film 41 and the second via 62 are arranged in a direction perpendicular to the main surface 201 and the back surface 202 of the substrate 20 (i.e., the thickness direction of the substrate 20). As a result, compared with the case where the lead wiring (e.g., the ground wiring) from one electrode of the MIM capacitor 70 is arranged side by side with the MIM capacitor 70 as in the structure described in Patent Document 2, the wiring area can be reduced. Therefore, the miniaturization of the semiconductor device 10 having the MIM capacitor 70 can be achieved.

[0059] Furthermore, in the present embodiment, the first metal film 41 is not used as the lower electrode of the MIM capacitor 70, but the second metal film 31 provided on the first insulating layer 51 is used as the lower electrode of the MIM capacitor 70. On the upper surface of the first insulating layer 51, the flatness is improved during the film formation of the first insulating layer 51, and thus the flatness of the upper surface of the second metal film 31 provided on the first insulating layer 51 is also improved. Therefore, the thickness of the second insulating layer 52 formed on the second metal film 31 can be made nearly uniform, and the quality of the MIM capacitor 70, such as the withstand voltage, can be improved.

[0060] Figure 4 : is a cross-sectional view of a semiconductor device 11 showing a modified example. The semiconductor device 11 has the same structure as the semiconductor device 10 except for the following points. In the semiconductor device 11, each first via 42 has a slight depression 421 on its upper surface. Each first via 42 is formed as follows: a hole is formed in the first insulating layer 51, and the hole is buried by metal plating or metal CVD (Chemical Vapor Deposition). When the hole in the first insulating layer 51 is buried with a metal material, the metal material is also accumulated on the inner side of the hole at the same accumulation speed as on the bottom surface of the hole. Therefore, near the center of the hole, the accumulation of the metal material is slow, so the upper surface of the first via 42 may sometimes be as shown in FIG. Figure 4 In this case, the upper surface of the second metal film 31 formed on the first via hole 42 and the upper surface of the second insulating layer 52 formed on the second metal film 31 also inherit the depression. For example, due to the depression of the upper surface of the first via hole 42, a depression may be generated on the upper surface of the second metal film 31, thereby generating unevenness on the upper surface of the second metal film 31. Even such a semiconductor device 11 can achieve the same effect as the semiconductor device 10.

[0061] It should be noted that the smaller the diameter of the hole, the smaller the depression 421 generated on the upper surface of the first via hole 42. On the other hand, when the ratio of the inner diameter A to the depth B of the hole (A / B) is too small, it is difficult for the metal material to enter the hole, and it is easy to generate a gap in the first via hole 42. In one example, the ratio of the inner diameter A to the depth B (A / B), in other words, the ratio of the diameter D to the length L of the first via hole 42 (D / L) is greater than 0.5 and less than 20.

[0062] like Figure 3As shown, the cross-sectional shape of each first via 42 may be a polygon, and the multiple corners of the polygon are respectively greater than 90 degrees. In the case where the cross-sectional shape of each of the multiple first vias 42 is a polygon, the smaller the angle of each of the multiple corners of the polygon, the slower the accumulation speed of the metal material at the multiple corners when the hole of the first insulating layer 51 is buried with a metal material, and it is easy to produce unevenness on the upper surface of the first via 42. In addition, the unevenness of the upper surface of the first via 42 is significant when the multiple corners of the polygon are respectively less than 90 degrees. Therefore, if the multiple corners of the polygon are respectively greater than 90 degrees, the unevenness of the upper surface of the first via 42 can be suppressed to be small. That is, the flatness of the upper surface of the first via 42 can be improved.

[0063] Suppressing the unevenness of the upper surface of the first via hole 42 helps to suppress the unevenness generated on the upper surface of the second metal film 31 formed on the first via hole 42 and the unevenness generated on the upper surface of the second insulating layer 52 formed on the second metal film 31. The unevenness on the upper surface of the second metal film 31 and the upper surface of the second insulating layer 52 may cause the MIM capacitor 70 to have a problem such as a local increase in the electric field between the second metal film 31 and the third metal film 33. By suppressing the unevenness of the upper surface of the first via hole 42, such a problem can be eliminated, and the reduction in the withstand voltage of the MIM capacitor 70 can be suppressed.

[0064] In this case, when the hole of the first insulating layer 51 is filled with a metal material, the growth rate of the metal material can be made nearly uniform along the circumference of the hole, and the unevenness of the upper surface of the first via hole 42 can be further suppressed.

[0065] [Modifications]

[0066] Figure 5 It is a plan view showing a semiconductor device 12 according to a modification of the present disclosure. Figure 6 It is along Figure 5 The cross-sectional view of the semiconductor device 12 along the line VI-VI is shown. In the semiconductor device 12, the difference from the semiconductor device 10 of the above-mentioned embodiment lies in the range in which the third metal film 33 is provided. That is, the third metal film 33 of this modification is provided in a manner avoiding the area directly above each first via 42. In other words, when viewed from the normal direction of the main surface 201, the third metal film 33 of this modification is provided in an area that does not overlap with each first via 42. Except for this point, the configuration of the semiconductor device 12 is the same as that of the semiconductor device 10.

[0067] Specifically, the planar shape of the third metal film 33 of this modification is smaller than the planar shape of the second metal film 31. When viewed from the normal direction of the main surface 201, the third metal film 33 of this modification is arranged between one column and the other column of the plurality of first via holes 42 arranged in two columns. In other words, one column of the plurality of first via holes 42 is arranged along one long side of the third metal film 33, and the other column of the plurality of first via holes 42 is arranged along the other long side of the third metal film 33.

[0068] As described above, bumps and depressions may be formed on the upper surface of each first via 42. In this case, the upper surface of the second metal film 31 formed on the first via 42 and the upper surface of the second insulating layer 52 formed on the second metal film 31 will also inherit the bumps and depressions. When the third metal film 33 is formed on such bumps and depressions, the uniformity of the thickness of the second insulating layer 52 in the MIM capacitor 70 may be impaired, and the withstand voltage of the MIM capacitor 70 may decrease. By providing the third metal film 33 in a manner avoiding the area directly above each of the plurality of first vias 42 as in this modification, the decrease in the withstand voltage of the MIM capacitor 70 can be avoided.

[0069] The semiconductor device disclosed in the present invention is not limited to the above-mentioned embodiment, and other various modifications are possible. For example, in the above-mentioned embodiment, an example is shown in which the semiconductor layer 21 is provided on the substrate 20 and the first metal film 41 is provided on the semiconductor layer 21, but the semiconductor layer 21 may not be provided, and the first metal film 41 may be in contact with the substrate 20. Even in this case, the effects of the above-mentioned embodiment can be appropriately achieved.

Claims

1. A semiconductor device comprising: A substrate having a main surface and a back surface facing opposite to the main surface; A first metal film is provided on the main surface of the substrate; A first insulating layer, disposed on the first metal film and in contact with the first metal film; A second metal film is disposed on the first insulating layer and is in contact with the first insulating layer; a plurality of first via holes, penetrating the first insulating layer, connecting the first metal film with the second metal film; A second insulating layer is disposed on the second metal film and is in contact with the second metal film; a third metal film, disposed on the second insulating layer, in contact with the second insulating layer, and insulated from the second metal film by the second insulating layer; a fourth metal film disposed on the back surface of the substrate; as well as a second via hole penetrating the substrate and connecting the first metal film and the fourth metal film; The second metal film, the second insulating layer and the third metal film constitute a MIM capacitor, The first metal film, the plurality of first via holes, the second via hole, and the MIM capacitor are arranged in a normal direction of the main surface.

2. The semiconductor device according to claim 1, wherein The third metal film is provided so as to avoid regions above each of the plurality of first via holes.

3. The semiconductor device according to claim 1 or 2, wherein: The substrate is a silicon carbide substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein: When the plurality of first via holes are cut along the cross section of the main surface, each of the plurality of first via holes has a cross-sectional shape of a polygon, and each of the plurality of corners of the polygon has a degree greater than 90 degrees.

5. The semiconductor device according to claim 4, wherein: The polygon is a regular polygon.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The plurality of first via holes include at least one metal material selected from the group consisting of Au, Cu, W, Ti, Al, Ru, and Co.

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