Semiconductor package

Abstract

A semiconductor package includes at least one first interconnect conductor in contact with at least one first pad, and a first peripheral conductor on an opposite side of the at least one first interconnect conductor, the first peripheral conductor extending in a first horizontal direction. The semiconductor package further includes at least one second interconnect conductor in contact with the at least one second pad, and a second peripheral conductor on an opposite side of the at least one second interconnect conductor, the second peripheral conductor extending in a second horizontal direction intersecting the first horizontal direction. In a plan view, first overlapping regions where the first peripheral conductor and the second peripheral conductor overlap are spaced apart from each other in the first horizontal direction and the second horizontal direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0150217 filed in the Korean Intellectual Property Office on November 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor package. Background Art

[0004] Semiconductor devices installed in electronic devices are required to achieve high performance, high capacity and miniaturization. In order to achieve high performance, high capacity and miniaturization, semiconductor packages that interconnect semiconductor chips stacked in a vertical direction using through electrodes (eg, through silicon vias) have been developed. Summary of the invention

[0005] According to an embodiment of the present disclosure, a semiconductor package having improved reliability is provided.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip is opposite to the second semiconductor chip in a vertical direction. The first semiconductor chip includes: a first substrate; a first interconnection member on a first surface of the first substrate; a first insulating layer covering at least a portion of the first interconnection member; at least one first pad on the first interconnection member; and a first passivation layer surrounding at least a portion of the at least one first pad. The second semiconductor chip includes: a second substrate; a second interconnection member on a first surface of the second substrate; a second insulating layer covering at least a portion of the second interconnection member; at least one second pad on the second interconnection member, the at least one second pad being in contact with the at least one first pad; and a second passivation layer covering at least a portion of the at least one second pad, the second passivation layer being in contact with the first passivation layer, wherein the first interconnection member includes at least one first interconnection conductor in contact with the at least one first pad, and a first peripheral conductor on an opposite side of the at least one first interconnection conductor, the first peripheral conductor extending in a first horizontal direction, wherein the second interconnection member includes at least one second interconnection conductor in contact with the at least one second pad, and a second peripheral conductor on an opposite side of the at least one second interconnection conductor, the second peripheral conductor extending in a second horizontal direction intersecting the first horizontal direction, and wherein, in a plan view, a first overlapping region where the first peripheral conductor overlaps with the second peripheral conductor is spaced apart from each other in the first horizontal direction and the second horizontal direction.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes a first semiconductor chip and a second semiconductor chip opposite to the first semiconductor chip. The first semiconductor chip includes: a first interconnect; at least one first pad on the first interconnect; and a first passivation layer covering at least a portion of the at least one first pad. The second semiconductor chip includes: a second interconnect; at least one second pad on the second interconnect, at least one second pad in contact with at least one first pad; and a second passivation layer covering at least a portion of the at least one second pad, the second passivation layer in contact with the first passivation layer, wherein the first interconnect includes at least one first interconnect conductor in contact with at least one first pad, the at least one first interconnect conductor extending in a first horizontal direction, and wherein the second interconnect includes at least one second interconnect conductor in contact with at least one second pad, the at least one second interconnect conductor extending in a second horizontal direction intersecting the first horizontal direction.

[0008] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip is opposite to the second semiconductor chip in a vertical direction. The first semiconductor chip includes: a first interconnection; a first insulating layer covering at least a portion of the first interconnection; a plurality of first pads, on the first insulating layer, the plurality of first pads are electrically connected to the first interconnection; and a first passivation layer covering at least a portion of the plurality of first pads. The second semiconductor chip includes: a second interconnect; a second insulating layer covering at least a portion of the second interconnect; a plurality of second pads on the second insulating layer, the plurality of second pads being electrically connected to the second interconnect, the plurality of second pads being respectively in contact with the plurality of first pads; and a second passivation layer covering at least a portion of the plurality of second pads, the second passivation layer being in contact with the first passivation layer, wherein the first interconnect includes a first intermediate conductor, and a first top conductor between the first intermediate conductor and the plurality of first pads in a vertical direction, wherein the second interconnect includes a second intermediate conductor, and a second top conductor between the second intermediate conductor and the plurality of second pads in a vertical direction, wherein at least some of the first top conductors extend in a first horizontal direction, and wherein at least some of the second top conductors extend in a second horizontal direction intersecting the first horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure;

[0011] Figure 1B yes Figure 1A A partial enlarged view of area "A";

[0012] Figure 2A It shows Figure 1B a plan view of a plan shape of a first top conductor;

[0013] Figure 2B It shows Figure 1B a plan view of a plan shape of a second top conductor;

[0014] Figure 3A is a plan view showing an arrangement relationship between a first top conductor and a second top conductor according to an example embodiment;

[0015] Figure 3B is a plan view showing an arrangement relationship between a first top conductor and a second top conductor according to an example embodiment;

[0016] Figure 4A is a partially enlarged view of a semiconductor package according to an example embodiment of the present disclosure;

[0017] Figure 4B It shows Figure 4A a plan view of an arrangement relationship between a first top conductor and a second top conductor;

[0018] Figure 5A is a partially enlarged view of a semiconductor package according to an example embodiment of the present disclosure;

[0019] Figure 5B It shows Figure 5A a plan view of an arrangement relationship between a first top conductor and a second top conductor;

[0020] Fig. 6A is a partially enlarged view of a semiconductor package according to an example embodiment of the present disclosure;

[0021] Figure 6B is a partially enlarged view of a semiconductor package according to an example embodiment of the present disclosure;

[0022] Figure 6C It shows Fig. 6A and Figure 6B A plan view of an arrangement relationship between a first top conductor and a second top conductor;

[0023] Fig. 7A is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure;

[0024] Figure 7B yes Fig. 7A A partial enlarged view of area "B";

[0025] Figure 8is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure;

[0026] Fig. 9 is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure;

[0027] Fig.10 is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure;

[0028] Fig.11A is a plan view showing an arrangement relationship of top conductors in a semiconductor package according to a comparative example;

[0029] Fig. 11B is a diagram showing a bonding surface formed using thermal compression bonding according to a comparative example;

[0030] Fig. 11C is a diagram showing a bonding surface formed using thermal compression bonding according to a comparative example;

[0031] Fig. 12A is a plan view showing an arrangement relationship of top conductors according to an example embodiment;

[0032] Fig. 12B It shows that according to Fig. 12A An illustration of a bonding surface formed using thermal compression bonding of an example embodiment of the present invention;

[0033] Fig. 12C It shows that according to Fig. 12A An image of a bonding surface formed using thermocompression bonding of an example embodiment of the present invention; and

[0034] FIG. 13A to FIG. 13E is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0035] Hereinafter, non-limiting example embodiments will be described in detail. Unless otherwise specified, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface" and "side surface" are based on the drawings and may change according to the direction in which the components are actually arranged.

[0036] In addition, ordinal numbers such as "first", "second", "third", etc. can be used as labels for specific elements, operations, directions, etc. to distinguish various elements, steps, directions, etc. from each other. Terms that are not described with "first", "second", etc. in the specification can still be referred to as "first" or "second" in the claims. In addition, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) can be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0037] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0038] Figure 1A is a cross-sectional view of a semiconductor package 10A according to an example embodiment of the present disclosure, and Figure 1B yes Figure 1A A partial enlarged view of area A.

[0039] Figure 2A and Figure 2B It is shown separately Figure 1B FIG. 1 is a plan view of the plan shapes of the first top conductor TC1 and the second top conductor TC2.

[0040] refer to Figure 1A , Figure 1B , Figure 2A and Figure 2B , a semiconductor package 10A according to an example embodiment may include two or more semiconductor chips, for example, a first semiconductor chip 100 and a second semiconductor chip 200, which are opposite to each other in a vertical direction D3. Two or more first semiconductor chips 100 may be disposed on the second semiconductor chip 200. The first semiconductor chip 100 and the second semiconductor chip 200 may include a chiplet included in a multi-chip module (MCM). In some example embodiments, the semiconductor package 10A may further include a molding layer 260 that seals at least a portion of each of the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 260 may include, for example, an epoxy molding compound (EMC), but the material of the molding layer 260 is not particularly limited.

[0041] The first semiconductor chip 100 and the second semiconductor chip 200 may be bonded and coupled to each other using metal-to-metal bonding and dielectric-to-dielectric bonding. The semiconductor package 10A may have a bonding surface BS defined by where the first pad PD1 and the first passivation layer PSV1 of the first semiconductor chip 100 and the second pad PD2 and the second passivation layer PSV2 of the second semiconductor chip 200 are bonded and coupled to each other. According to an example embodiment, the first top conductor TC1 and the second top conductor TC2, which are respectively arranged above the first passivation layer PSV1 and below the second passivation layer PSV2 bonded to each other, may extend in different directions, so that the overlapping area between the first top conductor TC1 and the second top conductor TC2 around the first pad PD1 and the second pad PD2 may be minimized. As a result, the quality degradation of the bonding surface BS caused by the expansion of the first passivation layer PSV1 and the second passivation layer PSV2 in the thermocompression bonding process may be prevented.

[0042] The first semiconductor chip 100 may include a first substrate 110 , a first circuit layer 120 , a first passivation layer PSV1 , and a plurality of first pads PD1 .

[0043] The first substrate 110 may be a semiconductor wafer. The first substrate 110 may include, for example, a semiconductor element (e.g., silicon or germanium), or a compound semiconductor (silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The first substrate 110 may have a conductive region 112 and an isolation region 113 formed on one surface 110S thereof. The conductive region 112 may be, for example, a well doped with impurities, or a structure doped with impurities. The isolation region 113 may be a device isolation structure having a shallow trench isolation (STI) structure, and may include silicon oxide.

[0044] The first circuit layer 120 may be disposed on one surface 110S of the first substrate 110 on which the conductive region 112 is formed. The first circuit layer 120 may include a single device ID, a first insulating layer IL1, and a first interconnect IC1. Hereinafter, the first insulating layer IL1 may be referred to as a front insulating layer or an interlayer insulating layer 121. The first interconnect IC1 may be referred to as an interconnect structure 125.

[0045] The individual device ID may be disposed on one surface 110S of the first substrate 110. The individual device ID may be electrically connected to the conductive region 112. The individual device ID may include, for example, a field effect transistor (FET) (e.g., a planar FET or a FinFET), a memory device (e.g., a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), an electrically erasable memory (EEPROM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM)), a logic device (e.g., AND, OR, or NOT), and various active and / or passive devices (e.g., a system large scale integration (LSI), a CMOS imaging sensor (CIS), and a microelectromechanical system (MEMS)).

[0046] The interlayer insulating layer 121 may be formed to cover the individual device ID and the interconnect structure 125 so that the individual device IDs disposed on the first substrate 110 are electrically isolated from each other. The interlayer insulating layer 121 may include a flowable oxide (FOX), a tonn silazane (TOSZ), an undoped silicon glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma enhanced tetraethyl orthosilicate (PETEOS), a fluorosilicate glass (FSG), a high density plasma (HDP) oxide, a plasma enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer 121 surrounding the interconnect structure 125 may include a low dielectric layer. The interlayer insulating layer 121 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process.

[0047] The interconnection structure 125 may have a multilayer structure including a plurality of interconnection patterns and a plurality of vias formed of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the interconnection pattern or / and the via and the interlayer insulating layer 121. The interconnection structure 125 may be electrically connected to a separate device ID through an interconnector 123 (e.g., a contact plug).

[0048] In example embodiments, the first interconnect IC1 may include a first intermediate conductor MC1 and a first top conductor TC1. The first intermediate conductor MC1 may be disposed in the first insulating layer IL1. The first intermediate conductor MC1 may be located between one surface 110S of the first substrate 110 and the first top conductor TC1. The first top conductor TC1 may be located between the first intermediate conductor MC1 and the plurality of first pads PD1 in the vertical direction D3. At least some of the first top conductors TC1 may extend in the first horizontal direction D1. Figure 2A As shown, the first top conductor TC1 may include at least one first interconnect conductor ITC1 in contact with at least one first pad PD1, and the at least one first interconnect conductor ITC1 has a long side extending in the first horizontal direction D1. In this case, the first interconnect conductor ITC1 may provide a power transmission path or a ground transmission path, but the embodiments of the present disclosure are not limited thereto. The thickness T1 of each first top conductor TC1 may be greater than the thickness t1 of each first intermediate conductor MC1. The thickness T1 of each first top conductor TC1 may be about 1 μm or more, for example, in a range from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, from about 1 μm to about 10 μm, or from about 1 μm to about 5 μm, but the embodiments of the present disclosure are not limited thereto.

[0049] According to example embodiments, the second top conductor TC2 of the second semiconductor chip 200 extends in a direction different from the extension direction of the first top conductor TC1, thereby improving the quality of the bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200. The first top conductor TC1 and the second top conductor TC2 may include aluminum (Al) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto. In some example embodiments, the first top conductor TC1 and the second top conductor TC2 may include a material similar to or the same as that of the first intermediate conductor MC1 and the second intermediate conductor MC2 (e.g., copper (Cu) or an alloy thereof).

[0050] In an example embodiment, the second interconnect IC2 of the second circuit layer 220 of the second semiconductor chip 200 may include a second intermediate conductor MC2 and a second top conductor TC2. The second intermediate conductor MC2 may be disposed in the second insulating layer IL2 of the second circuit layer 220 of the second semiconductor chip 200. The second intermediate conductor MC2 may be located between a surface 210S1 of the second substrate 210 of the second semiconductor chip 200 and the second top conductor TC2. The second top conductor TC2 may be located between the second intermediate conductor MC2 and the plurality of second pads PD2 in the vertical direction D3. At least some of the second top conductors TC2 may extend in the second horizontal direction D2 intersecting the first horizontal direction D1. Figure 2BAs shown, the second top conductor TC2 may include a second interconnect conductor ITC2 in contact with at least one second pad PD2, the second interconnect conductor ITC2 having a long side extending in the second horizontal direction D2. The thickness T2 of each second top conductor TC2 may be greater than the thickness t2 of each second intermediate conductor MC2. The thickness T2 of the second top conductor TC2 may be about 1 μm or more, for example, in a range from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, from about 1 μm to about 10 μm, or from about 1 μm to about 5 μm, but the embodiments of the present disclosure are not limited thereto.

[0051] A plurality of first pads PD1 may be disposed on the first interconnect IC1. The plurality of first pads PD1 may be electrically connected to the first interconnect IC1 through the first interconnect conductor ITC1. The plurality of first pads PD1 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the plurality of first pads PD1 may include at least one of copper (Cu) and its alloy. The thickness of each of the plurality of first pads PD1 may be 0.5 times or more and 2 times or less of the thickness T1 of the first interconnect conductor ITC1, but the embodiments of the present disclosure are not limited thereto. In order to distinguish the positions of the components in the first semiconductor chip 100 from each other, the plurality of first pads PD1 may be referred to as front pads 132.

[0052] A plurality of second pads PD2 may be disposed on the second interconnect IC2. The plurality of second pads PD2 may be electrically connected to the second interconnect IC2 through the second interconnect conductor ITC2. The plurality of second pads PD2 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the plurality of second pads PD2 may include at least one of copper (Cu) and its alloy. The thickness of each of the plurality of second pads PD2 may be 0.5 times or more and 2 times or less of the thickness T2 of the second interconnect conductor ITC2, but the embodiments of the present disclosure are not limited thereto. In order to distinguish the positions of the components in the second semiconductor chip 200 from each other, the plurality of second pads PD2 may be referred to as front pads 232.

[0053] The first passivation layer PSV1 may be formed to surround the side surfaces of the plurality of first pads PD1. The first passivation layer PSV1 may form a bonding surface provided for dielectric inter-bonding between the plurality of first pads PD1. The first passivation layer PSV1 may include, for example, silicon oxide (SiO) or silicon carbonitride (SiCN).

[0054] The second passivation layer PSV2 may be formed to surround the side surfaces of the plurality of second pads PD2. The second passivation layer PSV2 may form a bonding surface provided for dielectric bonding between the plurality of second pads PD2. The second passivation layer PSV2 may include, for example, silicon oxide (SiO) or silicon carbonitride (SiCN).

[0055] In the hot pressing process, the quality of the bonding surface between the first passivation layer PSV1 and the second passivation layer PSV2 may be affected by the arrangement of the first top conductor TC1 and the second top conductor TC2 located therebelow (or above it). According to example embodiments, the expansion of the first passivation layer PSV1 and the second passivation layer PSV2 around the first pad PD1 and the second pad PD2 bonded to each other may be minimized, thereby realizing a semiconductor package with excellent bonding quality.

[0056] The second semiconductor chip 200 may be disposed on one surface of the first semiconductor chip 100. In the second semiconductor chip 200, a plurality of second pads PD2 may be disposed in a direction opposite to the front pads 132 of the first semiconductor chip 100. In the present example embodiment, the second insulating layer IL2 may be referred to as a front insulating layer or an interlayer insulating layer 121, and the second interconnect IC2 may be referred to as an interconnect structure 125.

[0057] The second semiconductor chip 200 may include a second substrate 210, a second circuit layer 220, a second passivation layer PSV2, a plurality of second pads PD2, a plurality of through electrodes 240 (e.g., through holes), and a plurality of protruding electrodes 252. The second semiconductor chip 200 may include components substantially similar to those of the first semiconductor chip 100. For example, the second substrate 210 may be substantially similar to the first substrate 110, the second circuit layer 220 may be substantially similar to the first circuit layer 120, the second passivation layer PSV2 may be substantially similar to the first passivation layer PSV1, and the plurality of second pads PD2 may be substantially similar to the first pads PD1. Therefore, the same or similar components are represented by the same or similar terms and / or reference numerals, and repeated descriptions will be omitted below.

[0058] The through electrode 240 may pass through one surface 210S1 and the other surface 210S2 of the second substrate 210 to electrically connect the second interconnect IC2 and the protruding electrode 252. The one surface 210S1 of the second substrate 210 may be referred to as a front surface or a rear surface depending on whether the conductive region 112 (e.g., an active region) is formed. For example, the one surface 210S1 of the second substrate 210 according to the present example embodiment may be referred to as a “front surface”, and the other surface 210S2 may be referred to as a “rear surface”. Figure 7BOne surface 210S1 of the second substrate 210 of the example embodiment may be referred to as a “rear surface”. The through electrode 240 may include a via plug 245 and a side barrier layer 241 surrounding its side surface. The via plug 245 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed using an electroplating process, a PVD process, or a CVD process. The side barrier layer 241 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed using an electroplating process, a PVD process, or a CVD process. A side insulating film including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., a high aspect ratio process (HARP) oxide) may be formed between the side barrier layer 241 and the second substrate 210.

[0059] The through electrode 240 may pass through the insulating protective layer 213 formed on the other surface 210S2 of the second substrate 210. The insulating protective layer 213 may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 214 such as a polishing stop layer or a barrier layer (see Figure 7B ) may be disposed on an upper surface of the insulating protection layer 213. For example, the buffer film may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0060] The protruding electrode 252 may be disposed on the other surface 210S2 of the second substrate 210. The protruding electrode 252 may be electrically connected to the second interconnect IC2 and / or the front pad 232 through the through electrode 240. The protruding electrode 252 may be referred to as a "rear pad". The protruding electrode 252 may be connected to the connection bump 236. The connection bump 236 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn) and lead (Pb) and / or an alloy thereof. In some example embodiments, the connection bump 236 may have a combination of a metal column and a solder ball.

[0061] In the following, reference will be made to Figure 3A and Figure 3B The arrangement relationship between the first top conductor TC1 and the second top conductor TC2 is described.

[0062] Figure 3A and Figure 3B is a plan view illustrating an arrangement relationship between the first top conductor TC1 and the second top conductor TC2 according to example embodiments. Figure 3A and Figure 3B There are shown first and second top conductors TC1 and TC2 and first and second pads PD1 and PD2 arranged in a plan view.

[0063] refer to Figure 3A and Figure 3B The first top conductor TC1 and the second top conductor TC2 may include a first interconnect conductor ITC1 and a second interconnect conductor ITC2, respectively. The first interconnect conductor ITC1 may extend in a first horizontal direction D1, and the second interconnect conductor ITC2 may extend in a second horizontal direction D2 having a predetermined angle θ with the first horizontal direction D1.

[0064] In a plan view, a peripheral region of an overlap region CR between the first interconnect conductor ITC1 , the first pad PD1 , the second interconnect conductor ITC2 , and the second pad PD2 may be disposed in a non-overlap region in which the first interconnect conductor ITC1 and the second interconnect conductor ITC2 do not overlap each other.

[0065] In addition, in a plan view, the overlap region CR between the first interconnect conductor ITC1 and the second interconnect conductor ITC2 may have a first width Wa1 extending in the first horizontal direction D1, and a second width Wa2 extending in the second horizontal direction D2. The first width Wa1 may be equal to or greater than the line width La2 of the second interconnect conductor ITC2. The second width Wa2 may be equal to or greater than the line width La1 of the first interconnect conductor ITC1. The line width La1 of the first interconnect conductor ITC1 and the line width La2 of the second interconnect conductor ITC2 may be about 50 μm or less, for example, may be in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but the embodiments of the present disclosure are not limited thereto. In some example embodiments, the line width La1 of the first interconnect conductor ITC1 and the line width La2 of the second interconnect conductor ITC2 may be different from each other.

[0066] like Figure 3A As shown, when the predetermined angle θ between the first horizontal direction D1 and the second horizontal direction D2 is about 90°, the first width Wa1 may be equal to the line width La2 of the second interconnect conductor ITC2, and the second width Wa2 may be equal to the line width La1 of the first interconnect conductor ITC1.

[0067] like Figure 3B As shown, when the predetermined angle θ between the first horizontal direction D1 and the second horizontal direction D2 is less than about 90°, the first width Wa1 may be greater than the line width La2 of the second interconnect conductor ITC2, and the second width Wa2 may be greater than the line width La1 of the first interconnect conductor ITC1.

[0068] Figure 4A is a partially enlarged view of a semiconductor package 10a according to an example embodiment of the present disclosure, and Figure 4B It shows Figure 4A A plan view of the arrangement relationship between the first top conductor TC1 and the second top conductor TC2.

[0069] refer to Figure 4A and Figure 4B , except that the first top conductor TC1 and the second top conductor TC2 further include the first peripheral conductor PTC1 and the second peripheral conductor PTC2, respectively, the semiconductor package 10a according to the example embodiment may have the same Figures 1A to 3B Features described are the same or similar features.

[0070] The first top conductor TC1 may include a first interconnect conductor ITC1 and a first peripheral conductor PTC1. The first peripheral conductor PTC1 may be disposed on one or both sides of the first interconnect conductor ITC1. The first peripheral conductor PTC1 may extend in the same direction (eg, first horizontal direction D1) as the first interconnect conductor ITC1.

[0071] The second top conductor TC2 may include a second interconnect conductor ITC2 and a second peripheral conductor PTC2. The second peripheral conductor PTC2 may be disposed on one or both sides of the second interconnect conductor ITC2. The second peripheral conductor PTC2 may extend in the same direction (eg, second horizontal direction D2) as the second interconnect conductor ITC2.

[0072] In a plan view, the first overlapping regions PR1 of the first and second peripheral conductors PTC1 and PTC2 may be spaced apart from each other in the first and second horizontal directions D1 and D2.

[0073] In a plan view, an overlap region CR between the first interconnect conductor ITC1, the first pad PD1, the second interconnect conductor ITC2, and the second pad PD2 may be spaced apart from the first overlap region PR1. The overlap region CR may be surrounded by a non-overlap region NR in which the first interconnect conductor ITC1, the first peripheral conductor PTC1, the second interconnect conductor ITC2, and the second peripheral conductor PTC2 do not overlap each other.

[0074] In a plan view, a second overlap region PR2 in which the first interconnect conductor ITC1 and the second interconnect conductor ITC2 overlap the second peripheral conductor PTC2 and the first peripheral conductor PTC1, respectively, may be spaced apart from and adjacent to the first overlap region PR1 in the first horizontal direction D1 and the second horizontal direction D2. A first gap G1 between the first overlap region PR1 and the second overlap region PR2 in the first horizontal direction D1 may be equal to a distance SP2 between the second interconnect conductor ITC2 and the second peripheral conductor PTC2, and a second gap G2 between the first overlap region PR1 and the second overlap region PR2 in the second horizontal direction D2 may be equal to a distance SP1 between the first interconnect conductor ITC1 and the first peripheral conductor PTC1. The distance SP1 and the distance SP2 may be about 50 μm or less, for example, in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but the embodiments of the present disclosure are not limited thereto.

[0075] In a plan view, each first overlap region PR1 may have a first width Wb1 in the first horizontal direction D1 and a second width Wb2 in the second horizontal direction D2. The first width Wb1 of each first overlap region PR1 may be equal to or greater than the line width Lb2 of the second peripheral conductor PTC2. The second width Wb2 of each first overlap region PR1 may be equal to or greater than the line width Lb1 of the first peripheral conductor PTC1.

[0076] Each second overlapping region PR2 may have a first width Wc1 in the first horizontal direction D1 and a second width Wc2 in the second horizontal direction D2. The first width Wc1 of each second overlapping region PR2 may be equal to or greater than the line width of the second peripheral conductor PTC2 or the second interconnect conductor ITC2. The second width Wc2 of each second overlapping region PR2 may be equal to or greater than the line width of the first interconnect conductor ITC1 or the first peripheral conductor PTC1. The line width Lb1 of the first peripheral conductor PTC1 and the line width Lb2 of the second peripheral conductor PTC2 may be about 50 μm or less, for example, in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but the embodiments of the present disclosure are not limited thereto. In some example embodiments, the line width Lb1 of the first peripheral conductor PTC1 and the line width Lb2 of the second peripheral conductor PTC2 may be different from the line width La1 of the first interconnect conductor ITC1 and the line width La2 of the second interconnect conductor ITC2 (see Figure 5B ).

[0077] Figure 5Ais a partially enlarged view of a semiconductor package 10b according to an example embodiment of the present disclosure, and Figure 5B It shows Figure 5A A plan view of the arrangement relationship between the first top conductor TC1 and the second top conductor TC2.

[0078] refer to Figure 5A and Figure 5B The semiconductor package 10b according to the example embodiment may have the same structure as the reference 1 in addition to the first top conductor TC1 and the second top conductor TC2 including the first interconnect conductor ITC1 and the second interconnect conductor ITC2 contacting the plurality of first pads PD1 and the plurality of second pads PD2. Figures 1A to 4B Features described are the same or similar features.

[0079] The first top conductor TC1 may include a plurality of first interconnection conductors ITC1 spaced apart from each other in the second horizontal direction D2. A plurality of first pads PD1 may be arranged on the plurality of first interconnection conductors ITC1 in the first horizontal direction D1. The first peripheral conductor PTC1 may be provided on one or both sides of the first interconnection conductor ITC1.

[0080] The second top conductor TC2 may include a plurality of second interconnect conductors ITC2 spaced apart from each other in the first horizontal direction D1. A plurality of second pads PD2 may be arranged on the plurality of second interconnect conductors ITC2 in the second horizontal direction D2. A plurality of second pads PD2 and a plurality of first pads PD1 corresponding to each other may contact each other in the vertical direction D3. The second peripheral conductor PTC2 may be disposed on one side or both sides of the second interconnect conductor ITC2.

[0081] In a plan view, second overlapping regions PR2 in which a plurality of first interconnect conductors ITC1 and a plurality of second interconnect conductors ITC2 overlap with the second peripheral conductor PTC2 and the first peripheral conductor PTC1, respectively, may be arranged around the first pad PD1 and the second pad PD2. The second overlapping regions PR2 may be alternately disposed with the first overlapping regions PR1 in the first horizontal direction D1 and the second horizontal direction D2.

[0082] Fig. 6A and Figure 6B is a partially enlarged view of a semiconductor package 10c according to an example embodiment of the present disclosure, and Figure 6C It shows Fig. 6A and Figure 6B FIG. 1 is a plan view of the arrangement relationship of the first top conductor TC1 and the second top conductor TC2. Fig. 6A is along Figure 6C A cross-sectional view taken along line I1-I1′, and Figure 6B is along Figure 6C A cross-sectional view taken along line I2-I2′.

[0083] refer to Fig. 6A , Figure 6B and Figure 6C , except that the first interconnection conductor ITC1 and the second interconnection conductor ITC2 do not overlap with the first peripheral conductor PTC1 and the second peripheral conductor PTC2, the semiconductor package 10c according to the example embodiment may have the same Figures 1A to 5B The first interconnect conductor ITC1 and the second interconnect conductor ITC2 may be provided for signal transmission, but the embodiments of the present disclosure are not limited thereto.

[0084] The length L1 of the first interconnect conductor ITC1 may be smaller than the gap G3 between the adjacent second peripheral conductors PTC2. The length L2 of the second interconnect conductor ITC2 may be smaller than the gap G4 between the adjacent first peripheral conductors PTC1.

[0085] In a plan view, the first overlap regions PR1 between the first peripheral conductor PTC1 and the second peripheral conductor PTC2 may be spaced apart from each other in the first horizontal direction D1 and the second horizontal direction D2. The gap G3 between the first overlap regions PR1 in the first horizontal direction D1 may be greater than the distance SP2 between the second interconnect conductor ITC2 and the second peripheral conductor PTC2, and the gap G4 between the first overlap regions PR1 in the second horizontal direction D2 may be greater than the distance SP1 between the first interconnect conductor ITC1 and the first peripheral conductor PTC1. The distance SP1 and the distance SP2 may be about 50 μm or less, for example, in a range from about 1 μm to about 50 μm, from about 1 μm to about 40 μm, from about 1 μm to about 30 μm, from about 1 μm to about 20 μm, or from about 5 μm to about 10 μm, but the embodiments of the present disclosure are not limited thereto.

[0086] Fig. 7A is a cross-sectional view of a semiconductor package 10B according to an example embodiment of the present disclosure, and Figure 7B yes Fig. 7A A partial enlarged view of area B.

[0087] refer to Fig. 7A and Figure 7B , except that the second circuit layer 220 is disposed on the other surface 210S2 of the second substrate 210, the semiconductor package 10B according to the example embodiment may have the same Figures 1A to 6C Features described are the same or similar features.

[0088] The other surface 210S2 of the second substrate 210 may be referred to as a “front surface”. The second circuit layer 220 may include a reference Figure 1A and Figure 1B Individual devices, front interconnects, and interlayer insulating layers are described.

[0089] The second interconnect IC2, the second insulating layer IL2, the second pad PD2, and the second passivation layer PSV2 may be disposed on one surface 210S1 of the second substrate 210. Here, one surface 210S1 of the second substrate 210 may be referred to as a "rear surface". The second interconnect IC2, the second insulating layer IL2, and the second pad PD2 may be referred to as a rear interconnect 225, a rear insulating layer 251, and a protruding electrode 252 (e.g., a rear pad), respectively. The rear interconnect 225, the rear insulating layer 251, and the protruding electrode 252 have features similar to those of the above-mentioned front interconnect, the front insulating layer, and the front pad, and therefore repeated descriptions will be omitted. The buffer film 214 may be disposed between the insulating protection layer 213 and the second insulating layer IL2. The buffer film 214 may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0090] Figure 8 is a cross-sectional view of a semiconductor package 10C according to an example embodiment of the present disclosure.

[0091] refer to Figure 8 , except that the first semiconductor chip 100 is larger than the second semiconductor chip 200, the semiconductor package 10C according to the example embodiment may have the same Figures 1A to 7B Features described are the same or similar features.

[0092] The size (e.g., plane area, width, etc.) of the first semiconductor chip 100 may be greater than that of the second semiconductor chip 200. The second semiconductor chip 200 may be disposed in a direction along which the second circuit layer 220 is opposite to the first circuit layer 120. The through electrode 240 may protrude from the other surface 210S2 of the second substrate 210 to be electrically connected to the protruding electrode 252. The mold layer 260 may cover the side surface 210S3 and the other surface 210S2 of the second semiconductor chip 200, and may be formed to surround the end of the through electrode 240. In some example embodiments, a lower passivation layer covering the protruding electrode 252 and the connecting bump 236 may also be formed under the mold layer 260.

[0093] Fig. 9 is a cross-sectional view of a semiconductor package 10D according to an example embodiment of the present disclosure.

[0094] refer to Fig. 9 , a semiconductor package 10D according to an example embodiment may include a package structure PS, an interconnection substrate 600, and a heat dissipation structure 630. The package structure PS may include a first semiconductor chip, a second semiconductor chip, and a molding layer, and may be understood as having the same structure as reference 1. Figures 1A to 8The stacked chip structure may have the same or similar features as described above. For example, the package structure may be or include the semiconductor package 10A, the semiconductor package 10a, the semiconductor package 10b, the semiconductor package 10c, the semiconductor package 10B, or the semiconductor package 10C.

[0095] The interconnection substrate 600 may be a support substrate on which the package structure PS is mounted, and may be a substrate for semiconductor packaging (e.g., a printed circuit board (PCB), a ceramic substrate, or a tape-shaped interconnection substrate). The package structure PS may be electrically connected to the interconnection substrate 600 through a metal bump BP. The interconnection substrate 600 may include a lower pad 612, an upper pad 611, and an interconnection circuit 613 that electrically connects the lower pad 612 and the upper pad 611 to each other. The body of the interconnection substrate 600 may include different materials according to the type of substrate. For example, when the interconnection substrate 600 is a printed circuit board, the interconnection substrate 600 may be in the form of a main copper-clad laminate, or an interconnection layer additionally stacked on one or both surfaces of the copper-clad laminate. An external connection bump 620 may be provided on the lower portion of the interconnection substrate 600. The external connection bump 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and / or an alloy thereof.

[0096] The heat dissipation structure 630 may be provided to cover the upper portion of the package structure PS. The heat dissipation structure 630 may be attached to the interconnect substrate 600 using an adhesive. The adhesive may be a thermally conductive tape, a thermally conductive paste, or a thermally conductive adhesive. The heat dissipation structure 630 may be attached to the upper portion of the package structure PS via a thermally conductive material layer 631. The thermally conductive material layer 631 may include, for example, a thermally conductive tape, a thermally conductive paste, or a thermally conductive adhesive.

[0097] The heat dissipation structure 630 may include a conductive material having excellent thermal conductivity. For example, the heat dissipation structure 630 may include a metal or metal alloy including gold (Au), silver (Ag), copper (Cu), or iron (Fe), or a conductive material such as graphite or graphene. The heat dissipation structure 630 may have a Fig. 9 For example, the heat dissipation structure 630 may be formed to cover only the upper surface of the package structure PS.

[0098] Fig.10 is a cross-sectional view of a semiconductor package 10E according to an example embodiment of the present disclosure.

[0099] refer to Fig.10 , a semiconductor package 10E according to example embodiments may include a first package structure PS1 , a second package structure PS2 , a lower redistribution structure 310 , a sealant 320 , a pillar 330 , and an upper redistribution structure 350 .

[0100] The first package structure PS1 can be understood to have the same Figures 1A to 8 The stacked chip structure may have the same or similar features as described above (eg, semiconductor package). The first package structure PS1 may be connected to the lower redistribution layer 312 through metal bumps BP.

[0101] The second package structure PS2 may be disposed on the upper redistribution structure 350. The second package structure PS2 may be connected to the upper redistribution layer 352 via a metal bump BP. The second package structure PS2 may be electrically connected to the lower redistribution layer 312 via a plurality of pillars 330. The second package structure PS2 may be a bare chip, or a packaged chip on which a logic circuit or a memory circuit is formed. In some example embodiments, the second package structure PS2 may include a plurality of semiconductor chips. The second package structure PS2 may include a semiconductor chip type different from the semiconductor chip type of the first package structure PS1. For example, the first package structure PS1 may include a logic chip, and the second package structure PS2 may include a memory chip.

[0102] The heat dissipation member 340 may be disposed on at least one side of the second package structure PS2. In some example embodiments, the heat dissipation member 340 may have a shape surrounding four surfaces of the upper chip structure (e.g., the second semiconductor chip 200). The heat dissipation member 340 may control the warpage of the semiconductor package 10E and may radiate the heat generated from the first package structure PS1 to the outside.

[0103] The heat dissipation member 340 may include a heat transfer material layer 341 and a heat sink 342. The heat transfer material layer 341 may include, for example, a heat conductive tape, a heat conductive paste, or a heat conductive adhesive. The heat sink 342 may be disposed on the heat transfer material layer 341. The heat sink 342 may include a material having excellent thermal conductivity, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), iron (Fe), graphite, or graphene.

[0104] The lower redistribution structure 310 may include a supporting substrate on which a lower chip structure (e.g., a first semiconductor chip 100) is mounted, and may include a lower insulating layer 311, a lower redistribution layer 312, and a lower redistribution via 313. The lower insulating layer 311 may include a photosensitive resin, for example, a prepreg, an Ajinomoto built-in film (ABF), FR-4, bismaleimide-triazine (BT), or a photo-imaging dielectric (PID). The lower redistribution layer 312 may redistribute the first package structure PS1. The lower redistribution layer 312 may include, for example, a metal (including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti)) or an alloy thereof. The lower redistribution via 313 may be a filled via in which a through hole is filled with a metal material, or a conformal via in which a metal material extends along the inner wall of the through hole.

[0105] The sealant 320 may cover the first package structure PS1 and the pillars 330. The sealant 320 may include, for example, prepreg, ABF, FR-4, BT, EMC.

[0106] The pillar 330 may pass through the seal 320 to electrically connect the lower redistribution layer 312 and the upper redistribution layer 352 to each other. The pillar 330 may include copper (Cu), nickel (Ni), titanium (Ti), lead (Pb), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), or an alloy thereof.

[0107] The upper redistribution structure 350 may be disposed on the sealant 320, and may include an upper insulating layer 351, an upper redistribution layer 352, and an upper redistribution via 353. The upper insulating layer 351, the upper redistribution layer 352, and the upper redistribution via 353 may have features that are the same as or similar to those of the above-described lower insulating layer 311, the lower redistribution layer 312, and the lower redistribution via 313, and thus repeated description will be omitted.

[0108] The external connection bumps 360 may connect the semiconductor package 10E to an external device such as a module substrate or a system board. The external connection bumps 360 may include, for example, tin (Sn) or an alloy including tin (Sn) (eg, Sn—Ag—Cu).

[0109] Fig.11A is a plan view showing an arrangement relationship of a first top conductor TC1 and a second top conductor TC2 in a semiconductor package 10 ′ according to a comparative example, and Fig. 11B and Fig. 11C is a diagram showing a bonding surface BS′ formed using thermocompression bonding according to a comparative example. Fig. 11B and Fig. 11C Shown along Fig.11A A cross section taken along line II-II'.

[0110] refer to Fig.11A , the semiconductor package 10′ according to the comparative example may include a first top conductor TC1 and a second top conductor TC2 extending in the same direction. For example, the first top conductor TC1 and the second top conductor TC2 may extend in the first horizontal direction D1. The first top conductor TC1 may include a first interconnecting conductor ITC1 and a first peripheral conductor PTC1. The second top conductor TC2 may include a second interconnecting conductor ITC2 and a second peripheral conductor PTC2.

[0111] The first interconnect conductor ITC1 and the second interconnect conductor ITC2 corresponding to each other may form a first overlap region CR'. The first peripheral conductor PTC1 and the second peripheral conductor PTC2 corresponding to each other may form a second overlap region PR'. The first overlap region CR' and the second overlap region PR' according to the comparative example may extend continuously around the first pad PD1 and the second pad PD2.

[0112] refer to Fig. 11B In order to perform the hot pressing process, the first pad PD1, the second pad PD2, the first passivation layer PSV1, and the second passivation layer PSV2 may be planarized. The first recessed surface RS1 and the second recessed surface RS2 may be formed on the surfaces of the first pad PD1 and the second pad PD2, respectively. The first recessed surface RS1 on the first pad PD1 may be disposed opposite to the second recessed surface RS2 on the second pad PD2.

[0113] refer to Fig. 11C , a hot pressing process may be performed to bond and couple the first pad PD1 and the second pad PD2 to each other. The first pad PD1 and the second pad PD2 may expand in opposite directions to each other. However, in the first overlapping region CR' and the second overlapping region PR' according to the comparative example, the first passivation layer PSV1 and the second passivation layer PSV2 may expand together with the first top conductor TC1 and the second top conductor TC2, resulting in non-bonding between the first pad PD1 and the second pad PD2 and non-bonding between the first passivation layer PSV1 and the second passivation layer PSV2, and quality degradation of the bonding surface BS'.

[0114] For example, the first passivation layer PSV1 adjacent to the first pad PD1 in the first horizontal direction D1 may extend downward due to the first interconnect conductor ITC1, and the second passivation layer PSV2 adjacent to the second pad PD2 in the first horizontal direction D1 may extend upward due to the second interconnect conductor ITC2. The first passivation layer PSV1 adjacent to the first pad PD1 in the second horizontal direction D2 may extend downward due to the first peripheral conductor PTC1, and the second passivation layer PSV2 adjacent to the second pad PD2 in the second horizontal direction D2 may extend upward due to the second peripheral conductor PTC2 (see Fig. 11C ), resulting in reduced bonding reliability between the first recessed surface RS1 and the second recessed surface RS2.

[0115] Fig. 12A is a plan view showing an arrangement relationship of top conductors according to an example embodiment, and Fig. 12B and Fig. 12C is a diagram showing a bonding surface formed using thermal compression bonding according to an example. Fig. 12B Shown along Fig. 12A FIG. 1 is a cross section taken along line III1-III1′, and FIG. 1 2C shows a cross section taken along line III1-III1′. Fig. 12A A cross section taken along line III2-III2'.

[0116] refer to Fig. 12A , Fig. 12B and Fig. 12C , a semiconductor package according to example embodiments may include top conductors extending in different directions. For example, a first top conductor TC1 may extend in a first horizontal direction D1, and a second top conductor TC2 may extend in a second horizontal direction D2.

[0117] In a plan view, an overlap region CR between the first interconnect conductor ITC1, the first pad PD1, the second interconnect conductor ITC2, and the second pad PD2 may be spaced apart from the first overlap region PR1. The overlap region CR may be surrounded by a first non-overlap region NR1 in which the first interconnect conductor ITC1, the first peripheral conductor PTC1, the second interconnect conductor ITC2, and the second peripheral conductor PTC2 do not overlap each other.

[0118] In a plan view, second overlapping regions PR2 in which the first interconnect conductor ITC1 and the second interconnect conductor ITC2 overlap the second peripheral conductor PTC2 and the first peripheral conductor PTC1, respectively, may be alternately disposed with the first overlapping regions PR1 in the first horizontal direction D1 and the second horizontal direction D2. The overlapping region CR may be surrounded by a second non-overlapping region NR2 between the first overlapping region PR1 and the second overlapping region PR2.

[0119] like Fig. 12B and Fig. 12C As shown, in the first non-overlapping region NR1 and the second non-overlapping region NR2, the expansion of the first passivation layer PSV1 and the second passivation layer PSV2 can be reduced, thereby suppressing the non-bonding between the first pad PD1 and the second pad PD2, and the non-bonding between the first passivation layer PSV1 and the second passivation layer PSV2, and ensuring the bonding reliability between the first recessed surface RS1 and the second recessed surface RS2.

[0120] FIG. 13A to FIG. 13E is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0121] refer to Fig.13A , a semiconductor wafer 100W for the first semiconductor chip 100 may be prepared. The semiconductor wafer 100W may include a plurality of first semiconductor chips 100 divided by a scribe line SL. The semiconductor wafer 100W may include a first substrate 110, a first circuit layer 120, and a first bonding layer 130 formed thereon. The first bonding layer 130 may include a first passivation layer PSV1 and a first pad PD1. The semiconductor wafer 100W may be disposed on a carrier CAR such that a first active surface AS1 of the semiconductor wafer 100W faces upward.

[0122] Subsequently, the preliminary semiconductor chip 200p may be attached to the semiconductor wafer 100W. The preliminary semiconductor chip 200p may include a preliminary substrate 210p before adjusting the thickness using a back grinding process, a second circuit layer 220 and a second bonding layer 230 disposed on the active surface AS2 of the preliminary substrate 210p, and a plurality of preliminary through electrodes 240p embedded in the preliminary substrate 210p. The second bonding layer 230 may include a second passivation layer PSV2 and a second pad PD2. The preliminary semiconductor chip 200p may be disposed on the semiconductor wafer 100W so that the second active surface AS2 contacts the first active surface AS1.

[0123] Thereafter, a thermal pressing process may be performed to couple the first semiconductor chip 100 and the preliminary semiconductor chip 200 p to each other. The thermal pressing process may be performed in a thermal atmosphere within a range of about 100° C. to about 300° C. However, the temperature of the thermal atmosphere is not limited to the above range and may vary.

[0124] refer to Fig. 13B The preliminary substrate 210p may be etched so that at least a portion of each of the plurality of preliminary through electrodes 240p is exposed to the inactive surface of the preliminary semiconductor chip 200p. A back grinding process and an etch-back process may be applied to the preliminary substrate 210p to form a second substrate 210 having a desired thickness (see Fig. 13C). For example, a back grinding process may be performed to reduce the thickness of the preliminary substrate 210p to a predetermined thickness, and an etch-back process may be applied under appropriate conditions to sufficiently expose the plurality of preliminary through electrodes 240p.

[0125] refer to Fig. 13C A preliminary mold layer 260p covering the preliminary semiconductor chip 200p may be formed. The preliminary mold layer 260p may cover the inactive surface of the preliminary semiconductor chip 200p and each of the plurality of preliminary through electrodes 240p exposed from the preliminary substrate 210p.

[0126] refer to Fig.13D , a polishing process may be applied to the preliminary mold layer 260p and the plurality of preliminary through electrodes 240p to form a plane including the mold layer 260 and the plurality of through electrodes 240. The polishing process may include a chemical mechanical polishing (CMP) process.

[0127] refer to Fig.13E , the protruding electrodes 252 and the connecting bumps 236 may be sequentially formed on a plane formed using a polishing process. Thereafter, the semiconductor packages may be separated from each other by performing a cutting process along the scribe lines SL.

[0128] According to example embodiments of the present disclosure, a semiconductor package may have improved reliability by minimizing an overlapping area between top conductors respectively adjacent to bonding pads.

[0129] While non-limiting example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, The first semiconductor chip is opposite to the second semiconductor chip in a vertical direction. Wherein, the first semiconductor chip comprises: a first substrate; a first interconnect on a first surface of the first substrate; a first insulating layer covering at least a portion of the first interconnect; at least one first pad on the first interconnect; and a first passivation layer surrounding at least a portion of the at least one first pad, wherein the second semiconductor chip comprises: a second substrate; a second interconnect on the first surface of the second substrate; a second insulating layer covering at least a portion of the second interconnect; at least one second pad, on the second interconnect, the at least one second pad contacting the at least one first pad; and a second passivation layer covering at least a portion of the at least one second pad, the second passivation layer being in contact with the first passivation layer, wherein the first interconnection member comprises at least one first interconnection conductor contacting the at least one first pad, and a first peripheral conductor on an opposite side of the at least one first interconnection conductor, the first peripheral conductor extending in a first horizontal direction, wherein the second interconnection member includes at least one second interconnection conductor contacting the at least one second pad, and a second peripheral conductor on an opposite side of the at least one second interconnection conductor, the second peripheral conductor extending in a second horizontal direction intersecting the first horizontal direction, and Wherein, in a plan view, first overlapping regions where the first outer conductor overlaps with the second outer conductor are spaced apart from each other in the first horizontal direction and the second horizontal direction.

2. The semiconductor package according to claim 1, wherein In a plan view, each of the first overlapping regions has a first width in the first horizontal direction and a second width in the second horizontal direction.

3. The semiconductor package according to claim 2, wherein The first width is equal to or greater than the line width of the second peripheral conductor, and The second width is equal to or greater than a line width of the first outer conductor.

4. The semiconductor package according to claim 3, wherein: Each of a line width of the first peripheral conductor and a line width of the second peripheral conductor is in a range of 1 μm to 50 μm.

5. The semiconductor package according to claim 1, wherein In a plan view, a second overlapping region where the at least one first interconnection conductor, the at least one first pad, the at least one second interconnection conductor, and the at least one second pad overlap is spaced apart from the first overlapping region.

6. The semiconductor package according to claim 5, wherein: The second overlapping region is surrounded by a non-overlapping region in which the at least one first interconnecting conductor, the first peripheral conductor, the at least one second interconnecting conductor, and the second peripheral conductor do not overlap with each other.

7. The semiconductor package according to claim 1, wherein: said at least one first interconnect conductor extending in said first horizontal direction, wherein the at least one second interconnect conductor extends in the second horizontal direction, and Wherein, in a plan view, the second overlapping region is spaced apart from a first overlapping region in the first overlapping region that is adjacent to the second overlapping region in the first horizontal direction and the second horizontal direction, and in the second overlapping region, the at least one first interconnecting conductor and the at least one second interconnecting conductor overlap with the second peripheral conductor and the first peripheral conductor, respectively.

8. The semiconductor package according to claim 7, wherein: A first gap between the first overlapping region and the second overlapping region in the first horizontal direction is equal to a first distance between the at least one second interconnect conductor and the second peripheral conductor, and A second gap between the first overlap region and the second overlap region in the second horizontal direction is equal to a second distance between the at least one first interconnect conductor and the first peripheral conductor.

9. The semiconductor package according to claim 7, wherein: the at least one first interconnection conductor comprises a plurality of first interconnection conductors spaced apart from each other in the second horizontal direction, wherein the at least one second interconnecting conductor comprises a plurality of second interconnecting conductors spaced apart from each other in the first horizontal direction, wherein the at least one first pad comprises a plurality of first pads respectively on each of the plurality of first interconnect conductors in the first horizontal direction, and The at least one second pad includes a plurality of second pads respectively on each of the plurality of second interconnection conductors in the second horizontal direction, and the plurality of second pads are respectively in contact with the plurality of first pads.

10. The semiconductor package according to claim 9, wherein In a plan view, the second overlapping regions where the plurality of first interconnect conductors and the plurality of second interconnect conductors overlap the second peripheral conductor and the first peripheral conductor, respectively, are alternately arranged with the first overlapping regions in the first horizontal direction and the second horizontal direction.

11. The semiconductor package according to claim 1, wherein The first interconnect further includes a first intermediate conductor between the at least one first interconnect conductor and the first surface of the first substrate, wherein the thickness of the at least one first interconnect conductor is greater than the thickness of the first intermediate conductor, wherein the second interconnect further comprises a second intermediate conductor between the at least one second interconnect conductor and the first surface of the second substrate, and Wherein, the thickness of the at least one second interconnecting conductor is greater than the thickness of the second intermediate conductor.

12. The semiconductor package according to claim 11, wherein The thickness of the at least one first pad is 0.5 times or more and 2 times or less than the thickness of the at least one first interconnect conductor, and The thickness of the at least one second pad is 0.5 times or more and 2 times or less than the thickness of the at least one second interconnect conductor.

13. The semiconductor package according to claim 1, wherein The first semiconductor chip also includes a first separate device on the first surface of the first substrate, the first separate device being electrically connected to the first interconnect, and Wherein, the second semiconductor chip further includes: a second individual device on the first surface of the second substrate, the second individual device being electrically connected to the second interconnect; a protruding electrode on a second surface of the second substrate opposite to the first surface of the second substrate; and A through electrode passes through the second substrate, the through electrode electrically connecting the second interconnection to the protruding electrode.

14. The semiconductor package according to claim 1, wherein: The first semiconductor chip also includes a first separate device on the first surface of the first substrate, the first separate device being electrically connected to the first interconnect, and Wherein, the second semiconductor chip further includes: a second separate device on a second surface of the second substrate opposite to the first surface of the second substrate; a front interconnect electrically connected to the second individual device; an interlayer insulating layer covering the front interconnection member; a front pad on the interlayer insulating layer and electrically connected to the front interconnection; and A through electrode passes through the second substrate, wherein the through electrode electrically connects the second interconnection to the front interconnection.

15. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, opposite to the first semiconductor chip, Wherein, the first semiconductor chip comprises: a first interconnect; at least one first pad on the first interconnect; and a first passivation layer covering at least a portion of the at least one first pad, wherein the second semiconductor chip comprises: a second interconnect; at least one second pad, on the second interconnect, the at least one second pad contacting the at least one first pad; and a second passivation layer covering at least a portion of the at least one second pad, the second passivation layer being in contact with the first passivation layer, wherein the first interconnection member comprises at least one first interconnection conductor in contact with the at least one first pad, the at least one first interconnection conductor being elongated in a first horizontal direction, and The second interconnection member includes at least one second interconnection conductor in contact with the at least one second pad, and the at least one second interconnection conductor is elongated in a second horizontal direction intersecting the first horizontal direction.

16. The semiconductor package according to claim 15, wherein: In a plan view, an overlapping region where the at least one first interconnect conductor overlaps the at least one second interconnect conductor has a first width in the first horizontal direction and a second width in the second horizontal direction, the first width being equal to or greater than a line width of the at least one second interconnect conductor in the first horizontal direction, and the second width being equal to or greater than a line width of the at least one first interconnect conductor in the second horizontal direction.

17. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, The first semiconductor chip is opposite to the second semiconductor chip in a vertical direction. Wherein, the first semiconductor chip comprises: a first interconnect; a first insulating layer covering at least a portion of the first interconnect; a plurality of first pads on the first insulating layer, the plurality of first pads being electrically connected to the first interconnect; and a first passivation layer covering at least a portion of the plurality of first pads, Wherein, the second semiconductor chip comprises: a second interconnect; a second insulating layer covering at least a portion of the second interconnect; a plurality of second pads on the second insulating layer, the plurality of second pads being electrically connected to the second interconnect, the plurality of second pads being in contact with the plurality of first pads respectively; and a second passivation layer covering at least a portion of the plurality of second pads, the second passivation layer being in contact with the first passivation layer, wherein the first interconnect comprises a first intermediate conductor and a first top conductor between the first intermediate conductor and the plurality of first pads in the vertical direction, wherein the second interconnect comprises a second intermediate conductor and a second top conductor between the second intermediate conductor and the plurality of second pads in the vertical direction, wherein at least some of the first top conductors extend in a first horizontal direction, and At least some of the second top conductors extend in a second horizontal direction intersecting the first horizontal direction.

18. The semiconductor package according to claim 17, wherein: The thickness of the first top conductor is greater than the thickness of the first middle conductor, and Wherein, the thickness of the second top conductor is greater than the thickness of the second middle conductor.

19. The semiconductor package according to claim 17, wherein: The first top conductor and the second top conductor include at least one of aluminum Al, copper Cu and alloys thereof, and Wherein, the plurality of first pads and the plurality of second pads include at least one of copper Cu and an alloy thereof.

20. The semiconductor package according to claim 17, wherein The first passivation layer and the second passivation layer include at least one of silicon oxide SiO and silicon carbon nitride SiCN.

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