Semiconductor device

Abstract

A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring, a ground wiring, a MOS transistor, and a flip-flop circuit are formed in the plurality of layers, in which a power supply voltage is supplied to the power supply wiring, a ground voltage is supplied to the ground wiring, the MOS transistor is connected to the power supply wiring and the ground wiring, and the flip-flop circuit is electrically connected to a gate electrode of the MOS transistor via the first wiring. A MOS transistor and a flip-flop circuit are formed in a first layer, a first wiring is formed in a second layer that is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction and electrically connected to the first portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Japanese Patent Application No. 2023-187662 filed on November 1, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, such as semiconductor devices including electrostatic discharge (ESD) protection circuits. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] U.S. Patent No. 7,397,642

[0006] For example, Patent Document 1 discloses an ESD protection circuit including a field effect transistor (hereinafter also referred to as a MOS transistor) having a low withstand voltage. That is, Patent Document 1 discloses an ESD protection circuit in which the source-drain paths of two N-channel MOSFETs each have a withstand voltage (3.3 V) lower than the power supply voltage (5 V) and are connected in series to a main discharge wiring, wherein the withstand voltage is supplied to the main discharge wiring connected to the ESD protection circuit. Summary of the invention

[0007] As described later with reference to the accompanying drawings, as a result of research conducted by the inventors before the present invention, the inventors have discovered the following problem: in a semiconductor device including an ESD protection circuit, since a large amount of wiring resources are allocated to the main discharge wiring connected to the ESD protection circuit, sufficient wiring resources are not allocated to the wiring in the ESD protection circuit, and thus the ESD protection function is degraded.

[0008] Patent Document 1 does not focus on the main discharge wiring and the wiring in the ESD protection circuit, and the above-mentioned problem is not pointed out in Patent Document 1.

[0009] A representative overview of the embodiments disclosed in this application will be briefly described below.

[0010] That is, a semiconductor device according to an embodiment includes a semiconductor chip having a plurality of layers formed on a surface. Here, in the plurality of layers, a first power wiring supplied with a power supply voltage, a second power wiring supplied with a ground voltage, a MOS transistor connected to the first power wiring and the second power wiring and configured to electrically short-circuit the first power wiring and the second power wiring, and a trigger circuit electrically connected to a first gate electrode of the MOS transistor via the first wiring and configured to output a first control signal for controlling the first gate electrode are formed, the MOS transistor and the trigger circuit are formed in a first layer among the plurality of layers, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction and electrically connected to the first portion. Supply in the supply direction upward

[0011] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0012] According to one embodiment, it is possible to provide a semiconductor device capable of suppressing degradation of an ESD protection function. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment.

[0014] Figure 2 is a block diagram illustrating the configuration of an ESD protection circuit according to the first embodiment.

[0015] Figure 3 is a plan view illustrating a schematic layout of the ESD protection circuit according to the first embodiment.

[0016] Figure 4A is a diagram for describing layers according to the first embodiment.

[0017] Figure 4B is a diagram for describing layers according to the first embodiment.

[0018] Figure 4C is a diagram for describing layers according to the first embodiment.

[0019] Figure 4D is a diagram for describing layers according to the first embodiment.

[0020] Figure 4E is a diagram for describing layers according to the first embodiment.

[0021] Figure 5 is a plan view illustrating a wiring layout in a dedicated wiring area according to the first embodiment.

[0022] Fig. 6A is a diagram for describing layers according to the first embodiment.

[0023] Figure 6B is a diagram for describing layers according to the first embodiment.

[0024] Figure 6C is a diagram for describing layers according to the first embodiment.

[0025] Fig.6D is a diagram for describing layers according to the first embodiment.

[0026] Fig. 6E is a diagram for describing layers according to the first embodiment.

[0027] Figure 7 is a plan view illustrating a wiring layout in a dedicated wiring area according to the first embodiment.

[0028] Figure 8 is a plan view illustrating the layout of power wiring and ground wiring according to the first embodiment.

[0029] Fig. 9 A to Fig. 9 C is a diagram for describing the discharge switch circuit according to the first embodiment.

[0030] Fig.10 is a block diagram illustrating a configuration of an ESD protection circuit according to a second embodiment.

[0031] Fig.11 is a plan view illustrating the layout of the ESD protection circuit according to the second embodiment.

[0032] Fig.12 A and Fig.12 B is a diagram for describing an ESD protection circuit studied by the inventors prior to the present invention.

[0033] Fig.13 It is illustrated in Fig.12 A is a plan view of a schematic layout of an ESD protection circuit illustrated in FIG. DETAILED DESCRIPTION

[0034] Each embodiment of the present invention will be described below with reference to the accompanying drawings. Incidentally, the present disclosure is just an example, and it goes without saying that any modification that can be easily imagined by those skilled in the art while maintaining the gist of the present invention is included in the present invention, if necessary.

[0035] Furthermore, the same reference numerals are applied to the same elements that have been described with respect to the aforementioned drawings in this specification and the corresponding drawings, and descriptions thereof will be appropriately omitted in some cases.

[0036] <Study by the Existing Inventors>

[0037] First, the project studied by the inventors will be described with reference to the accompanying drawings. Fig.12 A and Fig.12 B is a diagram for describing an ESD protection circuit studied by the inventors before the present invention. Here, Fig.12 A is a block diagram illustrating a configuration of an ESD protection circuit ESDP, and Fig.12 B is a characteristic diagram illustrating the characteristics of the ESD protection circuit ESDP.

[0038] also, Fig.13 It's a picture. Fig.12 A and Fig.12 B is a plan view of a schematic layout of an ESD protection circuit. The ESD protection circuit ESDP is formed on the semiconductor chip CHP constituting the semiconductor device. Although a plurality of circuit blocks including the ESD protection circuit ESDP are formed on the semiconductor chip CHP, Fig.13 Only a schematic layout of the ESD protection circuit ESDP formed on part of the semiconductor chip CHP is illustrated to avoid complicating the drawing.

[0039] exist Fig.12 In A, VCCQ indicates a power port, a power voltage VCC is supplied to VCCQ, and VSSQ indicates a ground port, a ground voltage VSS is supplied to VSSQ. The power wiring (hereinafter also referred to as the first power wiring) LVCC is connected to the power port VCCQ, and the ground wiring (hereinafter also referred to as the second power wiring) LVSS is connected to the ground port VSSQ. The ESD protection circuit ESDP is connected between the power wiring LVCC and the ground wiring LVSS. For example, when a steep high voltage is applied to the power terminal VCCQ, a current flows through (discharge is performed on) the power wiring LVCC, the ESD protection circuit ESDP, and the ground wiring LVSS. Therefore, it is possible to prevent the steep high voltage from damaging a circuit block (not shown) (such as a processing circuit, which is connected between the power wiring LVCC and the ground wiring LVSS and operates using the power voltage VCC as an operating voltage).

[0040] The power wiring LVCC and the ground wiring LVSS are used as paths when discharging, and thus can be considered as main discharge wiring (main discharge path). The main discharge wiring is not only used as a path when discharging, but also used to supply operating voltage to a large number of circuit blocks, and thus is configured using sufficient wiring resources to reduce conductive resistance.

[0041] The ESD protection circuit ESDP includes resistors R1 to R4, an NMOS switch circuit NMOS-SW1, time constant circuits (RC circuits) RC-1 and RC-2, inverter circuits INV-1 and INV-2, a discharge switch circuit B-NMOS, and a reverse diode REV-D.

[0042] exist Fig.12 In A, LINA to LINC indicate the wiring (internal wiring) of the circuit (including elements) constituting the ESD protection circuit ESDP in the ESD protection circuit. The resistor R1, the NMOS switch circuit NMOS-SW1, the time constant circuit RC-1 and the inverter circuit INV-1 are linked in parallel between the power wiring LVCC and the internal wiring LINC. In addition, the resistor R2, the time constant circuit RC-2 and the inverter circuit INV-2 are connected in parallel between the internal wiring LINC and the ground wiring LVSS. In addition, the discharge switch circuit B-NMOS is connected between the power wiring LVCC and the ground wiring LVSS. The discharge switch circuit B-NMOS includes two NMOS transistors BN1 and BN2. The source-drain paths of the two NMOS transistors BN1 and BN2 are connected in series between the power wiring LVCC and the ground wiring LVSS. Furthermore, the output of the inverter circuit INV- 1 is supplied to the gate electrode of the NMOS transistor BN2 via the internal wiring LINA, and the output of the inverter circuit INV- 2 is supplied to the gate electrode of the NMOS transistor BN2 via the internal wiring LINB.

[0043] For example, when a steep high voltage is applied to the power supply port VCCQ (when an ESD event occurs), the voltage increases the voltage of the internal wiring LINC, the internal wiring LINA, and the internal wiring LINB, and turns on both the NMOS transistor BN1 and the NMOS transistor BN2. Therefore, current flows through the discharge switch circuit B-NMOS in the ESD protection circuit ESDP, and protects the circuit block (not shown) connected to the power supply wiring LVCC from the high voltage.

[0044] When viewed in plan view, Fig.13As shown in FIG. 1 , the circuits (NMOS-SW1, RC-1, RC-2, INV-1, INV-2, B-NMOS, and REV-D) constituting the ESD protection circuit ESDP are densely arranged on the semiconductor chip. Because the wiring resources of the internal wiring LINA to the internal wiring LINC constituting the ESD protection circuit ESDP are smaller than the wiring resources constituting the main discharge wiring, the wiring resistance of the internal wiring LINA to the internal wiring LINC is high. If the wiring resistance of the internal wiring LINA to the internal wiring LINC is high, when a steep high voltage is applied, the voltage of the gate electrode of the NMOS transistor BN1 and the NMOS transistor BN2 cannot be sufficiently increased, thereby deteriorating the protection function of the ESD protection circuit ESDP.

[0045] exist Fig.12 In FIG. 1B , “V” on the horizontal axis represents the voltage applied to the ESD protection circuit ESDP, that is, the voltage applied to the power supply port VCCQ with the ground port VSSQ as a reference, and “I” on the vertical axis represents the current flowing through the ESD protection circuit ESDP. The main current flowing through the ESD protection circuit ESDP is the current flowing between the source and the drain of each of the NMOS transistors BN1 and BN2, which constitute the discharge switch circuit B-NMOS. Fig.12 As shown in FIG. 2B , when a high voltage VOV is applied to the power supply port VCCQ, a current I starts to flow. When the wiring resistance of the internal wiring LINA to the internal wiring LINC is high (reference symbol RH), the flowing current I decreases compared to the case where the wiring resistance is low (reference symbol RL). As the flowing current I decreases, the protection function of the ESD protection circuit ESDP deteriorates.

[0046] According to the embodiments to be described hereinafter, it is possible to suppress the degradation of the ESD protection function.

[0047] (First embodiment)

[0048] <Semiconductor equipment configuration>

[0049] Figure 1 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment. Figure 1 , the portion CHP illustrated in the dotted line indicates a semiconductor chip constituting a semiconductor device. Although not particularly limited, various circuit blocks are formed on the semiconductor chip CHP by known semiconductor manufacturing technology. The semiconductor chip CHP is sealed by using, for example, packaging to configure a semiconductor device. The ports (power supply port, ground port, input / output port, etc.) of the circuit blocks formed in the semiconductor chip CHP are connected to an exposed port (not shown) of the semiconductor device.

[0050] Although various circuit blocks are formed in the semiconductor chip CHP as described above, Figure 1 Only circuit blocks required for the specification are illustrated in order to avoid complicating the drawings.

[0051] exist Figure 1 Two circuit blocks (units) are shown as representatives. That is, Figure 1 The diagram shows a power supply unit PW_CL and a signal unit IO_CL, which are connected to a common power supply wiring LVCC and a ground wiring LVSS. Here, when an ESD event occurs, the power supply unit PW_CL corresponds to the ESD protection circuit, and the signal unit IO_CL corresponds to the protected circuit protected by the ESD protection circuit PW_CL. Of course, the protected circuit is not limited to the signal unit IO_CL, and may be any circuit block connected to the same power supply wiring LVCC and ground wiring LVSS as the power supply unit PW_CL. In addition, the number of protected circuits is not limited to one, and a power supply unit PW_CL shared by a plurality of protected circuits may be supplied. Figure 1 In the diagram, reference marks VCCQ and VSSQ are Fig.12 A and Fig.12 B are the same as those described in, and identify power ports and ground ports connected to power wiring and ground wiring.

[0052] The power supply unit PW_CL (ESD protection circuit ESDP) includes a trigger circuit TGC, a discharge switch circuit B-NMOS, and a reverse diode REV-D connected in parallel between the power wiring LVCC and the ground wiring LVSS. The discharge switch circuit B-NMOS is connected to the trigger circuit TGC via the internal wiring LINA and the internal wiring LINB and is controlled by the trigger circuit TGC. Although the discharge switch circuit B-NMOS and the trigger circuit TGC will be described below with reference to the accompanying drawings, for example, when a steep high voltage is applied to the power port VCCQ, the trigger circuit TGC controls the discharge switch circuit B-NMOS to turn on, so that the power wiring LVCC and the ground wiring LVSS are short-circuited by the discharge switch circuit B-NMOS to perform discharge.

[0053] The reverse diode REV-D has an anode connected to the ground wiring LVSS and a cathode connected to the power wiring LVCC, and performs discharge from the ground wiring LVSS to the power wiring LVCC (for example, when a steep high voltage is applied to the ground port VSSQ) to thereby provide protection.

[0054] Although not particularly limited, the signal unit IO_CL includes an input / output port IO, protection diodes P-D and N-D, and a signal processing circuit SPC. The signal processing circuit SPC and the protection diodes P-D and N-D connected in series are connected in parallel between the power supply wiring LVCC and the ground wiring LVSS. The signal processing circuit SPC performs a predetermined operation using the power supply voltage VCC as an operating voltage. For example, when the input / output port IO is an input port, the signal supplied to the input / output port is input to the signal processing circuit SPC, and the signal processing circuit SPC performs a predetermined operation on the input signal and outputs a signal OUT. The output signal OUT is supplied to another circuit block (not shown) and processed by the other circuit block.

[0055] The protection diode P-D has an anode connected to the input node SPC_I of the signal processing circuit SPC and a cathode connected to the power supply wiring LVCC, and the input node SPC_I is connected to the input / output port IO. In addition, the protection diode N-D has a cathode connected to the input node SPC_I and an anode connected to the ground wiring LVSS. The protection diodes P-D and N-D are operated to discharge current between the input / output port IO and the power supply wiring LVCC or the ground wiring LVSS when a high voltage or a negative voltage is applied to the input / output port IO, and function to prevent the signal processing circuit SPC from being damaged by the high voltage or the negative voltage.

[0056] <ESD protection circuit (flip-flop circuit and discharge switch circuit) configuration>

[0057] Then, the configuration of the flip-flop circuit TGC and the discharge switch circuit B-NMOS illustrated in Figure 1 will be described with reference to the drawings.

[0058] Figure 2 is a block diagram illustrating the configuration of the ESD protection circuit according to the first embodiment. Here, an ESD protection circuit having a configuration similar to that in Fig.12 A is described as an example, but the present invention is not limited thereto.

[0059] 《Discharge switch circuit》

[0060] In the ESD protection circuit ESDP (power supply unit PW_CL), the discharge switch circuit B-NMOS includes two NMOS transistors BN1 and BN2, whose source-gate paths are connected in series between the power supply wiring LVCC and the ground wiring LVSS. Incidentally, the back gate electrodes of the NMOS transistors BN1 and BN2 are connected to the ground wiring LVSS. Here, an example is described in which the discharge switch circuit B-NMOS includes two NMOS transistors connected in series, but the present invention is not limited thereto. That is, the discharge switch circuit B-NMOS may include, for example, one MOS transistor, or may include three or more MOS transistors as described in the second embodiment.

[0061] Trigger Circuit

[0062] In the ESD protection circuit ESDP, the trigger circuit TGC includes resistors R1 to R4, an NMOS switch circuit NMOS-SW1, time constant circuits RC-1 and RC-2, inverter circuits INV-1 and INV-2, and internal wiring LINC. In addition, the trigger circuit TGC and gate electrodes of the NMOS transistors BN1 and BN2 constituting the discharge switch circuit B-NMOS are connected through internal wirings LINA and LINB and the like, and the trigger circuit TGC supplies a first control signal for controlling the NMOS transistors BN1 and BN2 to the gate electrodes (corresponding to the first gate electrodes) of the NMOS transistors BN1 and BN2.

[0063] In the case where the discharge switch circuit B-NMOS is considered to be formed by two-stage NMOS transistors, the trigger circuit TGC can also be considered to be formed by two stages. That is, it can be considered that the time constant circuit RC-1 and the inverter circuit INV-1 constitute the stage corresponding to the NMOS transistor BN1, and the time constant circuit RC-2 and the inverter circuit INV-2 constitute the stage corresponding to the NMOS transistor BN2. In this case, it can be considered that the NMOS switch circuit NMOS-SW1 constitutes the stage corresponding to the NMOS transistor BN1 or is commonly supplied to the two stages. In this case, the internal wiring LINA and the internal wiring LINB can be regarded as wiring connecting the corresponding stages.

[0064] The resistor R1 and the resistor R2 are connected in series between the power supply wiring LVCC and the ground wiring LVSS. The internal wiring LINC is connected to a connection node connecting the resistor R1 and the resistor R2.

[0065] The NMOS switch circuit NMOS-SW1 and the time constant circuit RC-1 are connected in parallel between the power supply wiring LVCC and the internal wiring LINC.

[0066] In addition, the inverter circuit INV-1 is also connected between the power supply wiring LVCC and the internal wiring LINC, and the inverter circuit INV-1 is operated using the voltage difference between the power supply wiring LVCC and the internal wiring LINC as an operation voltage. That is, the source-drain paths of the P-channel MOS transistor (hereinafter also referred to as the PMOS transistor) P1 and the NMOS transistor N1 constituting the inverter circuit INV-1 are connected in series between the power supply wiring LVCC and the internal wiring LINC.

[0067] The output signal OUT_1 of the time constant circuit RC-1 is supplied to the gate electrodes of the PMOS transistor P1 and the NMOS transistor N1 constituting the inverter circuit INV-1. In addition, the connection node connecting the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 is connected to the internal wiring LINA, and the internal wiring LINA is connected to the gate electrode of the NMOS transistor BN1. In addition, the resistor R3 is connected between the internal wiring LINA and the internal wiring LINC.

[0068] The time constant circuit RC-2 is connected between the internal wiring LINC and the ground wiring LVSS. In addition, the inverter circuit INV-2 is connected between the internal wiring LINC and the ground wiring LVSS, and the inverter circuit INV-2 is operated using the voltage difference between the internal wiring LINC and the ground wiring LVSS as an operation voltage. That is, the source-drain paths of the PMOS transistor P2 and the NMOS transistor N2 constituting the inverter circuit INV-2 are connected in series between the internal wiring LINC and the ground wiring LVSS.

[0069] The output signal OUT_2 of the time constant circuit RC-2 is supplied to the gate electrodes of the PMOS transistor P2 and the NMOS transistor N2 constituting the inverter circuit INV-2. In addition, the connection node connecting the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 is connected to the internal wiring LINB, and the internal wiring LINB is connected to the gate electrode of the NMOS transistor BN2. In addition, the resistor R4 is connected between the internal wiring LINB and the ground wiring LVSS.

[0070] Although not particularly limited, the NMOS switch circuit NMOS-SW1 includes an NMOS transistor N3 having a source-drain path connected between the power wiring LVCC and the internal wiring LINC. When a steep high voltage is applied to the power supply port VCCQ, the NMOS transistor N3 becomes conductive, and the NMOS switch circuit NMOS-SW1 causes the internal wiring LINC to rise to the voltage at the power wiring LVCC.

[0071] The time constant circuit RC-1 includes a capacitive element. Although there is no particular limitation, the capacitive element includes an NMMOS transistor N4 having a source and a drain connected to each other. When a steep high voltage is applied to the power supply port VCCQ, charging (including discharging) of the capacitive element (NMOS transistor N4) is performed in the time constant circuit RC-1, and during the period of charging of the capacitive element, the time constant circuit RC-1 sets the output signal OUT_1 to a low voltage (the voltage of the internal wiring LINC) and then sets the output signal OUT_1 to a high voltage (the voltage of the power supply wiring LVCC). That is, when a steep high voltage is applied to the power supply port VCCQ, the time constant circuit RC-1 sets the output signal OUT_1 to a low voltage within a time determined by the capacitive element.

[0072] The time constant circuit RC-2 is configured similarly to the time constant circuit RC-1, and when a steep high voltage is applied to the power supply VCCQ and the voltage of the internal wiring LINC increases, the time constant circuit RC-1 sets the output signal OUT_2 to a low voltage and then, similar to the time constant circuit RC-2, sets the output signal OUT_2 to a high voltage within a time determined by a capacitive element (not shown) included in the time constant circuit RC-2.

[0073] In response to the output signal OUT_1 of the time constant circuit RC-1, the inverter circuit INV-1 supplies the voltage (high level) of the power wiring LVCC or the voltage (low level) of the internal wiring LINC to the internal wiring LINA. The voltage propagates through the internal wiring LINA and is supplied to the gate electrode of the NMOS transistor BN1. Similarly, in response to the output signal OUT_2 of the time constant circuit RC-2, the inverter circuit INV-2 supplies the voltage (high level) of the internal wiring LINC or the voltage (low level) of the ground wiring to the internal wiring LINB. The voltage propagates through the internal wiring LINB and is supplied to the gate electrode of the NMOS transistor BN2.

[0074] When a steep high voltage is applied to the power supply port VCCQ, each of the output signal OUT_1 and the output signal OUT_2 is set to a low voltage within the time determined by the capacitive element, and the inverter circuit INV-1 and the inverter circuit INV-2 supply a high-high level to the internal wirings LINA and LINB, respectively. Therefore, when a steep high voltage is applied to the power supply port VCCO, both the NMOS transistor BN1 and the NMOS transistor BN2 are in a wired state, and the high voltage is discharged via the power supply wiring LVCC, the discharge switch circuit B-NMOS, and the ground wiring LVSS, and it is possible to prevent, for example Figure 1 the signal unit IO_CL illustrated in

[0075] from being damaged by the high voltage.

[0076] <Layout of the ESD protection circuit>

[0077] Figure 3 is a plan view illustrating the layout of the ESD protection circuit according to the first embodiment. As referred to Fig.13 above, the ESD protection circuit ESDP is formed on the semiconductor chip CHP constituting the semiconductor device. Although a plurality of circuit blocks including the ESD protection circuit ESDP (e.g., Figure 1 the signal unit IO_CL, etc. in Figure 3 are formed on the semiconductor chip CHP illustrated by the dashed line, only a schematic layout of the ESD protection circuit ESDP formed on a part of the semiconductor chip CHP is also illustrated so as not to complicate the drawing.

[0078] In the following description of the layout, the horizontal direction in the figure is the X direction (first direction) and the direction intersecting the X direction (i.e., the vertical direction in the figure) is the Y direction (second direction). With respect to including Figure 3In the layout diagram of FIG. 1 , arrows marked with reference signs X and Y respectively indicate the X direction and the Y direction.

[0079] In a plan view, the layout of the ESD protection circuit ESDP according to the first embodiment is similar to Fig.13 Unlike the layout of the ESD protection circuit illustrated in FIG. 1 , the main surface of the semiconductor chip CHP is viewed from above in a plan view. That is, the layout of the ESD protection circuit according to the first embodiment is provided with a dedicated wiring area (dedicated wiring space) in which the internal wiring of the ESD protection circuit ESDP (e.g. Figure 2 The internal wiring provided in the dedicated wiring area bundles the wirings connecting the circuits constituting the ESD protection circuit into one bundle, so that the wiring resistance of the wirings connecting the circuits may be reduced, and the degradation of the ESD protection function may be suppressed.

[0080] exist Figure 3 In the embodiment of the present invention, the dedicated wiring areas are identified by reference marks EXLSP-11 and EXLSP-21. The layout of the ESD protection circuit ESDP will be described in detail below.

[0081] exist Figure 3 In the embodiment, the discharge switch circuit B-NMOS, the reverse diode REV-D, the inverter circuit INV-2 and the inverter circuit INV-1, the time constant circuits RC-2 and RC-1, and the NMOS switch circuit NMOS-SW1 are placed in this order from the bottom to the top of the paper surface in the Y direction. In this case, the inverter circuit INV-2 and the inverter circuit INV-1 are arranged in this order from the bottom to the top of the paper surface in the X direction. Figure 3 The time constant circuit RC- 2 and the time constant circuit RC- 1 are horizontally placed in this order from the left side to the side edge of the paper surface, and similarly, the time constant circuit RC- 2 and the time constant circuit RC- 1 are horizontally placed in this order from the left side to the side edge of the paper surface.

[0082] like Figure 3 As shown in FIG. 1 , the dedicated wiring area EXLSP-11 is disposed above the time constant circuit RC-2 and the time constant circuit RC-1, and is partially disposed between the time constant circuit RC-2 and the NMOS switch circuit NMOS-SW1. Figure 3 As shown in FIG. 1 , the dedicated wiring area EXLSP- 21 is provided between the inverter circuit INV- 2 and the inverter circuit INV- 1 and the reverse diode REV-D.

[0083] Although it will be described later, a plurality of wirings are provided in the dedicated wiring area EXLSP-11, and the plurality of wirings are electrically connected to the wiring of the NMOS switch circuit NMOS-SW1, the wiring of the time constant circuit RC-2, the wiring of the time constant circuit RC-1, the wiring of the inverter circuit INV-2, and the wiring of the inverter circuit INV-1. It can be considered that the plurality of wirings provided in the dedicated wiring area EXLSP-11 constitute Figure 2 The internal wiring shown in LINC.

[0084] Although it will be described later, two wirings each including a plurality of wirings are arranged in the dedicated wiring area EXLSP-21. Figure 3 In FIG. 1 , two wirings are distinguished by a solid line and a dotted line. One wiring (dashed line) is electrically connected to the wiring of the inverter circuit INV-1 and the discharge switch circuit B-NMOS, and the other wiring (solid line) is electrically connected to the wiring of the inverter circuit INV-2 and the discharge switch circuit B-NMOS. It can be considered that the dotted wiring and the solid wiring provided in the dedicated wiring area EXLSP-21 form Figure 2 The internal wiring shown in LINA and Figure 2 The internal wiring shown in LINB.

[0085] Incidentally, Figure 3 Omitted Figure 2 Similarly, resistors corresponding to the resistors R1 to R4 are omitted in the following drawings related to the layout.

[0086] <Semiconductor Layer and Wiring Layer>

[0087] A plurality of layers (including semiconductor layers (such as diffusion regions and wiring layers)) formed on the surface of the semiconductor chip CHP form elements (such as MOS transistors and internal wiring (including wiring from LINA to LINC and connecting circuits)), power wiring LVCC, ground wiring LVSS, and the like that constitute the ESD protection circuit ESDP.

[0088] For example, in the case of a MOS transistor, a diffusion region of a source region, a drain region, and the like and a gate electrode provided with an inserted gate insulating film are formed on the surface of the semiconductor chip CHP, thereby forming a MOS transistor. In this specification, a description is given assuming that a diffusion region forming a source region and a drain region and a gate electrode provided with an inserted gate insulating film are formed with a layer (hereinafter also referred to as a diffusion layer or a first layer) formed on the surface of the semiconductor chip CHP.

[0089] In the first embodiment, with the surface of the semiconductor chip CHP as a reference, a plurality of wiring layers are formed on the diffusion layer. Each wiring layer is a conductive metal layer, and, for example, 14 wiring layers (metal wiring layers, hereinafter also referred to as metal layers) are formed above the diffusion layer. In this case, an insulating layer for electrical insulation between layers is formed between the diffusion layer and the metal layer (hereinafter also referred to as the first metal layer) closest to the diffusion layer and between metal layers close to each other in the upper layer of the first metal layer. In order to form the required circuit block, a contact hole is formed in the insulating layer between the diffusion layer and the first metal layer, and the diffusion layer and the first metal layer wiring formed using the first metal layer are electrically connected via the contact hole. In addition, the insulating layer between the metal layers will also be turned on when necessary, and the wiring formed using the metal layer is electrically connected through the via-hole.

[0090] Hereinafter, a description will be given with reference to the accompanying drawings. Hereinafter, a description will be given of an area including the dedicated wiring area EXLSP-21 and an area including the dedicated wiring area EXLSP-11, respectively. Figure 3 The ESD protection circuit ESDP shown in FIG.

[0091] 《Area including dedicated wiring area EXLSP-21》

[0092] FIG. 4A to FIG. 4E is a diagram for describing layers according to the first embodiment. FIG. 4A to FIG. 4E Schematically illustrates the Figure 3 The layout of the ESD protection circuit ESDP shown in FIG. 1 is a portion corresponding to the inverter circuit INV-1 and the inverter INV-2, the dedicated wiring area EXLSP-21, the reverse diode REV-D, and the discharge switch circuit B-NMOS. Here, Figure 4A The figure shows a diffusion layer formed on the semiconductor chip CHP. Figure 4B The diagram shows a first metal layer formed on the diffusion layer, and Figure 4C A second metal layer formed on the diffusion layer and closest to the first metal layer is illustrated. Figure 4D An example of a third metal layer to a twelfth metal layer as upper layers of the second metal layer is illustrated, and Figure 4E The thirteenth and fourteenth metal layers are illustrated as upper layers of the twelfth metal layer. Although not particularly limited, the thirteenth and fourteenth metal layers are used to supply a power supply voltage VCC and a ground voltage, and the first to twelfth metal layers are used to connect elements and circuits or the like. In this specification, the first to twelfth metal layers are also referred to as the second layer hereinafter, relative to the diffusion layer (first layer), which is an upper layer of the diffusion layer.

[0093] exist Figure 4A, the solid line D-AR indicates a diffusion region formed on the surface of the semiconductor chip CHP, and the solid line G-AR indicates a gate electrode formed on the surface of the semiconductor chip CHP, with a gate insulating film inserted therebetween. The MOS transistors constituting the inverter circuit INV-1 and the inverter circuit INV-2 and the discharge switch circuit B-NMOS include the diffusion region D-AR and the gate electrode G-AR. In addition, the reverse diode REV-D also includes the diffusion region D-AR. Incidentally, in Figure 4A In the figure, for schematic illustration, diffusion regions of different conductivity types are illustrated identically.

[0094] exist Figure 4A The area surrounded by the dotted line indicates Figure 3 In the first embodiment, the components constituting the ESD protection circuit ESDP are not formed in the dedicated wiring area ECLSP-21. That is, Figure 4A The portion of the dedicated wiring region EXLSP-21 corresponds to the surface of the semiconductor chip CHP.

[0095] exist Figure 4B In FIG. 1 , M1 indicates a first layer wiring formed using a first metal layer, the first metal layer is formed on a diffusion layer, and the diffusion layer is formed on the semiconductor chip CHP with an insulating layer (not shown) interposed therebetween. Figure 4B In the example, M1-E indicates a first layer wiring formed using a first metal layer, and the first metal layer is formed on the dedicated wiring area EXLSP-21 in the semiconductor chip CHP with an insulating layer (not shown) interposed therebetween. Figure 4A As shown in the figure, the diffusion region D-AR and the gate electrode G-AR are not formed in the dedicated wiring region EXLSP-21, and the first layer wiring M1-E is formed on the surface of the semiconductor chip CHP with an insulating layer (not shown) interposed therebetween.

[0096] exist Figure 4C In FIG. 1 , M2 indicates a second layer wiring formed on the semiconductor chip CHP using a second metal layer made of metal and formed on the first metal layer with an insulating layer (not shown) interposed therebetween. Figure 4C , M2-E indicates a second layer wiring formed using a second metal layer made of metal in the dedicated wiring area EXLSP-21, and formed on the first metal layer with an insulating layer (not shown) interposed therebetween.

[0097] like Figure 4B As shown, in principle, the first layer wiring M1 is formed to extend in the Y direction and to be arranged side by side in the X direction. Figure 4CAs shown, in principle, the second layer wiring M2 is formed to extend in the X direction and to be arranged side by side in the Y direction. Therefore, it is possible to form the inverter circuit INV-1 and the inverter INV-2 and the discharge switch circuit B-NMOS by connecting elements (such as MOS transistors) using the first layer wiring M1 and the second layer wiring M2. For example, the diffusion region can be connected to the MOS transistor (for example) by using the first layer wiring M1 and the second layer wiring M2 through the opening of the insulating layer. Figure 2 , N1 and P1) to realize the inverter circuit INV-1.

[0098] like Figure 4B As shown in FIG. 1 , the first layer wiring M1-E is formed in the dedicated wiring area EXLSP-21 to extend in the X direction and to be arranged side by side in the Y direction. Figure 4C As shown, the second layer wiring M2-E is also formed to extend in the X direction and to be arranged side by side in the Y direction. As will be described later with reference to the drawings, an opening is provided in the insulating layer between the first layer wiring M1-E and the second layer wiring M2-E, and the first layer wiring M1-E and the second layer wiring M2-E are electrically connected through a via-hole.

[0099] A plurality of metal layers (in the first embodiment, the third metal layer to the twelfth metal layer) are formed over the second layer wiring, using Figure 4C The second metal layer shown in forms the second layer wiring. Figure 4D The diagram shows a third layer wiring formed using a third metal layer in these metal layers. Figure 4D , M3 indicates a third layer wiring, and the third layer wiring M3 is formed to extend in the Y direction and to be arranged side by side in the X direction.

[0100] In the first embodiment, a plurality of circuits formed using a diffusion layer, a first metal layer, and a second metal layer are connected by a third-layer wiring to a twelfth-layer wiring, and a third-layer wiring to a twelfth-layer wiring is formed using the third metal layer to the twelfth metal layer. For example, as described above, the inverter circuit INV-1 is realized by connecting elements using the first-layer wiring M1 and the second-layer wiring M2, the first-layer wiring M1 is formed using the first metal layer, the second-layer wiring M2 is formed using the second metal layer, and the electrical connection between the inverter circuit INV-1 and the discharge switch circuit B-NMOS is realized by using the third-layer wiring to the twelfth-layer wiring formed by the third metal layer to the twelfth metal layer and the wiring set in the dedicated wiring area EXLSP-21. Here, the connection between the inverter circuit INV-1 and the discharge switch circuit B-NMOS is described as an example, but the same is applied to the connection between the inverter circuit INV-2 and the discharge switch circuit B-NMOS.

[0101] A thirteenth metal layer and a fourteenth metal layer are formed over the twelfth metal layer. FIG. 4 illustrates the thirteenth metal layer and the fourteenth metal layer formed over the twelfth metal layer on the surface of the semiconductor chip CHP. Figure 4E , the dotted line M13 indicates the thirteenth layer wiring formed using the thirteenth metal layer, and the dotted line M14 indicates the fourteenth layer wiring formed using the fourteenth metal layer. Although not particularly limited, the thirteenth layer wiring M13 is formed to extend in the X direction and arranged side by side in the Y direction, and the fourteenth layer wiring M14 is placed to extend in the Y direction and arranged side by side in the X direction.

[0102] In the first embodiment, some of the thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 formed using the thirteenth metal layer and some of the fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 formed using the fourteenth metal layer are electrically connected to form a power wiring LVCC. In addition, other thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 and other fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 are electrically connected to form a ground wiring LVSS.

[0103] The connection between the circuit constituting the ESD protection circuit ESDP (e.g., the inverter circuit INV-1) and the power wiring LVCC is realized by connecting the inverter circuit INV-1 with the thirteenth-layer wiring M13 and the fourteenth-layer wiring M14 constituting the power wiring LVCC using the third-layer wiring M3 to the twelfth-layer wiring M12. Similarly, the connection between the inverter circuit INV-1 and the ground wiring LVSS is also realized by connecting the inverter circuit INV-1 with the thirteenth-layer wiring M13 and the fourteenth-layer wiring M14 constituting the ground wiring LVSS using the third-layer wiring M3 to the twelfth-layer wiring M12.

[0104] "Wiring layout in dedicated wiring area"

[0105] Then, the detailed layout of the dedicated wiring area EXLSP-21 will be described with reference to the drawings. Figure 5 1 is a plan view illustrating a wiring layout in the dedicated wiring area EXLSP-21 according to the first embodiment. Figure 3 As shown in FIG. 1 , the internal wiring LINA and the internal wiring LINB are provided in the dedicated wiring area EXLSP-21, and the gate electrodes of the NMOS transistors BN1 and BN2 of the inverter circuit INV-1 and the inverter circuit INV-2 and the discharge switch circuit B-NMOS are connected using the internal wiring LINA and the internal wiring LINB. Figure 5In FIG. 1 , first-layer wirings M1 and M1-E formed using a first metal layer are illustrated with dotted lines, and second-layer wirings M2 and M2-E formed using a second metal layer and third-layer wiring M3 formed using a third metal layer are illustrated with solid lines. Figure 5 In FIG. 1 , BH indicates via-hole.

[0106] Although not particularly limited, in the first embodiment, the internal wiring LINA is composed of six wirings LINA_1 to LINA_6, and the internal wiring LINB is also composed of six wirings LINB_1 to LINB_6.

[0107] The first layer wiring M1-E formed by the first metal layer and the second layer wiring M2-E formed by the second metal layer constitute each of the wirings LINA_1 to LINA_6 and the wirings LINB_1 to LINB_6. That is, Figure 5 As shown in , when viewed in a plan view, the first layer wiring M1-E and the second layer wiring M2-E are formed to overlap each other, and the first layer wiring M1-E and the second layer wiring M2-E are electrically connected through the via-hole BH shown in the dotted line. Figure 5 The first layer wiring M1 -E is drawn larger than the second layer wiring M2 -E so that the wirings can be more easily distinguished, but the present invention is not limited thereto.

[0108] exist Figure 5 In FIG. 1 , the first layer wiring M1 is arranged outside the dedicated wiring area EXLSP- 21 along the Y direction, which indicates the first layer wiring of the inverter circuit INV- 1 and the inverter circuit INV- 2 . Figure 5 In, as reference Figure 2 As described above, the three first layer wirings M1 enclosed by reference numeral INV-1 are connected to the drain region of the PMOS transistor P1 and the drain region of the NMOS transistor N1. Figure 2 As described above, the three first layer wirings M1 enclosed by reference symbol INV-2 are connected to the drain region of the PMOS transistor P2 and the drain region of the NMOS transistor N2.

[0109] Although not particularly limited, the first layer wiring M1 of the inverter circuit INV-1 is connected to the third layer wiring M3-A formed by the third metal layer through the via-hole BH illustrated in a circle, and the third layer wiring M3-A is connected to the first layer wiring M1-E and the second layer wiring M2-E constituting each of the internal wirings LINA_1 to LINA_6 through the via-hole BH. In addition, the third layer wiring M3-A is connected to the gate electrode of the NMOS transistor BN1 constituting the discharge switch line B-NMOS.

[0110] Similarly, the first layer wiring M1 of the inverter circuit INV-2 is connected to the third layer wiring M3-B formed by the third metal layer through the via-hole BH, and the third layer wiring M3-B is connected to the first layer wiring M1-E and the second layer wiring M2-E constituting each of the internal wirings LINB_1 to LINB_6 through the via-hole BH. The third layer wiring M3-B is connected to the gate electrode of the NMOS transistor BN2 constituting the discharge switch circuit B-NMOS.

[0111] The wiring (hereinafter also referred to as the first wiring and the third wiring) connecting the inverter circuit INV-1 and the inverter circuit INV-2 and the discharge switch circuit B-NMOS, that is, connecting Figure 1 The first wiring and the third wiring of the trigger circuit TGC and the discharge switch circuit B-NMOS shown in the figure include the internal wiring (first part) LINA and the internal wiring LINB extending in the X direction and the third layer wiring (second part) M3-A and the third layer wiring M3-B extending in the Y direction intersecting with the X direction. In this case, a plurality of ( Figure 5 The third layer wiring M3-A (M3-B) is electrically connected to be bundled by a plurality of internal wirings LINA_1 to LINA_6 (LINB_1 to LINB_6). Therefore, the combined resistance value of the third layer wiring M3-A (M3-B) is less than or equal to the resistance value of the internal wiring LINA (LINB). In addition, the first layer wiring M1-E and the second layer wiring M2-E are also electrically connected in parallel in the internal wiring LINA (LINB) for bundling the third layer wiring M3-A (M3-B) into a bundle, which can reduce the combined resistance value of the internal wiring LINA (LINB), and the wiring with a low resistance value can bundle the third layer conductive M3-A (M3-B) into a bundle.

[0112] Figure 5 An example is illustrated in which the third layer wiring formed using the third metal layer is used as the wiring connecting the inverter circuit INV-1 and the inverter circuit INV-2, the internal wiring (LINA, LINB), and the discharge switch circuit B-NMOS, but the present invention is not limited thereto, and any of the fourth layer wiring to the twelfth layer wiring can be used. In addition, the number of wirings constituting each of the internal wiring LINA and the internal wiring LINB is not limited to 6, and can be, for example, 1. In addition, for example, the inverter circuit and the internal wiring, and the internal wiring and the discharge switch circuit can be connected by mutually different third layer wirings M3-A (M3-B).

[0113] Figure 5An example is illustrated in which the internal wiring LINA and the internal wiring LINB are placed in parallel in the X direction, but the present invention is not limited thereto, and for example, parts of the internal wiring LINA and the internal wiring LINB may be placed in parallel.

[0114] 《Area including dedicated wiring area EXLSP-11》

[0115] FIG. 6A to FIG. 6E is a diagram for describing layers according to the first embodiment. FIG. 6A to FIG. 6E Schematically illustrates the Figure 3 The layout of the ESD protection circuit ESDP shown in FIG. 1 includes the NMOS switch circuit NMOS-SW1, the dedicated wiring area EXLSP-11, the time constant circuit RC-1 and the time constant circuit RC-2, and the inverter circuit INV-1 and the inverter circuit INV-2. Here, FIG. 6A to FIG. 6E and FIG. 4A to FIG. 4E That is to say, Fig. 6A The figure shows a diffusion layer formed on the semiconductor chip CHP. Figure 6B The diagram shows a first metal layer formed on the diffusion layer, and Figure 6C The diagram shows a second metal layer formed on the diffusion layer with an insulating layer interposed therebetween. Fig.6D The diagram shows a third metal layer among the third metal layer to the twelfth metal layer formed on the second metal layer with an insulating layer interposed therebetween, and Fig. 6E The diagram illustrates a thirteenth metal layer and a fourteenth metal layer formed on the twelfth metal layer with an insulating layer interposed therebetween.

[0116] because FIG. 6A to FIG. 6E and FIG. 4A to FIG. 4E Similarly, detailed descriptions thereof except for the dedicated wiring area EXLSP-11 are omitted. In the dedicated wiring area EXLSP-11, as shown in FIG. Figure 6B As shown in FIG. 1 , a first layer wiring M1-E is formed by a first metal layer on the surface of a semiconductor chip, with an insulating layer interposed therebetween. Figure 6C As shown in FIG. 6 , a second layer wiring M2-E formed of a second metal layer is formed on the first layer wiring M1-E in the dedicated wiring area EXLSP-11, with an insulating layer interposed therebetween. When viewed in a plan view, the first layer wiring M1-E and the second layer wiring M2-E are placed to overlap each other, which are connected by via-holes and serve as internal wiring LINC. The internal wiring LINC is connected to the NMOS switch circuit NMOS-SW1, the time constant circuit RC-1 and the time constant circuit RC-2, and the inverter circuit INV-1 and the inverter circuit INV-2 through the third layer wiring M3 shown in FIG. 6 and the like.

[0117] "Wiring layout in dedicated wiring area"

[0118] Then, the detailed layout of the dedicated wiring area EXLSP-11 will be described in detail with reference to the drawings. Figure 7 FIG. 1 is a plan view illustrating a wiring layout in a dedicated wiring area according to one embodiment. Figure 3 As shown in FIG. 1 , the internal wiring LINC is provided in the dedicated wiring area EXLSP-11 and the NMOS switch circuit NMOS-SW1, the inverter circuit INV-1 and the inverter circuit INV-2, and the time constant circuit RC-1 and the time constant circuit RC-2 are connected using the internal wiring LINC. Figure 7 , first layer wirings M1 and M1 -E formed using a first metal layer are illustrated with dotted lines, and second layer wirings M2 and M2 -E formed using a second metal layer and third layer wiring M3 formed using a third metal layer are illustrated with solid lines.

[0119] Although not particularly limited, eight wirings LINC_1 to LINC_8 constitute the internal wiring LINC in the first embodiment.

[0120] Similar to the internal wiring LINA_1 to the internal wiring LINA_6 described above, the first layer wiring M1-E formed by the first metal layer and the second layer wiring M2-E formed by the second metal layer constitute each of the wirings LINC_1 to LINC_8. Figure 7 As illustrated in FIG. 1 , when viewed in a plan view, the first layer wiring M1-E and the second layer wiring M2-E are formed to overlap each other, and the first layer wiring M1-E and the second layer wiring M2-E are electrically connected through the via-hole BH. Figure 7 , the first layer wiring M1 -E is drawn larger than the second layer wiring M2 -E so that the wirings can be easily distinguished.

[0121] exist Figure 7 In FIG. 1 , the first layer wiring M1 placed outside the dedicated wiring area EXLSP-11 along the Y direction indicates the first layer wiring of the NMOS switch circuit NMOS-SW1. Figure 7 In, as reference Figure 2 As described above, the three first layer wirings M1 enclosed by reference symbol NMOS-SW1 are connected to, for example, the source region of the NMOS transistor N3.

[0122] Although not particularly limited, the first layer wiring M1 of the NMOS switch circuit NMOS-SW1 is connected to the third layer wiring M3-2 formed by the third metal layer through the via-hole BH illustrated in a circle, and the third layer wiring M3-2 is connected to the first layer wiring M1_E and the second layer wiring M2_E constituting each of the internal wiring LINC_1 to the internal wiring LINC_8 through the via-hole BH. In addition, these third layer wirings M3-2 are connected to the time constant circuit RC-2 and the inverter circuit INV-2.

[0123] Similarly, the third layer wiring M3-1 is connected to the first layer wiring M1_E and the second layer wiring M2_E constituting each of the internal wiring LINC_1 and the internal wiring LINC_8 through the via-hole BH. These third layer wirings M3-1 are connected to the time constant circuit RC-2 and the inverter circuit INV-2.

[0124] The wiring (hereinafter also referred to as the second wiring) connecting the NMOS switch circuit NMOS-SW1, the time constant circuit RC-1 and the time constant circuit RC-2, the inverter circuit INV-1 and the inverter circuit INV-2 includes the internal wiring (first part) LINC extending in the X direction and the third layer wiring (second part) M3-1 and the third layer wiring M3-2 extending in the Y direction intersecting the X direction. In this case, since the corresponding third layer wiring M3-1 and the third layer wiring M3-2 are electrically connected to be bundled by a plurality of internal wirings LINC_1 to LINC_8, the resistance value of the third layer wiring M3-1 and the third layer wiring M3-1 is less than or equal to the resistance value of the internal wiring LINC.

[0125] Figure 7 An example is shown in which the third layer wiring formed by the third metal layer is used as the wiring for connecting the NMOS switch circuit NMOS-SW1, the internal wiring (LINC), the time constant circuit RC-1 and the time constant circuit RC-2, and the inverter circuit INV-1 and the inverter circuit INV-2, but the present invention is not limited thereto, and any of the fourth layer wiring to the twelfth layer wiring can be used. In addition, as an example, the number of wirings constituting the internal wiring LINC is 8, but is not limited to 8, and can be, for example, 1.

[0126] 《Layout of power supply wiring and ground wiring》

[0127] Figure 8 is a plan view illustrating the layout of power wiring and ground wiring according to the first embodiment. Figure 8 The diagram shows the Figure 1 The layout of parts of the signal unit IO_CL and the power supply unit PW_CL is shown in FIG.

[0128] exist Figure 8 , reference symbol PD and reference symbol ND identify protection diodes provided in the signal unit IO_CL. Dotted lines drawn around the symbol PD and the symbol ND indicate diffusion regions constituting the protection diode PD and the protection diode ND.

[0129] exist Figure 8 In the embodiment, as described above, the power wiring LVCC is configured by electrically connecting some of the plurality of thirteenth layer wirings M13 and some of the fourteenth layer wirings M14 among the plurality of fourteenth layer wirings M14. In addition, the other thirteenth layer wirings M13 among the plurality of thirteenth layer wirings M13 and the other fourteenth layer wirings M14 among the plurality of fourteenth layer wirings M14 are electrically connected to form a ground wiring LVSS.

[0130] like Figure 8 As shown in FIG. 1 , when viewed in a plan view, the power supply wiring LVCC extends to overlap the discharge switch circuit B-NMOS and the protection diode PD and is electrically connected to the NMOS transistor BN1 ( Figure 2 ) of the drain region and the protection diode PD. In addition, the ground wiring LVSS extends to overlap the discharge switch circuit B-NMOS and the protection diode ND and is electrically connected to the NMOS transistor BN2 ( Figure 2 )'s source region and protection diode ND.

[0131] The power wiring LVCC is connected to the wiring VCCL, which is composed of the third layer wiring M3 to the twelfth layer wiring M12 and extends in the Y direction through the via-hole BH, and the ground wiring LVSS is connected to the wiring VSSL, which is composed of the third layer wiring M3 to the twelfth layer wiring M12 and extends in the Y direction through the via-hole BH. The wiring VCCL and the wiring VSSL are connected to the inside of the trigger circuit TGC and the reverse diode REV-D through the via-hole to supply the power supply voltage VCC and the ground voltage VSS.

[0132] That is, the power supply wiring LVCC and the ground wiring LVSS corresponding to the main discharge wiring are connected to the discharge switch circuit B-NMOS and the protection diode PD and the protection diode ND. On the other hand, for example, the inside of the trigger circuit TGC is connected to the main discharge wiring via the wiring VCCL and the wiring VSSL.

[0133] If the NMOS transistor BN1 and the NMOS transistor BN2 are arranged in a distributed manner, it is considered that the discharge performance is deteriorated, and therefore the NMOS transistor BN1 and the NMOS transistor BN2 constituting the discharge switch circuit B-NMOS are placed adjacent to each other.

[0134] Since the reverse diode REV-D forms a discharge path when a high voltage is applied to the ground port, it is also desirable to place the reverse diode REV-D close to the power wiring LVCC and the ground wiring LVSS. However, in the first embodiment, the reverse diode REV-D is placed between the discharge switch circuit B-NMOS and the trigger circuit TGC to preferentially place the NMOS transistor BN1 and the NMOS transistor BN2 adjacent to each other and prevent a dead space from occurring in the adjacent signal unit IO_CL. Although there is no Figure 8 , the internal wiring LINA to the internal wiring LINC extend in the X direction in the flip-flop circuit TGC. Therefore, the reverse diode REV-D is placed between the internal wiring LINA to the internal wiring LINC in the flip-flop circuit TGC and the NMOS transistors BN1 and BN2 along the X direction.

[0135] 《Layout of the Discharge Switch Circuit》

[0136] Fig. 9 A to Fig. 9 C is a diagram for describing a discharge switch circuit according to the first embodiment. Here, Fig. 9 A illustrates the circuit configuration of the discharge switch circuit B-NMOS, and Fig. 9 B and Fig. 9 C is a diagram illustrating the layout of the discharge switch circuit.

[0137] Fig. 9 The configuration of the discharge switch circuit B-NMOS shown in A is similar to Figure 1 Similar to that shown in the figure. Fig. 9 The difference in A is that the gate electrode of NMOS transistor BN1 is identified by reference mark A, the gate electrode of NMOS transistor BN2 is identified by reference mark B, the electrode of the drain region of NMOS transistor BN1 is identified by reference mark DD, and the electrode of the source region of NMOS transistor BN2 is identified by SS.

[0138] exist Fig. 9 In the layout shown in FIG. 2B , the gate electrode A of the NMOS transistor BN1 and the gate electrode B of the NMOS transistor BN2 are arranged in series between the drain electrode DD and the source electrode SS. Fig. 9 In the layout shown in C, the gate electrode A and the gate electrode B of the NMOS transistor BN1 and the NMOS transistor BN2 are separately arranged between the drain electrodes DD and between the source electrodes SS, respectively.

[0139] When using Fig. 9 B, it is possible to reduce the occupied area of ​​the discharge switch circuit B-NMOS and improve heat dissipation. Therefore, the discharge switch circuit B-NMOS according to the first embodiment can be adopted Fig. 9 The layout shown in B.

[0140] In the first embodiment, as shown in reference FIG. 4A to FIG. 4E and FIG. 6A to FIG. 6E As described above, the source region, drain region, etc. of the MOS transistor and the gate electrode are formed in the first layer (diffusion layer). Therefore, it can be considered that the MOS transistor and the trigger circuit TGC including the MOS transistor and the like are formed in the first layer. In this regard, it can be considered that the internal wiring and the wiring electrically connected to the internal wiring (for example, the third layer wiring) are formed in the second layer, and the second layer is the upper layer of the first layer. In addition, it can be considered that the power wiring LVCC and the ground wiring LVSS are formed in the upper layer of the second layer.

[0141] In the ESD protection circuit ESDP according to the first embodiment, internal wiring is arranged in a dedicated wiring area, wherein wiring in the same layer as the first layer wiring and the second layer wiring in the circuit used to constitute the ESD protection circuit constitutes the internal wiring, and wiring connecting the circuit (for example, the third layer wiring) is bundled into a bundle by the internal wiring.

[0142] (Second embodiment)

[0143] Fig.10 1 is a block diagram illustrating a configuration of an ESD protection circuit according to a second embodiment. In the ESD protection circuit according to the second embodiment, a discharge switch circuit B-NMOS connected to a main discharge wiring includes three-stage MOS transistors whose source-drain paths are connected in series. Therefore, a MOS transistor with a lower withstand voltage can be adopted as the discharge switch circuit B-NMOS.

[0144] Fig.10 and Figure 2 resemblance. Fig.10 The ESD protection circuit ESDP shown in the figure is Figure 2 The ESD protection circuit of FIG. 1 is different in that it further includes resistors R5 and R6, an NMOS switch circuit NMOS-SW2, a time constant circuit RC-3, an inverter circuit INV-3, and an NMOS transistor BN3. In addition, Fig.10 The ESD protection circuit ESDP in the embodiment is different in that it also includes internal wirings LIND and LINE.

[0145] like Fig.10As shown in the figure, resistor R1, NMOS switch circuit NMOS-SW1, time constant circuit RC-1, and inverter circuit INV-1 are connected to internal wiring LIND instead of power supply conductor LVCC. Resistor R5, NMOS switch circuit NMOS-SW2, time constant circuit RC-3, and inverter circuit INV-3 are connected in parallel between power supply wiring LVCC and internal wiring LIND. In addition, the output node of inverter INV-3 (the drain of PMOS transistor P3 and the drain of NMOS transistor N5 are connected to this node) is connected to the gate electrode of NMOS transistor BN3 via internal wiring LINE. In addition, resistor R6 is connected between internal wiring LIND and internal wiring LINE. As Fig.10 shown, NMOS transistors BN1 to BN3 are connected between power supply wiring LVCC and ground wiring LVSS such that the source-drain paths are connected in series between the power supply wiring and the ground wiring.

[0146] The functions of NMOS switch circuit NMOS-SW2, time constant circuit RC-3, inverter circuit INV-3, and resistors R5 and R6 are similar to Figure 2 those of NMOS switch circuit NMOS-SW1, time constant circuit RC-1, inverter circuit INV-1, and resistors R1 and R3 described in

[0147] <Layout of ESD protection circuit>

[0148] Fig.11 is a plan view illustrating the layout of the ESD protection circuit according to the second embodiment. That is to say, Fig.11 illustrates Fig.10 an example of the layout of the ESD protection circuit shown in Fig.11 is similar to Figure 3 that in Fig.11 except that NMOS switch circuit NMOS-SW2 is placed next to NMOS switch circuit NMOS-SW1 (in the X direction), and time constant circuit RC-3 and inverter circuit INV-3 are placed between NMOS switch circuit NMOS-SW2 and reverse diode REV-D (in the Y direction).

[0149] In addition, Figure 3The area of ​​the dedicated wiring area EXLSP-11 and the dedicated wiring area EXLSP-21 shown in the figure is increased to place them as dedicated wiring areas EXLSP-12 and EXLSP-22. Each of these internal wirings LINA to LINE is composed of the first layer wiring M1-E and the second layer wiring M2-E as described in the first embodiment. In addition, the third layer wiring M3 to the twelfth layer wiring M12 connect the internal wiring and circuit blocks (such as NMOS switch circuit, inverter circuit, time constant circuit, etc.) in the ESD protection circuit.

[0150] Also in the second embodiment, the internal wiring is arranged in the dedicated wiring area, wherein the wiring in the same layer as the first layer wiring and the second layer wiring used in the circuit constituting the ESD protection circuit constitutes the internal wiring, and the internal wiring bundles the wiring (e.g., the third layer wiring) connecting the circuits into one bundle. This can reduce the wiring resistance connecting the circuits constituting the ESD protection circuit ESDP and can suppress the degradation of the ESD protection function.

[0151] In addition, in the second embodiment, a MOS transistor having a lower withstand voltage can be used as an NMOS transistor (BN1 to BN3) constituting the discharge switch circuit B-NMOS. The withstand voltage of the NMOS transistor is determined by, for example, the film thickness of the gate insulating film. When a new generation of processes is adopted, the film thickness of the gate insulating film becomes thinner, and the withstand voltage of the NMOS transistor (BN1 to BN3) decreases. When the number of stages of the NMOS transistor constituting the discharge switch circuit is increased as in the second embodiment, the voltage reduction that may prevent the protection function from operating.

[0152] The MOS transistor may be a fin MOS transistor limited to a planar MOS transistor.

[0153] The present invention made by the inventors has been described in detail based on the embodiments as above, but the present invention is not limited to the embodiments described above, and needless to say, various types of modifications can be made within the scope not departing from the gist thereof.

Claims

1. A semiconductor device comprising: A semiconductor chip having a plurality of layers formed on a surface, Among the multiple layers are formed: a first power supply wiring, supplied with a power supply voltage, The second power supply wiring is supplied with a ground voltage supply, a MOS transistor connected to the first power wiring and the second power wiring and configured to electrically short-circuit the first power wiring and the second power wiring, and a trigger circuit electrically connected to the first gate electrode of the MOS transistor via a first wiring and configured to output a first control signal for controlling the first gate electrode, wherein the MOS transistor and the flip-flop circuit are formed in a first layer of the plurality of layers, wherein the first wiring is formed in a second layer which is an upper layer of the first layer, and The first wiring comprises: a first portion extending in a first direction; and A second portion extends in a second direction intersecting the first direction and is electrically connected to the first portion.

2. The semiconductor device according to claim 1, The resistance value of the second portion of the first wiring is less than or equal to the resistance value of the first portion of the first wiring.

3. The semiconductor device according to claim 2, The first wiring includes a plurality of wirings.

4. The semiconductor device according to claim 3, Wherein, in a plan view seen from the surface of the semiconductor chip, the second portion of the first wiring is arranged between the trigger circuit and the MOS transistor, and the second portion of the first wiring, the trigger circuit and the MOS transistor are arranged to face the first direction.

5. The semiconductor device according to claim 4, The trigger circuit comprises: a switch circuit electrically connected to the first power supply wiring; a first RC circuit electrically connected to the first power wiring; as well as a first inverter circuit electrically connected to the switch circuit and the first RC circuit via a second wiring and electrically connected to the first gate electrode of the MOS transistor via the first wiring, and The second wiring is formed in the second layer and includes a first portion extending in the first direction and a second portion extending in the second direction.

6. The semiconductor device according to claim 5, The resistance value of the second portion of the second wiring is less than or equal to the resistance value of the first portion of the second wiring.

7. The semiconductor device according to claim 6, The second wiring includes a plurality of wirings.

8. The semiconductor device according to claim 7, wherein in the plan view, the first RC circuit is arranged between the switch circuit and the first inverter circuit, and the first RC circuit, the switch circuit and the first inverter circuit are arranged to face the first direction, and The second portion of the second wiring is arranged between the switch circuit and the first RC circuit.

9. The semiconductor device according to claim 8, The trigger circuit further comprises: a second RC circuit electrically connected to the switch circuit via the second wiring; as well as a second inverter circuit electrically connected to the switch circuit and the second RC circuit via the second wiring, electrically connected to a second gate electrode of the MOS transistor in a subsequent stage of the first gate electrode via a third wiring, and configured to output a second control signal to the second gate electrode of the MOS transistor, and The third wiring is formed in the second layer, and includes a first portion extending in the first direction and a second portion extending in the second direction.

10. The semiconductor device according to claim 9, wherein a resistance value of the second portion of the third wiring is less than or equal to a resistance value of the first portion of the third wiring.

11. The semiconductor device according to claim 10, The third wiring includes a plurality of wirings.

12. The semiconductor device according to claim 11, wherein in the plan view, the second portion of the third wiring is arranged between the trigger circuit and the MOS transistor, and the second portion of the third wiring, the trigger circuit, and the MOS transistor are arranged to face the first direction, and The second portion of the third wiring is partially placed in parallel with the second portion of the first wiring.

13. The semiconductor device according to claim 4, further comprising: a diode connected to the first power wiring and the second power wiring and configured to electrically short-circuit the first power wiring and the second power wiring, In the plan view, the diode is arranged between the second portion of the first wiring and the MOS transistor along the first direction.

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