Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises the components of a substrate which comprises a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates through the interlayer dielectric layer and then is electrically connected with the device structure, and the metal layer further extends to a part of the interlayer dielectric layer; the at least two passivation layers are formed on the interlayer dielectric layer, and the at least two passivation layers further extend to the side wall of the metal layer at the corner of the chip area and the side wall of the metal layer at the non-corner of the chip area; the at least two passivation layers are not formed on the upper surface of the metal layer at the corner of the chip area. According to the technical scheme, the stress at the corner of the chip can be reduced, and then the reliability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In order to prevent external water vapor and free ions from affecting the internal structure of the device, traditional power devices usually cover the terminal area with a passivation layer, and the passivation layer extends all the way to the upper surface of the front metal layer on the cell area.

[0003] However, when performing reliability tests (such as TC tests, i.e., temperature cycle tests) on packaged devices formed after power devices are packaged, stress is generated between the layers due to mutual squeezing due to the different thermal expansion coefficients of the materials of the plastic layer, metal layer, and passivation layer in the packaged device; and the main stress when the passivation layer and the metal layer are combined is concentrated at the corners of the chip, resulting in excessive stress at the corners of the chip. When the stress at the corners of the chip exceeds the threshold, cracks will occur between the metal layer and the passivation layer on its surface, causing external water vapor and free ions to enter the device along the gaps created by the cracks, causing degradation of device performance or even device failure.

[0004] Therefore, how to reduce the stress at the chip corners is an urgent problem to be solved. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce stress at chip corners and thus improve chip reliability.

[0006] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0007] A substrate, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer;

[0008] At least two passivation layers are formed on the interlayer dielectric layer, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

[0009] Optionally, the at least two passivation layers include a first passivation layer and a second passivation layer from bottom to top, and the thickness of the first passivation layer is smaller than the thickness of the second passivation layer.

[0010] Optionally, the stress direction in the at least two passivation layers is a direction from the at least two passivation layers to the substrate.

[0011] Optionally, part of the metal layer is used as an electrode, and the at least two passivation layers also extend to the upper surface edge of the electrode at a non-corner portion of the chip region and the entire upper surface of the metal layer outside the electrode.

[0012] Optionally, a coverage ratio of the at least two passivation layers on the upper surface of the electrode at a non-corner portion of the chip region is less than or equal to 5%.

[0013] Optionally, among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

[0014] Optionally, the semiconductor device further includes:

[0015] A polyimide layer is formed on the at least two passivation layers, and the polyimide layer also extends to the upper surface of the metal layer at the corner of the chip area.

[0016] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0017] A substrate is provided, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer;

[0018] At least two passivation layers are formed on the interlayer dielectric layer, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

[0019] Optionally, the at least two passivation layers include a first passivation layer and a second passivation layer from bottom to top, and the thickness of the first passivation layer is smaller than the thickness of the second passivation layer.

[0020] Optionally, the stress direction in the at least two passivation layers is a direction from the at least two passivation layers to the substrate.

[0021] Optionally, part of the metal layer is used as an electrode, and the at least two passivation layers also extend to the upper surface edge of the electrode at a non-corner portion of the chip region and the entire upper surface of the metal layer outside the electrode.

[0022] Optionally, a coverage ratio of the at least two passivation layers on the upper surface of the electrode at a non-corner portion of the chip region is less than or equal to 5%.

[0023] Optionally, among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

[0024] Optionally, the method for manufacturing the semiconductor device further includes:

[0025] A polyimide layer is formed on the at least two passivation layers, and the polyimide layer also extends to the upper surface of the metal layer at the corner of the chip region.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] 1. The semiconductor device of the present invention comprises: a substrate, the substrate includes a chip area; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to part of the interlayer dielectric layer; at least two passivation layers are formed on the interlayer dielectric layer, the at least two passivation layers also extend to the sidewalls of the metal layer at the corner of the chip area and the sidewalls of the metal layer at the non-corner of the chip area, and the at least two passivation layers are not formed on the upper surface of the metal layer at the corner of the chip area. This makes it possible to reduce the stress at the corner of the chip, thereby improving the reliability of the chip.

[0028] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing a substrate, the substrate includes a chip area; forming a device structure, an interlayer dielectric layer and a metal layer on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to part of the interlayer dielectric layer; forming at least two passivation layers on the interlayer dielectric layer, the at least two passivation layers also extend to the sidewalls of the metal layer at the corner of the chip area and the sidewalls of the metal layer at the non-corner of the chip area, and the at least two passivation layers are not formed on the upper surface of the metal layer at the corner of the chip area. This makes it possible to reduce the stress at the corner of the chip, thereby improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;

[0030] Figure 2 yes Figure 1 The schematic cross-sectional structure diagram of the semiconductor device shown along the AA' direction;

[0031] Figure 3 yes Figure 1 The schematic cross-sectional structure diagram of the semiconductor device shown along the BB' direction;

[0032] Figure 4 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0033] Figure 5a to Figure 5g yes Figure 4 FIG. 1 is a schematic diagram of a device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] Among them, Figure 1 to Figure 5g The reference numerals are described as follows:

[0035] 10-base; 101-substrate; 102-epitaxial layer; 111-well region; 112-first contact region; 113-source region; 114-main junction; 115-second contact region; 116-gate oxide layer; 1171-gate layer; 1172-gate bus; 118-field limiting ring; 119-field oxide layer; 12-interlayer dielectric layer; 131-first electrode; 132-gate metal line; 133-second electrode; 134-third electrode; 141-first passivation layer; 142-second passivation layer; 15-polyimide layer. DETAILED DESCRIPTION

[0036] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer formed on the substrate, the interlayer dielectric layer covering the device structure, the metal layer passing through the interlayer dielectric layer and electrically connected to the device structure, the metal layer also extending to a portion of the interlayer dielectric layer; at least two passivation layers formed on the interlayer dielectric layer, the at least two passivation layers also extending to the side walls of the metal layer at the corners of the chip region and the side walls of the metal layer at non-corners of the chip region, the at least two passivation layers not being formed on the upper surface of the metal layer at the corners of the chip region.

[0038] See below Figure 1 to Figure 3 Describe in detail the semiconductor device provided by this embodiment, Figure 1 It is a top view schematic diagram of the chip area, the AA' position is the corner position of the chip area, and the BB' position is the non-corner position of the chip area.

[0039] The substrate 10 includes a chip area; a device structure, an interlayer dielectric layer 12 and a metal layer are formed on the substrate 10, the interlayer dielectric layer 12 covers the device structure, the metal layer penetrates the interlayer dielectric layer 12 and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer 12.

[0040] The substrate 10 further includes a dicing area, which is located between adjacent chip areas. Chips are obtained by cutting along the dicing area.

[0041] The chip region may include a cell region A1 and a terminal region A2 , and the terminal region A2 surrounds the cell region A1 .

[0042] The base 10 may include a substrate 101 and an epitaxial layer 102 formed on the substrate 101 .

[0043] The substrate 10 may be made of semiconductor materials such as silicon carbide, silicon or germanium.

[0044] The device structure may include a well region 111 , a first contact region 112 , a source region 113 , a main junction 114 , a second contact region 115 , a gate oxide layer 116 , a gate layer 1171 and a field limiting ring 118 .

[0045] The well region 111 and the main junction 114 extend from the surface of the epitaxial layer 102 of the cell region A1 into the epitaxial layer 102, the first contact region 112 is located at the top of the well region 111, the second contact region 115 is located at the top of the main junction 114, the source region 113 is located in the well region 111 on both sides of the first contact region 112, and the field limiting ring 118 extends from the surface of the epitaxial layer 102 of the terminal region A2 into the epitaxial layer 102; the gate oxide layer 116 and the gate layer 1171 are formed from bottom to top on the substrate 10 of the cell region A1, and the well region 111, the first contact region 112 and the source region 113 are located in the epitaxial layer 102 between adjacent gate layers 1171.

[0046] The device structure may also include a gate bus 1172, which is formed on the substrate 10 of the cell area A1 close to the terminal area A2, and the gate oxide layer 116 is also formed between the gate bus 1172 and the substrate 10, and the second contact area 115 is formed in the main junction 114 between the gate bus 1172 and the gate layer 1171 closest to the terminal area A2; one end of all the gate layers 1171 is connected to the gate bus 1172, so that all the gate layers 1171 are electrically connected through the gate bus 1172.

[0047] In one embodiment, the device structure may further include a field oxide layer 119 extending from a portion of the main junction 114 surface to the substrate 10 of the terminal region A2 , and the gate bus 1172 extending from a portion of the main junction 114 surface to a portion of the field oxide layer 119 .

[0048] The doping concentration of the first contact region 112 is greater than the doping concentration of the well region 111 , and the first contact region 112 is used to lead out the well region 111 ; the doping concentration of the second contact region 115 is greater than the doping concentration of the main junction 114 , and the second contact region 115 is used to lead out the main junction 114 .

[0049] The doping types of the well region 111 , the first contact region 112 , the main junction 114 , the second contact region 115 and the field limiting ring 118 are opposite to the doping types of the substrate 10 and the source region 113 .

[0050] It should be noted that the composition of the device structure is not limited to Figure 2 and Figure 3 The embodiment shown.

[0051] Part of the metal layer is used as an electrode, and another part of the metal layer other than the electrode can be used to achieve interconnection between the structure within the device structure and the electrode or other interconnection functions.

[0052] The material of the metal layer can be metal materials such as aluminum or copper.

[0053] exist Figure 1 to Figure 3In the illustrated embodiment, the metal layer may include the electrode and the gate metal line 132, and the electrode may include a first electrode 131, a second electrode 133, and a third electrode 134; wherein the first electrode 131 penetrates the interlayer dielectric layer 12 between adjacent gate layers 1171 and is electrically connected to the first contact area 112 and the source area 113, and the first electrode 131 also penetrates the interlayer dielectric layer 12 between the gate bus 1172 and the gate layer 1171 closest to the terminal area A2 and is electrically connected to the second contact area 115, and the second electrode 133 and the gate metal line 132 penetrate the interlayer dielectric layer 12 and can be electrically connected to the second contact area 115. The gate bus 1172 is electrically connected (the cross-sectional view of the second electrode 133 being electrically connected to the gate bus 1172 after penetrating the interlayer dielectric layer 12 is not shown), so that the first electrode 131 is used to electrically lead out the well region 111, the source region 113 and the main junction 114, and the second electrode 133 is used to electrically lead out the gate layer 1171; the third electrode 134 can also pass through the interlayer dielectric layer 12 and be electrically connected to a certain structure in the device structure or the substrate 10, and the third electrode 134 can be used for wire bonding in the packaging process; the first electrode 131, the second electrode 133 and the third electrode 134 are not electrically connected.

[0054] It should be noted that the metal layer is not limited to Figure 1 The structure shown may also include other electrodes for testing or wiring, or other metal lines for interconnection.

[0055] The at least two passivation layers are formed on the interlayer dielectric layer 12, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

[0056] like Figure 1 As shown, the chip area corners include the four corner areas B1 of the chip area; the chip area non-corner area is the area outside the area B1, including the areas of the four sides of the chip area and the internal area of ​​the chip area. The corners of the chip area can be rounded.

[0057] At the corner of the chip area, since the at least two passivation layers cover the side walls of the metal layer and the at least two passivation layers are not formed on the upper surface of the metal layer, the at least two passivation layers can block external water vapor and free ions from invading the inside of the device from between the metal layer and the interlayer dielectric layer 12 and affecting the internal structure of the device, and can also remove the contact stress generated by the mutual compression between the metal layer and the at least two passivation layers on its upper surface, thereby reducing the stress at the corner of the chip area, thereby improving the reliability of the chip, avoiding delamination and cracking between the metal layer and the passivation layer at the corner of the chip area during reliability testing (such as temperature cycling testing), and preventing device performance degradation or device failure during reliability testing.

[0058] At the non-corner part of the chip area, since the at least two passivation layers cover the side walls of the metal layer, the at least two passivation layers can prevent external water vapor and free ions from invading the device from between the metal layer and the interlayer dielectric layer 12 and affecting the internal structure of the device.

[0059] In one embodiment, at the non-corner of the chip area, in order to further improve the blocking effect of the at least two passivation layers on external water vapor and free ions, the at least two passivation layers can also extend to the upper surface of the metal layer; wherein, since the portion of the metal layer used as the electrode has a large area, and the electrode also needs to be used for testing or wiring, the at least two passivation layers can extend to the upper surface edge of the electrode at the non-corner of the chip area, so that the portion of the upper surface of the electrode at the non-corner of the chip area that is not covered by the at least two passivation layers can continue to be used for testing or wiring, and improve the at least two passivation layers. While the at least two passivation layers have a blocking effect on external water vapor and free ions, it can also avoid the at least two passivation layers extending to the area of ​​the upper surface of the electrode at the non-corner part of the chip area being too large, thereby causing excessive contact stress; and since the part of the metal layer other than the electrode is a small area, the at least two passivation layers can also extend to the entire upper surface of the metal layer outside the electrode at the non-corner part of the chip area, so that while the at least two passivation layers have a blocking effect on external water vapor and free ions, it can also avoid causing excessive contact stress between the at least two passivation layers and the entire upper surface of the metal layer outside the electrode.

[0060] When the at least two passivation layers extend to the edge of the upper surface of the electrode at the non-corner portion of the chip region, preferably, the coverage area ratio of the at least two passivation layers on the upper surface of the electrode at the non-corner portion of the chip region is less than or equal to 5%, so as to avoid excessive contact stress between the at least two passivation layers and the upper surface of the electrode.

[0061] In addition, since at least two passivation layers are formed on the interlayer dielectric layer 12, that is, the passivation layer includes at least two layers, the final required passivation layer is formed in at least two steps, so that the thickness of the first passivation layer formed in contact with the metal layer is thinned, thereby reducing the contact stress between the first passivation layer and the metal layer, thereby further reducing the stress at the corner of the chip area, and avoiding delamination between the first passivation layer and the metal layer during reliability testing; and the materials of the other passivation layers formed subsequently and the first passivation layer are both insulating materials (that is, the thermal expansion coefficients of the two are the same or similar), so that the contact stress between the other passivation layers formed subsequently and the first passivation layer is low, which can avoid delamination and cracking problems between the passivation layers during reliability testing.

[0062] The stress direction in the at least two passivation layers is the direction of the at least two passivation layers pointing to the substrate 10, that is, the stress direction in each passivation layer is the same, all of which are the direction of the passivation layer pointing to the substrate 10, so that the passivation layer can press the metal layer, thereby making it difficult for the passivation layer and the metal layer to delaminate.

[0063] Among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

[0064] The material of the passivation layer can be at least one of insulating materials such as silicon oxide, silicon nitride and silicon oxynitride.

[0065] When the passivation layer is two layers, that is, the at least two passivation layers include a first passivation layer 141 and a second passivation layer 142 from bottom to top, it is preferred that the thickness of the first passivation layer 141 is smaller than the thickness of the second passivation layer 142 .

[0066] Since the smaller the thickness of the passivation layer, the smaller the stress in the passivation layer, therefore, by making the thickness of the first passivation layer 141 smaller than the thickness of the second passivation layer 142, the stress in the first passivation layer 141 in contact with the metal layer is reduced, thereby reducing the contact stress between the first passivation layer 141 and the metal layer, thereby reducing the stress at the corner of the chip area; and the materials of the second passivation layer 142 and the first passivation layer 141 are both insulating materials (that is, the thermal expansion coefficients of the two are the same or similar), so that even if the thickness of the second passivation layer 142 is very thick, the contact stress between the second passivation layer 142 and the first passivation layer 141 will be very low, thereby avoiding the problem of delamination and cracking between the two during reliability testing.

[0067] In one embodiment, the thickness of the first passivation layer 141 is The thickness of the second passivation layer 142 is

[0068] The semiconductor device may further include: a polyimide layer 15 formed on the at least two passivation layers, wherein the polyimide layer 15 also extends to the metal layer at the corner of the chip region (eg Figure 2 The polyimide layer 15 also extends to the electrode at the non-corner of the chip region (e.g. Figure 3 The portion of the upper surface of the first electrode 131) in the embodiment of the present invention, the portion of the upper surface of the electrode not covered by the polyimide layer 15 is used for subsequent testing or wiring.

[0069] Preferably, the thickness of the polyimide layer 15 is greater than or equal to 10 μm to improve the reliability of the device.

[0070] In summary, the present invention provides a semiconductor device, comprising: a substrate, the substrate including a chip area; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to part of the interlayer dielectric layer; at least two passivation layers are formed on the interlayer dielectric layer, the at least two passivation layers also extend to the sidewalls of the metal layer at the corners of the chip area and the sidewalls of the metal layer at the non-corners of the chip area, and the at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area. The semiconductor device provided by the present invention can reduce the stress at the corners of the chip, thereby improving the reliability of the chip.

[0071] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 4 ,from Figure 4 It can be seen that the method for manufacturing the semiconductor device includes:

[0072] Step S1, providing a substrate, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer;

[0073] Step S2, forming at least two passivation layers on the interlayer dielectric layer, the at least two passivation layers also extending to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area, and the at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

[0074] See below Figure 1 , Figure 5a to Figure 5gThe method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 1 It is a top view schematic diagram of the chip area, AA' position is the corner position of the chip area, BB' position is the non-corner position of the chip area, Figure 5a to Figure 5c yes Figure 1 The schematic cross-sectional view of the chip area along the AA' or BB' direction is shown. Figure 5d and Figure 5f yes Figure 1 The schematic cross-sectional view of the chip area along the AA' direction is shown in FIG. Figure 5e and Figure 5g yes Figure 1 The schematic cross-sectional view of the chip region along the BB' direction is shown.

[0075] Follow step S1, refer to Figure 5a , providing a substrate 10, the substrate 10 includes a chip area; a device structure, an interlayer dielectric layer 12 and a metal layer are formed on the substrate 10, the interlayer dielectric layer 12 covers the device structure, the metal layer penetrates the interlayer dielectric layer 12 and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer 12.

[0076] The substrate 10 further includes a dicing area, which is located between adjacent chip areas. Chips are obtained by cutting along the dicing area.

[0077] The chip region may include a cell region A1 and a terminal region A2 , and the terminal region A2 surrounds the cell region A1 .

[0078] The base 10 may include a substrate 101 and an epitaxial layer 102 formed on the substrate 101 .

[0079] The substrate 10 may be made of semiconductor materials such as silicon carbide, silicon or germanium.

[0080] The device structure may include a well region 111 , a first contact region 112 , a source region 113 , a main junction 114 , a second contact region 115 , a gate oxide layer 116 , a gate layer 1171 and a field limiting ring 118 .

[0081] The well region 111 and the main junction 114 extend from the surface of the epitaxial layer 102 of the cell region A1 into the epitaxial layer 102, the first contact region 112 is located at the top of the well region 111, the second contact region 115 is located at the top of the main junction 114, the source region 113 is located in the well region 111 on both sides of the first contact region 112, and the field limiting ring 118 extends from the surface of the epitaxial layer 102 of the terminal region A2 into the epitaxial layer 102; the gate oxide layer 116 and the gate layer 1171 are formed from bottom to top on the substrate 10 of the cell region A1, and the well region 111, the first contact region 112 and the source region 113 are located in the epitaxial layer 102 between adjacent gate layers 1171.

[0082] The device structure may also include a gate bus 1172, which is formed on the substrate 10 of the cell area A1 close to the terminal area A2, and the gate oxide layer 116 is also formed between the gate bus 1172 and the substrate 10, and the second contact area 115 is formed in the main junction 114 between the gate bus 1172 and the gate layer 1171 closest to the terminal area A2; one end of all the gate layers 1171 is connected to the gate bus 1172, so that all the gate layers 1171 are electrically connected through the gate bus 1172.

[0083] In one embodiment, the device structure may further include a field oxide layer 119 extending from a portion of the main junction 114 surface to the substrate 10 of the terminal region A2 , and the gate bus 1172 extending from a portion of the main junction 114 surface to a portion of the field oxide layer 119 .

[0084] The doping concentration of the first contact region 112 is greater than the doping concentration of the well region 111 , and the first contact region 112 is used to lead out the well region 111 ; the doping concentration of the second contact region 115 is greater than the doping concentration of the main junction 114 , and the second contact region 115 is used to lead out the main junction 114 .

[0085] The doping types of the well region 111 , the first contact region 112 , the main junction 114 , the second contact region 115 and the field limiting ring 118 are opposite to the doping types of the substrate 10 and the source region 113 .

[0086] The well region 111 , the first contact region 112 , the source region 113 , the main junction 114 , the second contact region 115 and the field limiting ring 118 may be formed by implanting ions into the epitaxial layer 102 .

[0087] It should be noted that the composition of the device structure is not limited to Figure 5a The embodiment shown.

[0088] Part of the metal layer is used as an electrode, and another part of the metal layer other than the electrode can be used to achieve interconnection between the structure within the device structure and the electrode or other interconnection functions.

[0089] The material of the metal layer can be metal materials such as aluminum or copper.

[0090] exist Figure 1 and Figure 5a In the illustrated embodiment, the metal layer may include the electrode and the gate metal line 132, and the electrode may include a first electrode 131, a second electrode 133, and a third electrode 134; wherein the first electrode 131 penetrates the interlayer dielectric layer 12 between adjacent gate layers 1171 and is electrically connected to the first contact area 112 and the source area 113, and the first electrode 131 also penetrates the interlayer dielectric layer 12 between the gate bus 1172 and the gate layer 1171 closest to the terminal area A2 and is electrically connected to the second contact area 115, and the second electrode 133 and the gate metal line 132 penetrate the interlayer dielectric layer 12 and can be electrically connected to the second contact area 115. The gate bus 1172 is electrically connected (the cross-sectional view of the second electrode 133 being electrically connected to the gate bus 1172 after penetrating the interlayer dielectric layer 12 is not shown), so that the first electrode 131 is used to electrically lead out the well region 111, the source region 113 and the main junction 114, and the second electrode 133 is used to electrically lead out the gate layer 1171; the third electrode 134 can also pass through the interlayer dielectric layer 12 and be electrically connected to a certain structure in the device structure or the substrate 10, and the third electrode 134 can be used for wire bonding in the packaging process; the first electrode 131, the second electrode 133 and the third electrode 134 are not electrically connected.

[0091] It should be noted that the metal layer is not limited to Figure 1 The structure shown may also include other electrodes for testing or wiring, or other metal lines for interconnection.

[0092] According to step S2, at least two passivation layers are formed on the interlayer dielectric layer 12, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

[0093] like Figure 1As shown, the chip area corners include the four corner areas B1 of the chip area; the chip area non-corner area is the area outside the area B1, including the areas of the four sides of the chip area and the internal area of ​​the chip area. The corners of the chip area can be rounded.

[0094] At the corner of the chip area, since the at least two passivation layers cover the side walls of the metal layer and the at least two passivation layers are not formed on the upper surface of the metal layer, the at least two passivation layers can block external water vapor and free ions from invading the inside of the device from between the metal layer and the interlayer dielectric layer 12 and affecting the internal structure of the device, and can also remove the contact stress generated by the mutual compression between the metal layer and the at least two passivation layers on its upper surface, thereby reducing the stress at the corner of the chip area, thereby improving the reliability of the chip, avoiding delamination and cracking between the metal layer and the passivation layer at the corner of the chip area during reliability testing (such as temperature cycling testing), and preventing device performance degradation or device failure during reliability testing.

[0095] At the non-corner part of the chip area, since the at least two passivation layers cover the side walls of the metal layer, the at least two passivation layers can prevent external water vapor and free ions from invading the device from between the metal layer and the interlayer dielectric layer 12 and affecting the internal structure of the device.

[0096] In one embodiment, at the non-corner of the chip area, in order to further improve the blocking effect of the at least two passivation layers on external water vapor and free ions, the at least two passivation layers can also extend to the upper surface of the metal layer; wherein, since the portion of the metal layer used as the electrode has a large area, and the electrode also needs to be used for testing or wiring, the at least two passivation layers can extend to the upper surface edge of the electrode at the non-corner of the chip area, so that the portion of the upper surface of the electrode at the non-corner of the chip area that is not covered by the at least two passivation layers can continue to be used for testing or wiring, and improve the at least two passivation layers. While the at least two passivation layers have a blocking effect on external water vapor and free ions, it can also avoid the at least two passivation layers extending to the area of ​​the upper surface of the electrode at the non-corner part of the chip area being too large, thereby causing excessive contact stress; and since the part of the metal layer other than the electrode is a small area, the at least two passivation layers can also extend to the entire upper surface of the metal layer outside the electrode at the non-corner part of the chip area, so that while the at least two passivation layers have a blocking effect on external water vapor and free ions, it can also avoid causing excessive contact stress between the at least two passivation layers and the entire upper surface of the metal layer outside the electrode.

[0097] When the at least two passivation layers extend to the edge of the upper surface of the electrode at the non-corner portion of the chip region, preferably, the coverage area ratio of the at least two passivation layers on the upper surface of the electrode at the non-corner portion of the chip region is less than or equal to 5%, so as to avoid excessive contact stress between the at least two passivation layers and the upper surface of the electrode.

[0098] In addition, since at least two passivation layers are formed on the interlayer dielectric layer 12, that is, the passivation layer includes at least two layers, the final required passivation layer is formed in at least two steps, so that the thickness of the first passivation layer formed in contact with the metal layer is thinned, thereby reducing the contact stress between the first passivation layer and the metal layer, thereby further reducing the stress at the corner of the chip area, and avoiding delamination between the first passivation layer and the metal layer during reliability testing; and the materials of the other passivation layers formed subsequently and the first passivation layer are both insulating materials (that is, the thermal expansion coefficients of the two are the same or similar), so that the contact stress between the other passivation layers formed subsequently and the first passivation layer is low, which can avoid delamination and cracking problems between the passivation layers during reliability testing.

[0099] The stress direction in the at least two passivation layers is the direction of the at least two passivation layers pointing to the substrate 10, that is, the stress direction in each passivation layer is the same, all of which are the direction of the passivation layer pointing to the substrate 10, so that the passivation layer can press the metal layer, thereby making it difficult for the passivation layer and the metal layer to delaminate.

[0100] The stress direction in the passivation layer can be adjusted by adjusting the process parameters (such as the ratio of reaction gases, temperature, pressure and power, etc.) for forming the passivation layer through deposition.

[0101] Among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

[0102] The material of the passivation layer can be at least one of insulating materials such as silicon oxide, silicon nitride and silicon oxynitride.

[0103] The step S2 may include: firstly depositing at least two passivation layers on the entire surface of the chip area, that is, the at least two passivation layers cover the entire surface of the interlayer dielectric layer 12 and the metal layer, and then, using photolithography and etching processes to remove the at least two passivation layers on the upper surface of the metal layer at the corners of the chip area and the at least two passivation layers in the central area of ​​the upper surface of the electrode at the non-corner of the chip area.

[0104] Taking the passivation layer as two layers as an example, that is, the at least two passivation layers include a first passivation layer 141 and a second passivation layer 142 from bottom to top, the step S2 includes: Figure 5bAs shown in FIG. 1 , a first passivation layer 141 is formed on the entire surface of the chip region, that is, the first passivation layer 141 covers the entire surface of the interlayer dielectric layer 12 and the metal layer; then, as shown in FIG. Figure 5c As shown, a second passivation layer 142 is formed on the surface of the first passivation layer 141; then, as shown Figure 5d and Figure 5e As shown, photolithography and etching processes are performed to remove the metal layer at the corner of the chip region (eg Figure 5d The first passivation layer 141 and the second passivation layer 142 on the upper surface of the first electrode 131 and the gate metal line 132 in the chip region, and the electrodes (e.g. Figure 5e The first passivation layer 141 and the second passivation layer 142 are formed in the central area of ​​the upper surface of the first electrode 131).

[0105] When the at least two passivation layers include a first passivation layer 141 and a second passivation layer 142 from bottom to top, it is preferred that the thickness of the first passivation layer 141 is smaller than the thickness of the second passivation layer 142 .

[0106] Since the smaller the thickness of the passivation layer, the smaller the stress in the passivation layer, therefore, by making the thickness of the first passivation layer 141 smaller than the thickness of the second passivation layer 142, the stress in the first passivation layer 141 in contact with the metal layer is reduced, thereby reducing the contact stress between the first passivation layer 141 and the metal layer, thereby reducing the stress at the corner of the chip area; and the materials of the second passivation layer 142 and the first passivation layer 141 are both insulating materials (that is, the thermal expansion coefficients of the two are the same or similar), so that even if the thickness of the second passivation layer 142 is very thick, the contact stress between the second passivation layer 142 and the first passivation layer 141 will be very low, thereby avoiding the problem of delamination and cracking between the two during reliability testing.

[0107] In one embodiment, the thickness of the first passivation layer 141 is The thickness of the second passivation layer 142 is

[0108] like Figure 5f and Figure 5g As shown, the method for manufacturing the semiconductor device further includes: forming a polyimide layer 15 on the at least two passivation layers, wherein the polyimide layer 15 also extends to the metal layer at the corner of the chip region (eg Figure 5f The polyimide layer 15 also extends to the electrode at the non-corner of the chip region (e.g. Figure 5gThe portion of the upper surface of the first electrode 131) in the embodiment of the present invention, the portion of the upper surface of the electrode not covered by the polyimide layer 15 is used for subsequent testing or wiring.

[0109] Preferably, the thickness of the polyimide layer 15 is greater than or equal to 10 μm to improve the reliability of the device.

[0110] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a chip area; forming a device structure, an interlayer dielectric layer and a metal layer on the substrate, the interlayer dielectric layer covering the device structure, the metal layer passing through the interlayer dielectric layer and electrically connected to the device structure, and the metal layer also extending to part of the interlayer dielectric layer; forming at least two passivation layers on the interlayer dielectric layer, the at least two passivation layers also extending to the sidewalls of the metal layer at the corner of the chip area and the sidewalls of the metal layer at the non-corner of the chip area, and the at least two passivation layers are not formed on the upper surface of the metal layer at the corner of the chip area. The method for manufacturing a semiconductor device provided by the present invention can reduce the stress at the corner of the chip, thereby improving the reliability of the chip.

[0111] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer; At least two passivation layers are formed on the interlayer dielectric layer, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

2. The semiconductor device according to claim 1, wherein The at least two passivation layers include a first passivation layer and a second passivation layer from bottom to top, and the thickness of the first passivation layer is smaller than the thickness of the second passivation layer.

3. The semiconductor device according to claim 1, wherein The stress direction in the at least two passivation layers is the direction from the at least two passivation layers to the substrate.

4. The semiconductor device according to claim 1, wherein Part of the metal layer is used as an electrode, and the at least two passivation layers also extend to the upper surface edge of the electrode at the non-corner part of the chip region and the entire upper surface of the metal layer outside the electrode.

5. The semiconductor device according to claim 4, wherein: The coverage area ratio of the at least two passivation layers on the upper surface of the electrode at the non-corner of the chip region is less than or equal to 5%.

6. The semiconductor device according to claim 1, wherein: Among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A polyimide layer is formed on the at least two passivation layers, and the polyimide layer also extends to the upper surface of the metal layer at the corner of the chip area.

8. A method for manufacturing a semiconductor device, characterized in that: include: A substrate is provided, the substrate comprising a chip region; a device structure, an interlayer dielectric layer and a metal layer are formed on the substrate, the interlayer dielectric layer covers the device structure, the metal layer penetrates the interlayer dielectric layer and is electrically connected to the device structure, and the metal layer also extends to a portion of the interlayer dielectric layer; At least two passivation layers are formed on the interlayer dielectric layer, and the at least two passivation layers also extend to the side walls of the metal layer at the corners of the chip area and the side walls of the metal layer at the non-corners of the chip area. The at least two passivation layers are not formed on the upper surface of the metal layer at the corners of the chip area.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The at least two passivation layers include a first passivation layer and a second passivation layer from bottom to top, and the thickness of the first passivation layer is smaller than the thickness of the second passivation layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The stress direction in the at least two passivation layers is the direction from the at least two passivation layers to the substrate.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: Part of the metal layer is used as an electrode, and the at least two passivation layers also extend to the upper surface edge of the electrode at the non-corner part of the chip region and the entire upper surface of the metal layer outside the electrode.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The coverage area ratio of the at least two passivation layers on the upper surface of the electrode at the non-corner of the chip region is less than or equal to 5%.

13. The method for manufacturing a semiconductor device according to claim 8, wherein: Among the at least two passivation layers, materials of any two of the passivation layers are the same or different.

14. The method for manufacturing a semiconductor device according to claim 8, wherein: The method for manufacturing the semiconductor device further includes: A polyimide layer is formed on the at least two passivation layers, and the polyimide layer also extends to the upper surface of the metal layer at the corner of the chip region.

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