Array switch circuitry

Abstract

The invention discloses an array switch circuit system. The array switch circuit system comprises a substrate, a plurality of first conductive pads, a plurality of first row / column switches, a plurality of second conductive pads and a plurality of first transmission lines, the first conductive pads are arranged on the substrate at intervals and arranged in an array, and each of the first conductive pads has a column position and a row position in the array. Each of the first column switches is connected with two adjacent first conductive pads corresponding to the same column position. Each of the first row switches is connected with two adjacent first conductive pads corresponding to the same row position. The plurality of second conductive pads are arranged on the periphery of the first conductive pads. Each of the first transmission lines is connected with two of the second conductive pads and comprises a first conductor band and two second conductor bands, and the two second conductor bands are located on the two sides of the first conductor band respectively and are coplanar with the first conductor band.

Description

Technical Field

[0001] The present invention relates to an array switch circuit system, and more particularly to an array switch circuit system applicable to system packaging. Background Art

[0002] Traditional system packaging is to package multiple chips together into an integrated circuit (IC), wherein the connection between chips and the input and output pins of the package must be wired through the wires of the carrier board.

[0003] In order to solve the problem of excessive line width and line spacing of the packaging substrate conductors, the Embedded Multi-die Interconnect Bridge (EMIB) packaging technology was developed. By embedding a silicon wafer in the packaging substrate and utilizing the fine line width and line spacing in the silicon wafer, the problem of excessive line width and line spacing of the packaging substrate is solved, thereby greatly increasing the number of connecting wires. However, the disadvantage is that if the winding needs to be modified or the wafer needs to be replaced after testing, it must be remanufactured, which requires a longer research and development time.

[0004] The use of advanced packaging combined with embedded multi-die active bridge (EMAB) chips can create opportunities for programmable path correction. However, because the path signal transmission is composed of switching circuits, some high-speed and low-latency signals cannot be transmitted. Summary of the invention

[0005] In view of the above, the present invention provides an array switch circuit system.

[0006] According to an embodiment of the present invention, an array switch circuit system comprises a substrate, a plurality of first conductive pads, a plurality of first row switches, a plurality of first column switches, a plurality of second conductive pads, and a plurality of first transmission lines. The plurality of first conductive pads are disposed on the substrate at intervals and arranged in an array, wherein each of the plurality of first conductive pads has a column position and a row position in the array. The plurality of first column switches are disposed on the substrate, wherein each of the plurality of first column switches connects two adjacent ones of the plurality of first conductive pads corresponding to the same column position. The plurality of first row switches are disposed on the substrate, wherein each of the plurality of first row switches connects two adjacent ones of the plurality of first conductive pads corresponding to the same row position. The plurality of second conductive pads are disposed on the substrate and disposed at the periphery of the plurality of first conductive pads. The plurality of first transmission lines are disposed on the substrate, wherein each of the plurality of first transmission lines connects two of the plurality of second conductive pads, and comprises a first conductor strip and two second conductor strips, wherein the two second conductor strips are respectively located on both sides of the first conductor strip and are coplanar with the first conductor strip.

[0007] Through the above structure, the array switch circuit system disclosed by the present invention can change the connection of the redistribution layer (RDL) winding for the transmission of low-speed signals through the control of the array switch, so as to solve the problem of needing to redesign the redistribution layer; the transmission of high-speed signals can be carried out through transmission lines to achieve the effect of low latency, wherein the transmission line of the high-speed signal can be realized through a specially designed coplanar waveguide (CPW) to solve the impedance matching problem of the high-speed signal. In this way, the overall packaging carrier of the array switch circuit system of the present invention can only need to customize the metal layer of the transmission line, and the rest are all prefabricated designs, thereby shortening the product development time and reducing the R&D cost, and filling the gap in the packaging of various products.

[0008] The above description of the disclosed contents and the following description of the implementation modes are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit diagram of an array switch circuit system according to an embodiment of the present invention;

[0010] Figure 2 is a structural schematic diagram of an array switch circuit system according to an embodiment of the present invention;

[0011] Figure 3 According to an embodiment of the present invention, Figure 2 A cross-sectional schematic diagram of the array switch circuit system shown by the section line AA';

[0012] Figure 4 According to an embodiment of the present invention, Figure 2 A cross-sectional schematic diagram of the array switch circuit system shown by the section line BB';

[0013] Figure 5 is a schematic diagram of a first transmission line implemented by a coplanar waveguide in an array switch circuit system according to an embodiment of the present invention;

[0014] Figure 6 is a circuit diagram of an array switch circuit system according to another embodiment of the present invention;

[0015] Figure 7 is a circuit diagram of an array switch circuit system according to another embodiment of the present invention;

[0016] Figure 8is a schematic diagram of a plurality of transmission lines between two second conducting pads in an array switch circuit system according to another embodiment of the present invention;

[0017] Fig. 9 is a block diagram of a switch control circuit of an array switch circuit system according to an embodiment of the present invention;

[0018] Fig.10 is a circuit diagram of a switch circuit of an array switch circuit system according to an embodiment of the present invention;

[0019] Fig.11 is a circuit diagram of a switch circuit of an array switch circuit system according to another embodiment of the present invention;

[0020] Fig.12 is a circuit diagram of a switch circuit of an array switch circuit system according to another embodiment of the present invention;

[0021] Wherein, the reference numerals are:

[0022] 100, 100', 100": array switch circuit system;

[0023] 10:Substrate;

[0024] 1: first conductive pad;

[0025] 11,11',11": first row switches;

[0026] 12: first row switch;

[0027] 2: second conductive pad;

[0028] 2a: first target conductive pad;

[0029] 2b: second target conductive pad;

[0030] 21: first transmission line;

[0031] 211: first conductor strip;

[0032] 212: second conductor strip;

[0033] 22: Second row switch;

[0034] 23: second row switch;

[0035] 24: second transmission line;

[0036] 27: the third transmission line;

[0037] 3: the third conductive pad;

[0038] 31: the third row switch;

[0039] 32: the third row of switches;

[0040] R: array;

[0041] R1: conductive pad row;

[0042] R2: conductive pad array;

[0043] L1, L2, L3: layer body;

[0044] A-A', B-B': transversal line;

[0045] T: conductor layer thickness;

[0046] H: dielectric layer thickness;

[0047] W: width;

[0048] S: spacing;

[0049] T1: first switching element;

[0050] T2: second switching element;

[0051] C: switch control circuit;

[0052] C1: Packet detector and control generator;

[0053] C2: Addition generator;

[0054] C3: pulse generator;

[0055] C4: buffer;

[0056] C5: amplifier;

[0057] C6: memory;

[0058] C7: switch controller;

[0059] C8: selector;

[0060] Initial: initial signal;

[0061] Clk: clock signal;

[0062] M1-M12: transistors;

[0063] P1, P2, P11, P12, P21, P22, P31, P32: input and output terminals;

[0064] P13, P14, P23, P24, P33, P34: base control terminal;

[0065] 111: transmission gate;

[0066] 112,113: base control subcircuit;

[0067] 114,115,116: transistor group. DETAILED DESCRIPTION

[0068] The following detailed features and advantages of the present invention are described in detail in the embodiments, and the contents are sufficient to enable those skilled in the art to understand the technical content of the present invention and implement it accordingly. According to the contents disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the art can easily understand the relevant purposes and advantages of the present invention. The following examples are to further explain the viewpoints of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

[0069] Please refer to Figure 1 , Figure 1 FIG. 1 is a circuit diagram of an array switch circuit system according to an embodiment of the present invention. Figure 1 As shown, the array switch circuit system 100 includes a substrate 10, a plurality of first conductive pads 1, a plurality of first row switches 11, a plurality of first column switches 12, a plurality of second conductive pads 2, and a plurality of first transmission lines 21. The plurality of first conductive pads 1 are disposed on the substrate 10 at intervals and arranged in an array R, wherein each of the plurality of first conductive pads 1 has a row position and a column position in the array R. The plurality of first row switches 11 are disposed on the substrate 10, wherein each of the plurality of first row switches 11 connects two adjacent ones of the plurality of first conductive pads 1 corresponding to the same row position. The plurality of first column switches 12 are disposed on the substrate 10, wherein each of the plurality of first row switches 12 connects two adjacent ones of the plurality of first conductive pads 1 corresponding to the same column position. The plurality of second conductive pads 2 are disposed on the substrate 10 and disposed at the periphery of the plurality of first conductive pads 1. The plurality of first transmission lines 21 are disposed on the substrate 10, wherein each of the plurality of first transmission lines 21 connects two of the plurality of second conductive pads 2. Each first transmission line 21 includes a first conductor strip and two second conductor strips. The two second conductor strips are respectively located at two sides of the first conductor strip and are coplanar with the first conductor strip. The specific arrangement will be described later.

[0070] In this embodiment, the first conductive pads 1 and the second conductive pads 2 may be conductive pads made of metal materials. The first conductive pads 1 are arranged in an array. Figure 1 The number of rows and columns of the array shown is only an example, and the present invention does not limit the number of rows and columns of the first conductive pads 1. The second conductive pads 2 are arranged on the periphery of the first conductive pads 1. Figure 1 In the embodiment, the plurality of second conducting pads 2 are arranged into two conducting pad rows R1 and two conducting pad columns R2 ( Figure 1In the figure, only one row and one column are selected for schematic representation, the two conductive pad rows R1 are located at two opposite sides of the array R, the two conductive pad columns R2 are located at the other opposite sides of the array R, and the two of the plurality of second conductive pads 2 connected to each of the plurality of first transmission lines 21 belong to the two conductive pad rows R1, or belong to the two conductive pad columns R2. Specifically, the first transmission line 21 can extend along the row direction or the column direction of the array R and electrically connect the two second conductive pads 2 located at the two sides of the array R. Figure 1 The number of second conducting pads 2 in a row or a column is presented only as an example, and the present invention is not limited thereto.

[0071] By controlling the plurality of first row switches 11 and the plurality of first column switches 12 of the array switch circuit system 100, any first conductive pads 1 can be turned on or off, that is, the connection of the redistribution layer winding can be changed by controlling the array switch, so as to solve the problem of needing to redesign the redistribution layer. Further, the array switch circuit system 100 can further include an active switch control circuit to control the array switch, wherein the specific architecture of the control circuit will be described later. Furthermore, the array switch circuit system 100 can transmit high-speed signals between the second conductive pads 2 through the first transmission line 21, wherein the first transmission line 21 can be realized by a specially designed coplanar waveguide, solving the impedance matching problem of high-speed signals. Therefore, the overall packaging carrier of the array switch circuit system 100 can only need to customize the metal of the transmission line, and the rest are all prefabricated designs, so as to shorten the product development time and reduce the R&D cost, and fill the gap in the packaging of various products.

[0072] Please combine Figure 1 Reference Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the structure of an array switch circuit system according to an embodiment of the present invention. Figure 2As shown, the substrate 10 of the array switch circuit system 100 may include a plurality of layers, wherein the first conductive pad 1 and the second conductive pad 2 are disposed on the first layer (or the top layer) of the plurality of layers, the plurality of first transmission lines 21 and the plurality of first row switches 11 are located on different layers of the plurality of layers, and the plurality of first transmission lines 21 and the plurality of first column switches 12 are located on different layers of the plurality of layers, so that the first transmission lines 21 and the first row switches 11 and the first column switches 12 do not interfere with each other. In this embodiment, the layer of the first transmission line 21 is located between the layer of the first conductive pad 1 and the second conductive pad 2 and the layer of the first row switches 11 and the first column switches 12, and the layer of the first transmission line 21 may be closer to the layer of the first conductive pad 1 and the second conductive pad 2 and farther away from the layer of the first row switches 11 and the first column switches 12. It should be noted that the first transmission line 21 extending along the row direction of the array R and the first transmission line 21 extending along the column direction of the array R may be substantially located on the same layer. For example, one of two intersecting first transmission lines 21 located in the same layer can be connected to an adjacent layer through a through hole to cross another first transmission line 21, wherein the two intersecting first transmission lines 21 can be electrically isolated from each other by an insulating layer (such as silicon dioxide SiO2) at the intersection.

[0073] Please combine Figure 1 and Figure 2 refer to Figure 3 , Figure 3 According to an embodiment of the present invention, Figure 2 The cross-sectional diagram of the array switch circuit system is shown along the section line AA'. Figure 3 As shown, the multiple layers of the substrate 10 can be initially divided into a first layer L1, a second layer L2 and a third layer L3. It should be noted that Figure 3 The composition of the substrate 10 is presented exemplarily. In other embodiments, Figure 3 Any two layers shown may contain one or more additional layers, and the present invention is not limited thereto. Figure 3 As shown, the second conductive pad 2 and the first conductive pad 1 are disposed on the first layer L1 of the substrate 10, wherein the second conductive pad 2 and the first conductive pad 1 can be electrically connected to the layer below through respective vias. The first transmission line 21 is disposed on the second layer L2 of the substrate 10. The first row switch 11 is disposed on the third layer L3 of the substrate 10. In this way, two first conductive pads 1 adjacent to each other in the row direction can be electrically connected through the first row switch 11. In this embodiment, the second layer L2 on which the first transmission line 21 is disposed is closer to the first layer L1 on which the first conductive pad 1 and the second conductive pad 2 are disposed, and is farther from the third layer L3 on which the first row switch 11 is disposed, so that the mutual interference between the first transmission line 21 and the first row switch 11 can be further reduced.

[0074] Please combine Figure 1 and Figure 2 refer to Figure 4 , Figure 4 According to an embodiment of the present invention, Figure 2 The cross-sectional diagram of the array switch circuit system is shown along the section line BB'. Figure 4 As shown, the two second conductive pads 2 located on both sides and arranged on the first layer L1 can be electrically connected to each other through the first transmission line 21 arranged on the second layer L2. This electrical transmission path is separated from the first row of switches 12 arranged on the third layer L3, so that the mutual interference between the first transmission line 21 and the first row of switches 12 can be effectively reduced. Specifically, multiple layers can be arranged between the second layer L2 and the third layer L3, and the first layer L1 and the second layer L2 can be adjacent to each other to achieve the above effect. It should be noted that Figures 2 to 4 The cross-section lines AA' and BB' shown are selected along the row direction of the array, but the cross-section lines can also be selected along the column direction of the array, and the corresponding cross-sectional structures are similar to those in FIG. Figure 3 and Figure 4 , so this article will not go into details here.

[0075] Please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a first transmission line implemented by a coplanar waveguide in an array switch circuit system according to an embodiment of the present invention. Figure 5 As shown, the first transmission line 21 can be implemented as a coplanar waveguide, specifically including a first conductor strip 211 and two second conductor strips 212, wherein the two second conductor strips 212 are respectively located on both sides of the first conductor strip 211 and are coplanar with the first conductor strip 211. In this embodiment, the characteristic impedance of the first transmission line 21 is associated with the width W of the first conductor strip 211, the spacing S between the first conductor strip 211 and the two second conductor strips 212, the conductor layer thickness T of the first conductor strip 211 and the second conductor strip 212, and the dielectric layer thickness H of a layer of the substrate where the first transmission line 21 is located. It should be noted that Figure 5 2 is a tangent diagram of the first transmission line 21. The signal of the first transmission line 21 is transmitted by the first conductor strip 211, and the second conductor strip 212 is the ground end. The characteristic impedance of the first transmission line 21 in this example is independent of the length of the transmission line.

[0076] In this embodiment, the relationship between the characteristic impedance (Z0) of the first transmission line 21 and the width W, the spacing S, the conductor layer thickness T and the dielectric layer thickness H can be obtained through the following relationship (1-14).

[0077] Relationship 1: a = W × 2

[0078] Relation 2:

[0079] Relation 3:

[0080] Relation 4:

[0081] Relation 5:

[0082] Relation 6:

[0083] Relation 7:

[0084] Relation 8:

[0085] Relation 9:W e =W+Δ

[0086] Relation 10:S e =S-Δ

[0087] Relation 11:

[0088] Relation 12:

[0089] Relation 13:

[0090] Relation 14:

[0091] In the above relationship, ε re is the material dielectric constant of the substrate, The dielectric constant of the material of the substrate is the parameter that incorporates the conductor layer thickness T. Through the above relationship, a coplanar waveguide (first transmission line 21) with a specific impedance can be designed to solve the impedance matching problem of high-speed signals. In one embodiment, the range of the characteristic impedance of the first transmission line 21 is designed to be between 25 and 150 ohms. The design method of the coplanar waveguide of the first transmission line 21 of the present invention is not limited to the above relationship 1 to 14, but through the above relationship 1 to 14, the coplanar waveguide can have a better impedance matching effect.

[0092] Please combine Figure 1 refer to Figure 6 , Figure 6 FIG. 1 is a circuit diagram of an array switch circuit system according to another embodiment of the present invention. Figure 6 As shown, the array switch circuit system 100 of this embodiment has a first conductive pad in the central area and a second conductive pad in the peripheral area. Figure 1 The embodiments are basically the same, and repeated description is omitted here. In this embodiment, except Figure 1 In addition to the components included in the array switch circuit system 100, the array switch circuit system 100' further includes a plurality of second row switches 22 and a plurality of second column switches 23. The second row switches 22 are disposed on the substrate, and each of the second row switches 22 is connected to two adjacent second conductive pads 2 arranged in a conductive pad row. The second column switches 23 are disposed on the substrate, and each of the second column switches 23 is connected to two adjacent second conductive pads 2 arranged in a conductive pad column. Through the configuration of the second row switches 22 and the second column switches 23 of this embodiment, the plurality of second conductive pads 2 of this embodiment can not only transmit high-speed signals through the first transmission line 21, but also have the function of switching input and output signals.

[0093] Please combine Figure 6 refer to Figure 7 , Figure 7 FIG. 1 is a circuit diagram of an array switch circuit system according to another embodiment of the present invention. Figure 7 As shown, the array switch circuit system 100 of this embodiment is configured with the first conductive pad, the second conductive pad, the second row switch 22 and the second column switch 23. Figure 6 The embodiments are basically the same, and repeated description is omitted here. In this embodiment, except Figure 6 In addition to the components included in the array switch circuit system 100', the array switch circuit system 100" further includes one or more third conducting pads 3 arranged on the first layer of the substrate and a third row switch 31 and a third column switch 32 arranged on the inner layer of the substrate. The third conducting pad 3 is connected to the conducting pad row including the second conducting pad 2 through the third row switch 31, and is connected to the conducting pad column including the second conducting pad 2 through the third column switch 32.

[0094] Through the configuration of the third conducting pad 3, the third row switch 31 and the third column switch 32 of this embodiment, the array switch circuit system 100" of this embodiment can have more diverse signal transmission paths. For example, Figure 1 The second conducting pad 2 of the array switch circuit system 100 shown can only be electrically connected to the second conducting pad 2 on the opposite side through the first transmission line 21; Figure 6 The second conducting pad 2 of the array switch circuit system 100 ′ shown may be electrically connected to the second conducting pad 2 on the same side through the second row switch 22 and / or the second column switch 23 ; Figure 7 The second conducting pad 2 of the array switch circuit system 100" shown can be electrically connected to the surrounding second conducting pads 2 through the third conducting pad 3, the third row switch 31 and / or the third column switch 32. It should be noted that Figure 6 and Figure 7 The second row of switches 22, the second column of switches 23, the third row of switches 31, and the third column of switches 32 shown can be connected to Figure 3The first row of switches 11 is disposed on the same layer (third layer L3 ) of the substrate, and can also have a larger spacing with the first transmission line 21 to reduce mutual interference in signal transmission.

[0095] Please refer to Figure 8 , Figure 8 is a schematic diagram of a plurality of transmission lines between two second conductive pads 2 in an array switch circuit system according to other embodiments of the present invention. In the aforementioned embodiment, the two second conductive pads 2 are electrically connected via a first transmission line 21, and the first transmission line 21 may have a specific impedance. In other embodiments, the two second conductive pads may also be electrically connected via a plurality of transmission lines with different impedances. Figure 8 As shown, in this embodiment, a target transmission line among a plurality of first transmission lines 21 in the array switch circuit system is connected to a first target conductive pad 2a and a second target conductive pad 2b among the second conductive pads 2, and the array switch circuit system further includes a second transmission line 24, a first switching element T1 and a second switching element T2. The second transmission line 24 has an impedance different from that of the target transmission line (first transmission line 21). The first switching element T1 is connected to the first target conductive pad 2a, the target transmission line (first transmission line 21) and the second transmission line 24, and is used for switching so that one of the target transmission line (first transmission line 21) and the second transmission line 24 is connected to the first target conductive pad 2a. The second switching element T2 is connected to the second target conductive pad 2b, the target transmission line (first transmission line 21) and the second transmission line 24, and is used for switching so that one of the target transmission line (first transmission line 21) and the second transmission line 24 is connected to the second target conductive pad 2b.

[0096] Similarly, the array switch circuit system may also include a third transmission line 27 or more transmission lines with different impedances between the two second conductive pads. The first switching element T1 and the second switching element T2 of this embodiment can be exemplified by a high-frequency single-pole multi-throw switch. By including an embodiment of multiple transmission lines with different impedances, the array switch circuit system can select signal transmission paths with different impedances according to requirements, thereby increasing the flexibility of application.

[0097] In particular, the array switch circuit system described in the above-mentioned multiple embodiments can be implemented by a bridge chip, which can be an embedded multi-die hybrid bridge chip (EMHB) architecture that can be applied to system packaging, and has the architecture of both an embedded multi-die interconnect bridge chip and an embedded multi-die active bridge chip.

[0098] Please refer to Fig. 9 , Fig. 9FIG. 1 is a block diagram of a switch control circuit of an array switch circuit system according to an embodiment of the present invention. Fig. 9 As shown, each switch element of the array switch circuit system 100 of the present invention can be controlled by a switch control circuit C, wherein the switch control circuit C can include a packet detector and control generator C1, an addition generator C2, a pulse generator C3, a buffer C4, an amplifier C5, a memory C6, a switch controller C7 and a selector C8. In this embodiment, the memory can be a one-time programmable (OTP) memory or a multiple-times programmable (MTP) memory. The switch control circuit C can have two switch control modes, one is a one-time control mode in which the switch switching state is burned into the one-time programmable memory, and the switch switching state is directly read from the memory each time the chip is used; the other is a dynamic control mode in which the switch switching state is directly transmitted to the array switch circuit system, and the switch switching can be performed at any time, but the switch switching state will be lost after the chip is powered off, so the switch switching state needs to be re-entered. For example, after receiving the switch switching state data, the packet detector and control generator C1 will determine whether to write or read the memory C6 or directly control the array switch circuit system 100, and generate a corresponding control signal to the memory C6 and the selector C8, and transmit the switch switching state data to the memory C6 or the array switch circuit system 100. In addition, the initial signal Initial is transmitted to the switch control circuit C7, and the clock signal Clk is transmitted to the packet detector and control generator C1 and the buffer C4.

[0099] Please refer to Fig.10 , Fig.10 FIG. 1 is a circuit diagram of a switch circuit of an array switch circuit system according to an embodiment of the present invention. Fig.10 As shown, the switch circuit (first row switch 11) includes a transmission gate 111, two base control subcircuits 112 and 113, and a transistor group 114. The transmission gate 111 includes transistors M1 and M2, having two input-output terminals P11 and P12, two base control terminals P13 and P14, and two gate control terminals P15 and P16, and is used to turn the two input-output terminals P11 and P12 on or off according to the voltages of the two gate control terminals P15 and P16. Specifically, the source of the transistor M1 and the drain of the transistor M2 are connected to each other as the input-output terminal P11, and the drain of the transistor M1 and the source of the transistor M2 are connected to each other as the input-output terminal P12.

[0100] The base control subcircuit 112 includes a transistor M3 and a transistor M4. The first end of the transistor M3 is electrically connected to the input-output terminal P11, the second end of the transistor M3 is electrically connected to the base control terminal P13, and the control end of the transistor M3 is electrically connected to the gate control terminal P15. The first end of the transistor M4 is electrically connected to the base control terminal P13, the second end of the transistor M4 is electrically connected to the input-output terminal P12, and the control end of the transistor M4 is electrically connected to the gate control terminal P15. The base control subcircuit 113 includes a transistor M5 and a transistor M6. The first end of the transistor M5 is electrically connected to the input-output terminal P11, the second end of the transistor M5 is electrically connected to the base control terminal P14, and the control end of the transistor M5 is electrically connected to the gate control terminal P16. The first end of the transistor M6 is electrically connected to the base control terminal P14, the second end of the transistor M6 is electrically connected to the input-output terminal P12, and the control end of the transistor M6 is electrically connected to the gate control terminal P16.

[0101] The transistor group 114 includes a transistor M7 and a transistor M8. The first end of the transistor M7 is electrically connected to the base control terminal P13, the second end of the transistor M7 is used for grounding, and the control end of the transistor M7 is electrically connected to the gate control terminal P16. The first end of the transistor M8 is used to receive the working voltage Vdd, the second end of the transistor M8 is electrically connected to the base control terminal P14, and the control end of the transistor M8 is electrically connected to the gate control terminal P15.

[0102] Through the above circuit architecture, the two base control subcircuits 112 and 113 and the transistor group 114 can dynamically adjust the base voltages of the two transistors M1 and M2 of the transmission gate 111 according to the switch state of the transmission gate 111. Further, the dynamic adjustment operation may include: when the transmission gate 111 is in the open (ON) state, the two base control subcircuits 112 and 113 and the transistor group 114 make the base voltages of the transistors M1 and M2 of the transmission gate 111 synchronized with the voltage of the input signal (less than a preset value, or even equal to 0). In addition, when the transmission gate 111 is in the closed (OFF) state, the two base control subcircuits 112 and 113 and the transistor group 114 adjust the base voltages of the transistors M1 and M2 of the transmission gate 111 to the working voltage Vdd and the ground voltage respectively, thereby avoiding the problem of base leakage. In addition, the area occupied by the switch circuit 11 in the circuit wiring can be similar to that of a traditional transmission gate switch. That is to say, the switch circuit 11 has better characteristics than the conventional transmission gate switch and has a comparable area, which makes it more advantageous.

[0103] Furthermore, the two base control subcircuits 112 and 113 and the transistor group 114 of the switch circuit (first row switch 11) of this embodiment can form a two-terminal balanced circuit structure, so that the switch circuit 11 can have a consistent resistance value regardless of whether it is transmitting in the forward direction (for example, from the input-output terminal P11 to the input-output terminal P12) or the reverse direction (for example, from the input-output terminal P12 to the input-output terminal P11).

[0104] The circuit structure of the two base control subcircuits 112 and 113 and the transistor group 114 of the above switch circuit (first row switch 11) can be regarded as that the two base control subcircuits each include a first transistor and a second transistor, and the transistor group includes a third transistor and a fourth transistor. The electrical connection relationship between each base control subcircuit 112 / 113 and the transmission gate 111 can be regarded as: the first transistor has a first end electrically connected to the first of the two input-output terminals, a second end electrically connected to the first node, and a control end electrically connected to the second node; the second transistor has a first end electrically connected to the first node, a second end electrically connected to the second of the two input-output terminals, and a control end electrically connected to the second node; wherein the first node and the second node corresponding to one of the two base control subcircuits are respectively the first of the two base control terminals and the second of the two gate control terminals, and the first node and the second node corresponding to the other of the two base control subcircuits are respectively the second of the two base control terminals and the first of the two gate control terminals. The electrical connection between the transistor group 114 and the transmission gate 111 can be regarded as: the third transistor has a first end electrically connected to the first of the two base control terminals, a second end for grounding, and a control end electrically connected to the first of the two gate control terminals; the fourth transistor has a first end for receiving an operating voltage, a second end electrically connected to the second of the two base control terminals, and a control end electrically connected to the second of the two gate control terminals.

[0105] Please refer to Fig.11 , Fig.11 FIG. 1 is a circuit diagram of a switch circuit of an array switch circuit system according to another embodiment of the present invention. Fig.11 As shown, the switch circuit (first row switch 11') includes a transmission gate 111, base control subcircuits 112 and 113, a first transistor group 114, a second transistor group 115 and a third transistor group 116, wherein the transmission gate 111, the base control subcircuits 112 and 113 and the first transistor group 114 are electrically connected in the same manner as Fig.10 The connection method of the transmission gate 111, the base control subcircuit 112 and 113 and the transistor group 114 of the switch circuit (the first row switch 11) shown in FIG. 1 is the same and will not be repeated here.

[0106] The second transistor group 115 includes a transistor M9 and a transistor M10. The first end of the transistor M9 is electrically connected to the first end of the transistor M3, the second end of the transistor M9 is electrically connected to the second end of the transistor M3, and the control end of the transistor M9 is electrically connected to the control end of the transistor M5. The first end of the transistor M10 is electrically connected to the first end of the transistor M4, the second end of the transistor M10 is electrically connected to the second end of the transistor M4, and the control end of the transistor M10 is electrically connected to the control end of the transistor M6.

[0107] The third transistor group 116 includes a transistor M11 and a transistor M12. The first end of the transistor M11 is electrically connected to the first end of the transistor M5, the second end of the transistor M11 is electrically connected to the second end of the transistor M5, and the control end of the transistor M11 is electrically connected to the control end of the transistor M3. The first end of the transistor M12 is electrically connected to the first end of the transistor M6, the second end of the transistor M12 is electrically connected to the second end of the transistor M6, and the control end of the transistor M12 is electrically connected to the control end of the transistor M4. That is, the first end of the transistor M11 is electrically connected to the input-output terminal P31, the second end of the transistor M11 is electrically connected to the base control terminal P34, and the control end of the transistor M11 is electrically connected to the gate control terminal P15. The first end of the transistor M12 is electrically connected to the base control terminal P34, the second end of the transistor M12 is electrically connected to the input-output terminal P32, and the control end of the transistor M12 is electrically connected to the gate control terminal P15.

[0108] In the above-mentioned embodiment including the second and third transistor groups, the switch circuit (first row switch 11') can also perform the dynamic adjustment operation performed by the switch circuit (first row switch 11) as described above, thereby solving the problem of the switch on-resistance increase caused by the difference between the base voltage and the input signal voltage when the traditional transmission gate switch is turned on, thereby having a lower switch on-resistance and thus having a wider channel bandwidth. The switch circuit (first row switch 11') can also perform the above-mentioned operation that when the transmission gate 111 is in the closed (OFF) state, the base control subcircuits 112 and 113, the first transistor group 114, the second transistor group 115 and the third transistor group 116 adjust the base voltages of the transistors M1 and M2 of the transmission gate 111 to the working voltage Vdd and the ground voltage respectively, thereby avoiding the problem of base leakage. Furthermore, the base control subcircuits 112 and 113, the first transistor group 114, the second transistor group 115 and the third transistor group 116 of the switch circuit (the first row switch 11') can form a double-ended balanced circuit structure, so that the switch circuit (the first row switch 11') can have a consistent resistance value regardless of whether it is transmitted in the forward direction (e.g., from the input-output terminal P31 to the input-output terminal P32) or the reverse direction (e.g., from the input-output terminal P32 to the input-output terminal P31). In addition, compared to Fig.10 The switch circuit (the first row of switches 11 ) shown in FIG. 1 and the switch circuit (the first row of switches 11 ′) may have a lower on-resistance, thereby having a faster charge and discharge speed and a wider channel bandwidth.

[0109] The circuit structure of the above switch circuit (the first row of switches 11') can be regarded as Fig.10 The switch circuit (first row switch 11) shown further selectively includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein a first end of the fifth transistor is electrically connected to a first end of a first transistor of the first of the two base control subcircuits, a second end of the fifth transistor is electrically connected to a second end of the first transistor of the first of the two base control subcircuits, and a control end of the fifth transistor is electrically connected to a control end of a first transistor of the second of the two base control subcircuits, a first end of the sixth transistor is electrically connected to a first end of a second transistor of the first of the two base control subcircuits, a second end of the sixth transistor is electrically connected to a second end of a second transistor of the first of the two base control subcircuits, and a control end of the sixth transistor is electrically connected to a control end of the first transistor of the second of the two base control subcircuits. The control end of the second transistor of the second one of the two base control subcircuits, and wherein the first end of the seventh transistor is electrically connected to the first end of the first transistor of the second one of the two base control subcircuits, and the second end of the seventh transistor is electrically connected to the second end of the first transistor of the second one of the two base control subcircuits, and the control end of the seventh transistor is electrically connected to the control end of the first transistor of the first one of the two base control subcircuits, the first end of the eighth transistor is electrically connected to the first end of the second transistor of the second one of the two base control subcircuits, the second end of the eighth transistor is electrically connected to the second end of the second transistor of the second one of the two base control subcircuits, and the control end of the eighth transistor is electrically connected to the control end of the second transistor of the first one of the two base control subcircuits.

[0110] Please refer to Fig.12 , Fig.12 FIG. 1 is a circuit diagram of a switch circuit of an array switch circuit system according to another embodiment of the present invention. Fig.12 As shown, the switch circuit (first row switch 11") includes transistors M1, M2, M3, M4 and M5. The drain and source of transistor M1 are connected to the input and output terminals P1 and P2 respectively. The base of transistor M1 is connected to the drains of transistors M2 and M4. The gates of transistors M2 and M4 are connected to the drains of transistors M3 and M5. The gates of transistors M3 and M5 are connected to the input and output terminal P1. The sources of transistors M2 and M3 receive the working voltage Vdd. The sources of transistors M4 and M5 are grounded.

[0111] Through the above structure, the array switch circuit system disclosed by the present invention can change the connection of the redistribution layer (RDL) winding for the transmission of low-speed signals through the control of the array switch, so as to solve the problem of needing to redesign the redistribution layer; the transmission of high-speed signals can be carried out through transmission lines to achieve the effect of low latency, wherein the transmission line of the high-speed signal can be realized through a specially designed coplanar waveguide (CPW) to solve the impedance matching problem of the high-speed signal. In this way, the overall packaging carrier of the array switch circuit system of the present invention can only need to customize the metal layer of the transmission line, and the rest are all prefabricated designs, thereby shortening the product development time and reducing the R&D cost, and filling the packaging gap of various products. In addition, by setting an additional transmission line with different impedances between the two conductive pads used to transmit high-speed signals, and matching a high-frequency single-pole multi-throw switch, the array switch circuit system can select transmission paths with different impedances according to needs, increasing the flexibility of application.

[0112] Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

Claims

1. An array switch circuit system, characterized in that: Include: a substrate; A plurality of first conducting pads are disposed on the substrate at intervals and arranged in an array, wherein each of the first conducting pads has a row position and a column position in the array. A plurality of first row switches are disposed on the substrate, wherein each of the first row switches is connected to two adjacent first conductive pads corresponding to the same row position; A plurality of first row switches are disposed on the substrate, wherein each of the first row switches is connected to two adjacent first conductive pads corresponding to the same row position; A plurality of second conducting pads are disposed on the substrate and disposed around the first conducting pads; as well as A plurality of first transmission lines are disposed on the substrate, wherein each of the first transmission lines connects two of the second conducting pads and comprises a first conductor strip and two second conductor strips, the two second conductor strips are respectively located at two sides of the first conductor strip and are coplanar with the first conductor strip.

2. The array switch circuit system according to claim 1, characterized in that: The substrate comprises a plurality of layers, the first transmission lines and the first row switches are located at different layers among the layers, and the first transmission lines and the first column switches are located at different layers among the layers.

3. The array switch circuit system according to claim 1, characterized in that: The substrate comprises a plurality of layers, the first conducting pads and the second conducting pads are located on a first layer among the layers, and the first transmission lines are located on a second layer adjacent to the first layer among the layers.

4. The array switch circuit system according to claim 1, characterized in that: The second conductive pads are arranged into two conductive pad rows and two conductive pad columns, the two conductive pad columns are located at two opposite sides of the array, the two conductive pad columns are located at another two opposite sides of the array, and the two of the second conductive pads connected to each of the first transmission lines belong to the two conductive pad columns or the two conductive pad rows, respectively.

5. The array switch circuit system according to claim 1, characterized in that: A portion of the second conducting pads are arranged into a conducting pad row and a conducting pad column, and the array switch circuit system further comprises: A plurality of second row switches are disposed on the substrate, wherein each of the second row switches is connected to two adjacent conducting pads in the conducting pad row; and A plurality of second row switches are disposed on the substrate, wherein each of the second row switches is connected to two adjacent conducting pads in the conducting pad row.

6. The array switch circuit system according to claim 5, characterized in that: Also includes: a third row of switches disposed on the substrate; a third row of switches disposed on the substrate; A third conducting pad is disposed on the substrate, connected to the conducting pad row through the third row switch, and connected to the conducting pad row through the third row switch.

7. The array switch circuit system according to claim 1, characterized in that: A target transmission line among the first transmission lines is connected to a first target conducting pad and a second target conducting pad among the second conducting pads, and the array switch circuit system further comprises: a second transmission line having an impedance different from that of the target transmission line; a first switching element connected to the first target conducting pad, the target transmission line and the second transmission line, and used for switching to make one of the target transmission line and the second transmission line conduct with the first target conducting pad; and A second switching element is connected to the second target conducting pad, the target transmission line and the second transmission line, and is used for switching to make one of the target transmission line and the second transmission line conduct with the second target conducting pad.

8. The array switch circuit system according to claim 1, characterized in that: The characteristic impedance of each of the first transmission lines ranges from 25 to 150 ohms.

9. The array switch circuit system according to claim 1, characterized in that: One of the first row switches and the first column switches comprises: A transmission gate having two input and output terminals, two gate control terminals and two base control terminals, and used to connect or disconnect the two input and output terminals according to the voltage of the two gate control terminals; Two base control subcircuits, each comprising: a first transistor having a first terminal electrically connected to a first one of the two input / output terminals, a second terminal electrically connected to a first node, and a control terminal electrically connected to a second node; and a second transistor having a first terminal electrically connected to the first node, a second terminal electrically connected to a second one of the two input / output terminals, and a control terminal electrically connected to the second node; a third transistor having a first terminal electrically connected to a first one of the two base control terminals, a second terminal for grounding, and a control terminal electrically connected to a first one of the two gate control terminals; and a fourth transistor having a first terminal for receiving an operating voltage, a second terminal electrically connected to a second one of the two base control terminals, and a control terminal electrically connected to a second one of the two gate control terminals; The first node and the second node corresponding to one of the two base control subcircuits are respectively the first of the two base control terminals and the second of the two gate control terminals, and the first node and the second node corresponding to the other of the two base control subcircuits are respectively the second of the two base control terminals and the first of the two gate control terminals.

10. The array switch circuit system according to claim 9, characterized in that: The one of the first row switches and the first column switches further comprises: a fifth transistor, wherein a first terminal of the fifth transistor is electrically connected to the first terminal of the first transistor of a first one of the two base control subcircuits, a second terminal of the fifth transistor is electrically connected to the second terminal of the first transistor of the first one of the two base control subcircuits, and a control terminal of the fifth transistor is electrically connected to the control terminal of the first transistor of a second one of the two base control subcircuits; and A sixth transistor, wherein a first end of the sixth transistor is electrically connected to the first end of the second transistor of the first one of the two base control subcircuits, a second end of the sixth transistor is electrically connected to the second end of the second transistor of the first one of the two base control subcircuits, and a control end of the sixth transistor is electrically connected to the control end of the second transistor of the second one of the two base control subcircuits.

11. The array switch circuit system according to claim 10, characterized in that: The one of the first row switches and the first column switches further comprises: a seventh transistor, wherein a first terminal of the seventh transistor is electrically connected to the first terminal of the first transistor of the second of the two-base control subcircuit, a second terminal of the seventh transistor is electrically connected to the second terminal of the first transistor of the second of the two-base control subcircuit, and a control terminal of the seventh transistor is electrically connected to the control terminal of the first transistor of the first of the two-base control subcircuit; and An eighth transistor, wherein a first end of the eighth transistor is electrically connected to the first end of the second transistor of the second of the two base control subcircuits, and a second end of the eighth transistor is electrically connected to the second end of the second transistor of the second of the two base control subcircuits, and a control end of the eighth transistor is electrically connected to the control end of the second transistor of the first of the two base control subcircuits.

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