Semiconductor element with inclined conductive layer

Abstract

The present disclosure provides a semiconductor device including a bottom portion and a higher portion. The bottom portion includes a first stack structure, a first impurity region, and a conductive plug. The higher portion is disposed over the bottom portion and includes a second stack structure and a second impurity region. The first stack structure includes a plurality of gate elements coupled to the first impurity region, and the second stack structure includes a plurality of capacitor subunits coupled to the second impurity region. The first impurity region is electrically coupled to the second impurity region through the conductive plug. The conductive plug includes a plurality of conductive layers, a dielectric layer surrounding the conductive layers, and a top conductive layer electrically coupled to the conductive layers. Each of the conductive layers extends along a direction. The direction forms an acute angle with a top surface of the first impurity region.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2024102017570, filed on February 3, 2024, with the invention name of “Semiconductor element with inclined conductive layer”. Application No. 2024102017570 claims priority and benefits of U.S. formal application No. 18 / 385,979 filed on November 1, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element, and more particularly to a semiconductor element having an inclined conductive layer. Background Art

[0003] Semiconductor components have been used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the growing demand for computing power. However, various problems arise during the miniaturization process, and these problems continue to increase. Therefore, challenges remain in improving quality, yield, performance and reliability, and reducing complexity.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a semiconductor element, comprising a first die and a second die. The first die comprises a first dielectric layer disposed on a first substrate, a second dielectric layer disposed on the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via comprises a plurality of conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the conductive layers extends along a direction. The direction forms an acute angle greater than 0 degrees with a top surface of the first die. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

[0006] Another aspect of the present disclosure provides a semiconductor element, including a bottom portion and a higher portion. The bottom portion includes a first stacked structure, a first impurity region, and a conductive plug. The higher portion is disposed above the bottom portion and includes a second stacked structure and a second impurity region. The first stacked structure includes a plurality of gate components coupled to the first impurity region, and the second stacked structure includes a plurality of capacitor subunits coupled to the second impurity region. The first impurity region is electrically coupled to the second impurity region through the conductive plug. The conductive plug includes: a plurality of conductive layers, a dielectric layer surrounding the conductive layers, and a top conductive layer electrically coupled to the conductive layers. Each of the conductive layers extends along a direction. The direction forms an acute angle with a top surface of the first impurity region.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor element, comprising: forming a first grain, forming a second grain; and bonding the second grain to the first grain. Forming the first grain comprises: forming a first dielectric layer on a first substrate; forming a first metal layer in the first dielectric layer; forming a second dielectric layer on the first dielectric layer; and forming a first conductive via in the second dielectric layer. Forming the first conductive via in the second dielectric layer comprises: forming a third dielectric layer in the second dielectric layer; performing a first tilted etching process to form a plurality of first openings in the third dielectric layer; forming a plurality of first conductive layers in the first openings; and forming a first top conductive layer on the first conductive layers and the third dielectric layer. The first conductive layers extend along a first direction, wherein the first direction and a top surface of the first grain form a first acute angle greater than 0 degrees.

[0008] Due to the design of the semiconductor element disclosed in the present invention, the first inclined conductive layers can provide more contact surfaces with the substrate. Therefore, the electrical characteristics of the semiconductor element can be improved. That is, the performance of the semiconductor element can be improved. In addition, a first hard mask layer with a wider first hard mask opening can be used to form a narrower first inclined recess. In other words, the requirements for the lithography process for forming the narrower first inclined recess can be reduced. As a result, the yield of the semiconductor element can be improved.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The various aspects of the present disclosure can be read in conjunction with the following drawings and detailed descriptions for easy understanding. It is emphasized that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion.

[0011] Figure 1 According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is shown in the form of a flow chart.

[0012] Figure 2 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure.

[0013] Figure 3 According to an embodiment of the present disclosure, Figure 2 Schematic diagram of the cross section drawn by line AA'.

[0014] Figure 4 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure.

[0015] Figure 5 According to an embodiment of the present disclosure, Figure 4 Schematic diagram of the cross section drawn by line AA'.

[0016] Figure 6 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure.

[0017] Figures 7 to 9 According to an embodiment of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0018] Figures 10 to 15 According to some embodiments of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0019] Fig.16 and Fig.17 A schematic top view of a plurality of intermediate semiconductor elements is shown according to another embodiment of the present disclosure.

[0020] Fig.18 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0021] Fig.19 According to another embodiment of the present disclosure, Fig.18 Schematic diagram of the cross section drawn by line AA'.

[0022] Fig. 20A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0023] Fig.21 According to another embodiment of the present disclosure, Fig. 20 Schematic diagram of the cross section drawn by line AA'.

[0024] Fig. 22 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0025] Fig.23 According to another embodiment of the present disclosure, Fig. 22 Schematic diagram of the cross section drawn by line AA'.

[0026] Fig.24 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0027] Fig.25 According to another embodiment of the present disclosure, Fig.24 Schematic diagram of the cross section drawn by line AA'.

[0028] Fig.26 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0029] Fig. 27 According to another embodiment of the present disclosure, Fig.26 Schematic diagram of the cross section drawn by line BB'.

[0030] Fig.28 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure.

[0031] Fig.29 According to another embodiment of the present disclosure, Fig.28 Schematic diagram of the cross section drawn by line C-C'.

[0032] Figures 30 to 38 Schematic diagram showing an intermediate semiconductor element according to some embodiments of the present disclosure.

[0033] Fig.39A Schematic diagrams showing semiconductor devices according to some embodiments of the present disclosure.

[0034] Fig.39B Schematic diagrams showing semiconductor devices according to other embodiments of the present disclosure.

[0035] Figures 40 to 48 Schematic diagram showing an intermediate semiconductor element according to some embodiments of the present disclosure.

[0036] Fig.49Schematic diagrams showing semiconductor devices according to some embodiments of the present disclosure.

[0037] The reference numerals are described as follows:

[0038] 1A: Semiconductor components

[0039] 1B: Semiconductor components

[0040] 1C: Semiconductor components

[0041] 1D: Semiconductor components

[0042] 1E: Semiconductor components

[0043] 1F: Semiconductor components

[0044] 1G: Semiconductor components

[0045] 1H: Semiconductor components

[0046] 1S: First stacking structure

[0047] 2A: Semiconductor components

[0048] 2B: Semiconductor components

[0049] 2S: Second stacking structure

[0050] 10: Methods

[0051] 101: Substrate

[0052] 103: First insulation layer

[0053] 105: Second insulation layer

[0054] 201: first inclined conductive layer

[0055] 201BS: Bottom surface

[0056] 201SW: Sidewall

[0057] 201TS: Top surface

[0058] 203: Top conductive layer

[0059] 205: Second inclined conductive layer

[0060] 205BS: Bottom surface

[0061] 205SW: Sidewall

[0062] 207: Barrier layer

[0063] 209: Under Bump Metallization

[0064] 301: First hard mask layer

[0065] 303: First hard mask opening

[0066] 305: First inclined depression

[0067] 305BS: Bottom surface

[0068] 305SW: Sidewall

[0069] 307: First conductive material

[0070] 309: Second hard mask layer

[0071] 311: Second hard mask opening

[0072] 313: Second inclined depression

[0073] 313BS: Bottom surface

[0074] 313SW: Sidewall

[0075] 401: First inclined etching process

[0076] 403: Second inclined etching process

[0077] 500: First semiconductor grain

[0078] 501: Semiconductor substrate

[0079] 503: Dielectric layer

[0080] 507: Dielectric layer

[0081] 511: Conductive polymer materials

[0082] 513: Hard mask layer

[0083] 515: Conductive layer

[0084] 517: Barrier layer

[0085] 519: Metal layer

[0086] 521: Top conductive layer

[0087] 523: Bottom surface

[0088] 553: Energy Removable Materials

[0089] 600: Second semiconductor grain

[0090] 601: Tilt Etching Process

[0091] 603: Dielectric layer

[0092] 607: Dielectric layer

[0093] 611: Conductive polymer materials

[0094] 615: Conductive layer

[0095] 617: Barrier layer

[0096] 619: Metal layer

[0097] 621: Top conductive layer

[0098] 653: Energy Removable Materials

[0099] 701: Substrate

[0100] 703: Buried Bit Lines

[0101] 705: First insulation material

[0102] 707: Semiconductor layer

[0103] 709: Internal spacer

[0104] 713: First impurity region

[0105] 714: Second impurity region

[0106] 715: Gate Dielectric

[0107] 717: Gate electrode

[0108] 721: First insulation layer

[0109] 723: Intermediate insulation layer

[0110] 725: Dielectric layer

[0111] 727: Hard mask layer

[0112] 729: Top conductive layer

[0113] 731: Conductive layer

[0114] 753: Bottom surface

[0115] 800: Conductive plug

[0116] 801: Tilt Etching Process

[0117] 901: Semiconductor layer

[0118] 903: Capacitor Dielectric

[0119] 905: Internal spacer

[0120] 907: Capacitor Electrode

[0121] 909: The third impurity region

[0122] 911: The fourth impurity region

[0123] A-A': line

[0124] B-B': Line

[0125] BT: bottom part

[0126] C-C': Line

[0127] CU: Capacitor Subunit

[0128] D1: Distance

[0129] D2: Distance

[0130] D3: Distance

[0131] D4: Distance

[0132] E1: Direction

[0133] E2: Direction

[0134] E3: Direction

[0135] E4: Direction

[0136] F1: Virtual Frame

[0137] F2: Virtual Frame

[0138] FS: First Side

[0139] G1: Energy Removable Structure

[0140] G2: Air Gap

[0141] GA: Gate Assembly

[0142] H1: Height

[0143] H2: Height

[0144] H3: Height

[0145] H4: Height

[0146] O1: Opening

[0147] O2: Opening

[0148] O3: inclined depression

[0149] O4: Opening

[0150] O5: Oblique depression

[0151] O6: Opening

[0152] R1: Row

[0153] R2: Row

[0154] S11: Steps

[0155] S13: Steps

[0156] S15: Steps

[0157] S17: Steps

[0158] UT: Upper part

[0159] W1: Width

[0160] W2: Width

[0161] W3: Width

[0162] W4: Width

[0163] W5: Width

[0164] W6: Width

[0165] W7: Width

[0166] W8: Width

[0167] X: First axis

[0168] Y: Second axis

[0169] Z: Axis

[0170] α: Angle of incidence

[0171] β: acute angle

[0172] γ: acute angle

[0173] ε: acute angle

[0174] δ: angle of incidence

[0175] ζ: acute angle

[0176] θ1: Angle of incidence

[0177] θ2: acute angle

[0178] θ3: Angle of incidence

[0179] θ4: Acute angle DETAILED DESCRIPTION

[0180] The following disclosure provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not be used to limit the scope of the embodiments of the present disclosure. For example, when the description mentions that a first component is formed "on" or "on" a second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which there are other components formed between the two without direct contact. In addition, the present disclosure may repeat reference symbols and / or marks in different embodiments. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the relationship between the different embodiments and / or structures discussed.

[0181] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used herein to facilitate describing the relationship between one element or component as shown in the drawings and another element or component. These spatially relative terms are intended to encompass different orientations of the element in use or operation other than the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative adjectives used therein may be interpreted similarly.

[0182] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0183] It should be understood that although the words first, second, etc. may be used herein to describe various elements, these elements should not be limited by these words. Unless otherwise specified, these words are only used to distinguish one element from another element. Therefore, for example, without departing from the teachings of the present disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0184] Unless the context indicates otherwise, words such as "same," "equal," "planar," or "coplanar" used herein in reference to an orientation, layout, position, shape, size, quantity, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to encompass nearly identical orientations, layouts, positions, shapes, sizes, quantities, or other measurements within an acceptable range of variation, such as due to manufacturing processes. The word "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variation, such as due to manufacturing processes.

[0185] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0186] It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of direction Z, and below or down corresponds to the arrow direction opposite to direction Z.

[0187] Figure 1 According to one embodiment of the present disclosure, a method 10 for manufacturing a semiconductor device 1A is shown in the form of a flow chart. Figure 2 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure. Figure 3 According to an embodiment of the present disclosure, Figure 2 Schematic diagram of the cross section drawn by line AA'.

[0188] Reference Figures 1 to 3 In step S11 , a substrate 101 may be provided, a first insulating layer 103 may be formed on the substrate 101 , a first hard mask layer 301 may be formed on the first insulating layer 103 , and a plurality of first hard mask openings 303 may be formed along the first hard mask layer 301 .

[0189] Reference Figure 2 and Figure 3 In some embodiments, substrate 101 may include a semiconductor-on-insulator structure, which includes, from bottom to top, a processing substrate, an insulator layer, and a topmost semiconductor layer. The processing substrate and the topmost semiconductor layer may include, for example, an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductors or Group II-VI compound semiconductors; or a combination of the foregoing. The insulator layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. The insulator layer may have a thickness between about 10 nm and 200 nm.

[0190] In some embodiments, substrate 101 may include a dielectric, an insulating layer, or a conductive component formed on the topmost semiconductor layer. The dielectric or insulating layer may include, for example, a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, tetraethyl orthosilicate oxide, phosphosilicate glass, borophosphosilicate glass, fluorinated silica glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or a combination of the foregoing. The conductive component may be a wire, a conductive via, a conductive contact, or the like. The dielectric or insulating layer may serve as an insulator that supports the conductive component and electrically isolates it.

[0191] In some embodiments, device elements (not shown) may be formed in the substrate 101. The device elements may be, for example, bipolar junction transistors, metal-oxide semiconductor field effect transistors, diodes, system large-scale integration, flash memory, dynamic random-access memories, static random-access memories, electrically erasable programmable read-only memories, image sensors, micro-electromechanical systems, active devices, or passive devices. The device elements may be electrically isolated from adjacent device elements by an insulating structure such as shallow trench isolation.

[0192] Reference Figure 2 and Figure 3In some embodiments, the first insulating layer 103 may include, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, flowable oxide, tonn silazen, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, plasma-enhanced tetra-ethyl orthosilicate, fluoride silicate glass, carbon-doped silicon oxide, organosilicate glass, low-k dielectric material, or a combination of the foregoing.

[0193] In some embodiments, the first insulating layer 103 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, polyimide, polybenzoxazole, phosphosilicate glass, undoped silicate glass, or fluorosilicate glass. The first insulating layer 103 may be referred to as a passivation layer.

[0194] In some embodiments, the first insulating layer 103 may include a bottom passivation layer (not shown for clarity) and a top passivation layer (not shown for clarity). The bottom passivation layer may be formed on the substrate 101. The top passivation layer may be formed on the bottom passivation layer. The bottom passivation layer may include, for example, silicon oxide or phosphosilicate glass. The top passivation layer may include, for example, silicon nitride, silicon oxynitride, or silicon nitride oxide. The bottom passivation layer may be used as a stress buffer between the top passivation layer and the substrate 101. The top passivation layer may be used as a high vapor barrier to prevent moisture from entering from above.

[0195] In some embodiments, the first insulating layer 103 may include a material different from the first hard mask layer 301. Specifically, the first insulating layer 103 may include a material having an etching selectivity to the first hard mask layer 301.

[0196] Reference Figure 2 and Figure 3In some embodiments, the first hard mask layer 301 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, similar materials, or combinations thereof. The first hard mask layer 301 may be fabricated using a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, low pressure chemical vapor deposition, or similar processes.

[0197] It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0198] Alternatively, in some embodiments, the first hard mask layer 301 may include, for example, a carbon film. The term "carbon film" is used herein to describe a material whose mass is primarily carbon, whose structure is primarily defined by carbon atoms, or whose physical and chemical properties are determined by its carbon content. The term "carbon film" is intended to exclude materials that simply contain mixtures or compounds of carbon, such as dielectric materials (such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon). These terms do include, for example, graphite, charcoal, and halogenated carbons.

[0199] In some embodiments, the carbon film may be deposited by a process comprising introducing into the process chamber a process gas mixture consisting of one or more hydrocarbon compounds having the formula C x H y , where x ranges from 2 to 4 and y ranges from 2 to 10. Hydrocarbons may be, for example, propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H 10 ), butylene (C4H8), butadiene (C4H6), or acetylene (C2H2), or a combination thereof. In some embodiments, partially or fully fluorinated derivatives of hydrocarbons may be used. Doped derivatives include boron-containing derivatives of hydrocarbons and fluorinated derivatives thereof.

[0200] In some embodiments, the carbon film may be deposited from the process gas mixture by maintaining the substrate temperature between about 100° C. and about 700° C., specifically, between about 350° C. and about 550° C. In some embodiments, the carbon film may be deposited from the process gas mixture by maintaining the chamber pressure between about 1 Torr and about 20 Torr. In some embodiments, the carbon film may be deposited from the process gas mixture by introducing a hydrocarbon gas, and any inert or reactive gas, at a flow rate between about 50 sccm and about 2000 sccm, respectively.

[0201] In some embodiments, the processing gas mixture may further include an inert gas, such as argon. However, other inert gases, such as nitrogen or other rare gases, such as helium, may also be used. Inert gases can be used to control the density and deposition rate of the carbon film. In addition, a variety of gases can be added to the processing gas mixture to change the properties of the carbon film. The gas can be a reactive gas, such as hydrogen, ammonia, a mixture of hydrogen and nitrogen, or a combination of the foregoing. The addition of hydrogen or ammonia can be used to control the hydrogen ratio of the carbon film to control layer properties, such as etching selectivity, chemical mechanical polishing resistance, and reflectivity. In some embodiments, a mixture of reactive gases and inert gases can be added to the processing gas mixture to deposit the carbon film.

[0202] The carbon film may include carbon and hydrogen atoms, which may be an adjustable carbon:hydrogen ratio ranging from about 10% hydrogen to about 60% hydrogen. Controlling the hydrogen ratio of the carbon film may adjust the corresponding etch selectivity and chemical mechanical polishing resistance. As the hydrogen content decreases, the etch resistance of the carbon film increases, thereby increasing its selectivity. The reduced removal rate of the carbon film may make the carbon film suitable as a mask layer when an etching process is performed to transfer a desired pattern to an underlying layer.

[0203] Alternatively, in some embodiments, the first hard mask layer 301 may include, for example, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. In some embodiments, the first hard mask layer 301 may be formed with the assistance of a plasma process, a UV curing process, a thermal annealing process, or a combination thereof. The substrate temperature for forming the first hard mask layer 301 may be between about 20° C. and about 1000° C. The process pressure for forming the first hard mask layer 301 may be between about 10 mTorr and about 760 Torr.

[0204] When the first hard mask layer 301 is formed with the aid of a plasma process, the plasma of the plasma process may be provided by RF power. In some embodiments, the RF power may be between about 2 W and about 5000 W at a single low frequency between about 100 kHz and about 1 MHz. In some embodiments, the RF power may be between about 30 W and about 1000 W at a single high frequency greater than about 13.6 MHz.

[0205] When the first hard mask layer 301 is formed with the assistance of a UV curing process, the UV curing may be provided by any UV source, such as mercury microwave arc lamps, pulsed xenon flashlamps, or high-efficiency UV light emitting diode arrays. The UV source may have a wavelength between about 170 nm and about 400 nm. The UV source may provide a photon energy between about 0.5 eV and about 10 eV; specifically, between about 1 eV and about 6 eV. The assistance of the UV curing process may remove hydrogen from the first hard mask layer 301. Since hydrogen may diffuse to other areas of the semiconductor device 1A and may reduce the reliability of the semiconductor device 1A, removing hydrogen with the assistance of the UV curing process may improve the reliability of the semiconductor device 1A. In addition, the UV curing process may increase the density of the first hard mask layer 301.

[0206] Reference Figure 2 and Figure 3 , a first hard mask opening 303 may be formed along the first hard mask layer 301. A portion of the first insulating layer 103 may be exposed through the first hard mask opening 303. In a top view angle, the first hard mask opening 303 may be configured in a grid dot pattern. The first hard mask openings 303 may be equidistantly arranged along the first axis X and the second axis Y. The first axis X and the second axis Y are perpendicular to each other. Specifically, a distance D1 between adjacent pairs of first hard mask openings 303 along the first axis X may be equal to a distance D2 between adjacent pairs of first hard mask openings 303 along the second axis Y. In a cross-sectional angle, a ratio of a width W1 of the first hard mask opening 303 to a height H1 of the first hard mask opening 303 may be between about 5:1 and about 1:15, between about 3:1 and about 1:13, between about 1:1 and about 1:11, or between about 5:1 and about 1:8.

[0207] Figure 4 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure. Figure 5 According to an embodiment of the present disclosure, Figure 4 Schematic diagram of the cross section drawn by line A-A'

[0208] Reference Figure 1 , Figure 4 ,and Figure 5 In step S13 , a first inclined etching process 401 may be performed to form a first inclined recess 305 along the first insulating layer 103 .

[0209] Reference Figure 4 and Figure 5 The first oblique etching process 401 may use the first hard mask layer 301 as a pattern guide to remove a portion of the first insulating layer 103 and simultaneously form a first oblique recess 305 along the first insulating layer 103. In the cross-sectional view, the first oblique recess 305 may be formed adjacent to the first side FS of the first hard mask layer 301.

[0210] In some embodiments, the incident angle α of the first oblique etching process 401 may be defined by the width W1 of the first hard mask opening 303 and the height H1 of the first hard mask opening 303 .

[0211] In some embodiments, the incident angle α of the first oblique etching process 401 may be between about 5 degrees and about 80 degrees. In some embodiments, the incident angle α of the first oblique etching process 401 may be between about 20 degrees and about 60 degrees. In some embodiments, the incident angle α of the first oblique etching process 401 may be between about 20 degrees and about 40 degrees.

[0212] In some embodiments, the first oblique etching process 401 may be an anisotropic etching process, such as a reactive ion etching process. The reactive ion etching process may include an etchant gas and a passivation gas, which may suppress the isotropic effect to limit the removal of material in the horizontal direction. The etchant gas may include chlorine and boron trichloride. The passivation gas may include fluoroform or other suitable halogenated carbons. In some embodiments, the first hard mask layer 301 formed of a carbon film may be used as a halogenated carbon source for the passivation gas of the reactive ion etching process.

[0213] In some embodiments, the etching rate of the first insulating layer 103 of the first oblique etching process 401 may be faster than the etching rate of the first hard mask layer 301 of the first oblique etching process 401. For example, during the first oblique etching process 401, the etching rate ratio of the first insulating layer 103 to the first hard mask layer 301 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0214] Reference Figure 4 and Figure 5, the width W2 of the first inclined recess 305 may be less than the width W1 of the first hard mask opening 303. The acute angle β between the bottom surface 305BS of the first inclined recess 305 and the sidewall 305SW of the first inclined recess 305 may be between about 10 degrees and about 85 degrees, between about 20 degrees and about 80 degrees, between about 45 degrees and about 80 degrees, between about 60 degrees and about 80 degrees, or between about 70 degrees and about 80 degrees. In some embodiments, the first inclined recess 305 may extend in the first direction E1. The first direction E1 may be inclined relative to the axis Z and the first axis X.

[0215] Figure 6 A schematic top view of a middle semiconductor element is shown according to an embodiment of the present disclosure. Figures 7 to 9 According to an embodiment of the present disclosure, Figure 6 For the sake of clarity, some components are not shown. Figure 6 middle.

[0216] Reference Figure 1 , Figure 6 ,and Figure 7 In step S15 , the first hard mask layer 301 may be removed.

[0217] Reference Figure 6 and Figure 7 , the first hard mask layer 301 may be removed by a hard mask etching process. The hard mask etching process may be an anisotropic dry etching process or a wet etching process. In some embodiments, an etching rate of the first hard mask layer 301 of the hard mask etching process may be faster than an etching rate of the first insulating layer 103 of the hard mask etching process. For example, during the hard mask etching process, an etching rate ratio of the first hard mask layer 301 to the first insulating layer 103 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0218] Reference Figure 6 , in a top view, the first inclined recesses 305 may be configured in a grid dot pattern. The first inclined recesses 305 may be set equidistantly along the first axis X and the second axis Y. Specifically, a distance D3 between adjacent pairs of first inclined recesses 305 along the first axis X may be equal to a distance D4 between adjacent pairs of first inclined recesses 305 along the second axis Y. A portion of the substrate 101 may be exposed through the first inclined recesses 305.

[0219] In some embodiments, after removing the first hard mask layer 301, a cleaning process and a passivation process may be performed on the first inclined recess 305. The cleaning process may remove oxide from the top surface of the topmost conductive component in the substrate 101 without damaging the topmost conductive component in the substrate 101, the oxide being oxide oxidized from oxygen in the air. The cleaning process may include applying a mixture of hydrogen and argon as a remote plasma source to the first inclined recess 305. The temperature of the cleaning process may be between about 250° C. and about 350° C. The process pressure of the cleaning process may be between about 1 Torr and about 10 Torr. Bias energy may be applied to the equipment performing the cleaning process. The bias energy may be between about 0 W and 200 W.

[0220] The passivation process may include soaking the intermediate semiconductor element after the cleaning process with a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or the like at a process temperature between about 200° C. and about 400° C. Ultraviolet radiation may be used to promote the passivation process. The passivation process may passivate the sidewalls of the first insulating layer 103 exposed by the first inclined recess 305 by sealing the surface holes of the first insulating layer 103. Undesirable sidewall growth that may affect the electrical characteristics of the semiconductor element 1A may be reduced by the passivation process. As a result, the performance and reliability of the semiconductor element 1A may be improved.

[0221] Reference Figure 1 , Figure 8 ,and Fig. 9 In step S17 , a first inclined conductive layer 201 may be formed in the first inclined recess 305 , and a top conductive layer 203 covering the first inclined conductive layer 201 may be formed.

[0222] Reference Figure 8 , the first inclined conductive layer 201 may be formed to completely fill the first inclined recess 305 and cover the top surface of the first insulating layer 103. In some embodiments, the first inclined conductive layer 201 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The fabrication techniques of the first inclined conductive layer 201 may include deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or sputtering. A planarization process such as chemical mechanical polishing may be performed until the top surface of the first insulating layer 103 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0223] Reference Figure 8, in the cross-sectional angle, the shape of the first inclined conductive layer 201 may be defined by the first inclined recess 305. That is, the acute angle γ between the bottom surface 201BS of the first inclined conductive layer 201 and the sidewall 201SW of the first inclined conductive layer 201 may be between about 10 degrees and about 85 degrees, between about 20 degrees and about 80 degrees, between about 45 degrees and about 80 degrees, between about 60 degrees and about 80 degrees, or between about 70 degrees and about 80 degrees. In some embodiments, the first inclined conductive layer 201 may extend in the first direction E1.

[0224] Reference Fig. 9 , a second insulating layer 105 may be formed on the first insulating layer 103. The second insulating layer 105 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, a low-k dielectric material, the like, or a combination thereof. The low-k dielectric material may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant of less than 2.0. The fabrication technique of the second insulating layer 105 may include a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating.

[0225] Reference Fig. 9 , the top conductive layer 203 may be formed in the second insulating layer 105 and cover the top surface 201TS of the first inclined conductive layer 201. In some embodiments, the top conductive layer 203 may include, for example, copper, aluminum, titanium, tungsten, the like, or a combination thereof. The manufacturing technology of the top conductive layer 203 may include a damascene process. The first inclined conductive layer 201 may be referred to as a conductive via of the semiconductor device 1A, and the top conductive layer 203 may be referred to as a conductive wire of the semiconductor device 1A.

[0226] Fig.10 and Fig.11 According to another embodiment of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0227] Reference Fig.10 For the preparation of the semiconductor element 1B, a method similar to Figures 2 to 7The steps shown in the figure are used to prepare an intermediate semiconductor element. The first conductive material 307 layer can completely fill the first inclined recess 305 and cover the top surface of the first insulating layer 103. The first conductive material 307 can be aluminum, copper, aluminum-copper alloy, aluminum alloy, or copper alloy. The manufacturing technology of the first conductive material 307 layer can include a deposition process such as physical vapor deposition, chemical vapor deposition, or sputtering. A planarization process such as chemical mechanical polishing can be performed to provide a substantially flat surface for subsequent process steps. The first conductive material 307 layer filled in the first inclined recess 305 can be referred to as a conductive via of the semiconductor element 1B.

[0228] Reference Fig.11 A lithography process may be performed to define a desired pattern of the first conductive material 307 layer. An etching process may then be performed to remove a portion of the first conductive material 307 layer and simultaneously form a top conductive layer 203 having a desired pattern. The top conductive layer 203 may be referred to as a pad layer of the semiconductor device 1B.

[0229] Fig.12 and Fig.13 According to another embodiment of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0230] Reference Fig.12 For the preparation of semiconductor element 1C, a method similar to Figures 2 to 7 3. The steps shown in FIG. 3 are used to prepare an intermediate semiconductor device. The barrier layer 207 may be conformally formed in the first inclined recess 305. The barrier layer 207 may include, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof. The barrier layer 207 may be fabricated using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or sputtering. In some embodiments, the barrier layer 207 may have a thickness between about 10 angstroms and about 15 angstroms. In some embodiments, the barrier layer 207 may have a thickness between about 11 angstroms and about 13 angstroms.

[0231] Reference Fig.13 , which can be used similar to Fig.10 and Fig.11 The top conductive layer 203 is formed on the barrier layer 207 by the steps shown. The barrier layer 207 can be used as an adhesion layer between the first sloped conductive layer 201 and the topmost conductive line in the substrate 101. The barrier layer 207 can also prevent metal ions of the first sloped conductive layer 201 or the top conductive layer 203 from diffusing into the first insulating layer 103 or the substrate 101.

[0232] Fig.14 According to another embodiment of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0233] Reference Fig.14 For the preparation of semiconductor device 1D, a method similar to Figures 2 to 7 The steps shown in FIG. 1 are used to prepare an intermediate semiconductor device. The top conductive layer 203 may completely fill the first inclined recess 305 and cover a portion of the top surface of the first insulating layer 103. The top conductive layer 203 may include, for example, a material including tin, silver, copper, gold, an alloy, or a combination thereof. The top conductive layer 203 may be referred to as a solder unit of the semiconductor device 1D.

[0234] During a wiring process, a process of forming a solder unit, or a packaging process, stress may be applied to the semiconductor device, and this stress may cause delamination of the first insulating layer 103. In order to reduce the influence of the stress in the aforementioned process, the first inclined recess 305 can be used as a buffer space to reduce the stress of the aforementioned process, reduce the warping of the semiconductor device 1D, and prevent the layer below the first insulating layer 103 from being delaminated.

[0235] Fig.15 According to another embodiment of the present disclosure, Figure 6 Schematic diagram of the cross section drawn by line AA'.

[0236] Reference Fig.15 For the preparation of the semiconductor element 1E, a method similar to Figures 2 to 7 The steps shown in the figure are used to prepare an intermediate semiconductor element. The under bump metallization layer 209 can be conformally formed in the first inclined recess 305. The under bump metallization layer 209 can be a single-layer structure or a multi-layer stacked structure. For example, the under bump metallization layer 209 may include a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence. The first conductive layer can be used as an adhesive layer to stably attach the top conductive layer 203 to the substrate 101 and the first insulating layer 103. For example, the first conductive layer may include at least one of titanium, titanium-tungsten, chromium, and aluminum. The second conductive layer can be used as a barrier layer to prevent the conductive material contained in the under bump metallization layer 209 from diffusing into the substrate 101 or the first insulating layer 103. The second conductive layer may include at least one of copper, nickel, chromium copper, and nickel-vanadium. The third conductive layer can be used to form a sublayer of the top conductive layer 203 or a wetting layer for improving the wetting characteristics of the top conductive layer 203. The third conductive layer may include at least one of nickel, copper, and aluminum. Can use similar Fig.14 The top conductive layer 203 is formed by the steps shown.

[0237] Fig.16 and Fig.17 A schematic top view of a plurality of intermediate semiconductor elements is shown according to another embodiment of the present disclosure.

[0238] Reference Fig.16 For the preparation of semiconductor element 1F, a method similar to Figures 2 to 5 1. An intermediate semiconductor element is prepared by the steps shown. The first hard mask openings 303 may be arranged in a diagonal dot pattern. The first hard mask openings 303 may be classified into two groups. The first group of first hard mask openings 303 may be arranged along the columns R1 of the first group. The second group of first hard mask openings 303 may be arranged along the columns R2 of the second group. The columns R1 of the first group and the columns R2 of the second group may be parallel to the first axis X. The columns R1 of the first group and the columns R2 of the second group may be arranged alternately. With respect to the second axis Y, the first hard mask openings 303 arranged along the columns R2 of the second group may be offset from the first hard mask openings 303 arranged along the columns R1 of the first group. Since the first inclined recesses 305 may be formed using the first hard mask layer 301 and the first hard mask openings 303 as pattern guides, the configuration of the first inclined recesses 305 may be similar to the configuration of the first hard mask openings 303.

[0239] Reference Fig.17 , can be Fig.16 The intermediate semiconductor element shown is similar to Figures 6 to 8 Steps shown. Since the configuration of the first inclined conductive layer 201 can be defined by the configuration of the first inclined recess 305, that is, the first inclined conductive layer 201 can also be configured as a diagonal dot pattern. Specifically, the first inclined conductive layer 201 can also be classified into two groups. The first group of first inclined conductive layers 201 can be arranged along the column R1 of the first group. The second group of first inclined conductive layers 201 can be arranged along the column R2 of the second group. The columns R1 of the first group and the columns R2 of the second group can be parallel to the first axis X. The columns R1 of the first group and the columns R2 of the second group can be arranged alternately. Relative to the second axis Y, the first inclined conductive layer 201 arranged along the column R2 of the second group can be offset from the first inclined conductive layer 201 arranged along the column R1 of the first group.

[0240] The first inclined conductive layers 201 configured in a diagonal dot pattern may maximize the distance between any two adjacent first inclined conductive layers 201. Therefore, parasitic capacitance between the first inclined conductive layers 201 may be minimized.

[0241] Fig.18 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig.19 According to another embodiment of the present disclosure, Fig.18 Schematic diagram of the cross section drawn by line AA'.

[0242] Reference Fig.18 and Fig.19 For the preparation of semiconductor device 1G, a method similar to Figures 2 to 5In the top view, the first hard mask opening 303 can be configured as a diagonal dot pattern, and the first inclined recess 305 can be configured as a pattern similar to the first hard mask opening 303. In the cross-sectional view, the first inclined recess 305 can have a pattern similar to Figure 5 The acute angle β is shown, and the first inclined recess 305 may extend in the first direction E1. After forming the first inclined recess 305, the first hard mask layer 301 may be removed.

[0243] Fig. 20 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig.21 According to another embodiment of the present disclosure, Fig. 20 Schematic diagram of the cross section drawn by line AA'.

[0244] Reference Fig. 20 and Fig.21 , which can be used similar to Figure 2 and Figure 3 The step of forming the first hard mask layer 301 as shown forms a second hard mask layer 309 on the first insulating layer 103. The second hard mask layer 309 may include the same material as the first hard mask layer 301, but is not limited thereto. A plurality of second hard mask openings 311 may be formed along the second hard mask layer 309. In a top view, the second hard mask openings 311 may be arranged in a diagonal dot pattern. The second hard mask openings 311 may be arranged vertically or horizontally between adjacent pairs of first inclined recesses 305. In other words, the first inclined recesses 305 and the second hard mask openings 311 may be arranged alternately along the first axis X and the second axis Y. That is, the first inclined recesses 305 and the second hard mask openings 311 may be staggered. In cross-sectional view, a ratio of a width W3 of the second hard mask opening 311 to a height H2 of the second hard mask opening 311 may be between about 5:1 and about 1:15, between about 3:1 and about 1:13, between about 1:1 and about 1:11, or between about 5:1 and about 1:8.

[0245] Reference Fig. 20 and Fig.21 , the second oblique etching process 403 may use the second hard mask layer 309 as a pattern guide to remove a portion of the first insulating layer 103, and simultaneously form a second oblique recess 313 along the first insulating layer 103. In some embodiments, the incident angle δ of the second oblique etching process 403 may have the same value as the incident angle δ of the first oblique etching process 401, but the incident direction of the second oblique etching process 403 may be opposite to the incident direction of the first oblique etching process 401. In other words, the incident angle δ of the second oblique etching process 403 may be opposite to the incident angle δ of the first oblique etching process 401.

[0246] In some embodiments, the second bevel etching process 403 may be an anisotropic etching process, such as a reactive ion etching process. The process parameters of the second bevel etching process 403 may be the same as those of the first bevel etching process 401, but only the incident angle is different.

[0247] In some embodiments, the incident angle δ of the second oblique etching process 403 may be between about -5 degrees and about -80 degrees, between about -20 degrees and about -60 degrees, or between about -20 degrees and about -40 degrees.

[0248] In some embodiments, the incident angle δ of the second oblique etching process 403 may be defined by the width W3 of the second hard mask opening 311 and the height H2 of the second hard mask opening 311 .

[0249] In some embodiments, the etching rate of the first insulating layer 103 of the second oblique etching process 403 may be faster than the etching rate of the second hard mask layer 309 of the second oblique etching process 403. For example, during the second oblique etching process 403, the etching rate ratio of the first insulating layer 103 to the second hard mask layer 309 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0250] Reference Fig. 20 and Fig.21 , the width W4 of the second inclined recess 313 may be less than the width W3 of the second hard mask opening 311. In some embodiments, the acute angle ε between the bottom surface 313BS of the second inclined recess 313 and the sidewall 313SW of the second inclined recess 313 may be different from or opposite to the acute angle β between the bottom surface 305BS of the first inclined recess 305 and the sidewall 305SW of the first inclined recess 305. In some embodiments, the acute angle ε between the bottom surface 313BS of the second inclined recess 313 and the sidewall 313SW of the second inclined recess 313 may be between about -10 degrees and about -85 degrees, between about -20 degrees and about -80 degrees, between about -45 degrees and about -80 degrees, between about -60 degrees and about -80 degrees, or between about -70 degrees and about -80 degrees.

[0251] In some embodiments, the second inclined recess 313 may extend in a direction different from the first direction E1. In some embodiments, the second inclined recess 313 may extend in a second direction E2. The second direction E2 may be inclined relative to the axis Z and the first axis X. The second direction E2 may be opposite to the first direction E1 relative to the axis Z.

[0252] Fig. 22A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig.23 According to another embodiment of the present disclosure, Fig. 22 Schematic diagram of the cross section drawn by line AA'.

[0253] Reference Fig. 22 and Fig.23 , similar to Figure 6 , Figure 7 ,and Fig.14 The steps shown are to remove the second hard mask layer 309 and form the first inclined conductive layer 201, the second inclined conductive layer 205, and the top conductive layer 203. The first inclined conductive layer 201 may be formed in the first inclined recess 305 and may have the same Figure 8 The same acute angle γ and extension direction are shown.

[0254] The second inclined conductive layer 205 may be formed in the second inclined recess 313. In the cross-sectional angle, the shape of the second inclined conductive layer 205 may be defined by the second inclined recess 313. That is, in some embodiments, the acute angle z between the bottom surface 205BS of the second inclined conductive layer 205 and the sidewall 205SW of the second inclined conductive layer 205 may be between about -10 degrees and about -85 degrees, between about -20 degrees and about -80 degrees, between about -45 degrees and about -80 degrees, between about -60 degrees and about -80 degrees, or between about -70 degrees and about -80 degrees. In some embodiments, one of the first inclined conductive layers 201 and the adjacent one of the second inclined conductive layers 205 may extend in different directions. In some embodiments, the second inclined conductive layer 205 may extend in the second direction E2.

[0255] The top conductive layer 203 may be formed on the first insulating layer 103 and cover the first inclined conductive layer 201 and the second inclined conductive layer 205 .

[0256] Fig.24 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig.25 According to another embodiment of the present disclosure, Fig.24 Schematic diagram of the cross section drawn by line AA'.

[0257] Reference Fig.24 and Fig.25 For the preparation of semiconductor element 1H, a method similar to Figures 2 to 5 The steps shown in the figure are used to prepare an intermediate semiconductor device. In the top view, the first hard mask opening 303 can be arranged along the first group of columns R1. The first group of columns R1 can be parallel to the first axis X. The configuration of the first inclined recess 305 can be similar to the configuration of the first hard mask opening 303. In the cross-sectional view, the first inclined recess 305 can have a similar Figure 5 Similar acute angles and extension directions are shown. After forming the first inclined recess 305, the first hard mask layer 301 may be removed.

[0258] Fig.26 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig. 27 According to another embodiment of the present disclosure, Fig.26 Schematic diagram of the cross section drawn by line BB'.

[0259] Reference Fig.26 and Fig. 27 , similar to Fig. 20 and Fig.21 The steps shown. In a top view, the second hard mask openings 311 can be arranged along the second group of columns R2. The second group of columns R2 can be parallel to the first axis X. The first group of columns R1 and the second group of columns R2 can be arranged alternately; in other words, the first group of columns R1 and the second group of columns R2 can be staggered. The configuration of the second inclined recess 313 can be similar to the configuration of the second hard mask opening 311. In a cross-sectional view, the second inclined recess 313 can have a similar Fig.21 Similar acute angles and extension directions are shown.

[0260] Fig.28 A schematic top view of a middle semiconductor element is shown according to another embodiment of the present disclosure. Fig.29 According to another embodiment of the present disclosure, Fig.28 Schematic diagram of the cross section drawn by line C-C'.

[0261] Reference Fig.28 and Fig.29 , similar to Fig. 22 and Fig.23 The steps shown are to remove the second hard mask layer 309 and form the first inclined conductive layer 201, the second inclined conductive layer 205, and the top conductive layer 203. In the cross-sectional view, the first inclined conductive layer 201 can be formed in the first inclined recess 305 and can have the same Fig.23 The second inclined conductive layer 205 may be formed in the second inclined recess 313 and may have the same acute angle γ and extension direction as shown. Fig.23 The same acute angle z and extension direction are shown. In the top view, the first inclined conductive layer 201 can be disposed along the first group of columns R1, and the second inclined conductive layer 205 can be disposed along the second group of columns R2. Since the first inclined etching process 401 and the second inclined etching process 403 have different incident directions, the second inclined conductive layer 205 can be offset from the first inclined conductive layer 201 relative to the second axis Y.

[0262] The top conductive layer 203 may be formed on the first insulating layer 103 and cover the first inclined conductive layer 201 and the second inclined conductive layer 205 .

[0263] In some embodiments, the semiconductor devices 1A to 1H described above may be applied to other semiconductor devices, such as the semiconductor devices 2A and 2H shown in FIG. Fig.49 The semiconductor element 2B is shown.

[0264] Reference Figures 30 to 39A and Fig.39B . Figures 30 to 38 Schematic diagram showing an intermediate semiconductor element 2A according to some embodiments of the present disclosure. Fig.39A Schematic diagram showing a semiconductor device 2A according to some embodiments of the present disclosure. Fig.39B Schematic diagram of a semiconductor device 2A is shown according to another embodiment of the present disclosure.

[0265] The semiconductor element 2A includes a first semiconductor die 500 and a second semiconductor die 600 bonded to the first semiconductor die. In some embodiments, the configurations of the first semiconductor die 500 and the second semiconductor die 600 are substantially mirror-symmetrical. In addition, the preparation processes of the first semiconductor die 500 and the second semiconductor die 600 are similar. For the sake of brevity, only the first semiconductor die 500 is described below.

[0266] exist Fig.30 In the embodiment, a dielectric layer 503 is disposed on a semiconductor substrate 501, and a metal layer 519 is disposed in the dielectric layer 503. The metal layer 519 is separated from the dielectric layer 503 by a barrier layer 517. The dielectric layer 503, the barrier layer 517, and the metal layer 519 are coplanar.

[0267] exist Fig.31 In the embodiment of the present invention, a dielectric layer 507 is formed on the dielectric layer 503, the barrier layer 517, and the metal layer 519. Then, the dielectric layer 507 is etched by using a patterned mask (not shown) to form a plurality of openings O1. The openings O1 expose a portion of the top surface of the metal layer 519. The manufacturing technology of the openings O1 may include a wet etching process, a dry etching process, or a combination of the foregoing. After the openings O1 are formed, the patterned mask is removed.

[0268] exist Fig.32In the embodiment of the present invention, a conductive polymer material 511 is filled into the opening O1. In some embodiments, the conductive polymer material 511 includes graphene or a conjugated polymer, such as poly(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In some embodiments, the manufacturing technology of the conductive polymer material 511 may include a CVD process, a PVD process, an ALD process, a spin coating process, or another applicable process. After the conductive polymer material 511 is filled into the opening O1, an etching process and / or a planarization process is performed to remove excess conductive polymer material 511 on the top surface of the dielectric layer 507. Therefore, the top surface of the dielectric layer 507 and the top surface of the conductive polymer material 511 are coplanar with each other.

[0269] exist Fig.33 In the embodiment, an energy removable material 553 is formed in the dielectric layer 507. The dielectric layer 507 is etched using a patterned mask (not shown) to form a plurality of openings, wherein the openings are not disposed between the conductive polymer materials 511. After the openings are formed, the energy removable material 553 is filled into the openings. Next, the patterned mask is removed. Fig.33 As shown, each of the energy removable materials 553 is in contact with the metal layer 519 , and at least one of the energy removable materials 553 is further in contact with the barrier layer 517 and the dielectric layer 503 .

[0270] In some embodiments, the energy removable material 553 includes a thermally decomposable material. In some other embodiments, the energy removable material 553 includes a photon decomposable material, an electron beam decomposable material, or another applicable energy decomposable material. In some embodiments, the energy removable material 553 includes a substrate and a decomposable porogen material that is substantially removed upon exposure to an energy source (e.g., heat). In some embodiments, the substrate includes hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO2), and the decomposable porogen material includes a porogen organic compound that can provide porosity to the space initially occupied by the energy removable material 553 during subsequent processing.

[0271] exist Fig.34 In, display Fig.33The area enclosed by the virtual frame F1 shown in FIG. In the virtual frame F1, a hard mask layer 513 is formed on the dielectric layer 507. The hard mask layer 513 is patterned to have a plurality of openings O2 disposed between the conductive polymer materials 511, and the openings O2 expose a portion of the top surface of the dielectric layer 507.

[0272] It should be noted that the dielectric layer 507 outside the area surrounded by the dummy frame F1 is completely covered by the hard mask layer 513. In other words, no opening O2 is formed outside the area surrounded by the dummy frame F1.

[0273] exist Fig.35 In the process, a tilted etching process 601 is performed to form a tilted recess O3 (eg Fig.36 ) in the dielectric layer 507. The oblique etching process 601 may use the hard mask layer 513 as a pattern guide to remove a portion of the dielectric layer 507 and simultaneously form an oblique recess O3 along the dielectric layer 507. The incident angle θ1 of the oblique etching process 601 may be defined by the width W5 of the opening O2 and the height H3 of the opening O2.

[0274] In some embodiments, the incident angle θ1 of the oblique etching process 601 may be between about 5 degrees and about 80 degrees. In some embodiments, the incident angle θ1 may be between about 20 degrees and about 60 degrees. In some embodiments, the incident angle θ1 may be between about 20 degrees and about 40 degrees.

[0275] In some embodiments, the tilted etching process 601 can be an anisotropic etching process, such as a reactive ion etching process. The reactive ion etching process may include an etchant gas and a passivation gas, which may suppress the isotropic effect to limit the removal of material in the horizontal direction. The etchant gas may include chlorine and boron trichloride. The passivation gas may include fluoroform or other suitable halogenated carbons. In some embodiments, the hard mask layer 513 formed of a carbon film may be used as a halogenated carbon source for the passivation gas of the reactive ion etching process.

[0276] In some embodiments, the etching rate of the dielectric layer 507 of the oblique etching process 601 may be faster than the etching rate of the hard mask layer 513 of the oblique etching process 601. For example, during the oblique etching process 601, the etching rate ratio of the dielectric layer 507 to the hard mask layer 513 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0277] The width W6 of the inclined recess O3 is less than the width W5 of the opening O2. The acute angle θ2 between the bottom surface 523 and the sidewall of the inclined recess O3 may be between about 10 degrees and about 85 degrees, between about 20 degrees and about 80 degrees, between about 45 degrees and about 80 degrees, between about 60 degrees and about 80 degrees, or between about 70 degrees and about 80 degrees. In some embodiments, the bottom surface 523 is also the top surface of the metal layer 519.

[0278] exist Fig.36 , the hard mask layer 513 is removed by a hard mask etching process. The hard mask etching process may be an anisotropic dry etching process or a wet etching process. In some embodiments, the etching rate of the hard mask layer 513 of the hard mask etching process may be faster than the etching rate of the dielectric layer 507 of the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the hard mask layer 513 to the dielectric layer 507 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0279] In some embodiments, after removing the hard mask layer 513, a cleaning process and a passivation process may be performed on the inclined recess O3. The cleaning process may remove oxides. The cleaning process may include applying a mixture of hydrogen and argon as a remote plasma source to the inclined recess O3. The process temperature of the cleaning process may be between about 250° C. and about 350° C. The process pressure of the cleaning process may be between about 1 Torr and about 10 Torr. Bias energy may be applied to the equipment performing the cleaning process. The bias energy may be between about 0 W and 200 W.

[0280] The passivation process may include soaking the intermediate semiconductor element 2A after the cleaning process with a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or the like at a process temperature between about 200° C. and about 400° C. Ultraviolet radiation may be used to promote the passivation process. The passivation process may passivate the sidewalls of the dielectric layer 507 exposed by the inclined recess O3 by sealing the surface holes of the dielectric layer 507. Undesirable sidewall growth that may affect the electrical characteristics of the semiconductor element 2A may be reduced by the passivation process. As a result, the performance and reliability of the semiconductor element 2A may be improved.

[0281] exist Fig.37 In the embodiment of the present invention, a conductive layer 515 is formed to fill the inclined recess O3. The conductive layer 515 is formed along the direction E3 (eg Fig.35) as shown. In some embodiments, the conductive layer 515 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The conductive layer 515 may be fabricated using deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or sputtering. A planarization process such as chemical mechanical polishing may be performed until the top surface of the dielectric layer 507 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0282] exist Fig.38 In the embodiment of the present invention, a top conductive layer 521 is formed on the conductive layer 515. More specifically, the conductive layer 515 is etched, and the dielectric layer 507 in the conductive polymer material 511 is etched. The top surfaces of the etched conductive layer 515 and the etched dielectric layer 507 are coplanar with each other. Then, the top conductive layer 521 is formed on the etched conductive layer 515 and the etched dielectric layer 507. The manufacturing technology of the top conductive layer 521 may include a damascene process. In some embodiments, a planarization process may be performed to make the top surface of the top conductive layer 521, the top surface of the conductive polymer material 511, and the top surface of the dielectric layer 507 flush.

[0283] exist Fig.39A , the first semiconductor die 500 is bonded to the second semiconductor die 600. Similar to the first semiconductor die 500, the second semiconductor die 600 includes a dielectric layer 603, a barrier layer 617, a metal layer 619, a dielectric layer 607, a plurality of energy removable materials 653, a plurality of conductive polymer materials 611, a conductive layer 615, and a top conductive layer 621 disposed on a semiconductor substrate. For the sake of brevity, the configuration details of the second semiconductor die 600 are omitted.

[0284] The conductive polymer material 511 and the top conductive layer 521 of the first semiconductor die 500 are bonded to the conductive polymer material 611 and the top conductive layer 621 of the second semiconductor die 600, respectively. The energy removable material 553 is bonded to the energy removable material 653. In some embodiments, the sizes of the conductive polymer material 511, the top conductive layer 521, and the energy removable material 553 are the same as the sizes of the conductive polymer material 611, the top conductive layer 621, and the energy removable material 653. In some embodiments, the top conductive layer 521, the conductive layer 515, and the dielectric layer 507 are configured as conductive vias of the first semiconductor die 500, and the top conductive layer 621, the conductive layer 615, and the dielectric layer 607 are configured as conductive vias of the second semiconductor die 600. The conductive vias in the first semiconductor die 500 are configured to be electrically connected to the conductive vias in the second semiconductor die 600.

[0285] After the bonding process, the semiconductor device 2A is formed. In other embodiments, a heat treatment process may be performed to transform the energy removable materials 553 and 653 into an energy removable structure G1 surrounding the air gap G2, such as Fig.39B shown.

[0286] Reference Figures 40 to 49 . Figures 40 to 48 Schematic diagram showing an intermediate semiconductor element 2B according to some embodiments of the present disclosure. Fig.49 Schematic diagram showing a semiconductor device 2B according to some embodiments of the present disclosure.

[0287] The semiconductor device 2B includes a bottom portion BT and a higher portion UT. The bottom portion BT includes a first stacked structure 1S on a substrate 701, an intermediate insulating layer 723 on the first stacked structure 1S, and an inner spacer 709 disposed on opposite sides of the first stacked structure 1S. The higher portion UT includes a second stacked structure 2S located on the intermediate insulating layer 723. The bottom portion BT further includes a conductive plug 800 along the intermediate insulating layer 723 and electrically coupling the higher portion UT and the bottom portion BT. In some embodiments, the semiconductor device 2B uses the semiconductor device 1A as the conductive plug 800. In various embodiments, the semiconductor device 2B uses one of the semiconductor devices 1B to 1H as the conductive plug 800.

[0288] exist Fig.41 A bottom portion BT is provided. The bottom portion BT includes a first stacked structure 1S on a substrate 701, a first impurity region 713, a second impurity region 714, a buried bit line 703, a first insulating material 705, and a first insulating layer 721.

[0289] The buried bit line 703 is formed in the substrate 701. The first stacked structure 1S is formed on the substrate 701. The first stacked structure 1S does not overlap the buried bit line 703. The first impurity region 713 and the second impurity region 714 are formed on opposite sides of the first stacked structure 1S, and the second impurity region 714 is electrically connected to the buried bit line 703.

[0290] The first insulating material 705 is formed to cover the substrate 701 , the first impurity region 713 , the second impurity region 714 , and the first stacked structure 1S.

[0291] The first stacked structure 1S includes a plurality of gate assemblies GA, and each gate assembly GA includes a gate dielectric 715, a gate electrode 717, and a semiconductor layer 707. The first impurity region 713 and the second impurity region 714 are electrically connected to the semiconductor layer 707. More specifically, since both ends of each semiconductor layer 707 protrude from the inner spacer 709, the end of the semiconductor layer 707 can be electrically coupled to the first impurity region 713 and the second impurity region 714.

[0292] exist Fig.41 In the embodiment, a dielectric layer 725 penetrates the intermediate insulating layer 723 , the first insulating layer 721 , and the first insulating material 705 , and contacts the first impurity region 713 .

[0293] exist Fig.42 In, display Fig.41 The area enclosed by the virtual frame F2 shown in FIG. Fig.41 As shown in FIG. 1 , in the virtual frame F2 , the hard mask layer 727 is disposed on the bottom portion BT of the semiconductor device 2B. The hard mask layer 727 is patterned to have a plurality of openings O4 on the dielectric layer 725 . The openings O4 expose a portion of the dielectric layer 725 .

[0294] exist Fig.43 In the process, a tilted etching process 801 is performed to form a tilted recess O5 (eg Fig.44 The oblique etching process 801 may use the hard mask layer 727 as a pattern guide to remove a portion of the dielectric layer 725 and simultaneously form an oblique recess O5 along the dielectric layer 725. The incident angle θ3 of the oblique etching process 801 may be defined by the width W7 of the opening O4 and the height H4 of the opening O4.

[0295] In some embodiments, the incident angle θ3 of the oblique etching process 801 may be between about 5 degrees and about 80 degrees. In some embodiments, the incident angle θ3 may be between about 20 degrees and about 60 degrees. In some embodiments, the incident angle θ3 may be between about 20 degrees and about 40 degrees.

[0296] In some embodiments, the tilted etching process 801 can be an anisotropic etching process, such as a reactive ion etching process. The reactive ion etching process may include an etchant gas and a passivation gas, which may suppress the isotropic effect to limit the removal of material in the horizontal direction. The etchant gas may include chlorine and boron trichloride. The passivation gas may include fluoroform or other suitable halogenated carbons. In some embodiments, the hard mask layer 727 formed of a carbon film may be used as a halogenated carbon source for the passivation gas of the reactive ion etching process.

[0297] In some embodiments, the etching rate of the dielectric layer 725 of the oblique etching process 801 may be faster than the etching rate of the hard mask layer 727 of the oblique etching process 801. For example, during the oblique etching process 801, the etching rate ratio of the dielectric layer 725 to the hard mask layer 727 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0298] The width W8 of the inclined recess O5 is less than the width W7 of the opening O4. The acute angle θ4 between the bottom surface 753 and the sidewall of the inclined recess O5 may be between about 10 degrees and about 85 degrees, between about 20 degrees and about 80 degrees, between about 45 degrees and about 80 degrees, between about 60 degrees and about 80 degrees, or between about 70 degrees and about 80 degrees. In some embodiments, the bottom surface 753 is also the top surface of the first impurity region 713.

[0299] exist Fig.44 , the hard mask layer 727 is removed by a hard mask etching process. The hard mask etching process may be an anisotropic dry etching process or a wet etching process. In some embodiments, the etching rate of the hard mask layer 727 of the hard mask etching process may be faster than the etching rates of the dielectric layer 725 and the intermediate insulating layer 723 of the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the hard mask layer 727 to the dielectric layer 725 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0300] In some embodiments, after removing the hard mask layer 727, a cleaning process and a passivation process may be performed on the inclined recess O5. The cleaning process may remove oxides. The cleaning process may include applying a mixture of hydrogen and argon as a remote plasma source to the inclined recess O5. The process temperature of the cleaning process may be between about 250° C. and about 350° C. The process pressure of the cleaning process may be between about 1 Torr and about 10 Torr. Bias energy may be applied to the equipment performing the cleaning process. The bias energy may be between about 0 W and 200 W.

[0301] The passivation process may include soaking the intermediate semiconductor element 2B after the cleaning process with a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or the like at a process temperature between about 200° C. and about 400° C. Ultraviolet radiation may be used to promote the passivation process. The passivation process may passivate the sidewalls of the dielectric layer 725 exposed by the inclined recess O5 by sealing the surface holes of the dielectric layer 725. Undesirable sidewall growth that may affect the electrical characteristics of the semiconductor element 2B may be reduced by the passivation process. As a result, the performance and reliability of the semiconductor element 2B may be improved.

[0302] exist Fig.45 In the embodiment, a conductive layer 731 is formed to fill the inclined recess O5. The conductive layer 731 is formed along the direction E4 (eg Fig.43 ) as shown. In some embodiments, the conductive layer 731 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The conductive layer 731 may be fabricated using deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or sputtering. A planarization process such as chemical mechanical polishing may be performed until the top surface of the dielectric layer 725 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0303] exist Fig.46 In the embodiment, the dielectric layer 725 and the conductive layer 731 are etched to form an opening O6. In some embodiments, the bottom of the opening O6 is higher than the bottom surface of the intermediate insulating layer 723.

[0304] exist Fig.47 In the embodiment, a top conductive layer 729 is formed on the conductive layer 731. In some embodiments, the manufacturing technology of the top conductive layer 729 may include a damascene process. In some embodiments, a planarization process may be performed to make the top surface of the top conductive layer 729 flush with the top surface of the intermediate insulating layer 723.

[0305] exist Fig.48 In the embodiment, the upper portion UT of the semiconductor element 2B is disposed above the bottom portion BT of the semiconductor element 2B. The upper portion UT of the semiconductor element 2B includes a second stacked structure 2S, a third impurity region 909, and a fourth impurity region 911 (eg, Fig.49 shown).

[0306] The capacitor dielectric 903 and the capacitor electrode 907 together constitute a capacitor sub-unit CU. The second stacked structure 2S includes a plurality of capacitor sub-units CU disposed on opposite sides of the second stacked structure 2S, a plurality of semiconductor layers 901, and an internal spacer 905. Adjacent capacitor sub-units CU may be separated by corresponding semiconductor layers 901 interposed therebetween.

[0307] It should be noted that the bottommost semiconductor layer 901 is not in contact with the top conductive layer 729. In other words, the second stacked structure 2S is not in direct contact with the top conductive layer 729.

[0308] exist Fig.49 In the embodiment of the present invention, the third impurity region 909 and the fourth impurity region 911 are formed on opposite sides of the second stacked structure 2S. The third impurity region 909 may be electrically connected to the top conductive layer 729. Since both ends of each semiconductor layer 901 protrude from the inner spacer 905, the end of the semiconductor layer 901 can be electrically coupled to the third impurity region 909 and the fourth impurity region 911. In some embodiments, the third impurity region 909 and the fourth impurity region 911 may be operably associated with the semiconductor layers 901.

[0309] In some embodiments, the second stacked structure 2S can be used as a memory to store binary information such as "1" or "0". The second stacked structure 2S can be called a dielectric-all-around type capacitor. The semiconductor layers 901 can be used as one electrode of the capacitor structure. The capacitor electrode 907 can be used as the other electrode of the capacitor structure. The capacitor dielectric 903 can be used as an insulating layer to separate the two electrodes of the capacitor structure.

[0310] One aspect of the present disclosure provides a semiconductor element, comprising a first die and a second die. The first die comprises a first dielectric layer disposed on a first substrate, a second dielectric layer disposed on the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via comprises a plurality of conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the conductive layers extends along a direction. The direction forms an acute angle greater than 0 degrees with a top surface of the first die. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

[0311] Another aspect of the present disclosure provides a semiconductor element, including a bottom portion and a higher portion. The bottom portion includes a first stacked structure, a first impurity region, and a conductive plug. The higher portion is disposed above the bottom portion and includes a second stacked structure and a second impurity region. The first stacked structure includes a plurality of gate components coupled to the first impurity region, and the second stacked structure includes a plurality of capacitor subunits coupled to the second impurity region. The first impurity region is electrically coupled to the second impurity region through the conductive plug. The conductive plug includes: a plurality of conductive layers, a dielectric layer surrounding the conductive layers, and a top conductive layer electrically coupled to the conductive layers. Each of the conductive layers extends along a direction. The direction forms an acute angle with a top surface of the first impurity region.

[0312] Another aspect of the present disclosure provides a method for preparing a semiconductor element, comprising: forming a first grain, forming a second grain; and bonding the second grain to the first grain. Forming the first grain comprises: forming a first dielectric layer on a first substrate; forming a first metal layer in the first dielectric layer; forming a second dielectric layer on the first dielectric layer; and forming a first conductive via in the second dielectric layer. Forming the first conductive via in the second dielectric layer comprises: forming a third dielectric layer in the second dielectric layer; performing a first tilted etching process to form a plurality of first openings in the third dielectric layer; forming a plurality of first conductive layers in the first openings; and forming a first top conductive layer on the first conductive layers and the third dielectric layer. The first conductive layers extend along a first direction, wherein the first direction and a top surface of the first grain form a first acute angle greater than 0 degrees.

[0313] Due to the design of the semiconductor device disclosed in the present invention, the first inclined conductive layers 201 can provide more contact surfaces for the substrate 101. Therefore, the electrical characteristics of the semiconductor device 1A can be improved. That is, the performance of the semiconductor device 1A can be improved. In addition, the first hard mask layer 301 with a wider first hard mask opening 303 can be used to form a narrower first inclined recess 305. In other words, the requirements for the lithography process for forming the narrower first inclined recess 305 can be reduced. As a result, the yield of the semiconductor device 1A can be improved.

[0314] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and many of the above processes may be replaced by other processes and combinations thereof.

[0315] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a bottom portion including a first stacked structure, a first impurity region, and a conductive plug; as well as a higher portion, disposed above the bottom portion, comprising a second stacked structure and a second impurity region, wherein the first stack structure includes a plurality of gate components coupled to the first impurity region, and the second stack structure includes a plurality of capacitor subunits coupled to the second impurity region, wherein the first impurity region is electrically coupled to the second impurity region through the conductive plug, The conductive plug includes: multiple conductive layers; a dielectric layer surrounding the plurality of conductive layers; and a top conductive layer electrically coupled to the plurality of conductive layers, Each of the plurality of conductive layers extends along a direction, wherein the direction forms an acute angle with a top surface of the first impurity region.

2. The semiconductor device as claimed in claim 1, wherein the bottom portion further comprises: a substrate; as well as an intermediate insulating layer, The first stacking structure is disposed on the substrate, and the intermediate insulating layer is disposed on the first stacking structure. The conductive plug passes through the middle insulating layer to contact the first stacking structure.

3. The semiconductor device as claimed in claim 2, wherein the bottom portion further comprises: a buried bit line buried in the substrate; a third impurity region, wherein the first impurity region and the third impurity region are disposed on opposite sides of the first stacked structure; an insulating material disposed on the first stacked structure, the first impurity region, the third impurity region, and the substrate; and an insulating layer, disposed on the insulating material, The middle insulating layer contacts the insulating layer, the insulating material, and the first stacked structure. The semiconductor device as claimed in claim 3 , wherein the conductive plug further passes through the insulating layer and the insulating material. The semiconductor device as claimed in claim 1 , wherein the plurality of conductive layers are separated from each other by the dielectric layer. 6 . The semiconductor device as claimed in claim 5 , wherein the first impurity region is in contact with the plurality of conductive layers and the dielectric layer, and the second impurity region is in contact with the top conductive layer. 7 . The semiconductor device as claimed in claim 1 , wherein the higher portion further comprises a fourth impurity region, wherein the second impurity region and the fourth impurity region are disposed on opposite sides of the second stacked structure.

8. The semiconductor device of claim 1 , wherein each of the plurality of gate elements comprises: a gate electrode; a gate dielectric surrounding the gate electrode; and A first semiconductor layer.

9. The semiconductor device as claimed in claim 8, wherein the first stacked structure further comprises: a first internal spacer; and a second inner spacer, wherein the first inner spacer and the second inner spacer are disposed on opposite sides of the first stacked structure, Each of the first semiconductor layers of the plurality of gate elements protrudes from the first inner spacer, and a protruding portion of each of the first semiconductor layers is electrically coupled to the first impurity region.

10. The semiconductor device of claim 1, wherein each of the plurality of capacitor subunits comprises: a capacitor electrode; and a capacitor dielectric surrounding the capacitor electrode, The second stacking structure further comprises a plurality of second semiconductor layers, wherein the plurality of second semiconductor layers and the plurality of capacitor sub-units are inserted into each other.

11. The semiconductor device as claimed in claim 10, wherein the second stacked structure further comprises: a third internal spacer; and a fourth inner spacer, wherein the third inner spacer and the fourth inner spacer are disposed on opposite sides of the second stacked structure, Each of the plurality of second semiconductor layers protrudes from the third inner spacer, and a protruding portion of each of the plurality of second semiconductor layers is electrically coupled to the second impurity region.

12. A method for preparing a semiconductor element, comprising: Forming a first die includes: forming a first dielectric layer on a first substrate; forming a first metal layer in the first dielectric layer; forming a second dielectric layer on the first dielectric layer; and Forming a first conductive via in the second dielectric layer comprises: forming a third dielectric layer in the second dielectric layer; Performing a first tilted etching process to form a plurality of first openings in the third dielectric layer; forming a plurality of first conductive layers in the plurality of first openings; as well as forming a first top conductive layer on the plurality of first conductive layers and the third dielectric layer; forming a second grain; as well as bonding the second die to the first die, The plurality of first conductive layers extend along a first direction, wherein the first direction and a top surface of the first metal layer form a first acute angle greater than 0 degrees.

13. The method of claim 12, wherein forming the first grain further comprises: A barrier layer is formed in the first dielectric layer, wherein the first metal layer is separated from the first dielectric layer by the barrier layer.

14. The method of claim 12, wherein forming the first conductive via in the second dielectric layer further comprises: recessing the third dielectric layer and the plurality of conductive layers, The first top conductive layer formed on the third dielectric layer and the plurality of first conductive layers is recessed.

15. The method of claim 12, wherein forming the first conductive via in the second dielectric layer further comprises: Before forming the third dielectric layer, a first conductive polymer material and a second conductive polymer material are formed. The third dielectric layer is formed between the first conductive polymer material and the second conductive polymer material.

16. The method of claim 12, wherein forming the first grain further comprises: forming a plurality of energy removable materials in the second dielectric layer, wherein each of the plurality of energy removable materials contacts the first metal layer, At least one of the plurality of energy removable materials is further in contact with the first dielectric layer.

17. The method of claim 12, wherein forming the second grain comprises: forming a fourth dielectric layer on a second substrate; forming a second metal layer in the fourth dielectric layer; forming a fifth dielectric layer on the fourth dielectric layer; and forming a second conductive via in the fifth dielectric layer, After the second die is bonded to the first die, the first conductive via is aligned with the second conductive via.

18. The method of claim 17, wherein forming the second conductive via on the fifth dielectric layer comprises: forming a sixth dielectric layer in the fifth dielectric layer; Performing a second tilted etching process to form a plurality of second openings in the sixth dielectric layer; forming a plurality of second conductive layers in the plurality of second openings; and forming a second top conductive layer on the plurality of second conductive layers and the sixth dielectric layer, The plurality of second conductive layers extend along a second direction, wherein the second direction and a top surface of the second metal layer form a second acute angle greater than 0 degree. The preparation method as claimed in claim 18 , wherein the first acute angle is equal to the second acute angle.

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