Preparation method of hyperfine ultrahigh depth-to-width ratio vertical interconnection structure and hyperfine ultrahigh depth-to-width ratio vertical interconnection structure

Abstract

The invention discloses a preparation method of a hyperfine ultra-high aspect ratio vertical interconnection structure. The preparation method comprises the following steps: preparing a first dielectric layer and a first interconnection line layer in sequence based on a temporary wafer support plate; repeating the steps for multiple times to form a vertical interconnection structure of a plurality of dielectric layers and a plurality of layers of interconnection lines; thinning the dielectric layer at the topmost layer and removing the temporary wafer carrier plate at the bottom; and scribing the prepared vertical interconnection structure to form independent interconnection structures, and stacking the independent interconnection structures. According to the invention, the vertical interconnection line structure is obtained by splicing and rotating the horizontal interconnection line structure prepared in a plane, so that a hyperfine vertical interconnection channel with an ultra-high depth-to-width ratio can be realized, and the requirements on high-density vertical interconnection channels in 2.5 D and 3D advanced packaging integration processes are met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a preparation method and structure of an ultra-fine ultra-high aspect ratio vertical interconnection structure. Background Art

[0002] Advanced packaging technology is one of the effective solutions to improve the function and performance of integrated circuits under cost control in the "post-Moore era". According to the process route, advanced packaging technology can be mainly divided into 2D planar integration, 2.5D integration and 3D integration technology. Among them, 2.5D and 3D three-dimensional integration technology realizes vertical interconnection of chips in space through vertical interconnection structure, which can greatly reduce the interconnection length between core particles, increase data transmission bandwidth, and improve integration.

[0003] At present, the mainstream vertical interconnection structure preparation method in the industry is usually to etch through holes on the substrate material by wet or dry process, and then fill the through holes with metal conductive materials by electroplating process. The above method can effectively prepare high-density vertical interconnection structure. In the vertical interconnection process, the aspect ratio of the through hole is an important indicator. The mainstream vertical interconnection structure preparation process is subject to the influence of the through hole etching process, and it is difficult to make further breakthroughs in the preparation of fine diameter through holes.

[0004] In order to meet the needs of the "post-Moore era" 2.5D and 3D stereo integration technologies for ultra-fine and ultra-high-density vertical interconnection channels, it is urgent to develop a method for preparing a vertical interconnection structure with simple processes and advanced indicators. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure and its structure to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure, comprising the following steps:

[0007] sequentially preparing a first dielectric layer and a first interconnection line based on a temporary wafer carrier;

[0008] Repeating the above steps for multiple times forms a vertical interconnection structure of multiple dielectric layers and multiple interconnection lines;

[0009] Thinning the top dielectric layer and removing the bottom temporary wafer carrier;

[0010] The prepared vertical interconnect structure is diced to form individual interconnect structures, and the individual interconnect structures are stacked.

[0011] In one embodiment, the dielectric layer is prepared by ABF lamination and thinning processes, and the interconnection line is prepared by sputtering, photolithography, electroplating, degumming, and etching processes.

[0012] In one embodiment, the interconnection line is a line structure with controllable length and thickness; after subsequent splicing and rotation, the horizontal structure length of the interconnection line is converted into a vertical structure depth, and the horizontal structure thickness is converted into a vertical structure width.

[0013] The present invention also provides an ultra-fine ultra-high aspect ratio vertical interconnect structure, which is prepared based on the above preparation method.

[0014] The present invention provides a method for preparing an ultra-fine and ultra-high aspect ratio vertical interconnect structure and a structure thereof, which can solve the problems of difficult etching process in the preparation of traditional vertical interconnect structures and difficulty in further reducing the through-hole diameter, and can simplify the preparation process of the vertical interconnect structure and further improve the core process indicators, thereby meeting the needs of the "post-Moore era" 2.5D and 3D stereo integration technologies for ultra-fine and ultra-high density vertical interconnect channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1-Figure 8 A preparation method flow chart and structure diagram of an ultra-fine ultra-high aspect ratio vertical interconnect structure proposed by the present invention;

[0016] Fig. 9 Three-view diagram of an ultra-fine and ultra-high aspect ratio vertical interconnect structure proposed by the present invention. DETAILED DESCRIPTION

[0017] The following is a further detailed description of a method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure and its structure proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] The present invention provides a method for preparing an ultra-fine ultra-high aspect ratio vertical interconnection structure, the process steps comprising: (1) preparing a first dielectric layer, (2) preparing a first interconnection line, (3) preparing a second dielectric layer, (4) forming a multi-layer interconnection line through multiple cycles, (5) thinning the top dielectric layer, (6) removing a temporary carrier, (7) wafer dicing, and (8) three-dimensional stacking.

[0019] The detailed steps are as follows:

[0020] (1) Preparation of the first dielectric layer: Figure 1 As shown, a first dielectric layer 102 is prepared on a temporary wafer carrier 101 through ABF lamination and thinning processes;

[0021] (2) Preparation of first layer interconnection lines: On the first dielectric layer 102, the first layer interconnection lines 201 are prepared by sputtering, photolithography, electroplating, degumming, etching and other processes; Figure 2 As shown, the first layer interconnection line 201 is a line structure with controllable length and thickness. After subsequent splicing and rotation, the horizontal structure length is converted into the vertical structure depth, and the horizontal structure thickness is converted into the vertical structure width;

[0022] (3) Preparation of the second dielectric layer: Figure 3 As shown, on the first layer of interconnection lines 201, a second dielectric layer 103 is formed by ABF lamination;

[0023] (4) Multiple cycles to form multi-layer interconnects: Figure 4 As shown, by cycling the above two-step process, the preparation of multi-layer interconnection lines and dielectric layers can be completed;

[0024] (5) Thinning the top dielectric layer: Thinning the thickness of the last (i.e., top) dielectric layer, such as Figure 5 As shown;

[0025] (6) Temporary wafer carrier removal: Figure 6 As shown, the temporary wafer carrier 101 is removed by a debonding method;

[0026] (7) Wafer dicing: Figure 7 As shown, the prepared wafer array interconnection line structure is diced to form a separate interconnection structure;

[0027] (8) Three-dimensional stacking: Figure 8 As shown, the above-mentioned separate interconnect structures are stacked through a three-dimensional stacking process to further increase the number of interconnection channels.

[0028] The dielectric layer selected above can be an organic ABF film or other laminated dielectric materials; in the horizontal interconnect structure, the line length can be very long and the thickness can be very thin, so the corresponding depth of the vertical structure obtained by rotation can be very deep and the width can be very small, forming an arrayed ultra-fine and ultra-high aspect ratio vertical interconnect structure.

[0029] The three-view image of the final ultra-fine and ultra-high aspect ratio vertical interconnect structure is shown in the figure below: Fig. 9 shown.

[0030] It should be noted that the specific structure and arrangement order of the present application example are not limited to the above typical structure and can be modified according to specific circumstances. For example, the materials and sizes of the interconnection lines, dielectric layers, and temporary carriers are different, and the specific structure used is also different.

[0031] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure, characterized in that: The steps include: sequentially preparing a first dielectric layer and a first interconnection line based on a temporary wafer carrier; Repeating the above steps for multiple times forms a vertical interconnection structure of multiple dielectric layers and multiple interconnection lines; Thinning the top dielectric layer and removing the bottom temporary wafer carrier; The prepared vertical interconnect structure is diced to form individual interconnect structures, and the individual interconnect structures are stacked.

2. The method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure according to claim 1, characterized in that: The dielectric layer is prepared through ABF lamination and thinning processes, and the interconnection line is prepared through sputtering, photolithography, electroplating, degumming and etching processes.

3. The method for preparing an ultra-fine ultra-high aspect ratio vertical interconnect structure according to claim 1, characterized in that: The interconnection line is a line structure with controllable length and thickness; after subsequent splicing and rotation, the horizontal structure length of the interconnection line is converted into a vertical structure depth, and the horizontal structure thickness is converted into a vertical structure width.

4. An ultra-fine ultra-high aspect ratio vertical interconnect structure, characterized in that: It is prepared based on the preparation method according to any one of claims 1 to 3.

Images