Packaging structure, chip stacking structure, electronic equipment and packaging method

Abstract

The invention relates to a packaging structure, a chip stacking structure, electronic equipment and a packaging method, the packaging structure comprises a first chip and a second chip which are mutually stacked, and the first chip is internally provided with a first element and a shielding element; wherein the second chip and the active surface of the first chip are oppositely arranged, the shielding element is arranged between the first element and the second chip in the thickness direction of the packaging structure, and the shielding element is used for reducing signal interference of the second chip on the first element. According to the packaging structure disclosed by the invention, the first element and the shielding element are arranged in the first chip, and the shielding element is arranged between the first element and the second chip in the thickness direction of the packaging structure, so that the signal interference of the second chip on the first element can be reduced by utilizing the shielding element, and the signal quality of the first element is improved; and the signal quality of the packaging structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure, a chip stacking structure, an electronic device, and a packaging method. Background Art

[0002] Three-dimensional stacked chips can not only achieve high-density vertical interconnection between chips through hybrid bonding and other methods, improve the equivalent two-dimensional integration density of chips, but also integrate heterogeneous heterogeneous integration at different process nodes, improve the functional density of the system, and meet the growing computing power requirements. However, stacking chips with high integration density results in a small distance between chips, and high-speed signals inside different chips will interfere with each other, affecting the integrity of high-speed signals. Summary of the invention

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of the packaging structure.

[0004] The packaging structure disclosed in the present invention includes a first chip and a second chip stacked on each other, wherein the first chip is provided with a first element and a shielding element; wherein the second chip is arranged opposite to the active surface of the first chip, and the shielding element is arranged between the first element and the second chip in the thickness direction of the packaging structure, and the shielding element is used to reduce the signal interference of the second chip on the first element.

[0005] Optionally, the first chip includes multiple first wiring layers, the multiple first wiring layers are arranged along the thickness direction of the packaging structure, at least one of the first wiring layers is a top layer, the top layer is arranged closer to the second chip than the other first wiring layers in the thickness direction of the packaging structure, and the shielding element is at least partially arranged on the top layer.

[0006] Optionally, at least one of the first wiring layers forms a sub-top layer, which is arranged on a side of the top layer away from the second chip in the thickness direction of the packaging structure and adjacent to the top layer, and the first element is at least partially arranged on the sub-top layer.

[0007] Optionally, at least two of the first wiring layers form the second top layer.

[0008] Optionally, an orthographic projection of the shielding element in a direction toward the first element at least partially covers the first element.

[0009] Optionally, an area of ​​an orthographic projection of the shielding element in a direction toward the first element is larger than an area of ​​a region where the first element is located.

[0010] Optionally, the first chip is provided with a plurality of first electrical connectors, the second chip is provided with a plurality of second electrical connectors, and the second electrical connectors are interconnected with the first electrical connectors.

[0011] Optionally, the first chip and the second chip are electrically connected by hybrid bonding.

[0012] Optionally, the shielding element comprises a metal layer.

[0013] Optionally, the metal density of the area where the metal layer is located is 30% to 50%.

[0014] Optionally, the shielding element includes a first shielding part and a second shielding part, and the first shielding part and the second shielding part are both comb-tooth-shaped; the first shielding part includes a plurality of first metal strips arranged side by side, and the second shielding part includes a plurality of second metal strips arranged side by side, and the first metal strips and the second metal strips are arranged alternately and at intervals in sequence.

[0015] Optionally, the first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

[0016] Optionally, a side of the first chip away from the second chip is connected to a circuit board.

[0017] Optionally, the shielding element is grounded or connected to a power source.

[0018] In a second aspect, the present disclosure provides a packaging method.

[0019] The packaging method disclosed in the present invention is used to form any of the packaging structures described above, and the packaging method includes:

[0020] Disposing a first element and a shielding element on the first chip;

[0021] The first chip and the second chip are stacked, wherein the shielding element is arranged between the first element and the second chip, the second chip is arranged opposite to the active surface of the first chip, and the shielding element is used to reduce the signal interference of the second chip on the first element.

[0022] Optionally, the first chip is provided with a first element and a shielding element, including:

[0023] forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure;

[0024] forming the first element through at least one of the first wiring layers;

[0025] The shielding element is formed by at least one of the first wiring layers.

[0026] Optionally, at least one of the first wiring layers is a top layer, the top layer is arranged closer to the second chip than the other first wiring layers in the thickness direction of the packaging structure, and the shielding element is at least partially arranged on the top layer.

[0027] Optionally, at least one of the first wiring layers forms a sub-top layer, which is arranged on a side of the top layer away from the second chip in the thickness direction of the packaging structure and adjacent to the top layer, and the first element is at least partially arranged on the sub-top layer.

[0028] In a third aspect, the present disclosure provides a chip stacking structure.

[0029] The chip stacking structure disclosed in the present invention comprises a substrate and any one of the above-mentioned packaging structures, wherein the packaging structure is arranged on the substrate.

[0030] In a fourth aspect, the present disclosure provides an electronic device.

[0031] The electronic device disclosed in the present invention comprises a printed circuit board and any one of the above-mentioned packaging structures, wherein the printed circuit board is connected to the packaging structure.

[0032] The packaging structure disclosed in the present invention arranges a first element and a shielding element in a first chip, and arranges the shielding element between the first element and the second chip in the thickness direction of the packaging structure, so that the shielding element can reduce the signal interference of the second chip on the first element, thereby improving the signal quality of the first element and the signal quality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0034] Figure 2 FIG. 4 is a partial cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0035] Figure 3 is a cross-sectional view of a chip according to another embodiment of the present disclosure.

[0036] Figure 4 yes Figure 3 Enlarged view of point A in the middle.

[0037] Figure 5 It is a schematic structural diagram of a chip shielding element according to another embodiment of the present disclosure.

[0038] Figure 6 It is a schematic structural diagram of a shielding element and a first element of a chip according to another embodiment of the present disclosure.

[0039] Figure 7 It is a schematic structural diagram of a chip shielding element according to yet another embodiment of the present disclosure.

[0040] Figure 8 4 is a schematic structural diagram of a chip shielding element according to another embodiment of the present disclosure.

[0041] Fig. 9 4 is a schematic structural diagram of a chip shielding element according to another embodiment of the present disclosure.

[0042] Reference numerals:

[0043] 10. Packaging structure;

[0044] 1. first chip; 11. first element; 12. shielding element; 121. first shielding part; 1211. first metal strip; 122. second shielding part; 1221. second metal strip; 123. shielding part; 1231. metal strip; 13. first electrical connection member; 14. first through hole; 101. first wiring layer; 1011. top layer; 1012. second top layer; 102. first line;

[0045] 2. second chip; 21. second electrical connection member; 22. second through hole; 201. second wiring layer; 2011. second line;

[0046] 100. Packaging structure; 1001. First chip; 1002. Second chip; 1003. Inductor element; 1004. Circuit. DETAILED DESCRIPTION

[0047] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.

[0048] like Figure 1 and Figure 2 A package structure 100 is disclosed in one embodiment of the present disclosure. Figure 1 and Figure 2In the example, the inductor element 1003 needs to be provided with a clearance area of ​​a certain size to prevent other routing lines from affecting the Q value and inductance value of the inductor element 1003. Since the active surfaces of the first chip 1001 and the second chip 1002 in the packaging structure 100 are connected by a hybrid bonding method, the spacing L between the first chip 1001 and the second chip 1002 is only a few microns. The inductor element 1003 of the first chip 1001 cannot achieve a clearance area that meets the requirements, and the line 1004 on the second chip 1002 will interfere with the inductor element 1003 of the first chip 1001, reduce the signal quality of the inductor element 1003, and further affect the operation of the first chip 1001, especially in high-speed scenarios, such as when the transmission speed reaches more than 10BPS, the inductor element 1003 is more susceptible to the influence of the second chip 1002. Therefore, how to improve the signal quality of the inductor element 1003 in the first chip 1001 is a technical problem that needs to be solved urgently.

[0049] As Figure 3 and Figure 4 As shown, the package structure 10 of the embodiment of the present disclosure includes a first chip 1 and a second chip 2 stacked on each other, and a first element 11 and a shielding element 12 are provided in the first chip 1. The second chip 2 is arranged opposite to the active surface of the first chip 1. In the thickness direction of the package structure 10, the shielding element 12 is arranged between the first element 11 and the second chip 2. The shielding element 12 is used to reduce the signal interference of the second chip 2 on the first element 11.

[0050] It should be noted that the chip in the embodiment of the present disclosure can be a grain (also referred to as a particle or a bare chip) (die) or a chip wafer. It is understandable that after the epitaxial layer is grown on the wafer, the chip wafer is formed, and the chip wafer is cut to obtain a bare chip (die). Grains can be bonded to each other (die-to-die bonding, D2D bonding). The bonding of chip wafers is called wafer-to-wafer bonding (wafer-to-wafer bonding, W2W bonding). Multiple grains are stacked on a chip wafer, and such a structure can be called grain-to-wafer bonding (die-to-wafer bonding, D2W bonding). The package disclosed in the present disclosure can also be at least one of chip-to-wafer (Chip to Wafer, C2W) bonding, die-to-wafer (Die to Wafer, D2C) bonding, and chip-to-chip (Chip to Chip, C2C) bonding.

[0051] The present disclosure does not limit the number of chips stacked in the chip stacking structure, and the number of chips stacked can be set according to application requirements. In addition, the above-mentioned chip can be a memory chip, a logic chip or a chip with other functions.

[0052] The packaging structure 10 of the embodiment of the present disclosure arranges the first element 11 and the shielding element 12 in the first chip 1, and arranges the shielding element 12 between the first element 11 and the second chip 2 in the thickness direction of the packaging structure 10, so that the shielding element 12 can reduce the signal interference of the second chip 2 on the first element 11, thereby improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0053] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a memory chip. Alternatively, both the first chip 1 and the second chip 2 are logic chips.

[0054] Among them, the logic chip can be an application chip, and the memory chip can be a dynamic random access memory chip.

[0055] In the embodiment of the present disclosure, the first element 11 may include an element with a specific function, that is, a functional element.

[0056] Optionally, the first element 11 includes an inductor. It is understandable that the first element 11 may also be other functional devices affected by the second chip 2, such as a sensor, a capacitor, and the like.

[0057] In the present disclosure, the inductor element is very susceptible to the influence of the second chip 2 , and the present application solution can be preferably used in the scenario where the first element 11 is an inductor.

[0058] By providing the shielding element 12 , the signal interference of the second chip 2 on the inductor, sensor or capacitor can be reduced or even avoided, thereby improving the signal quality of the packaging structure 10 .

[0059] In order to make the technical solution of the present disclosure easier to understand, the technical solution of the present disclosure is further described below by taking the thickness direction of the packaging structure 10 as being consistent with the up-down direction. Figure 3 and Figure 4 shown.

[0060] For example, the first chip 1 is disposed on a lower side of the second chip 2 , and the first element 11 is disposed on a lower side of the shielding element 12 .

[0061] Alternatively, if Figure 3 and Figure 4As shown, the first chip 1 includes a plurality of first wiring layers 101, and the plurality of first wiring layers 101 are arranged along the thickness direction of the package structure 10. At least one first wiring layer 101 is a top layer 1011, and the top layer 1011 is arranged closer to the second chip 2 than the remaining first wiring layers 101 in the thickness direction of the package structure 10. The shielding element 12 is at least partially arranged on the top layer 1011.

[0062] The shielding element 12 is at least partially disposed on the top layer 1011 , which can be understood as: a portion of the shielding element 12 is disposed on the top layer 1011 , and another portion of the shielding element 12 is disposed on other first wiring layers 101 except the top layer 1011 ; or, the shielding element 12 is disposed entirely on the top layer 1011 .

[0063] For example, a plurality of first wiring layers 101 are arranged in the up-down direction, one of the first wiring layers 101 is a top layer 1011 , and the top layer 1011 is located at the uppermost side among the plurality of first wiring layers 101 .

[0064] In the embodiment of the present disclosure, among the plurality of first wiring layers 101 , the first wiring layer 101 closer to the second chip 2 has a greater thickness and a smaller resistance.

[0065] By at least partially disposing the shielding element 12 on the top layer 1011, the first element 11 can be arranged on the first wiring layer 101 with a relatively large thickness, thereby reducing the parasitic resistance of the first element 11, thereby improving the Q value of the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0066] Alternatively, if Figure 3 and Figure 4 As shown, at least one first wiring layer 101 forms a sub-top layer 1012. The sub-top layer 1012 is disposed on a side of the top layer 1011 away from the second chip 2 in the thickness direction of the package structure 10 and is disposed adjacent to the top layer 1011. The first element 11 is at least partially disposed on the sub-top layer 1012.

[0067] Among them, the first element 11 is at least partially arranged on the sub-top layer 1012, which can be understood as: a part of the first element 11 is arranged on the sub-top layer 1012, and another part of the first element 11 is arranged on other first wiring layers 101 except the top layer 1011 and the sub-top layer 1012; or, the first element 11 is arranged as a whole on the top layer 1011.

[0068] As described above, among the plurality of first wiring layers 101 , the first wiring layers 101 closer to the second chip 2 have greater thickness and lower resistance.

[0069] By at least partially disposing the first element 11 on the sub-top layer 1012 , the parasitic resistance of the first element 11 can be reduced, thereby increasing the Q value of the first element 11 , further improving the signal quality of the first element 11 , and improving the signal quality of the packaging structure 10 .

[0070] Optionally, at least two first wiring layers 101 form the sub-top layer 1012 .

[0071] For example, the number of first wiring layers 101 is three, the first wiring layer 101 located on the top side is the top layer 1011, and the two first wiring layers 101 located below the top layer 1011 form a sub-top layer 1012, that is, the two first wiring layers 101 are combined to form the sub-top layer 1012 to increase the thickness of the sub-top layer 1012.

[0072] By forming a sub-top layer 1012 through at least two first wiring layers 101, the thickness of the sub-top layer 1012 can be reduced, thereby reducing the parasitic resistance of the first element 11 arranged on the sub-top layer 1012, further improving the Q value of the first element 11, improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0073] Alternatively, if Figure 3 As shown, the first chip 1 further includes a first circuit 102 . The first circuit 102 is arranged on at least one side of the first element 11 in a preset direction. The preset direction is perpendicular to the thickness direction of the package structure 10 .

[0074] In order to make the technical solution of the present disclosure easier to understand, the following takes the preset direction and the left-right direction as an example to further describe the technical solution of the present disclosure. Figure 3 and Figure 4 shown.

[0075] For example, the first lines 102 are located on both left and right sides of the first element 11 in the left-right direction.

[0076] By arranging the first line 102 on at least one side of the first element 11 in a preset direction, compared with arranging the first line 102 on a side of the first element 11 away from the shielding element 12 in the preset direction, the interference of the first line 102 on the first element 11 can be reduced, thereby further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0077] Alternatively, if Figure 3 and Figure 4 As shown, the second chip 2 includes a plurality of second wiring layers 201 , which are arranged along the thickness direction of the package structure 10 , and at least one second wiring layer 201 is provided with a second line 2011 .

[0078] For example, the second chip 2 includes three second wiring layers 201 , which are arranged in the up-and-down direction, and each second wiring layer 201 is provided with a second line 2011 .

[0079] Alternatively, if Figure 3 and Figure 4 As shown, the first chip 1 is provided with a plurality of first electrical connectors 13, and the second chip 2 is provided with a plurality of second electrical connectors 21, which correspond to and are electrically connected to the first electrical connectors 13. At least one first electrical connector 13 is grounded and electrically connected to the shielding element 12.

[0080] like Figure 3 As shown, the first chip 1 is provided with a first through hole 14, and the first electrical connector 13 extends to the circuit of the first chip 1 through the first through hole 14. The second chip 2 is provided with a second through hole 22, and the second electrical connector 21 extends to the circuit of the second chip 2 through the second through hole 22.

[0081] By grounding the at least one first electrical connection member 13 and electrically connecting it to the shielding element 12 , the shielding element 12 is conveniently grounded.

[0082] Optionally, the first chip 1 and the second chip 2 are electrically connected by hybrid bonding.

[0083] The first chip 1 and the second chip 2 are connected by a hybrid bonding method, so that a higher density and a larger bandwidth of the packaging structure 10 can be achieved.

[0084] Optionally, the shielding element 12 includes a shielding layer made of electromagnetic shielding material.

[0085] Optionally, the shielding element 12 comprises a metal layer.

[0086] It can be understood that the shielding element 12 in the present disclosure is not limited to a metal layer or an electromagnetic shielding layer, but may also be other elements having an electromagnetic shielding function.

[0087] By configuring the shielding element 12 to include a metal layer, the signal shielding effect of the shielding element 12 can be improved, and the signal quality of the first element 11 can be further improved, thereby improving the signal quality of the packaging structure 10 .

[0088] Optionally, the metal density of the area where the metal layer is located is 30% to 50%.

[0089] For example, Figure 5 As shown, the area of ​​the dotted line frame is the area where the shielding element 12 is located, and the ratio of the area of ​​the metal layer to the area of ​​the dotted line frame is the metal density of the area where the metal layer is located.

[0090] By setting the metal density of the area where the metal layer is located to 30% to 50%, the metal amount of the shielding element 12 can be reduced while ensuring the shielding effect of the shielding element 12, thereby reducing the cost of the packaging structure 10.

[0091] Optionally, the shielding element 12 is grounded or connected to a power source.

[0092] For example, the shielding element 12 is electrically connected to the first wiring layer 101 , and the first wiring layer 101 is grounded or connected to a power source, thereby enabling the shielding element 12 to be grounded or connected to a power source.

[0093] By grounding the shielding element 12 , the signal shielding effect of the shielding element 12 can be improved, the signal interference generated by the second chip 2 on the first element 11 can be reduced, and the signal quality of the packaging structure 10 can be further improved.

[0094] Alternatively, if Figures 5 to 7 As shown, the shielding element 12 includes at least one shielding portion 123 , and the shielding portion 123 is in a comb-teeth shape.

[0095] For example, Figure 5 and Figure 6 As shown, the shielding element 12 includes two shielding portions 123 , and both shielding portions 123 are in a comb-teeth shape.

[0096] By configuring the shielding portion 123 of the shielding element 12 to be comb-shaped, the shielding element 12 is utilized to effectively improve the signal shielding effect of the shielding element 12 , reduce signal interference to the first element 11 , and further improve the signal quality of the packaging structure 10 .

[0097] Alternatively, if Figure 5 and Figure 6 As shown, the shielding element 12 includes a plurality of shielding parts 123, at least one shielding part 123 is a first shielding part 121, and at least one shielding part 123 is a second shielding part 122. The first shielding part 121 includes a plurality of first metal strips 1211 arranged side by side, and the second shielding part 122 includes a plurality of second metal strips 1221 arranged side by side, and the first metal strips 1211 and the second metal strips 1221 are arranged alternately and at intervals in sequence.

[0098] For example, Figure 5 and Figure 6 As shown, the first shielding part 121 is arranged at the front side of the second shielding part 122, and a plurality of first metal strips 1211 and a plurality of second metal strips 1221 are arranged alternately and at intervals along the left-right direction. Figure 5 and Figure 6 As shown, the left and right directions are Figure 5 and Figure 6 shown.

[0099] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference to the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0100] Alternatively, if Figure 5 and Figure 6 As shown, the width of the first metal strip 1211 and the second metal strip 1221 is 0.4 μm to 12.5 μm.

[0101] For example, Figure 5 As shown, the width of the first metal strip 1211 and the second metal strip 1221 are both K1, and K1 is 1.8 μm.

[0102] By setting the width of the first metal strip 1211 and the second metal strip 1221 to 0.4 μm to 12.5 μm, the processing and manufacturing of the shielding element 12 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which helps to reduce the cost of the packaging structure 10 .

[0103] Alternatively, if Figure 5 and Figure 6 As shown, the distance between the first metal strip 1211 and the second metal strip 1221 is 0.4 μm to 25 μm.

[0104] For example, Figure 5 As shown, the distance between the first metal strip 1211 and the second metal strip 1221 is K2, and K2 is 2.7 μm.

[0105] By setting the spacing between the first metal strip 1211 and the second metal strip 1221 to 0.4 μm to 25 μm, the processing and manufacturing of the shielding element 12 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which is beneficial to reducing the cost of the packaging structure 10 .

[0106] Alternatively, if Figure 8 As shown, the shielding element 12 includes a plurality of shielding parts 123, and the plurality of shielding parts 123 are evenly arranged along the circumference of the preset rectangular frame, and the shielding part 123 includes a plurality of V-shaped metal strips 1231. The plurality of metal strips 1231 of the same shielding part 123 are arranged at intervals along the inner and outer directions, and the length of the metal strip 1231 located on the outer side is less than the length of the metal strip 1231 located on the inner side. Figure 8 The dotted box in is the preset rectangular box.

[0107] Herein, inward can be understood as: a direction close to the center of the rectangular frame in the plane where the shielding element 12 is located; outward can be understood as: a direction away from the center of the rectangular frame in the plane where the shielding element 12 is located.

[0108] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference to the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0109] Alternatively, if Figure 8 As shown, the number of shielding parts 123 is four, and the angle of the metal strips 1231 is 90°.

[0110] By setting the number of shielding parts 123 to four and the included angle of the metal strip 1231 to 90°, the processing and manufacturing of the shielding element 12 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which helps to reduce the cost of the packaging structure 10 .

[0111] Alternatively, if Fig. 9 As shown, the shielding element 12 has a rectangular pulse signal waveform.

[0112] By setting the shielding element 12 to the above structure, the signal shielding effect of the shielding element 12 can be effectively improved, the signal interference generated on the first element 11 can be reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved. In addition, the shielding element 12 is set to have a rectangular pulse signal waveform, which can also facilitate the processing and manufacturing of the shielding element 12, thereby facilitating the processing and manufacturing of the packaging structure 10, which is conducive to reducing the cost of the packaging structure 10.

[0113] Alternatively, if Figure 3 , Figure 4 and Figure 6 As shown, the orthographic projection of the shielding element 12 in the direction toward the first element 11 at least partially covers the first element 11 .

[0114] Among them, the orthographic projection of the shielding element 12 in the direction toward the first element 11 at least partially covers the first element 11, which can be understood as: the orthographic projection of the shielding element 12 in the direction toward the first element 11 covers the first element 11 as a whole; or, a part of the orthographic projection of the shielding element 12 in the direction toward the first element 11 covers the first element 11, and the other part of the orthographic projection of the shielding element 12 in the direction toward the first element 11 does not cover the first element 11.

[0115] By setting the orthographic projection of the shielding element 12 in the direction toward the first chip 1 to at least partially cover the first element 11 , the signal shielding effect of the shielding element 12 can be improved, and the signal quality of the first element 11 and the package structure 10 can be further improved.

[0116] Alternatively, if Figure 6As shown, the area of ​​the orthographic projection of the shielding element 12 in the direction toward the first chip 1 is larger than the area of ​​the region where the first element 11 is located. In other words, the orthographic projection of the shielding element 12 in the direction toward the first element 11 not only covers the entire first element 11, but also covers the edge area of ​​the first element 11, so as to cover more signals generated by the first element 11.

[0117] By making the area of ​​the orthographic projection of the shielding element 12 in the direction toward the first chip 1 larger than the area of ​​the first element 11 , the signal shielding effect of the shielding element 12 can be further improved, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0118] Optionally, a side of the first chip 1 away from the second chip 2 is connected to a circuit board.

[0119] For example, the lower side of the first chip 1 is connected to the circuit board.

[0120] The packaging structure 10 of the embodiment of the present disclosure can reduce the signal interference of the second chip 2 on the first element 11 and the interference of the first element 11 on the circuit of the second chip 2 by setting the first element 11 and the shielding element 12 on the first chip 1, thereby improving the signal quality of the first element 11 and improving the signal quality of the packaging structure 10.

[0121] The packaging method of the embodiment of the present disclosure is used for the packaging structure 10 of any of the above embodiments, and the packaging method includes:

[0122] A first element 11 and a shielding element 12 are provided on the first chip 1;

[0123] The first chip 1 and the second chip 2 are stacked, wherein the shielding element 12 is arranged between the first element 11 and the second chip 2 , and the second chip 2 is arranged opposite to the active surface of the first chip 1 , and the shielding element 12 is used to reduce the signal interference of the second chip 2 on the first element 11 .

[0124] Optionally, the first chip 1 is provided with a first element 11 and a shielding element 12, including:

[0125] At least one first wiring layer 101 is formed on the active surface of the first chip 1, and the first wiring layer 101 is arranged along the thickness direction of the package structure 10;

[0126] A first element 11 is formed by at least one first wiring layer 101;

[0127] By at least one first wiring layer 101 , the shielding member 12 is formed.

[0128] Optionally, at least one first wiring layer 101 is a top layer 1011 , which is disposed closer to the second chip 2 than other first wiring layers 101 in the thickness direction of the package structure 10 , and the shielding element 12 is at least partially disposed on the top layer 1011 .

[0129] Optionally, at least one first wiring layer 101 forms a sub-top layer 1012 , which is arranged on a side of the top layer 1011 away from the second chip 2 in the thickness direction of the package structure 10 and adjacent to the top layer 1011 , and the first element 11 is at least partially arranged on the sub-top layer 1012 .

[0130] The chip stacking structure of the embodiment of the present disclosure includes a substrate and a package structure 10 of any of the above embodiments, and the package structure 10 is disposed on the substrate.

[0131] The electronic device according to the embodiment of the present disclosure includes a printed circuit board and a packaging structure 10 according to any one of the above embodiments, and the packaging structure 10 is connected to the printed circuit board.

[0132] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0133] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0134] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0135] In the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0136] In the present disclosure, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0137] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and cannot be construed as limitations on the present disclosure. Changes, modifications, substitutions and variations of the above embodiments by those of ordinary skill in the art are all within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that: include A first chip and a second chip are stacked on each other, wherein the first chip is provided with a first element and a shielding element; The second chip is arranged opposite to the active surface of the first chip, and the shielding element is arranged between the first element and the second chip in the thickness direction of the packaging structure, and the shielding element is used to reduce the signal interference of the second chip on the first element.

2. The packaging structure according to claim 1, characterized in that: The first chip includes multiple first wiring layers, which are arranged along the thickness direction of the packaging structure. At least one of the first wiring layers is a top layer, and the top layer is closer to the second chip than the other first wiring layers in the thickness direction of the packaging structure. The shielding element is at least partially arranged on the top layer.

3. The packaging structure according to claim 2, characterized in that: At least one of the first wiring layers forms a sub-top layer, which is arranged on a side of the top layer away from the second chip in the thickness direction of the packaging structure and adjacent to the top layer, and the first element is at least partially arranged on the sub-top layer.

4. The packaging structure according to claim 3, characterized in that: At least two of the first wiring layers form the second top layer.

5. The packaging structure according to claim 1, characterized in that: An orthographic projection of the shielding element in a direction toward the first element at least partially covers the first element.

6. The packaging structure according to claim 5, characterized in that: The area of ​​the orthographic projection of the shielding element in the direction toward the first element is larger than the area of ​​the region where the first element is located.

7. The packaging structure according to claim 1, characterized in that: The first chip is provided with a plurality of first electrical connectors, and the second chip is provided with a plurality of second electrical connectors, and the second electrical connectors are connected to the first electrical connectors.

8. The packaging structure according to claim 7, characterized in that: The first chip and the second chip are electrically connected by hybrid bonding.

9. The packaging structure according to any one of claims 1 to 8, characterized in that: The shielding element comprises a metal layer.

10. The packaging structure according to claim 9, characterized in that: The metal density of the area where the metal layer is located is 30% to 50%.

11. The packaging structure according to claim 9, characterized in that: The shielding element comprises a first shielding portion and a second shielding portion, wherein the first shielding portion and the second shielding portion are both in a comb-tooth shape; The first shielding part includes a plurality of first metal strips arranged side by side, and the second shielding part includes a plurality of second metal strips arranged side by side. The first metal strips and the second metal strips are arranged alternately and at intervals.

12. The packaging structure according to any one of claims 1 to 8, characterized in that: The first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

13. The packaging structure according to any one of claims 1 to 8, characterized in that: A side of the first chip away from the second chip is connected to a circuit board.

14. The packaging structure according to any one of claims 1 to 8, characterized in that: The shielding element is grounded or connected to a power source.

15. A packaging method, characterized in that: The packaging method is used to form the packaging structure according to any one of claims 1 to 14, and the packaging method comprises: Disposing a first element and a shielding element on the first chip; The first chip and the second chip are stacked, wherein the shielding element is arranged between the first element and the second chip, the second chip is arranged opposite to the active surface of the first chip, and the shielding element is used to reduce the signal interference of the second chip on the first element.

16. The packaging method according to claim 15, characterized in that: The first chip is provided with a first element and a shielding element, including: forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure; forming the first element through at least one of the first wiring layers; The shielding element is formed by at least one of the first wiring layers.

17. The packaging method according to claim 16, characterized in that: At least one of the first wiring layers is a top layer, which is arranged closer to the second chip than the other first wiring layers in the thickness direction of the packaging structure, and the shielding element is at least partially arranged on the top layer.

18. The packaging method according to claim 17, characterized in that: At least one of the first wiring layers forms a sub-top layer, which is arranged on a side of the top layer away from the second chip in the thickness direction of the packaging structure and adjacent to the top layer, and the first element is at least partially arranged on the sub-top layer.

19. A chip stacking structure, characterized in that: The invention comprises a substrate and the packaging structure according to any one of claims 1 to 14, wherein the packaging structure is arranged on the substrate.

20. An electronic device, characterized in that: The invention comprises a printed circuit board and the packaging structure according to any one of claims 1 to 14, wherein the printed circuit board is connected to the packaging structure.

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