Electronic package and fabrication method thereof

Abstract

An electronic package and a manufacturing method thereof are provided, and a plurality of optical chips and auxiliary electronic components are separately arranged on a package module to shorten the transmission distance of optical signals, so that the signal transmission rate of a circuit structure can be improved, and the operation efficiency of the whole electronic package is further improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, in particular to a multifunctional electronic packaging component and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-function and high performance. In order to meet the packaging needs of miniaturization of electronic packaging, wafer level packaging (WLP) technology has been developed.

[0003] Figures 1A to 1E It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package 1 using wafer-level packaging technology.

[0004] like Figure 1A As shown, a thermal release tape 100 is formed on a carrier 10 .

[0005] Next, a plurality of communication chips 11 are placed on the thermal release adhesive layer 100 . The communication chips 11 have opposite active surfaces 11 a and inactive surfaces 11 b . Each active surface 11 a has a plurality of electrode pads 110 , and each active surface 11 a is adhered to the thermal release adhesive layer 100 .

[0006] like Figure 1B As shown, a packaging glue 14 is formed on the thermal release glue layer 100 to cover the communication chips 11 .

[0007] like Figure 1C As shown, the packaging colloid 14 is baked to harden the thermal release adhesive layer 100 , and then the thermal release adhesive layer 100 and the carrier 10 are removed to expose the active surfaces 11 a of the communication chips 11 .

[0008] like Figure 1D As shown, a circuit structure 16 is formed on the active surface 11a of the encapsulant 14 and the communication chips 11, so that the circuit structure 16 is electrically connected to the electrode pad 110. Next, an insulating protection layer 18 is formed on the circuit structure 16, and the insulating protection layer 18 exposes a portion of the surface of the circuit structure 16 for bonding with a conductive element 17 such as a solder ball.

[0009] like Figure 1E As shown, along Figure 1D The cutting path L shown is used for performing a singulation process to obtain a plurality of semiconductor packages 1 .

[0010] However, as the amount of data transmitted by data transmission networks increases significantly, data transmission equipment must meet the ever-increasing bandwidth requirements, and the disadvantages of using copper as data channels (such as the lines of the line structure 16) are becoming increasingly obvious. Therefore, optical fiber communication is becoming increasingly important in communication equipment that transmits a large amount of data at this stage, and the existing structure is no longer sufficient for optical communication.

[0011] Therefore, the industry is actively developing packaging structures that can be used for mass data transmission to meet the needs of current applications in various fields. This is indeed a technical problem that all sectors are eager to solve. Summary of the invention

[0012] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a coating layer having a first surface and a second surface opposite to each other and side surfaces adjacent to the first surface and the second surface; a first electronic component embedded in the coating layer; a plurality of conductive pillars embedded in the coating layer; a circuit structure formed on the first surface of the coating layer and electrically connecting the plurality of conductive pillars and the first electronic component; an auxiliary electronic component disposed on the circuit structure and connected to the circuit structure; and a plurality of second electronic components disposed on the circuit structure and electrically connected to the circuit structure, wherein the plurality of second electronic components are optical chips.

[0013] The present invention also provides a method for manufacturing an electronic package, comprising: arranging a plurality of conductive pillars and a first electronic component on a carrier board; forming a coating layer on the carrier board, and allowing the coating layer to coat the first electronic component and the plurality of conductive pillars, wherein the coating layer has a first surface and a second surface opposite to each other, the end surfaces of the plurality of conductive pillars are exposed on the first surface of the coating layer, and the coating layer is bonded to the carrier board with its second surface; forming a circuit structure on the first surface of the coating layer, and allowing the circuit structure to electrically connect the plurality of conductive pillars and the first electronic component, and allowing the coating layer to form a side surface adjacent to the first surface and the second surface; arranging an auxiliary electronic component and a plurality of second electronic components on the circuit structure, and allowing the auxiliary electronic component and the plurality of second electronic components to connect to the circuit structure, wherein the plurality of second electronic components are optical chips; and removing the carrier board.

[0014] In the aforementioned electronic package and its manufacturing method, the first electronic component combines and electrically connects a plurality of conductors. For example, the plurality of conductors are coated with a protective film and embedded in the coating layer and electrically connected to the circuit structure.

[0015] In the aforementioned electronic package and its manufacturing method, the plurality of conductive pillars surround the first electronic element.

[0016] In the aforementioned electronic package and its manufacturing method, the auxiliary electronic component is a switch or a semiconductor chip for heat dissipation.

[0017] In the aforementioned electronic package and its manufacturing method, the plurality of second electronic components protrude from the side surface of the covering layer.

[0018] In the aforementioned electronic package and its manufacturing method, the plurality of second electronic components are externally connected to electrical connectors.

[0019] The aforementioned electronic package and its manufacturing method further include forming a circuit portion on the second surface of the coating layer, and making the circuit portion electrically connected to the plurality of conductive pillars. Further, it may include forming a plurality of conductive elements on the circuit portion.

[0020] The aforementioned electronic package and its manufacturing method also include arranging a bearing structure on the second surface of the covering layer.

[0021] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly integrate optical chips and auxiliary electronic components into the same packaging module to shorten the distance between the switch and components such as optical / electrical signals. Therefore, compared with the prior art, the present invention can improve the signal transmission rate of the circuit structure and reduce latency, thereby improving the overall operating performance of the electronic package.

[0022] Furthermore, the manufacturing method of the present invention can be implemented by using existing semiconductor packaging processes, so there is no need to develop special processes or purchase equipment of special specifications. Therefore, the manufacturing method of the present invention can effectively reduce the production cost of the electronic packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1A to 1E It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.

[0024] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0025] Figure 3 for Figure 2E A cross-sectional schematic diagram of the subsequent process.

[0026] Description of Reference Numerals

[0027] 1 Semiconductor Package

[0028] 10 Bearing

[0029] 100 Thermal release adhesive layer

[0030] 11 Communication Chip

[0031] 11a,21a Action surface

[0032] 11b, 21b Non-active surface

[0033] 110,210 Electrode pads

[0034] 14 Encapsulation colloid

[0035] 16,20 Line structure

[0036] 17,24 Conductive elements

[0037] 18 Insulation protection layer

[0038] 2 Electronic packaging

[0039] 2a Package module

[0040] 20 Line structure

[0041] 200 Insulation

[0042] 201 Line redistribution layer

[0043] 202 Electrical contact pad

[0044] 21 First Electronic Components

[0045] 211 Protective film

[0046] 212 Bonding layer

[0047] 22 Conductors

[0048] 22a,23a,23b End face

[0049] 23 Conductive column

[0050] 240 Line Department

[0051] 25 Coating

[0052] 25a First surface

[0053] 25b Second surface

[0054] 25c Side

[0055] 26 Second electronic component

[0056] 27 Conductive bump

[0057] 270 Under Bump Metal

[0058] 28 Auxiliary electronic components

[0059] 29,302 Primer

[0060] 30 Load-bearing structure

[0061] 30a Upper surface

[0062] 30b Lower surface

[0063] 300 Solder Balls

[0064] 301 External pad

[0065] 31 Strong firmware

[0066] 40 Electrical connector

[0067] 9 Loading plate

[0068] 9a Seed layer

[0069] 9b Metal layer

[0070] 90 Release layer

[0071] 91 Insulation layer

[0072] L,S cutting path. DETAILED DESCRIPTION

[0073] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0074] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0075] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0076] like Figure 2A As shown, a plurality of conductive pillars 23 are formed on a carrier board 9 , and at least one first electronic component 21 is disposed on the carrier board 9 (two first electronic components 21 are shown in this embodiment), wherein a plurality of conductors 22 are combined and electrically connected to the first electronic component 21 .

[0077] In the present embodiment, the carrier plate 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), on which a release layer 90, a metal layer 9b such as titanium / copper, an insulating layer 91 such as a dielectric material or a solder mask material, and a seed layer 9a are sequentially formed by, for example, coating. A patterned resist layer (not shown) may be formed on the seed layer 9a so that the resist layer exposes a portion of the surface of the seed layer 9a to form the conductive pillars 23 by electroplating. After the conductive pillars 23 are manufactured, the patterned resist layer and the seed layer 9a thereunder are removed so that the conductive pillars 23 are disposed on the insulating layer 91.

[0078] Furthermore, the material forming the plurality of conductive pillars 23 is a metal material such as copper or a solder material, and the plurality of conductors 22 are spherical such as solder balls, or pillars of metal materials such as copper pillars, solder bumps, or stud-shaped conductive parts made by a wire bonding machine, but are not limited thereto.

[0079] In addition, the first electronic component 21 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, the first electronic component 21 is a semiconductor chip, which has an active surface 21a and an inactive surface 21b opposite to each other. The first electronic component 21 is bonded to the insulating layer 91 with its inactive surface 21b through a bonding layer 212, and the active surface 21a has a plurality of electrode pads 210 and a protective film 211 such as a dielectric material, and the conductor 22 is in the protective film 211.

[0080] In addition, the first electronic component 21 is such as a driver or a transimpedance amplifier (TIA) to provide the required functions, such as driving a laser diode or converting an analog signal into a digital signal to improve the signal-to-noise ratio (S / N) or other functions of an electrical application function-related chip. For example, a semiconductor material such as silicon dioxide (SiO2) can be used to make the required wafer substrate, and an 8-inch wafer process can be performed with a specification requirement of 130 nanometers (nm) to make the driver or transimpedance amplifier. Specifically, one of the first electronic components 21 is used as a transimpedance amplifier (TIA), and the other first electronic component 21 can be used as a driver to process the photocurrent converted by the photodetector through the transimpedance amplifier (the first electronic component 21) and a limiting amplifier. The transimpedance amplifier and the limiting amplifier can convert the photocurrent into a voltage signal with a smaller amplitude, and then convert it into a digital signal through a comparator circuit at the back end.

[0081] like Figure 2BAs shown, a coating layer 25 is formed on the insulating layer 91 of the carrier board 9 so that the coating layer 25 covers the first electronic components 21, the conductors 22 and the conductive pillars 23, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the protective film 211, the end surfaces 22a of the plurality of conductors 22 and the end surfaces 23a of the plurality of conductive pillars 23 are exposed on the first surface 25a of the coating layer 25, and the coating layer 25 is bonded to the insulating layer 91 of the carrier board 9 with its second surface 25b.

[0082] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy resin or other types of packaging materials (molding compound). For example, the coating layer 25 can be formed on the insulating layer 91 by lamination or compression molding.

[0083] Furthermore, a flattening process can be performed to make the first surface 25a of the cladding layer 25 flush with the protective film 211, the end surfaces 23a of the plurality of conductive pillars 23, and the end surfaces 22a of the plurality of conductors 22, so that the end surfaces 23a of the plurality of conductive pillars 23 and the end surfaces 22a of the plurality of conductive bodies 22 are exposed on the first surface 25a of the cladding layer 25. For example, the flattening process removes part of the material of the protective film 211, part of the material of the conductive pillars 23, part of the material of the conductive bodies 22, and part of the material of the cladding layer 25 by grinding.

[0084] In addition, the other end surfaces 23 b of the conductive pillars 23 are also flush with the second surface 25 b of the cladding layer 25 .

[0085] like Figure 2C As shown, a circuit structure 20 is formed on the first surface 25 a of the cladding layer 25 , and the circuit structure 20 is electrically connected to the plurality of conductive pillars 23 and the plurality of conductive bodies 22 .

[0086] In this embodiment, the circuit structure 20 includes a plurality of insulating layers 200 and a plurality of redistribution layers (RDL) 201 disposed on the insulating layers 200, and the outermost insulating layer 200 can be used as a solder mask, and the outermost redistribution layer 201 is exposed from the solder mask to serve as a plurality of electrical contact pads 202. Alternatively, the circuit structure 20 may include only a single insulating layer 200 and a single redistribution layer 201.

[0087] Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or the material of the outermost insulating layer 200 can be a solder mask material such as green paint, ink, etc.

[0088] like Figure 2D As shown, along Figure 2C The cutting path S shown in the figure is used for the singulation process to obtain a plurality of package modules 2a, so that the encapsulation layer 25 is formed with a side surface 25c adjacent to the first surface and the second surface, and at least one auxiliary electronic component 28 and a plurality of second electronic components 26 are arranged on the circuit structure 20 of the package module 2a, so that the plurality of second electronic components 26 protrude from the side surface 25c of the encapsulation layer 25 for subsequent external electrical connectors 40 (such as Figure 2E shown).

[0089] In this embodiment, the auxiliary electronic component 28 is a semiconductor chip, such as a switch die or a thermal die, which can be located between the second electronic components 26 without protruding from the side surface 25 c of the cladding layer 25 .

[0090] Furthermore, the second electronic component 26 is an optical chip (Photonic integrated circuit) 26, which is a device for converting optical signals into electrical signals to detect / receive optical signals. For example, the second electronic component 26 can be made of semiconductor materials such as indium phosphide (InP), gallium arsenide (GaAs), silicon-germanium (SiGe) or a combination thereof to form a required wafer substrate, and a 4 or 6-inch wafer process is performed according to the specification requirement of 130 nanometers to form the optoelectronic chip.

[0091] In addition, the auxiliary electronic component 28 and / or the second electronic component 26 are electrically connected to the plurality of electrical contact pads 202 through a plurality of conductive bumps 27 such as solder bumps, copper bumps or other conductive bumps. In this embodiment, a plurality of under bump metallurgy (UBM) 270 may be formed on the plurality of electrical contact pads 202 to facilitate the combination of the conductive bumps 27.

[0092] In addition, an underfill 29 may be formed between the circuit structure 20 and the auxiliary electronic component 28 and / or the plurality of second electronic components 26 to cover the conductive bumps 27 .

[0093] like Figure 2EAs shown, the carrier board 9 and the release layer 90 and the metal layer 9 b thereon are removed, and the insulating layer 91 is retained. A circuit portion 240 is then formed on the insulating layer 91 to electrically connect the plurality of conductive pillars 23 to manufacture the electronic package 2 .

[0094] In this embodiment, the insulating layer 91 is formed with a plurality of openings by laser so that the end surfaces 23b of the conductive pillars 23 and / or a portion of the second surface 25b of the cladding layer 25 are exposed in the openings for bonding the circuit portion 240. For example, the circuit portion 240 is an under bump metal layer (UBM) for bonding conductive elements 24 such as a plurality of solder bumps or solder balls; or the circuit portion 240 can be formed on the insulating layer 91 by an RDL process for bonding the plurality of conductive elements 24 or the UBM. It should be understood that there are many embodiments of the circuit portion 240, and there is no particular limitation.

[0095] Furthermore, by providing a carrier plate 9 with an insulating layer 91, after removing the carrier plate 9, the insulating layer 91 can be used to form the circuit portion 240, so there is no need to arrange a dielectric layer, thereby saving process time and process steps, thereby achieving the purpose of reducing process costs.

[0096] Therefore, during operation, the driver (one of the first electronic components 21) drives the second electronic component 26 so that the electrical connector 40 on one of the second electronic components 26 receives an optical signal from an optical fiber cable (not shown), and then converts the optical signal into an electrical signal through the first electronic component 21 and the auxiliary electronic component 28.

[0097] In the subsequent process, Figure 3 As shown, the conductive elements 24 can be disposed on a carrier structure 30. Further, the carrier structure 30 is subjected to a ball implantation process to form a plurality of solder balls 300 for subsequent processes. The carrier structure 30 is disposed on a circuit board (not shown) with the solder balls 300 on the bottom thereof.

[0098] In the present embodiment, the supporting structure 30 is in the form of a substrate having an upper surface 30a and a lower surface 30b opposite to each other, so that the conductive elements 24 are disposed on the upper surface 30a of the supporting structure 30. For example, the supporting structure 30 is a package substrate having a core layer and a circuit structure or a coreless circuit structure, and the circuit structure includes at least one insulating layer and at least one circuit layer combined with the insulating layer. It should be understood that the supporting structure 30 may also be other plates, such as a wafer, or other carriers with metal routing, etc., and is not limited to the above.

[0099] Furthermore, the conductive elements 24 are electrically connected to the external pads 301 of the supporting structure 30 , and the conductive elements 24 are covered with the bottom glue 302 .

[0100] In addition, a reinforcement member 31 may be provided on the supporting structure 30 as required, such as Figure 3 The metal frame shown can suppress the stress concentration problem and avoid the warping of the supporting structure 30, and can further provide heat dissipation for the electronic package.

[0101] Therefore, in the manufacturing method of the present invention, the optical chip (second electronic component 26) and the switch (auxiliary electronic component 28) are mainly integrated into the same packaging module 2a to shorten the distance between the switch and components such as optical / electrical signals. Therefore, the manufacturing method of the present invention can increase the signal transmission rate of the circuit structure 20 and reduce latency, thereby improving the overall operating performance of the electronic package 2.

[0102] Furthermore, the manufacturing method of the present invention can be implemented by using existing semiconductor packaging processes, so there is no need to develop special processes or purchase equipment with special specifications. Therefore, the manufacturing method of the present invention can effectively reduce the production cost of the electronic package 2.

[0103] In addition, the present invention utilizes a silicon bridge design to allow the embedded first electronic component 21 to electrically bridge the second electronic component 26 and the auxiliary electronic component 28 to shorten the electrical loss of signal transmission, and to provide high current and / or shielding effects through a plurality of conductive pillars 23 surrounding the first electronic components 21.

[0104] In addition, the auxiliary electronic component 28 and the second electronic component 26 are manufactured separately to reduce the difficulty of manufacturing and improve the manufacturing yield. For example, the second electronic component 26 for transmitting and receiving signals may be damaged due to high temperature under long-term action. When the second electronic component 26 is damaged, the second electronic component 26 can be replaced without scrapping the entire packaging module 2a and the good auxiliary electronic component 28. Therefore, the present invention can avoid the problem of wasting materials and thus reduce the replacement cost at the user end. Furthermore, in other embodiments, the auxiliary electronic component 28 can be a heat dissipation chip to facilitate the heat dissipation of the high heat energy generated by the first electronic component 21 and the second electronic component 26 under long-term action, thereby avoiding damage to the first electronic component 21 and the second electronic component 26.

[0105] The present invention further provides an electronic package 2 , which includes: a coating layer 25 , a first electronic component 21 , a plurality of conductive pillars 23 , a circuit structure 20 , at least one auxiliary electronic component 28 and a plurality of second electronic components 26 .

[0106] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other and a side surface 25c adjacent to the first and second surfaces 25a and 25b.

[0107] The first electronic component 21 is embedded in the coating layer 25 , and a plurality of conductors 22 are combined and electrically connected to the first electronic component 21 , wherein the plurality of conductors 22 are covered by a protective film 211 and embedded in the coating layer 25 , and the end faces 22a of the plurality of conductors 22 are exposed on the first surface 25a of the coating layer 25 .

[0108] The plurality of conductive pillars 23 are embedded in the cladding layer 25 , and the end surfaces 22 a of the plurality of conductive pillars 23 are exposed on the first surface 25 a of the cladding layer 25 .

[0109] The circuit structure 20 is disposed on the first surface 25 a of the cladding layer 25 and electrically connects the plurality of conductive pillars 23 and the plurality of conductive bodies 22 .

[0110] The auxiliary electronic component 28 is disposed on the circuit structure 20 and electrically connected to the circuit structure 20 .

[0111] The plurality of second electronic components 26 are disposed on the circuit structure 20 and electrically connected to the circuit structure 20 , wherein the plurality of second electronic components 26 are optical chips.

[0112] In one embodiment, the plurality of conductive pillars 23 surround the first electronic component 21 .

[0113] In one embodiment, the auxiliary electronic component 28 is a switch or a semiconductor chip for heat dissipation.

[0114] In one embodiment, the plurality of second electronic components 26 protrude from the side surface 25 c of the covering layer 25 .

[0115] In one embodiment, the plurality of second electronic components 26 are connected to the electrical connector 40 .

[0116] In one embodiment, the electronic package 2 further includes a circuit portion 240 formed on the second surface 25 b of the cladding layer 25 and electrically connected to the plurality of conductive pillars 23 . Further, the electronic package 2 may include a plurality of conductive elements 24 formed on the circuit portion 240 .

[0117] In one embodiment, the electronic package 2 further includes a supporting structure 30 disposed on the second surface 25 b of the covering layer 25 .

[0118] In summary, the electronic package and its manufacturing method of the present invention integrate optical chips and auxiliary electronic components into the same packaging module to shorten the distance between the switch and components such as optical / electrical signals, thereby increasing the signal transmission rate of the circuit structure and reducing latency, thereby improving the operating performance of the overall electronic package.

[0119] Furthermore, the manufacturing method of the present invention can be implemented by using existing semiconductor packaging processes, so there is no need to develop special processes or purchase equipment of special specifications, thereby effectively reducing the production cost of the electronic packaging.

[0120] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A cladding layer having a first surface and a second surface opposite to each other and a side surface adjacent to the first surface and the second surface; A first electronic component embedded in the coating layer; A plurality of conductive pillars embedded in the cladding layer; A circuit structure formed on the first surface of the cladding layer and electrically connecting the plurality of conductive pillars and the first electronic element; an auxiliary electronic component, which is disposed on the circuit structure and connected to the circuit structure; as well as A plurality of second electronic components are disposed on the circuit structure and electrically connected to the circuit structure, wherein the plurality of second electronic components are optical chips.

2. The electronic package according to claim 1, wherein: The first electronic component combines and electrically connects a plurality of conductors.

3. The electronic package of claim 2, wherein: The plurality of conductors are covered by the protection film and embedded in the covering layer, and are electrically connected to the circuit structure.

4. The electronic package of claim 1, wherein: The plurality of conductive pillars surround the first electronic component.

5. The electronic package of claim 1, wherein: The auxiliary electronic component is a switch or a semiconductor chip for heat dissipation.

6. The electronic package of claim 1, wherein: The plurality of second electronic components protrude from the side surface of the covering layer.

7. The electronic package of claim 1, wherein: The plurality of second electronic components are externally connected to electrical connectors.

8. The electronic package of claim 1, wherein: The electronic package also includes a circuit portion formed on the second surface of the covering layer and electrically connected to the plurality of conductive pillars.

9. The electronic package of claim 8, wherein: The electronic package also includes a plurality of conductive elements formed on the circuit portion.

10. The electronic package of claim 1, wherein: The electronic package also includes a bearing structure arranged on the second surface of the covering layer.

11. A method for manufacturing an electronic package, comprising: Disposing a plurality of conductive pillars and a first electronic component on a carrier board; Forming a coating layer on the carrier board, and making the coating layer cover the first electronic component and the plurality of conductive pillars, wherein the coating layer has a first surface and a second surface opposite to each other, the end surfaces of the plurality of conductive pillars are exposed on the first surface of the coating layer, and the coating layer is bonded to the carrier board with its second surface; Forming a circuit structure on the first surface of the cladding layer, and making the circuit structure electrically connect the plurality of conductive pillars and the first electronic element, and forming the cladding layer with a side surface adjacent to the first surface and the second surface; Disposing an auxiliary electronic component and a plurality of second electronic components on the circuit structure, and connecting the auxiliary electronic component and the plurality of second electronic components to the circuit structure, wherein the plurality of second electronic components are optical chips; and Remove the carrier plate.

12. The method for manufacturing an electronic package according to claim 11, wherein: The first electronic component combines and electrically connects a plurality of conductors.

13. The method for manufacturing an electronic package according to claim 12, wherein: The plurality of conductors are covered by the protection film and embedded in the covering layer, and are electrically connected to the circuit structure.

14. The method for manufacturing an electronic package according to claim 11, wherein: The plurality of conductive pillars surround the first electronic component.

15. The method for manufacturing an electronic package according to claim 11, wherein: The auxiliary electronic component is a switch or a semiconductor chip for heat dissipation.

16. The method for manufacturing an electronic package according to claim 11, wherein: The plurality of second electronic components protrude from the side surface of the covering layer.

17. The method for manufacturing an electronic package according to claim 11, wherein: The plurality of second electronic components are externally connected to electrical connectors.

18. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes forming a circuit portion on the second surface of the cladding layer, and making the circuit portion electrically connected to the plurality of conductive pillars.

19. The method for manufacturing an electronic package according to claim 18, wherein: The manufacturing method further includes forming a plurality of conductive elements on the circuit portion.

20. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes arranging a bearing structure on the second surface of the coating layer.

Images