Highly integrated ultra-wideband miniaturized low-cost active antenna

Abstract

The application discloses a kind of high integration ultra-wideband miniaturization low-cost active antennas, for radio frequency and antenna integration design, including: planar spiral antenna board, broadband coaxial balun, wave-absorbing foam, back cavity, radio frequency main carrier plate and back plate, the radio frequency main carrier plate includes radio frequency power supply, radio frequency circuit, radio frequency, radio frequency circuit includes radio frequency transceiver front end FE SIP, first frequency conversion circuit MIX1 SIP, intermediate frequency filter circuit IF1 SIP, secondary frequency conversion circuit MIX2 SIP, intermediate frequency circuit IF SIP, anti-aliasing filter AAF and internal integrated VCO frequency synthesizer PLL+VCO, the application has the characteristics of high integration, miniaturization, low cost, and can quickly build the verification platform of different array scheme, without redeveloping microwave front end.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave communication, specifically to a highly integrated, ultra-wideband, miniaturized, and low-cost active antenna. Background Technology

[0002] There are many existing antenna array schemes, but microwave modules have low versatility and no microwave modules that can be applied to multiple array schemes. The separate design of antenna and microwave front-end makes it difficult to achieve miniaturization. Compared with the traditional MCM (Multi-Chip Module) technology, the recently emerging SIP (System in Package) technology is used to package multiple single-function RF dies into a multi-function SIP, reducing metal cavities and RF connectors, achieving low cost and miniaturization. A single-channel independent local oscillator scheme is adopted, and the local oscillator source and single-channel frequency conversion module are integrated into one design. When using multi-channel applications, it is difficult to achieve local oscillator phase synchronization between channels. Summary of the Invention

[0003] The purpose of this invention is to provide a highly integrated, ultra-wideband, miniaturized, and low-cost active antenna to address the shortcomings of narrow operating bandwidth and complex structure mentioned in the background art. Polarization reconfigurable antennas still have considerable room for improvement.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a highly integrated, ultra-wideband, miniaturized, low-cost active antenna, which is an integrated design of radio frequency and antenna, comprising: a planar spiral antenna board, a broadband coaxial balun, absorbing foam, a back cavity, an RF main carrier board, and a backplate. The planar spiral antenna is a composite planar spiral antenna loaded with a sine function. The high-frequency region of the planar spiral antenna uses a tightly wound equiangular spiral, which smoothly transitions to an Archimedean spiral loaded with sine modulation at the tail end. The final antenna board diameter is 63mm, the thickness is 0.8mm, the final antenna size is 60mm, and the VSWR is less than 2.5 in the 0.8-18GHz frequency band.

[0005] The RF mainboard has a diameter of 63mm and a thickness of 2mm. Including components and board thickness, the maximum height is less than 10mm. It mainly includes an RF power supply, RF circuits, and RF components. The RF circuits include a single-channel RF transceiver front-end and a single-channel RF frequency conversion channel. The RF circuits are implemented using SiP technology and include an RF transceiver front-end FE SiP, a first-conversion circuit MIX1 SiP, an intermediate frequency filter circuit IF1 SiP, a second-conversion circuit MIX2 SiP, an intermediate frequency circuit IF SiP, an anti-aliasing filter AAF, and a frequency synthesizer PLL+VCO with an internally integrated VCO. The SiP and the mainboard have a passive transition simulation structure. The SiP top-player microstrip transitions to the SiP bottom layer pads through a simulated pseudo-coaxial structure. The mainboard top layer pads transition to the Layer 2 stripline through a simulated pseudo-coaxial structure. The SiP and the mainboard are soldered using BGA solder balls.

[0006] Preferably, the RF main carrier board TOP LAYER has the RF in and RF out interfaces at its center, the RF transceiver front-end FE SIP at the upper right corner, the first frequency conversion circuit MIX1 SIP at the lower right, the intermediate frequency filter circuit IF1 SIP in the middle of the lower half, the second frequency conversion circuit MIX2 SIP at the lower left, and the intermediate frequency circuit IF SIP at the upper left.

[0007] FE SIP is the RF transceiver front-end, the first stage of the RF link. Internally, it uses RF switches to select the transmit and receive paths. The receive path includes two stages of low-noise amplifiers, an equalizer, and a digitally controlled attenuator; the transmit path includes two stages of power amplifiers (PAs), serving as a driver amplifier and a transmit power amplifier, respectively.

[0008] The MIX1 SIP is the primary frequency conversion circuit, internally integrating a switching filter bank, a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator quadruple frequency circuit.

[0009] The IF1 SIP is an intermediate frequency (IF) filter circuit whose function is to suppress out-of-band mixer intermodulation components and local oscillator, IF, and RF leakage.

[0010] The MIX2 SIP is a double-conversion circuit, internally integrating a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator frequency quadrupling circuit. The IF SIP is an intermediate frequency circuit, including intermediate frequency transmit / receive amplification, receive gain adjustment, transmit / receive band gain equalization, and temperature equalization functions.

[0011] AAF (Anti-aliasing Filter) is used for pre-processing filtering of digital signals to limit the signal bandwidth, ensuring that the signal bandwidth matches the sampling bandwidth of the digital signal processing.

[0012] The PLL+VCO is a frequency synthesizer with an integrated VCO. The selected chip has phase synchronization functionality. When multiple chips reference the same parameter signal, the phase synchronization function can achieve coherent output from multiple chips, satisfying the requirement of local oscillator coherence between channels in multi-channel array configurations.

[0013] The center of the BOT LAYER features a 100MHz PLL reference source input. To the left and right are the local oscillator sources for LO2 and LO1, respectively. The lower left and upper left are the power supply circuits POWER1 and POWER2 of the RF mainboard. The lower right contains the mainboard's control circuit, FPGA, and peripheral circuits. The upper right features the anti-aliasing filter AAF and the intermediate frequency output port.

[0014] The FPGA is the main control chip, and the FPGA plus peripheral circuits form the control circuit.

[0015] Preferably, POWER1 and POWER2 are the power supply circuits of the main carrier board, with an external input voltage of 12V. The board has three voltage conversion functions: 12V to 5V, 5V to 3.3V, and 5V to -5V.

[0016] Preferably, the backplane includes three interfaces: IF in, IF out, REF 100MHz IN, and Power&Ctrl. The backplane has slots at the IF in, IF out, and REF 100MHz IN interfaces. The optical interface can be plugged into SMP-K. M2 threaded holes are drilled on both sides of the interface for fixing external connectors. The Power&Ctrl is a J30J-21ZK interface used for transmission control and power supply.

[0017] Preferably, RF in and RFout are internal interfaces, which are led out using RF insulators and interconnected with the antenna coaxial balun; IFin, IF out and REF 100MHz IN are external interfaces, which are led out using RF insulators; external power and control are led out using pads and soldered to the connector leads locked on the back panel.

[0018] Compared with the prior art, the beneficial effects of the present invention are:

[0019] 1. The advantage of this invention lies in the integrated design of an ultra-wideband miniaturized circularly polarized antenna, an ultra-wideband RF transceiver front-end, and an ultra-wideband transceiver conversion channel, and the miniaturization of the RF circuitry using SIP technology. In phase interferometer direction finding applications, existing phase interferometer direction finding technologies offer various array configurations, such as linear arrays, orthogonal arrays, and uniform circular arrays. Furthermore, the spacing and number of array elements vary depending on the required direction finding accuracy, resulting in diverse array configurations. Traditional phase interferometer designs separate the microwave module from the antenna. Verifying multiple array configurations requires redeveloping the microwave module, leading to high development costs and long development cycles. In contrast, integrating the antenna with a single-channel microwave module only necessitates redesigning the antenna element arrangement, allowing for the rapid construction of verification platforms for various array configurations.

[0020] 2. The system using this active antenna has independent operating frequencies for multiple channels because the local oscillator is integrated into the active antenna. It can simultaneously perform ultra-wideband spectrum monitoring. When direction finding is required for a certain frequency band, multiple channels can operate in the same frequency band, and the phase synchronization function can be used to keep the phase of the local oscillator of multiple channels synchronized. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the antenna of the present invention;

[0022] Figure 2 This is a layout diagram of the RF main carrier board TOP LAYER of the present invention;

[0023] Figure 3 This is a layout diagram of the radio frequency main carrier board (BOT LAYER) of the present invention.

[0024] Figure 4 This is a schematic diagram of the backplane interface of the present invention;

[0025] Figure 5 This is a connection block diagram of the array element system of the present invention;

[0026] Figure 6 This is a schematic diagram of the structure of the present invention.

[0027] Figure 7 This is a schematic diagram of the radio frequency circuit of the present invention.

[0028] 1-Planar spiral antenna board, 2-Broadband coaxial balun, 3-Absorbing foam, 4-Back cavity, 5-RF main carrier board, 6-Backplate. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] This invention provides a highly integrated, ultra-wideband, miniaturized, and low-cost active antenna, featuring an integrated RF and antenna design. From top to bottom, it comprises: a planar helical antenna plate 1, a wideband coaxial balun 2, absorbing foam 3, a back cavity 4, an RF main carrier board 5, and a backplate 6. The planar helical antenna is a composite planar helical antenna with sinusoidal loading. The high-frequency region of the planar helical antenna uses a tightly wound equiangular helix, smoothly transitioning to a sinusoidally modulated Archimedean spiral at the tail end. Using a sinusoidally loaded composite planar helical antenna achieves better circular polarization performance and a wider bandwidth within the same size. The final antenna plate diameter is 63mm, the thickness is 0.8mm, the final antenna size is 60mm, and the VSWR is less than 2.5 in the 0.8-18GHz frequency band.

[0031] The RF main carrier board 5 has a diameter of 63mm and a thickness of 2mm. Including components and board thickness, its maximum height is less than 10mm. It mainly includes an RF power supply, RF circuitry, and RF components. The RF circuitry includes a single-channel RF transceiver front-end and a single-channel RF frequency conversion channel. Its RF circuit schematic is shown below. Figure 7 As shown, to achieve module miniaturization, the RF circuit is implemented using SiP (System-in-Package) technology. This includes the RF transceiver front-end FE SiP, the first frequency conversion circuit MIX1 SiP, the first intermediate frequency filter circuit IF1 SiP, the second frequency conversion circuit MIX2 SiP, the intermediate frequency circuit IF SiP, the anti-aliasing filter AAF, and the frequency synthesizer PLL+VCO with an internally integrated VCO. The simulation shows a passive transition structure between the SiP and the main board. The SiP top layer microstrip transitions to the SiP bottom layer pads via a simulated pseudo-coaxial structure, and the main board top layer pads transition to the Layer 2 stripline via a simulated pseudo-coaxial structure. The SiP and the main board are soldered using BGA solder balls.

[0032] The RF main carrier board 5TOP LAYER has RF in and RF out interfaces in the center, RF transceiver front-end FESIP in the upper right corner, MIX1 SIP for the first frequency conversion circuit in the lower right corner, IF1 SIP for the intermediate frequency filter circuit in the middle of the lower half, MIX2 SIP for the second frequency conversion circuit in the lower left corner, and IF SIP for the intermediate frequency circuit in the upper left corner.

[0033] FE SIP is the RF transceiver front-end, the first stage of the RF link. Internally, it uses RF switches to select the transmit and receive paths. The receive path includes two stages of low-noise amplifiers, an equalizer, and a digitally controlled attenuator; the transmit path includes two stages of power amplifiers (PAs), serving as a driver amplifier and a transmit power amplifier, respectively. Its main functions affect the system's maximum transmit power, receive noise figure, and receive gain.

[0034] The MIX1 SIP is the primary frequency conversion circuit, internally integrating a switching filter bank, a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator frequency multiplier circuit. The switching filter bank suppresses interference signals at image frequencies and undesired frequencies, as well as suppresses out-of-band spurious signals. The main function of the local oscillator filter circuit is to suppress local oscillator harmonics. The function of the local oscillator drive circuit and the local oscillator frequency multiplier circuit is to reduce the module's local oscillator requirements.

[0035] The IF1 SIP is an intermediate frequency filter circuit whose function is to suppress out-of-band mixer intermodulation components and local oscillator, intermediate frequency, and radio frequency leakage.

[0036] The MIX2 SIP is a dual-frequency conversion circuit that integrates a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator frequency multiplier circuit. The main function of the local oscillator filter circuit is to suppress local oscillator harmonics, while the function of the local oscillator drive circuit and the local oscillator frequency multiplier circuit is to reduce the module's local oscillator requirements.

[0037] IF SIP is an intermediate frequency circuit that includes intermediate frequency transmit and receive amplification, receive gain adjustment, transmit and receive gain equalization, and temperature equalization functions.

[0038] AAF stands for Anti-aliasing Filter, used for filtering and limiting the signal bandwidth before digital signal processing, so that the signal bandwidth is the same as the sampling bandwidth of digital signal processing.

[0039] PLL+VCO is a frequency synthesizer with an internally integrated VCO. The selected chip has a phase synchronization function. When multiple chips reference the same parameter signal, the phase synchronization function can achieve coherent output from multiple chips, satisfying the local oscillator coherence between channels in the case of multi-channel array.

[0040] The center of the BOT LAYER is the 100MHz PLL reference source input, then the left and right sides are the local oscillator sources of LO2 and LO1 respectively, the lower left and upper left are the power supply circuits POWER1 and POWER2 of the RF main board 5, the lower right is the control circuit of the main board, FPGA plus peripheral circuits, and the upper right is the anti-aliasing filter AAF and the intermediate frequency output port.

[0041] POWER1 and POWER2 are the power supply circuits of the main carrier board. The external input voltage is 12V. The board has three voltage conversion functions: 12V to 5V, 5V to 3.3V, and 5V to -5V.

[0042] The FPGA is the main control chip, and the FPGA plus peripheral circuits form the control circuit, which has the functions of parsing external control information and controlling the switching of module states.

[0043] RF in and RFout are internal interfaces, which are led out using RF insulators and interconnected with the antenna coaxial balun; IF in, IFout and REF 100MHz IN are external interfaces, which are led out using RF insulators; external power and control are led out using pads and soldered to the connector leads locked on back panel 6.

[0044] Backplane 6 includes three interfaces: IF in, IF out, REF 100MHz IN, and Power&Ctrl. Backplane 6 has slots at the IF in, IF out, and REF 100MHz IN interfaces, and the optical interface can be plugged into SMP-K. M2 threaded holes are drilled on both sides of the interface for fixing external connectors. Power&Ctrl is a J30J-21ZK interface used for transmission control and power supply.

[0045] Operational flow: In the receiving link, the RF signal enters the RF transceiver front-end FE SIP from the antenna for limiting, amplification, and gain adjustment, then enters the first frequency conversion circuit MIX1 SIP for first-intermediate frequency filtering, then enters the first intermediate frequency filter circuit IF1 SIP for first-intermediate frequency filtering, then enters the second frequency conversion circuit MIX2 SIP for second-intermediate frequency mixing and conversion to IF, then enters the intermediate frequency circuit IF SIP for amplification, gain control, and temperature compensation, and finally enters the anti-aliasing filter AAF for anti-aliasing filtering before being output from the IF out port.

[0046] In the transmit link, the IF signal enters from the IF in and IF out ports, is filtered by the anti-aliasing filter AAF, then enters the intermediate frequency circuit IF SIP for amplification, then enters the secondary frequency conversion circuit MIX2 SIP for frequency conversion to the first intermediate frequency, then enters the first intermediate frequency filtering circuit IF1 SIP for first intermediate frequency filtering, then enters the first frequency conversion circuit MIX1 for frequency conversion to RF, and finally enters the RF transceiver front end FESIP for amplification before being sent to the antenna output.

[0047] The technical means disclosed in this invention are not limited to those described above, but also include technical solutions composed of equivalent substitutions of the above technical features. Matters not covered in this invention are common knowledge to those skilled in the art.

Claims

1. A highly integrated, ultra-wideband, miniaturized, low-cost active antenna, characterized by its integrated radio frequency and antenna design, wherein... include: The system comprises a planar helical antenna board, a broadband coaxial balun, absorbing foam, a back cavity, an RF main carrier board, and a backplate. The planar helical antenna on the surface of the planar helical antenna board is a composite planar helical antenna loaded with a sine function. The high-frequency region of the planar helical antenna uses a tightly wound equiangular helix, which smoothly transitions to an Archimedean spiral loaded with sine modulation at the tail end. The RF mainboard includes an RF power supply, RF circuitry, and RF components. The RF circuitry includes a single-channel RF transceiver front-end and a single-channel RF frequency conversion channel. The RF circuitry is implemented using SiP (System-in-Package) technology and includes an RF transceiver front-end (FE SiP), a first-conversion circuit (MIX1 SiP), a first-IF filter circuit (IF1 SiP), a second-conversion circuit (MIX2 SiP), an IF circuit (IFSIP), an anti-aliasing filter (AAF), and a frequency synthesizer (PLL+VCO) with an internally integrated VCO. A passive transition simulation structure is used between the SiP and the mainboard. The SiP top layer microstrip transitions to the SiP bottom layer pads via a simulated pseudo-coaxial structure. The mainboard top layer pads transition to Layer 2 striplines via a simulated pseudo-coaxial structure. The SiP and the mainboard are soldered using BGA solder balls. The RF main carrier board TOP LAYER has RF in and RF out interfaces at its center, RF transceiver front-end FE SIP at the upper right corner, first-conversion circuit MIX1 SIP at the lower right, intermediate frequency filter circuit IF1 SIP in the middle of the lower half, second-conversion circuit MIX2 SIP at the lower left, and intermediate frequency circuit IF SIP at the upper left. FE SIP is the RF transceiver front-end, the first stage of the RF link. Internally, it uses RF switches to select the transmit and receive paths. The receive path includes two stages of low-noise amplifiers, an equalizer, and a digitally controlled attenuator; the transmit path includes two stages of power amplifiers (PAs), serving as a driver amplifier and a transmit power amplifier, respectively. The MIX1 SIP is the primary frequency conversion circuit, internally integrating a switching filter bank, a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator quadruple frequency circuit. IF1 SIP is an intermediate frequency filter circuit. The MIX2 SIP is a double-conversion circuit, internally integrating a local oscillator drive circuit, a local oscillator filter circuit, and a local oscillator frequency quadrupling circuit. The IF SIP is an intermediate frequency circuit, including intermediate frequency transmit / receive amplification, receive gain adjustment, transmit / receive band gain equalization, and temperature equalization functions. AAF (Anti-aliasing Filter) is used for pre-processing filtering of digital signals to limit the signal bandwidth, ensuring that the signal bandwidth matches the sampling bandwidth of the digital signal processing. The PLL+VCO is a frequency synthesizer with an integrated VCO. The selected chip has phase synchronization functionality. When multiple chips reference the same parameter signal, the phase synchronization function can achieve coherent output from multiple chips, satisfying the requirement of local oscillator coherence between channels in multi-channel array configurations. The center of the BOT LAYER features a 100MHz PLL reference source input. To the left and right are the local oscillator sources for LO2 and LO1, respectively. The lower left and upper left are the power supply circuits POWER1 and POWER2 of the RF mainboard. The lower right contains the mainboard's control circuit, FPGA, and peripheral circuits. The upper right features the anti-aliasing filter AAF and the intermediate frequency output port. The FPGA is the main control chip, and the FPGA plus peripheral circuits form the control circuit.

2. The highly integrated, ultra-wideband, miniaturized, low-cost active antenna according to claim 1, characterized in that, POWER1 and POWER2 are the power supply circuits of the main carrier board. The external input voltage is 12V. The board has three voltage conversion functions: 12V to 5V, 5V to 3.3V, and 5V to -5V.

3. The highly integrated, ultra-wideband, miniaturized, low-cost active antenna according to claim 1, characterized in that, The backplane includes three interfaces: IF in, IF out, REF 100MHz IN, and Power&Ctrl. The backplane has slots at the IF in, IF out, and REF100MHz IN interfaces. The optical interface can be plugged into the SMP-K interface. M2 threaded holes are drilled on both sides of the interface for fixing external connectors. The Power&Ctrl interface is a J30J-21ZK interface used for transmission control and power.

4. The highly integrated, ultra-wideband, miniaturized, low-cost active antenna according to claim 1, characterized in that, RFin and RF out are internal interfaces, which are led out using RF insulators and interconnected with the antenna coaxial balun; IF in, IF out and REF100MHz IN are external interfaces, which are led out using RF insulators; external power and control are led out using pads and soldered to the connector leads locked on the back panel.

5. The highly integrated ultra-wideband miniaturized low-cost active antenna according to claim 1, wherein the planar helical antenna plate has a diameter of 63mm and a thickness of 0.8mm, the final antenna size is 60mm, and the standing wave ratio is less than 2.5 in the 0.8-18GHz frequency band.

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