A UPS system busbar balancing hybrid topology circuit

Abstract

An embodiment of the present invention discloses a UPS system bus balancing hybrid topology circuit, comprising: a phase A branch, a phase B branch, a phase C branch, a battery positive discharge unit, a battery negative discharge unit, and a bus balancing unit; the phase A branch includes a first dual-boost PFC circuit; the phase C branch includes a second dual-boost PFC circuit; the phase B branch includes a first switch and a Vienna PFC circuit; the Vienna PFC circuit includes a bus balancing unit connected to the first switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected to batteries; and each circuit is respectively connected to a DC power supply. By implementing the circuit of the embodiment of the present invention, it is possible to eliminate battery midpoint cables and achieve battery voltage balancing by adding a bus balancing circuit, reducing cable installation costs and lowering the complexity and cost of PCB design.

Description

Technical Field

[0001] The present invention relates to the technical field of UPS systems, and in particular to a UPS system busbar balancing hybrid topology circuit. Background Art

[0002] In conventional three-phase uninterruptible power supply systems, most inverters use a three-level inverter structure, which includes a positive bus and a negative bus. In order to effectively manage the battery current, the battery discharge circuit is usually divided into a positive side battery discharge circuit and a negative side battery discharge circuit, such as Figure 1 As shown in Figure 1, a battery pack generally consists of two parts: a positive battery pack and a negative battery pack. The battery pack is connected to the UPS system via three main cables: a positive battery cable connected to the positive terminal of the battery pack, a midpoint battery cable connected to the midpoint of the battery pack, and a negative battery cable connected to the negative terminal of the battery pack.

[0003] In conventional applications, the wire diameter of the battery midpoint cable should be consistent with the wire diameter of the battery positive and negative cables to ensure balanced current distribution. However, in actual applications, especially when the power of the UPS system is large, the installation cost of the battery midpoint cable may be very high. This is because the battery midpoint cable hardly carries current under normal working conditions, and only carries current under special circumstances such as a short circuit at the UPS end. Therefore, the cost performance of the battery midpoint cable is relatively low. In order to reduce the cost of cable installation, reduce waste, and contribute to energy conservation and emission reduction, the industry hopes to remove the battery midpoint cable. To this end, one of the current technical solutions is to introduce a bus balancing circuit, such as Figure 2 As shown in Figure 1, inductor L3 and switching elements Q3 and Q4 form a busbar balancing circuit, which maintains battery pack balance by adjusting the voltage difference between the positive and negative busbars. The introduction of this balancing circuit effectively fulfills the function of a battery pack midpoint cable, eliminating the battery midpoint cable in the design. A side effect of this solution is that it increases PCB size and cost.

[0004] Therefore, it is necessary to design a new circuit that can not only remove the battery midpoint cable and achieve battery voltage balance by adding a bus balancing circuit, reduce the cable installation cost, but also reduce the increase in PCB design complexity and cost. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide a UPS system busbar balancing hybrid topology circuit.

[0006] To solve the above technical problems, the objective of the present invention is achieved through the following technical solutions: providing a UPS system bus balancing hybrid topology circuit, comprising: an A-phase branch, a B-phase branch, a C-phase branch, a battery positive discharge unit, a battery negative discharge unit, and a bus balancing unit; the A-phase branch comprises a first dual-BOOST PFC circuit; the C-phase branch comprises a second dual-BOOST PFC circuit; the B-phase branch comprises a first switching switch and a Vienna PFC circuit; the Vienna PFC circuit comprises the bus balancing unit, and the Vienna PFC circuit is connected to the first switching switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected to a battery; and the first dual-BOOST PFC circuit, the second dual-BOOST PFC circuit, and the Vienna PFC circuit are respectively connected to a DC power supply.

[0007] Its further technical solution is: the DC power supply includes a positive pole and a negative pole; the bus balancing unit includes a second switching switch RLY2, an inductor L5, a switching element Q9 and a switching element Q10; one end of the second switching switch RLY2 is connected to one end of the inductor L5; one end of the switching element Q9 and the switching element Q10 are respectively connected to the other end of the inductor L5; the other end of the switching element Q9 is connected to the DC power supply positive discharge unit; and the other end of the switching element Q10 is connected to the negative pole of the DC power supply.

[0008] A further technical solution is as follows: the switching element Q9 and the switching element Q10 are switching tubes with integrated anti-parallel diodes.

[0009] Its further technical solution is: the Vienna PFC circuit includes the inductor L5, the switching element Q9, the switching element Q10, the switching tube Q11 with an integrated anti-parallel diode, and the switching tube Q12 with an integrated anti-parallel diode; one end of the switching tube Q11 with an integrated anti-parallel diode is connected to the other end of the inductor L5; the other end of the switching tube Q11 with an integrated anti-parallel diode is connected to one end of the switching tube Q12 with an integrated anti-parallel diode; the other end of the switching tube Q12 with an integrated anti-parallel diode is connected to the neutral point.

[0010] Its further technical solution is: the bus balancing unit includes a switch tube Q11 with an integrated anti-parallel diode, a switch tube Q12 with an integrated anti-parallel diode, an inductor L5, a switch element Q9 and a switch element Q10; one end of the switch element Q9 and the switch element Q10 are respectively connected to one end of the inductor L5; one end of the inductor L5 is connected to the first switching switch; the other end of the inductor L5 is connected to one end of the switch tube Q11 with an integrated anti-parallel diode; the other end of the switch tube Q11 with an integrated anti-parallel diode is connected to one end of the switch tube Q12 with an integrated anti-parallel diode; the other end of the switch tube Q12 with an integrated anti-parallel diode is connected to the neutral point.

[0011] Its further technical solution is: the Vienna PFC circuit includes the inductor L5, the switching element Q9, the switching element Q10, the diode D5 and the diode D6; one end of the diode D5 and the diode D6 are respectively connected to the other end of the inductor L5; the other end of the diode D5 is connected to the neutral point; the other end of the diode D6 is connected to the neutral point.

[0012] Its further technical solution is: the first dual BOOST PFC circuit includes a thyristor Q1, a thyristor Q2, an inductor L1, an inductor L4, a switch tube Q15 with an integrated anti-parallel diode, a switch tube Q16 with an integrated anti-parallel diode, a diode D1, and a diode D4; one end of the thyristor Q1 is connected to the neutral point, the other end of the thyristor Q1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the diode D1, and the other end of the diode D1 is connected to the positive electrode of the DC power supply; one end of the thyristor Q2 is connected to the neutral point, the other end of the thyristor Q2 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to one end of the diode D4, and the other end of the diode D4 is connected to the negative electrode of the DC power supply.

[0013] Its further technical solution is: the second dual BOOST PFC circuit includes a thyristor Q3, a thyristor Q4, an inductor L2, an inductor L3, a switch tube Q13 with an integrated anti-parallel diode, a switch tube Q14 with an integrated anti-parallel diode, a diode D2, and a diode D3; one end of the thyristor Q3 is connected to the neutral point, the other end of the thyristor Q3 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to one end of the diode D2, and the other end of the diode D2 is connected to the positive electrode of the DC power supply; one end of the thyristor Q4 is connected to the neutral point, the other end of the thyristor Q4 is connected to one end of the inductor L3, the other end of the inductor L3 is connected to one end of the diode D3, and the other end of the diode D3 is connected to the negative electrode of the DC power supply.

[0014] Its further technical solution is: the battery includes a positive electrode and a negative electrode, and the battery positive and discharge unit includes a thyristor Q5, a thyristor Q7, the inductor L1, the inductor L2, the switch tube Q13 with an integrated anti-parallel diode, the switch tube Q15 with an integrated anti-parallel diode, the diode D1, and the diode D2; one end of the thyristor Q5 and the thyristor Q7 are respectively connected to the positive electrode of the battery; the other end of the thyristor Q5 is connected to one end of the inductor L2, and the other end of the thyristor Q7 is connected to one end of the inductor L1.

[0015] Its further technical solution is: the battery negative discharge unit includes a thyristor Q6, a thyristor Q8, the inductor L3, the inductor L4, the switch tube Q14 with an integrated anti-parallel diode, the switch tube Q16 with an integrated anti-parallel diode, a diode D3, and a diode D4; one end of the thyristor Q6 and the thyristor Q8 are respectively connected to the negative electrode of the battery; the other end of the thyristor Q6 is connected to one end of the inductor L3, and the other end of the thyristor Q8 is connected to one end of the inductor L4.

[0016] The beneficial effects of the present invention compared with the prior art are as follows: the present invention provides A-phase, B-phase and C-phase branches, as well as a battery discharge unit and a bus balancing unit. The A-phase branch and the C-phase branch each include a dual BOOST PFC circuit, while the B-phase branch is equipped with a Vienna PFC circuit and a first switching switch. All of these circuit units are connected to a DC power supply and a battery. The Vienna PFC circuit includes a bus balancing unit. By reusing the rectifier power devices of the Vienna PFC, a balanced circuit structure is formed. This can not only remove the battery midpoint cable and achieve battery voltage balance by adding a bus balancing circuit, thereby reducing cable installation costs, but also reduce the increase in PCB design complexity and cost.

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A circuit schematic diagram of a battery discharge circuit in the prior art;

[0020] Figure 2 A circuit schematic diagram of a bus balancing circuit in the prior art;

[0021] Figure 3A schematic diagram illustrating a bus balancing hybrid topology circuit for a UPS system according to an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the current flow direction of the A-phase branch of a UPS system bus balancing hybrid topology circuit in the positive half-cycle inductor L1 energy storage stage provided by an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the current flow direction of the phase A branch of a UPS system bus balancing hybrid topology circuit in the positive half-cycle inductor L1 energy release stage provided by an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of the current flow direction of the phase A branch of a UPS system bus balancing hybrid topology circuit in the negative half-cycle inductor L4 energy storage stage provided by an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of the current flow in the A-phase branch of a UPS system bus balancing hybrid topology circuit in the negative half-cycle inductor L4 energy release stage provided by an embodiment of the present invention;

[0026] Figure 8 A schematic diagram of the current flow direction of the B-phase branch of a UPS system bus balancing hybrid topology circuit in the positive half-cycle inductor L5 energy storage stage provided by an embodiment of the present invention;

[0027] Figure 9 A schematic diagram of the current flow direction of the B-phase branch of a UPS system bus balancing hybrid topology circuit in the positive half-cycle inductor L5 energy release stage provided by an embodiment of the present invention;

[0028] Figure 10 A schematic diagram of the current flow direction of the B-phase branch of a UPS system bus balancing hybrid topology circuit in the negative half-cycle inductor L5 energy storage stage provided by an embodiment of the present invention;

[0029] Figure 11 A schematic diagram of the current flow direction of the B-phase branch of a UPS system bus balancing hybrid topology circuit in the negative half-cycle inductor L5 energy release stage provided by an embodiment of the present invention;

[0030] Figure 12 A schematic diagram of the current flow during the energy storage phase of the battery positive discharge inductor L1 in the A-phase branch of a UPS system busbar balancing hybrid topology circuit provided by an embodiment of the present invention;

[0031] Figure 13 A schematic diagram of the current flow during the energy storage and release phase of the battery positive discharge inductor L1 in the A-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0032] Figure 14 A schematic diagram of the current flow during the energy storage phase of the C-phase branch battery positive electrode discharge inductor L2 of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0033] Figure 15 A schematic diagram of the current flow during the energy release phase of the C-phase branch battery positive electrode discharge inductor L2 of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0034] Figure 16 A schematic diagram of the current flow during the energy storage phase of the battery negative electrode discharge inductor L4 in the A-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0035] Figure 17 A schematic diagram of the current flow during the energy storage and release phase of the battery negative electrode discharge inductor L4 in the A-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0036] Figure 18 A schematic diagram of the current flow during the energy storage phase of the battery negative electrode discharge inductor L3 in the C-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0037] Figure 19 A schematic diagram of the current flow during the energy release phase of the battery negative electrode discharge inductor L3 in the C-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention;

[0038] Figure 20 A schematic diagram of the current flow during the energy storage stage of the inductor L5 in the positive busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention, transferring energy from the positive busbar to the negative busbar;

[0039] Figure 21 A schematic diagram of the current flow during the energy release phase of the inductor L5 in the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention, when the positive busbar transfers energy to the negative busbar;

[0040] Figure 22 A schematic diagram of the current flow during the energy storage stage of the inductor L5 in the negative busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention, transferring energy to the positive busbar;

[0041] Figure 23 A schematic diagram of the current flow during the energy release phase of the inductor L5 in the negative busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by an embodiment of the present invention, transferring energy to the positive busbar;

[0042] Figure 24 A schematic diagram illustrating a bus balancing hybrid topology circuit for a UPS system according to another embodiment of the present invention;

[0043] Figure 25 A schematic diagram of current flow during the energy storage stage of the inductor L5 in the positive busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by another embodiment of the present invention;

[0044] Figure 26 A schematic diagram of current flow during the energy release phase of the inductor L5 in a UPS system bus balancing hybrid topology circuit of the phase B branch transferring energy from the positive bus to the negative bus, provided by another embodiment of the present invention;

[0045] Figure 27 A schematic diagram of current flow during the energy storage phase of the inductor L5 in the negative busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by another embodiment of the present invention;

[0046] Figure 28 A schematic diagram of current flow during the energy release stage of the inductor L5 in the negative busbar of the B-phase branch of a UPS system bus balancing hybrid topology circuit provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0049] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] The introduction of an existing balancing circuit can effectively realize the function of the battery pack's midpoint cable, thereby removing the battery midpoint cable from the design. A side effect of this solution is that it increases the size and cost of the PCB.

[0052] To this end, an embodiment of the present invention proposes a UPS system busbar balanced hybrid topology circuit, in which the A / C phases are dual-boost PFC circuits, and the B phase is a Vienna PFC circuit. By reusing the rectifier power devices of the Vienna PFC, a balanced circuit structure is formed, thereby reducing system cost and PCB size.

[0053] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0054] See also Figures 3 to 23 A UPS system bus balancing hybrid topology circuit includes: an A-phase branch, a B-phase branch, a C-phase branch, a battery positive discharge unit, a battery negative discharge unit, and a bus balancing unit; the A-phase branch includes a first dual-BOOST PFC circuit; the C-phase branch includes a second dual-BOOST PFC circuit; the B-phase branch includes a first switch and a Vienna PFC circuit; the Vienna PFC circuit includes a bus balancing unit, and the Vienna PFC circuit is connected to the first switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected to a battery; the first dual-BOOST PFC circuit, the second dual-BOOST PFC circuit, and the Vienna PFC circuit are respectively connected to a DC power supply.

[0055] The A-phase branch, the B-phase branch, and the C-phase branch are connected to the mains respectively.

[0056] Dual Boost PFC circuit (Phase A and Phase C): Improves the power factor and raises the input voltage to the required voltage level; Vienna PFC circuit (Phase B): Improves the power factor and has a built-in bus balancing unit, which maintains bus voltage stability by balancing current distribution, reducing the need for additional cables.

[0057] By reusing the rectifier power devices of the Vienna PFC circuit, bus balancing function is achieved, avoiding additional cable wiring, thereby reducing PCB size and overall system cost; reducing midpoint cables, reducing wiring complexity and possible failure points; adopting a hybrid topology structure to optimize circuit design, making the system more integrated; and optimizing the balancing circuit in traditional UPS systems.

[0058] In one embodiment, see Figure 3 The above-mentioned DC power supply includes a positive electrode and a negative electrode; the bus balancing unit includes a second switching switch RLY2, an inductor L5, a switching element Q9 and a switching element Q10; one end of the second switching switch RLY2 is connected to one end of the inductor L5; one end of the switching element Q9 and one end of the switching element Q10 are respectively connected to the other end of the inductor L5; the other end of the switching element Q9 is connected to the DC power supply positive discharge unit; and the other end of the switching element Q10 is connected to the negative electrode of the DC power supply.

[0059] In one embodiment, see Figure 3 The switching element Q9 and the switching element Q10 are switching tubes with integrated anti-parallel diodes.

[0060] In one embodiment, see Figure 3 The Vienna PFC circuit includes an inductor L5, a switching element Q9, a switching element Q10, a switching tube Q11 with an integrated anti-parallel diode, and a switching tube Q12 with an integrated anti-parallel diode; one end of the switching tube Q11 with an integrated anti-parallel diode is connected to the other end of the inductor L5; the other end of the switching tube Q11 with an integrated anti-parallel diode is connected to one end of the switching tube Q12 with an integrated anti-parallel diode; and the other end of the switching tube Q12 with an integrated anti-parallel diode is connected to the neutral point.

[0061] In one embodiment, see Figure 3 The first dual BOOST PFC circuit includes a thyristor Q1, a thyristor Q2, an inductor L1, an inductor L4, a switch tube Q15 with an integrated anti-parallel diode, a switch tube Q16 with an integrated anti-parallel diode, a diode D1, and a diode D4; one end of the thyristor Q1 is connected to the neutral point, the other end of the thyristor Q1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the diode D1, and the other end of the diode D1 is connected to the positive electrode of the DC power supply; one end of the thyristor Q2 is connected to the neutral point, the other end of the thyristor Q2 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to one end of the diode D4, and the other end of the diode D4 is connected to the negative electrode of the DC power supply.

[0062] In one embodiment, see Figure 3The second dual-BOOST PFC circuit includes a thyristor Q3, a thyristor Q4, an inductor L2, an inductor L3, a switch tube Q13 with an integrated anti-parallel diode, a switch tube Q14 with an integrated anti-parallel diode, a diode D2, and a diode D3; one end of the thyristor Q3 is connected to the neutral point, the other end of the thyristor Q3 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to one end of the diode D2, and the other end of the diode D2 is connected to the positive electrode of the DC power supply; one end of the thyristor Q4 is connected to the neutral point, the other end of the thyristor Q4 is connected to one end of the inductor L3, the other end of the inductor L3 is connected to one end of the diode D3, and the other end of the diode D3 is connected to the negative electrode of the DC power supply.

[0063] In one embodiment, see Figure 3 The above-mentioned battery includes a positive electrode and a negative electrode. The battery positive and discharge unit includes a thyristor Q5, a thyristor Q7, an inductor L1, an inductor L2, a switch tube Q13 with an integrated anti-parallel diode, a switch tube Q15 with an integrated anti-parallel diode, a diode D1, and a diode D2. One end of the thyristor Q5 and the thyristor Q7 are respectively connected to the positive electrode of the battery; the other end of the thyristor Q5 is connected to one end of the inductor L2, and the other end of the thyristor Q7 is connected to one end of the inductor L1.

[0064] The battery positive discharge unit includes two paths, and the two paths are cross-connected in parallel.

[0065] In one embodiment, see Figure 3 The above-mentioned battery negative discharge unit includes a thyristor Q6, a thyristor Q8, an inductor L3, an inductor L4, a switch tube Q14 with an integrated anti-parallel diode, a switch tube Q16 with an integrated anti-parallel diode, a diode D3, and a diode D4; one end of the thyristor Q6 and the thyristor Q8 are respectively connected to the negative electrode of the battery; the other end of the thyristor Q6 is connected to one end of the inductor L3, and the other end of the thyristor Q8 is connected to one end of the inductor L4.

[0066] The battery negative discharge unit includes two paths, and the two paths are staggered and connected in parallel.

[0067] In one embodiment, a capacitor C1 is connected between the positive electrode of the DC power supply and the neutral point, and a capacitor C2 is connected between the neutral point and the negative electrode of the DC power supply.

[0068] When the UPS operates in primary mode, the first switch (relay RLY1 in this embodiment) of the phase B branch is closed, the second switch RLY2 is open, and switching elements Q9 and Q10 are not driven. Only the anti-parallel diodes in switching elements Q9 and Q10 are active, and the circuit primarily implements the PFC function. The energy flow in primary mode specifically includes the following:

[0069] See also Figure 4When the A-phase branch is in the positive half cycle, the switch tube Q15 with integrated anti-parallel diode is turned on. At this time, the current starts from the neutral point, passes through the thyristor Q1, the inductor L1, the switch tube Q15 with integrated anti-parallel diode in sequence, and then returns to the neutral point. During the whole process, the inductor L1 is in the energy storage state.

[0070] See also Figure 5 When the A-phase branch is in the positive half cycle, the switch tube Q15 with the integrated anti-parallel diode is turned off. At this time, the current starts from the neutral point, passes through the thyristor Q1, inductor L1, diode D1, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L1 is in the energy release state.

[0071] See also Figure 6 When the A-phase branch is in the negative half cycle, the switch tube Q16 with integrated anti-parallel diode is turned on. At this time, the current starts from the neutral point, passes through the switch tube Q16 with integrated anti-parallel diode, inductor L4, thyristor Q2 in sequence, and then returns to the neutral point. During the whole process, the inductor L4 is in the energy storage state.

[0072] See also Figure 7 When the A-phase branch is in the negative half cycle, the switch tube Q16 with the integrated anti-parallel diode is turned off. At this time, the current starts from the neutral point, passes through the capacitor C2, the diode D4, the inductor L4, the thyristor Q2 in sequence, and then returns to the neutral point. During the whole process, the inductor L4 is in the energy release state.

[0073] See also Figure 8 When the B-phase branch is in the positive half cycle, the switch tube Q11 with integrated anti-parallel diode and the switch tube Q12 with integrated anti-parallel diode are turned on. At this time, the current starts from the neutral point, passes through the first switch, the inductor L5, the switch tube Q11 with integrated anti-parallel diode, and the switch tube Q12 with integrated anti-parallel diode, and then returns to the neutral point. During the whole process, the inductor L5 is in an energy storage state.

[0074] See also Figure 9 When the B-phase branch is in the positive half cycle, the switch tube Q11 with integrated anti-parallel diode and the switch tube Q12 with integrated anti-parallel diode are turned off. At this time, the current starts from the neutral point, passes through the first switching switch, inductor L5, switching element Q9, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L5 is in a state of releasing energy.

[0075] See also Figure 10 When the B-phase branch is in the negative half cycle, the switch tube Q14 with integrated anti-parallel diode is turned on. The current starts from the neutral point, passes through the switch tube Q12 with integrated anti-parallel diode, the switch tube Q11 with integrated anti-parallel diode, the inductor L5 and the first switching switch in sequence, and then returns to the neutral point. During the whole process, the inductor L5 is in an energy storage state.

[0076] See also Figure 11 When the B-phase branch is in the negative half cycle, the switch tube Q14 with the integrated anti-parallel diode is turned off. The current starts from the neutral point, passes through the capacitor C2, the switching element Q10, the inductor L5 and the first switching switch in sequence, and then returns to the neutral point. During the whole process, the inductor L5 is in the energy release state.

[0077] When the C-phase branch is in the positive half cycle, the switch tube Q13 with an integrated anti-parallel diode is turned on. At this time, the current starts from the neutral point, passes through the thyristor Q3, the inductor L2, the switch tube Q13 with an integrated anti-parallel diode in sequence, and then returns to the neutral point. During the whole process, the inductor L2 is in an energy storage state.

[0078] When the C-phase branch is in the positive half cycle, the switch tube Q13 with an integrated anti-parallel diode is turned off. At this time, the current starts from the neutral point, passes through the thyristor Q3, inductor L2, diode D2, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L2 is in a state of releasing energy.

[0079] When the C-phase branch is in the negative half cycle, the switch tube Q14 with an integrated anti-parallel diode is turned on. At this time, the current starts from the neutral point, passes through the switch tube Q14 with an integrated anti-parallel diode, the inductor L3, and the thyristor Q4 in sequence, and then returns to the neutral point. During the whole process, the inductor L3 is in an energy storage state.

[0080] When the C-phase branch is in the negative half cycle, the switch tube Q14 with an integrated anti-parallel diode is turned off. At this time, the current starts from the neutral point, passes through the capacitor C2, the diode D3, the inductor L3, the thyristor Q4 in sequence, and then returns to the neutral point. During the whole process, the inductor L3 is in a state of releasing energy.

[0081] When the UPS operates in battery mode, the positive side circuit of the A / C phase branch of the PFC realizes the positive side discharge function of the battery, the negative side circuit of the A / C phase branch realizes the negative side discharge function of the battery, and the B phase branch realizes the balancing bridge function. The specific energy flow includes the following:

[0082] See also Figure 12 For the A-phase branch, when the positive electrode of the battery is discharging and the switch tube Q15 with integrated anti-parallel diode is turned on, the current starts from the positive electrode of the battery, passes through the thyristor Q7, the inductor L1, the switch tube Q15 with integrated anti-parallel diode in sequence, and then returns to the neutral point. During the whole process, the inductor L1 is in an energy storage state;

[0083] See also Figure 13 For the phase A branch, when the positive electrode of the battery is discharged, when the switch tube Q15 with integrated anti-parallel diode is turned off, the current starts from the positive electrode of the battery, passes through the thyristor Q7, inductor L1, diode D1, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L1 is in the energy release state;

[0084] See also Figure 14For the C-phase branch, when the positive electrode of the battery is discharging and the switch tube Q13 with integrated anti-parallel diode is turned on, the current starts from the positive electrode of the battery, passes through the thyristor Q5, the inductor L1, the switch tube Q13 with integrated anti-parallel diode in sequence, and then returns to the neutral point. During the whole process, the inductor L2 is in an energy storage state;

[0085] See also Figure 15 For the C-phase branch, when the positive electrode of the battery is discharging, when the switch tube Q13 with the integrated anti-parallel diode is turned off, the current starts from the positive electrode of the battery, passes through the thyristor Q5, inductor L2, diode D2, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L2 is in the energy release state;

[0086] See also Figure 16 For the A-phase branch, when the negative electrode of the battery is discharged, when the switch tube Q16 with integrated anti-parallel diode is turned on, the current starts from the neutral point, passes through the switch tube Q16 with integrated anti-parallel diode, inductor L4, thyristor Q8 in sequence, and then returns to the negative electrode of the battery. During the whole process, the inductor L4 is in an energy storage state;

[0087] See also Figure 17 For the A-phase branch, when the negative electrode of the battery is discharged, when the switch tube Q16 with the integrated anti-parallel diode is turned off, the current starts from the neutral point and passes through the capacitor C2, diode D4, inductor L4, and thyristor Q8 in sequence to return to the negative electrode of the battery. During the whole process, the inductor L4 is in the energy release state;

[0088] See also Figure 18 For the C-phase branch, when the negative electrode of the battery is discharging, when the switch tube Q14 with integrated anti-parallel diode is turned on, the current starts from the neutral point, passes through the switch tube Q14 with integrated anti-parallel diode, inductor L3, thyristor Q6 in sequence, and then returns to the negative electrode of the battery. During the whole process, the inductor L3 is in an energy storage state;

[0089] See also Figure 19 For the C-phase branch, when the negative electrode of the battery is discharged and the switch tube Q13 with an integrated anti-parallel diode is turned off, the current starts from the neutral point and passes through the capacitor C2, diode D3, inductor L3, and thyristor Q6 in sequence back to the negative electrode of the battery. During the whole process, the inductor L3 is in an energy release state.

[0090] Among them, the discharge work of the positive electrode of the battery in the A / C phase branch is staggered in parallel, and the discharge work of the negative electrode of the battery in the A / C phase branch is staggered in parallel.

[0091] In the B-phase branch, the relay RLY1 (the first switch) is disconnected, and the second switch RLY2 is closed. Switching elements Q9, Q10, and inductor L5 form a balanced circuit. The working energy flow diagram is as follows:

[0092] See also Figure 20, the positive busbar transfers energy to the negative busbar, and the switch element Q9 is turned on. At this time, the current starts from the neutral point, passes through the capacitor C1, the switch element Q9, the inductor L5 in sequence, and then returns to the neutral point through the second switch. During the whole process, the inductor L5 is in a state of storing energy;

[0093] See also Figure 21 , the positive busbar transfers energy to the negative busbar, and the switch element Q9 is turned off. At this time, the current starts from the neutral point, passes through the capacitor C2, the switch element Q10, the inductor L5, and then returns to the neutral point through the second switch. During the whole process, the inductor L5 is in a state of releasing energy;

[0094] See also Figure 22 , the negative busbar transfers energy to the positive busbar, and the switch element Q10 is turned on. At this time, the current starts from the neutral point, passes through the second switch, inductor L5, switch element Q10, capacitor C2 in sequence, and then returns to the neutral point. During the whole process, the inductor L5 is in the energy storage state;

[0095] See also Figure 23 , the negative bus transfers energy to the positive bus, and the switching element Q10 is turned off. At this time, the current starts from the neutral point, passes through the second switch, inductor L5, switching element Q9, capacitor C1 in sequence, and then returns to the neutral point. During the whole process, the inductor L5 is in a state of releasing energy.

[0096] In another embodiment, see Figure 24 The bus balancing unit includes a switch tube Q11 with an integrated anti-parallel diode, a switch tube Q12 with an integrated anti-parallel diode, an inductor L5, a switching element Q9, and a switching element Q10; one end of the switching element Q9 and the switching element Q10 are respectively connected to one end of the inductor L5; one end of the inductor L5 is connected to the first switch; the other end of the inductor L5 is connected to one end of the switch tube Q11 with an integrated anti-parallel diode; the other end of the switch tube Q11 with an integrated anti-parallel diode is connected to one end of the switch tube Q12 with an integrated anti-parallel diode; and the other end of the switch tube Q12 with an integrated anti-parallel diode is connected to the neutral point.

[0097] In one embodiment, see Figure 24 The Vienna PFC circuit includes an inductor L5, a switching element Q9, a switching element Q10, a diode D5, and a diode D6; one end of the diode D5 and the diode D6 are respectively connected to the other end of the inductor L5; the other end of the diode D5 is connected to the neutral point; the other end of the diode D6 is connected to the neutral point.

[0098] This embodiment can save on the number of transistors and achieve PFC and balanced bridge functions. This variant topology places the arms of the balanced bridge separately, i.e., diodes D5 and D6 are inoperative. Switching element Q9, switching element Q10, inductor L5, switching tube Q11 with integrated anti-parallel diode, and switching tube Q12 with integrated anti-parallel diode form a balanced bridge. The switching tubes Q11 with integrated anti-parallel diode and Q12 with integrated anti-parallel diode form a balanced bridge to achieve the function of the second switching switch in the first embodiment. In battery mode, the first switching switch is disconnected, and the switching tubes Q11 with integrated anti-parallel diode and Q12 with integrated anti-parallel diode are normally on. Switching element Q9, switching element Q10, and inductor L5 form a balanced bridge topology. Its energy flow diagram is shown below:

[0099] See also Figure 25 , the positive busbar transfers energy to the negative busbar, the switch element Q9 is turned on, and the current starts from one end of the capacitor C1, passes through the switch element Q9, the inductor L5, the switch tube Q11 with an integrated anti-parallel diode, and the switch tube Q12 with an integrated anti-parallel diode, and then returns to the other end of the capacitor C1. During the whole process, the inductor L5 is in a state of storing energy;

[0100] See also Figure 26 , the positive busbar transfers energy to the negative busbar, the switch element Q9 is turned off, and the current starts from one end of the capacitor C2, passes through the switch element Q10, the inductor L5, the switch tube Q11 with an integrated anti-parallel diode, and the switch tube Q12 with an integrated anti-parallel diode, and then returns to the other end of the capacitor C2. During the whole process, the inductor L5 is in a state of storing energy;

[0101] See also Figure 27 , the negative busbar transfers energy to the positive busbar, the switch element Q10 is turned on, and the current starts from one end of the capacitor C2, passes through the switch tube Q12 with integrated anti-parallel diode, the switch tube Q11 with integrated anti-parallel diode, the inductor L5, the switch element Q10, and returns to the other end of the capacitor C2. During the whole process, the inductor L5 is in a state of storing energy;

[0102] See also Figure 28 , the negative bus transfers energy to the positive bus, the switching element Q10 is turned off, and the current starts from one end of the capacitor C1, passes through the switching tube Q12 with integrated anti-parallel diode, the switching tube Q11 with integrated anti-parallel diode, the inductor L5, the switching element Q9, and returns to the other end of the capacitor C1. During the whole process, the inductor L5 is in an energy storage state.

[0103] The above-mentioned UPS system bus balancing hybrid topology circuit is provided with A-phase, B-phase and C-phase branches, as well as a battery discharge unit and a bus balancing unit. The A-phase branch and the C-phase branch each contain a dual BOOST PFC circuit, while the B-phase branch is equipped with a Vienna PFC circuit and a first switching switch. All these circuit units are connected to a DC power supply and a battery. The Vienna PFC circuit includes a bus balancing unit. By reusing the rectifier power devices of the Vienna PFC, a balanced circuit structure is formed. This can not only remove the battery midpoint cable and achieve battery voltage balance by adding a bus balancing circuit, thereby reducing cable installation costs, but also reduce the increase in PCB design complexity and cost.

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A UPS system busbar balancing hybrid topology circuit, characterized in that: include: Phase A branch, phase B branch, phase C branch, a battery positive discharge unit, a battery negative discharge unit, and a bus balancing unit; the phase A branch includes a first dual BOOST PFC circuit; the phase C branch includes a second dual BOOST PFC circuit; the phase B branch includes a first switch and a Vienna PFC circuit; the Vienna PFC circuit includes the bus balancing unit, and the Vienna PFC circuit is connected to the first switch; the battery positive discharge unit and the battery negative discharge unit are respectively connected to a battery; the first dual BOOST PFC circuit, the second dual BOOST PFC circuit, and the Vienna PFC circuit are respectively connected to a DC power supply; The DC power supply includes a positive electrode and a negative electrode; the bus balancing unit includes a switch tube Q11 with an integrated anti-parallel diode, a switch tube Q12 with an integrated anti-parallel diode, a second switch RLY2, an inductor L5, a switch element Q9, and a switch element Q10; one end of the second switch RLY2 is connected to one end of the inductor L5; one end of the switch element Q9 and one end of the switch element Q10 are respectively connected to the other end of the inductor L5; the other end of the switch element Q9 is connected to the DC power supply positive discharge unit; the other end of the switch element Q10 is connected to the negative electrode of the DC power supply; and the other end of the second switch RLY2 is connected to the neutral point. One end of the inductor L5 is connected to the first switching switch; the other end of the inductor L5 is connected to one end of the switch tube Q11 with an integrated anti-parallel diode; the other end of the switch tube Q11 with an integrated anti-parallel diode is connected to one end of the switch tube Q12 with an integrated anti-parallel diode; the other end of the switch tube Q12 with an integrated anti-parallel diode is connected to the neutral point.

2. A UPS system bus balancing hybrid topology circuit according to claim 1, characterized in that: The switching element Q9 and the switching element Q10 are switching tubes with integrated anti-parallel diodes.

3. The UPS system busbar balancing hybrid topology circuit according to claim 2, characterized in that: The Vienna PFC circuit includes the inductor L5, the switching element Q9, the switching element Q10, a diode D5, and a diode D6; one end of the diode D5 and the diode D6 are respectively connected to the other end of the inductor L5; the other end of the diode D5 is connected to the positive electrode; and the other end of the diode D6 is connected to the negative electrode.

4. The UPS system bus balancing hybrid topology circuit according to any one of claims 1 to 3, characterized in that: The first dual BOOST PFC circuit includes a thyristor Q1, a thyristor Q2, an inductor L1, an inductor L4, a switch tube Q15 with an integrated anti-parallel diode, a switch tube Q16 with an integrated anti-parallel diode, a diode D1, and a diode D4; one end of the thyristor Q1 is connected to phase A, the other end of the thyristor Q1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the diode D1, and the other end of the diode D1 is connected to the positive electrode of the DC power supply; one end of the thyristor Q2 is connected to phase A, the other end of the thyristor Q2 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to one end of the diode D4, and the other end of the diode D4 is connected to the negative electrode of the DC power supply, one end of the switch tube Q15 with an integrated anti-parallel diode and the other end of the switch tube Q16 with an integrated anti-parallel diode are connected to the neutral point; the other end of the switch tube Q15 with an integrated anti-parallel diode is connected to the positive electrode; the other end of the switch tube Q16 with an integrated anti-parallel diode is connected to the negative electrode.

5. The UPS system bus balancing hybrid topology circuit according to claim 4, characterized in that: The second dual BOOST PFC circuit includes a thyristor Q3, a thyristor Q4, an inductor L2, an inductor L3, a switch tube Q13 with an integrated anti-parallel diode, a switch tube Q14 with an integrated anti-parallel diode, a diode D2, and a diode D3; one end of the thyristor Q3 is connected to phase C, the other end of the thyristor Q3 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to one end of the diode D2, and the other end of the diode D2 is connected to the positive electrode of the DC power supply; one end of the thyristor Q4 is connected to phase C, the other end of the thyristor Q4 is connected to one end of the inductor L3, the other end of the inductor L3 is connected to one end of the diode D3, and the other end of the diode D3 is connected to the negative electrode of the DC power supply; one end of the switch tube Q13 with an integrated anti-parallel diode and the other end of the switch tube Q14 with an integrated anti-parallel diode are connected to the neutral point; the other end of the switch tube Q13 with an integrated anti-parallel diode is connected to the positive electrode; the other end of the switch tube Q14 with an integrated anti-parallel diode is connected to the negative electrode.

6. The UPS system bus balancing hybrid topology circuit according to claim 5, characterized in that: The battery includes a positive electrode and a negative electrode. The battery positive and discharge unit includes a thyristor Q5, a thyristor Q7, the inductor L1, the inductor L2, the switch tube Q13 with an integrated anti-parallel diode, the switch tube Q15 with an integrated anti-parallel diode, the diode D1, and the diode D2. One end of the thyristor Q5 and the thyristor Q7 are respectively connected to the positive electrode of the battery; the other end of the thyristor Q5 is connected to one end of the inductor L2, and the other end of the thyristor Q7 is connected to one end of the inductor L1.

7. The UPS system bus balancing hybrid topology circuit according to claim 6, characterized in that: The battery negative discharge unit includes a thyristor Q6, a thyristor Q8, the inductor L3, the inductor L4, the switch tube Q14 with an integrated anti-parallel diode, the switch tube Q16 with an integrated anti-parallel diode, a diode D3, and a diode D4; one end of the thyristor Q6 and the thyristor Q8 are respectively connected to the negative electrode of the battery; the other end of the thyristor Q6 is connected to one end of the inductor L3, and the other end of the thyristor Q8 is connected to one end of the inductor L4.

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