Power consumption seamless switching circuit suitable for high-gain long-endurance application

Abstract

The invention discloses a power consumption seamless switching circuit suitable for high-gain long-endurance application, and solves the problem that electronic pulse interference and random noise are brought to a system when bias current is directly switched through a switch in the prior art. The circuit comprises a voltage and current conversion circuit, a power consumption seamless switching circuit and a comparator circuit, the power consumption seamless switching circuit is used for comparing the duration time of a high level in the VCTL signal with the blanking time set in the blanking circuit and determining the states of the Y2 signal and the VSW signal; obtaining a VSML signal according to the Y2 and the VSW signal; the voltage and current conversion circuit controls the size of an access resistor to realize seamless switching of voltage and current, and outputs an ISML signal; the comparator circuit controls the size of a resistor connected into the comparator circuit according to the states of the VSW signal and the VSML signal so as to realize seamless switching of gains, and outputs a VCMP signal; the precision of the system is ensured, and system disorder in a sleep mode is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a power consumption seamless switching circuit suitable for high-gain and long-endurance applications. Background Art

[0002] Portable electronic devices usually require extremely low power consumption to improve device endurance. The traditional solution is to set a sleep mode inside the chip. When the system is working, it will switch between normal working mode and sleep mode. In sleep mode, extremely low static current can be achieved, thereby improving work efficiency and extending the working time of the device.

[0003] The traditional solution is to switch the bias current directly through a switch to achieve the conversion of the system from normal working mode to sleep mode, but directly switching the bias current through a switch will bring problems such as electronic pulse interference and random noise to the system. Taking the switching power supply as an example, the direct switching of the bias current may also cause the loop comparator to flip incorrectly, affecting the normal operation of the system; at the same time, the power consumption and gain of the loop comparator are a compromise relationship. Under the traditional solution, the gain of the loop comparator in sleep mode will decrease due to the reduction of the bias current, resulting in a decrease in the recognition accuracy of the comparator, which in turn leads to an increase in the delay of the comparator flipping, and even a false flipping, causing system operation disorder. Summary of the invention

[0004] The present invention provides a power consumption seamless switching circuit suitable for high-gain and long-endurance applications, thereby solving the problem of directly switching the bias current through a switch in the prior art, which may cause electronic pulse interference and random noise to the system, ensuring the accuracy of the system and avoiding system disorder in sleep mode.

[0005] The present invention provides a power consumption seamless switching circuit suitable for high-gain and long-endurance applications, the circuit comprising: a voltage-current conversion circuit, a power consumption seamless switching circuit and a comparator circuit;

[0006] The power consumption seamless switching circuit is used to determine the state of the Y2 signal and the state of the VSW signal respectively by comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit; and obtain the VSML signal according to the state of the Y2 signal and the state of the VSW signal; wherein the state includes: low level and high level;

[0007] The voltage-current conversion circuit is used to determine whether the first current mirror in the voltage-current conversion circuit is enabled according to the state of the VSML signal and the state of the VSW signal, and then control the size of the access resistor in the voltage-current conversion circuit to achieve seamless switching of voltage and current, and output an ISML signal;

[0008] The comparator circuit is used to control the size of the resistor connected to the comparator circuit according to the state of the VSW signal, and to achieve seamless gain switching in combination with the second current mirror according to the VSML signal, and output a VCMP signal.

[0009] In a possible implementation, comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit to respectively determine the state of the Y2 signal and the state of the VSW signal includes:

[0010] If the VCTL signal is a low level signal, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0011] If the VCTL signal is a high level signal, and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0012] If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, during the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; outside the blanking time, the state of the Y2 signal is a high level, and the state of the VSW signal is a low level.

[0013] In a possible implementation, the power consumption seamless switching circuit includes: a first inverter, a second inverter, a blanking circuit, a switch tube M7, a switch tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9;

[0014] The VCTL signal is input to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter;

[0015] The output terminal of the second inverter is connected to the input terminal of the blanking circuit;

[0016] The output end of the blanking circuit is connected to the gate end of the switch tube M7 and the gate end of the switch tube M8 respectively;

[0017] The source end of the switch tube M7 is connected to the power supply VDD, and the drain end of the switch tube M7 is connected to the drain end of the switch tube M8;

[0018] The source end of the switch tube M8 is grounded;

[0019] The upper plate of the capacitor C1 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected to the drain end of the mirror tube M9;

[0020] The upper plate of the capacitor C2 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C2 is connected to the first end of the resistor R5;

[0021] The gate end of the mirror tube M9 is connected to the lower plate of the capacitor C1 , and the source end of the mirror tube M9 is connected to the second end of the resistor R5 and the drain end of the switch tube M7 .

[0022] In a possible implementation, the voltage-current conversion circuit includes: an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4;

[0023] The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal of the error amplifier EA is connected to the source terminal of the power tube M2 and the first terminal of the load resistor R1, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube M2;

[0024] The source end of the mirror tube M1 is connected to the power supply VDD, and the gate end of the mirror tube M1 is connected to the drain of the mirror tube M1, the drain end of the power tube M2, and the comparator circuit;

[0025] The second end of the load resistor R1 is connected to the drain end of the mirror tube M3;

[0026] The gate end of the mirror tube M3 is connected to the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected to the second end of the resistor R2;

[0027] The first end of the resistor R2 is connected to the second end of the load resistor R1, and the second end of the resistor R2 is grounded;

[0028] The gate end of the switch tube M4 is connected to the power consumption seamless switching circuit, the drain end of the switch tube M4 is connected to the first end of the resistor R2, and the source end of the switch tube M4 is grounded.

[0029] In a possible implementation, the first current mirror includes: a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M3 in the voltage-current conversion circuit.

[0030] In a possible implementation, the comparator circuit includes: a comparator CMP, a mirror tube M5, a switch tube M6, a resistor R3 and a load resistor R4;

[0031] The current bias input terminal of the comparator CMP is connected to the voltage-current conversion circuit, and the output terminal of the comparator CMP is connected to the first terminal of the resistor R3;

[0032] The second end of the resistor R3 is connected to the drain end of the switch tube M6;

[0033] The source end of the switch tube M6 is grounded, and the gate end of the switch tube M6 is connected to the power consumption seamless switching circuit;

[0034] The source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected to the power consumption seamless switching circuit, and the second end of the drain end resistor R3 of the mirror tube M5 is connected;

[0035] A first end of the load resistor R4 is connected to a first end of the resistor R3 , and a second end of the load resistor R4 is grounded.

[0036] In a possible implementation, the second current mirror includes: a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M5 in the comparator circuit.

[0037] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0038] The present invention realizes seamless switching of current bias by combining a power consumption seamless switching circuit with a voltage-current conversion circuit, thereby avoiding problems such as random noise, electronic pulses and system stability caused by switching. While realizing seamless switching of current bias, high gain in a low-power sleep condition is maintained by switching the load resistor in the comparator circuit, thereby ensuring the accuracy of the system and avoiding system disorder in the sleep mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a power consumption seamless switching circuit adapted to high-gain and long-endurance applications provided by an embodiment of the present invention;

[0040] Figure 2 A circuit diagram for seamless power consumption switching provided by an embodiment of the present invention;

[0041] Figure 3 A voltage-to-current conversion circuit diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The present invention provides a power consumption seamless switching circuit suitable for high-gain and long-endurance applications, such as Figure 1As shown, the circuit includes: a voltage-current conversion circuit, a power consumption seamless switching circuit and a comparator circuit.

[0044] The ISML signal is the output voltage signal of the voltage-to-current conversion circuit, which provides bias current for the comparator and is a voltage signal with a gentle change.

[0045] The VSW signal is a switching signal for controlling the switch tubes M4 and M6.

[0046] The VSML signal is the gate voltage of the current mirror M9 in the power consumption seamless switching circuit, which controls the mirror tubes M3 and M5 and is a voltage signal that changes smoothly.

[0047] VCTL is the control signal for power switching, and a high level indicates that the voltage-to-current conversion circuit outputs a small bias current.

[0048] The VCMP signal is the output signal of the comparator.

[0049] The power consumption seamless switching circuit is used to determine the state of the Y2 signal and the state of the VSW signal respectively by comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit; and obtain the VSML signal according to the state of the Y2 signal and the state of the VSW signal; wherein the state includes: low level and high level; here, the purpose of the blanking circuit is to reduce the disturbance of the previous stage control signal and the influence of frequent switching.

[0050] Specifically, in a power consumption seamless switching circuit, such as Figure 2 As shown, it includes: a first inverter, a second inverter, a blanking circuit, a switch tube M7, a switch tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9.

[0051] The input end of the first inverter inputs a VCTL signal, and the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter is connected to the input end of the blanking circuit; the output end of the blanking circuit is respectively connected to the gate end of the switch tube M7 and the gate end of the switch tube M8; the source end of the switch tube M7 is connected to the power supply VDD, and the drain end of the switch tube M7 is connected to the drain end of the switch tube M8; the source end of the switch tube M8 is grounded; the upper plate of the capacitor C1 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected to the drain end of the mirror tube M9; the upper plate of the capacitor C2 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C2 is connected to the first end of the resistor R5; the gate end of the mirror tube M9 is connected to the lower plate of the capacitor C1, and the source end of the mirror tube M9 is connected to the second end of R5 and the drain end of the switch tube M7.

[0052] Specifically, if the VCTL signal is a low level signal, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0053] If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level;

[0054] If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, the state of the Y2 signal is low during the blanking time, and the state of the VSW signal is high; outside the blanking time, the state of the Y2 signal is high, and the state of the VSW signal is low.

[0055] For example, Figure 2 As shown, when the control signal VCTL is at a low level, the Y1 signal output is low, and when VSW is at a high level, the switch tube M4 is turned on, the resistor R2 is short-circuited, and the voltage-current conversion circuit outputs a large bias current.

[0056] The control signal VCTL is high but lasts for less than the blanking time. The Y1 signal first flips to a high level, but because of the blanking circuit, the Y2 signal is still a low level. Before the blanking time ends, the Y1 signal turns low again, so the VSW signal is always high during this process, and the voltage-current conversion circuit maintains a large output bias current.

[0057] The control signal VCTL is at a high level and lasts longer than the blanking time. Since the VSW signal is at a high level during the blanking time, the lower plates of the capacitors C1 and C2 are charged through the resistor R5. At this time, CS is equal to the VSW signal, which is at a high level. At this time, the VGS of the mirror tube M9 is 0 (gate-source voltage), so the mirror tubes M9 and M3 in the first current mirror are not enabled.

[0058] For example, Figure 2 As shown, the VCTL signal is the input signal of the power consumption seamless circuit. After passing through the two-stage inverter and the blanking circuit, the Y2 signal is generated. The Y2 signal is connected to the gate ends of the switch tubes M7 and M8, the source end of the switch tube M7 is connected to the power supply VDD, and the source end of the switch tube M8 is connected to the ground. The drain end of the switch tube M7 is connected to the drain end of M8 and is connected to the lower end of the resistor R5 and the source end of the mirror tube M9. The drain end and the gate end of the mirror tube M9 are connected to the upper end of R5 and connected to the lower plates of the capacitors C1 and C2. The upper plates of the capacitors C1 and C2 are connected to the lower end of the load resistor R1 in the voltage-current conversion circuit. At the same time, the gate end of the mirror tube M9 is connected to the gate end of the mirror tube M5 of the comparator circuit and the gate end of the mirror tube M3 in the voltage conversion circuit as the output signal of the power consumption seamless switching circuit.

[0059] A voltage-current conversion circuit, used to determine whether the first current mirror in the voltage-current conversion circuit is enabled according to the state of the VSML signal and the state of the VSW signal, and then control the size of the access resistor in the voltage-current conversion circuit to achieve seamless switching of voltage and current, and output an ISML signal;

[0060] Specifically, Figure 3 As shown, the voltage-current conversion circuit includes: an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4;

[0061] The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal of the error amplifier EA is connected to the source terminal of the power tube M2 and the first terminal of the load resistor R1, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube M2;

[0062] The source end of the mirror tube M1 is connected to the power supply VDD, and the gate end of the mirror tube M1 is connected to the drain of the mirror tube M1, the drain end of the power tube M2, and the comparator circuit;

[0063] The second end of the load resistor R1 is connected to the drain end of the mirror tube M3;

[0064] The gate end of the mirror tube M3 is connected to the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected to the second end of the resistor R2;

[0065] A first end of the resistor R2 is connected to a second end of the load resistor R1 , and a second end of the resistor R2 is grounded.

[0066] For example, Figure 3 As shown, the function of the error amplifier EA is to clamp the voltage. The output of the error amplifier EA is connected to the power tube M2, the positive input of the error amplifier EA is connected to the VREF voltage, and the negative input is connected to the load resistor R1. The voltage-to-current conversion circuit achieves current switching by changing the output load by controlling the resistor R2 connected to the circuit through the switch tube M4. The key to seamless switching lies in the mirror tube M3, which is the mirror tube of the current mirror. When the system is in normal working mode, because the mirror tube of the current mirror has no current, the load of the voltage-to-current conversion circuit is R1 connected to the ground through a switch tube M4; when the system switches from normal working mode to sleep mode, the VCTL signal flips from low level to high level, and the current mirror is enabled.

[0067] The positive input of the error amplifier EA is connected to the VREF voltage, and the output is connected to the gate of the power tube M2. The source of the power tube M2 is connected to the negative input of the op amp and the upper end of the load resistor R1. The lower end of the load resistor R1 is connected to the drain of the mirror tube M3, the switch tube M4 and the upper end of the resistor R2. The gate of the mirror tube M3 is connected to the output signal VSML of the power consumption seamless switching circuit, and the gate of the switch tube M4 is connected to the output signal VSW of the power consumption seamless switching circuit. The source of the mirror tube M3, the switch tube M4 and the lower end of the resistor R2 are connected to the ground. The drain of the power tube M2 is connected to the drain of the mirror tube M1, and is also connected to the gate of the mirror tube M1, and is connected to the comparator circuit as an output signal. The source of the mirror tube M1 is connected to the power supply VDD.

[0068] When the high level time of the control signal VCTL is longer than the blanking time, the Y2 signal flips to a high level, and the voltage VSW signal at the drain end of M7 and the drain end of M8 becomes low instantly. At this time, the switch tube M4 is turned off, and the resistor R2 is connected to the load of the voltage-current conversion circuit; at the same time, the CS node of the lower plate of the capacitor is discharged through the switch tube M8 and the resistor R5. Compared with the VSW signal node, the capacitor discharge process is a slow process. At this time, after the VSW signal of the mirror tube M9 becomes low instantly, because the capacitor plate voltage will not change suddenly, the voltage difference between the CS node and the VSW signal node is VDD, that is, the VGS of the mirror tube M9 =VDD, at this time, the mirror tube M9 and the mirror tube M3 are enabled as current mirrors, and a larger current is mirrored to the voltage-current conversion circuit. The addition of the mirror current avoids the output bias current of the voltage-current conversion circuit from changing too fast due to the instantaneous switching of the load resistor. As the capacitor discharges, the voltage of the lower plate of the lower plate capacitor of the capacitor C1 and C2 gradually decreases, and the mirror current gradually decreases until the voltage of the lower plate of the capacitor C1 and C2 decreases to the threshold voltage of the mirror tube M9, and the mirror current of the current mirror decreases to 0. At this point, the seamless switching of the bias current is completed, and the system is switched from the normal working mode to the sleep mode. The difference between the bias current generated by the voltage-current conversion circuit in this process and the bias current obtained by directly switching the voltage-current circuit load by the switch is that the former obtains a slowly changing output current, thereby avoiding problems such as electronic pulse interference, random noise and system stability to the system.

[0069] The comparator circuit controls the size of the resistor connected to the comparator circuit according to the state of the VSW signal, realizes seamless gain switching in combination with the second current mirror according to the VSML signal, and outputs a VCMP signal.

[0070] Specifically, Figure 3The comparator CMP, the mirror tube M5, the switch tube M6, the resistor R3 and the load resistor R4 are shown; the current bias input end of the comparator CMP is connected to the voltage-current conversion circuit, and the output end of the comparator CMP is connected to the first end of the resistor R3; the second end of the resistor R3 is connected to the drain end of the switch tube M6; the source end of the switch tube M6 is grounded, and the gate end of the switch tube M6 is connected to the power consumption seamless switching circuit; the source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected to the power consumption seamless switching circuit, and the drain end of the mirror tube M5 is connected to the second end of the resistor R3; the first end of the load resistor R4 is connected to the first end of the resistor R3, and the second end of the load resistor R4 is grounded.

[0071] Here, the second current mirror includes: a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M5 in the comparator circuit.

[0072] Exemplarily, the seamless switching of gain is achieved by changing the load resistance of the comparator, and the process of seamless switching of gain is as follows: Taking the loop comparator in the switching power supply as an example, the resistor R3 and the load resistor R4 represent the load resistance inside the comparator, and the seamless switching of gain is achieved through the mirror tube M5, the switch tube M6 and the load resistor R4. Similar to the power switching process, during the normal operation of the comparator circuit, the VSW signal is at a high level, and the load resistor R4 is short-circuited through the switch tube M6. At this time, the load inside the comparator is the resistor R3, and the comparator gain is relatively small.

[0073] When the VCTL signal control signal is high level and lasts longer than the blanking time, VSW is a signal low level, the switch tube M6 is turned off, and the load resistor R4 is connected to the comparator circuit. However, through the analysis of the power consumption seamless switching process, it can be seen that the mirror tube M5 will have a large mirror current at this time, so the current of the comparator almost flows into the ground through the mirror tube M5. At this time, the mirror tube M5 is in the deep linear region and the impedance is very small. In order to obtain high gain, the resistance value of the load resistor R4 is very large. At this moment, the impedance of the mirror tube M5 is much smaller than the load resistor R4. The equivalent impedance of the two in parallel is very small, which is equivalent to the mirror tube M5 short-circuiting the load resistor R4. Therefore, the gain of the comparator at this moment is the same as when the switch tube M6 is turned on, but as the current mirror current gradually decreases, the impedance of the load resistor R4 and the equivalent resistance of the mirror tube M5 in parallel gradually increases, and the gain of the comparator circuit gradually increases as the mirror current decreases. Because the mirror current of the mirror tube changes slowly, the gain of the comparator is also gradually increasing slowly. This process realizes the seamless switching of the comparator gain.

[0074] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. All or part of the present invention can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the present invention.

Claims

1. A power consumption seamless switching circuit suitable for high-gain and long-endurance applications, characterized in that: include: Voltage-current conversion circuit, power consumption seamless switching circuit and comparator circuit; The power consumption seamless switching circuit is used to determine the state of the Y2 signal and the state of the VSW signal respectively by comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit; and obtain the VSML signal according to the state of the Y2 signal and the state of the VSW signal; wherein the state includes: low level and high level; The voltage-current conversion circuit is used to determine whether the first current mirror in the voltage-current conversion circuit is enabled according to the state of the VSML signal and the state of the VSW signal, and then control the size of the access resistor in the voltage-current conversion circuit to achieve seamless switching of voltage and current, and output an ISML signal; The comparator circuit is used to control the size of the resistor connected to the comparator circuit according to the state of the VSW signal, and to achieve seamless gain switching in combination with the second current mirror according to the VSML signal, and output a VCMP signal.

2. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The method of comparing the duration of the high level in the VCTL signal with the blanking time set in the blanking circuit to respectively determine the state of the Y2 signal and the state of the VSW signal includes: If the VCTL signal is a low level signal, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; If the VCTL signal is a high level signal, and the duration of the high level of the VCTL signal is less than the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; If the VCTL signal is a high-level signal, and the duration of the high level of the VCTL signal is greater than or equal to the blanking time, during the blanking time, the state of the Y2 signal is a low level, and the state of the VSW signal is a high level; outside the blanking time, the state of the Y2 signal is a high level, and the state of the VSW signal is a low level.

3. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 1, characterized in that: The power consumption seamless switching circuit includes: a first inverter, a second inverter, a blanking circuit, a switch tube M7, a switch tube M8, a capacitor C1, a capacitor C2, a resistor R5, and a mirror tube M9; The VCTL signal is input to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the input terminal of the blanking circuit; The output end of the blanking circuit is connected to the gate end of the switch tube M7 and the gate end of the switch tube M8 respectively; The source end of the switch tube M7 is connected to the power supply VDD, and the drain end of the switch tube M7 is connected to the drain end of the switch tube M8; The source end of the switch tube M8 is grounded; The upper plate of the capacitor C1 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C1 is connected to the drain end of the mirror tube M9; The upper plate of the capacitor C2 is connected to the voltage-current conversion circuit, and the lower plate of the capacitor C2 is connected to the first end of the resistor R5; The gate end of the mirror tube M9 is connected to the lower plate of the capacitor C1 , and the source end of the mirror tube M9 is connected to the second end of the resistor R5 and the drain end of the switch tube M7 .

4. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 3, characterized in that: The voltage-current conversion circuit includes: an error amplifier EA, a power tube M2, a load resistor R1, a mirror tube M1, a mirror tube M3, a resistor R2 and a switch tube M4; The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal of the error amplifier EA is connected to the source terminal of the power tube M2 and the first terminal of the load resistor R1, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube M2; The source end of the mirror tube M1 is connected to the power supply VDD, and the gate end of the mirror tube M1 is connected to the drain of the mirror tube M1, the drain end of the power tube M2, and the comparator circuit; The second end of the load resistor R1 is connected to the drain end of the mirror tube M3; The gate end of the mirror tube M3 is connected to the power consumption seamless switching circuit, and the source end of the mirror tube M3 is connected to the second end of the resistor R2; The first end of the resistor R2 is connected to the second end of the load resistor R1, and the second end of the resistor R2 is grounded; The gate end of the switch tube M4 is connected to the power consumption seamless switching circuit, the drain end of the switch tube M4 is connected to the first end of the resistor R2, and the source end of the switch tube M4 is grounded.

5. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 4, characterized in that: The first current mirror includes: a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M3 in the voltage-current conversion circuit.

6. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 3, characterized in that: The comparator circuit includes: a comparator CMP, a mirror tube M5, a switch tube M6, a resistor R3 and a load resistor R4; The current bias input terminal of the comparator CMP is connected to the voltage-current conversion circuit, and the output terminal of the comparator CMP is connected to the first terminal of the resistor R3; The second end of the resistor R3 is connected to the drain end of the switch tube M6; The source end of the switch tube M6 is grounded, and the gate end of the switch tube M6 is connected to the power consumption seamless switching circuit; The source end of the mirror tube M5 is grounded, the gate end of the mirror tube M5 is connected to the power consumption seamless switching circuit, and the second end of the drain end resistor R3 of the mirror tube M5 is connected; A first end of the load resistor R4 is connected to a first end of the resistor R3 , and a second end of the load resistor R4 is grounded.

7. The power consumption seamless switching circuit suitable for high-gain and long-endurance applications according to claim 6, characterized in that: The second current mirror includes: a mirror tube M9 in the power consumption seamless switching circuit and a mirror tube M5 in the comparator circuit.

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