Self-regulating bootstrap recharging system in dual-switch flyback converter

Abstract

The invention relates to a self-regulating bootstrap recharging system in a dual-switch flyback converter. According to one embodiment, a converter is provided. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high voltage side switch having a source terminal coupled to the bootstrap capacitor through a floating ground node; a low-voltage side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch, and to provide a second control signal to a control terminal of the low-side switch, after a duration from a transition of the first control signal to turn off the high-side switch, a transition of the second control signal to turn off the low side switch is delayed, where the delay is automatically adjusted by detecting a condition associated with the converter, where the delay begins in response to a voltage at the floating ground node being less than zero.

Description

Technical Field

[0001] The present disclosure relates generally to power electronics and, in particular embodiments, to a self-regulated bootstrap recharging system in a dual-switch flyback converter. Background Art

[0002] The two-switch flyback converter is a design topology used in power electronics. However, just like any other electronic system, it also struggles with specific technical challenges that need to be solved to achieve optimal performance. One of the most prominent issues at the forefront is ensuring that the bootstrap capacitor maintains sufficient charge under all operating conditions, especially for driving the high-side switch of the converter.

[0003] To initiate charging of the bootstrap capacitor, the low-side switch can be turned on for a specific duration - an approach that mirrors the technique used in a half-bridge configuration. By activating the low-side switch, the potential at the floating ground (FGND) node is essentially zero. Charging of the bootstrap capacitor is facilitated via the low-side switch and the primary winding of the converter's transformer.

[0004] As the converter operates and switches, the recharging of the bootstrap capacitor comes into play. The presence of a large amount of energy in the leakage inductance of the transformer causes the potential at the floating ground (FGND) to approach zero, resulting in the recharging of the bootstrap capacitor. This is further amplified when the recirculation diode of the converter is activated during the off-state of the high-side switch and the low-side switch. When the high-side switch and the low-side switch are deactivated, the voltage excursion across the primary winding is equal to the reflected voltage (V R ) and leakage inductance (V x ) is the sum of the voltage spikes caused by R ) and leakage inductance (V x ) is lower than the input voltage (V IN ), a potential challenge arises if the potential at the floating ground (FGND) node does not reach zero.

[0005] The integrity of the converter operation depends on sufficient recharging of the bootstrap capacitor. When the leakage inductance does not have enough energy to bring the potential at the floating ground (FGND) node close to zero, the bootstrap capacitor can no longer be charged. Over time, this eventually leads to a failure to activate the high-side switch, derailing the converter's operation. Summary of the invention

[0006] Technical advantages may generally be achieved by embodiments of the present disclosure, which describe a self-regulated bootstrap recharging system in a dual-switch flyback converter.

[0007] A first aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal to turn off the low-side switch is delayed after a duration from a transition of the first control signal to turn off the high-side switch, wherein the delay is automatically adjusted by detecting a condition associated with the converter, wherein the delay begins in response to a voltage at the floating ground node being less than zero.

[0008] A second aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal to turn off the low-side switch is based on detecting a condition related to the converter after a transition of the first control signal to turn off the high-side switch.

[0009] A third aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal for turning off the low-side switch is based on a programmable delay after a transition of the first control signal for turning off the high-side switch, the programmable delay being a function of a maximum current flowing through a transformer of the converter.

[0010] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram of a conventional DC-DC converter;

[0013] Figure 2 is a schematic diagram of a conventional two-switch flyback converter;

[0014] Figure 3is a set of waveforms corresponding to an example operation of a two-switch flyback converter, where the bootstrap capacitor (C BOOT ) is recharged;

[0015] Figure 4 is a set of waveforms corresponding to an example operation of a two-switch flyback converter, where the bootstrap capacitor (C BOOT ) has not been recharged;

[0016] Figure 5 A flow chart illustrating an embodiment method for operating a two-switch flyback converter is illustrated;

[0017] Figure 6 is a schematic diagram of a closed-loop regulation circuit of an embodiment, which can be used in a dual-switch flyback converter for Figure 5 The method is implemented in condition A;

[0018] Figure 7 is a schematic diagram of a closed-loop regulation circuit of an embodiment, which can be used in a dual-switch flyback converter for Figure 5 The method is implemented in condition B;

[0019] Figure 8 is a schematic diagram of a closed-loop regulation circuit of an embodiment, which can be used in a dual-switch flyback converter for Figure 5 The method is implemented by condition C;

[0020] Fig. 9 is a flow chart of an embodiment method for operating a dual-switch flyback converter based on direct delay setting (DDS);

[0021] Fig.10 is a flow chart of an embodiment method for operating a two-switch flyback converter using an open-loop control algorithm;

[0022] Fig.11 Can be based on Fig. 9 A schematic diagram of an embodiment DDS circuit of the method implemented in a dual-switch flyback converter;

[0023] Fig.12 Can be based on Fig. 9 A schematic diagram of another embodiment of a DDS circuit implemented in a dual-switch flyback converter;

[0024] Fig.13 Can be based on Fig. 9 A schematic diagram of an embodiment DDS circuit of the method implemented in a dual-switch flyback converter;

[0025] Fig.14 Can be based on Fig.10A schematic diagram of an open-loop regulation circuit of an embodiment of the method implemented in a dual-switch flyback converter; and

[0026] Fig.15 is a block diagram of an embodiment system. DETAILED DESCRIPTION

[0027] The present disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. Specific embodiments only illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form additional embodiments. Various embodiments are illustrated in the accompanying drawings, in which the same components and elements are identified by the same figure marks, and repeated descriptions are omitted for the sake of brevity. The changes or modifications described in one of these embodiments may also be applied to other embodiments. In addition, various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims. Although aspects of the present disclosure are mainly described in the context of a dual-switch flyback converter, it should also be understood that these inventive aspects may also be applied to other types of power converters.

[0028] Figure 1 The schematic diagram of a conventional DC-DC converter 100 is shown. The DC-DC converter 100 includes a high-side drive circuit system 102, a high-side transistor 104, a low-side drive circuit system 106, a low-side transistor 108, a bootstrap diode 110, a bootstrap capacitor (C BOOT )114, output capacitor 116, inductor 118 and DC voltage source 120.

[0029] In the DC-DC converter 100, the control circuit system 112 drives the high-side transistor 104 and the low-side transistor 108 to turn on and off alternately via the high-side signal (HVG) and the low-side signal (LVG) respectively to generate a desired output voltage (V out The DC voltage source 120 is configured to generate a regulated voltage (V cc ), which is provided to the bootstrap diode 110 and the low-side drive circuit system 106. In an embodiment, the regulated voltage (V cc ) is generated by a DC voltage source 120 using an auxiliary winding (not shown) coupled to a transformer, a rectifier diode (not shown), and a buffer capacitor (not shown) to obtain a basic DC voltage.

[0030] Output capacitor 116 and inductor 118 form an LC circuit at the output of DC-DC converter 100 to produce a desired DC output voltage.

[0031] The bootstrap diode 110 and the bootstrap capacitor (CBOOT ) 114 forms a bootstrap circuit to generate a boost voltage (i.e., greater than or equal to the minimum gate-source voltage (V gs )), thereby efficiently driving the high-side transistor 104 through the high-side driving circuit system 102.

[0032] Typically, low-side transistor 108 is directly controlled using control circuitry 112 coupled to an input of low-side driver circuitry 106. However, directly controlling high-side transistor 104 via control circuitry 112 becomes more challenging because when high-side transistor (Q 1 ) 104 is implemented as an n-channel metal oxide semiconductor field effect transistor (MOSFET) in, for example, a buck converter, the source terminal of the high side transistor 104 is not connected to the ground reference.

[0033] During the on-state of the low-side transistor 108 (i.e., the off-phase of the converter), the switch node (SW) is connected to ground. cc ) flows through the bootstrap diode 110, the bootstrap capacitor (C BOOT )114 is charged to a voltage equal to the regulated voltage (V cc ) and the threshold voltage of the bootstrap diode 110. The bootstrap diode 110 is forward biased and the bootstrap capacitor (C BOOT )114 is charged to a voltage slightly lower than the regulated voltage (V cc ) voltage.

[0034] During the on-state of the high-side transistor 104 (i.e., the on-phase of the converter), the gate voltage of the high-side transistor 104 must rise to at least a threshold voltage above the source voltage level to ensure that it is fully turned on. However, since the source of the high-side transistor 104 is not connected to a ground reference, driving it directly from the control circuitry 112 is challenging.

[0035] During the on-state of the high-side transistor 104, the bootstrap circuit comes into play. The control circuit system 112 asserts the high-side signal (HVG), which allows the stored charge in the bootstrap capacitor (C BOOT ) 114 is applied to the control terminal of the high-side transistor 104 through the high-side drive circuit system 102. BOOT ) 114 is applied to the control terminal of the high-side transistor 104 so that the gate-source voltage (V gs ) is sufficient to turn on the high-side transistor 104.

[0036] After the high-side transistor 104 is turned on, the voltage (VFGND ) is connected to the input power supply (V in The cathode of the bootstrap diode 110 (bootstrap power supply) is equal to the input power supply (V in ) and across the bootstrap capacitor (C BOOT )114 and the sum of the charges stored. The bootstrap diode is reverse biased, and the bootstrap capacitor is connected to the regulated voltage (V cc ) is disconnected. This cycle repeats continuously when the high-side transistor 104 is turned off, and the bootstrap capacitor (C BOOT ) 114 is recharged during the on-state of the low side transistor 108.

[0037] Figure 2 FIG. 2 is a schematic diagram of a conventional dual-switch flyback converter 200. The dual-switch flyback converter 200 includes a high-side switch (Q 1 )202, low voltage side switch (Q 2 )204, transformer 206, first diode (D 1 )208, the second diode (D 2 )210, output diode (D OUT )212, sensing resistor (R S )214, control circuit system 216, input capacitor (C IN )218, bootstrap diode 110, bootstrap capacitor (C BOOT ) 114 and a DC voltage source 120. As shown in the figure, the regulated voltage (V cc ) is generated by the DC voltage source 120 and provided to the control circuit system 216.

[0038] High-side switch (Q 1 )202 and low voltage side switch (Q 2 Each of the transistors 204 is typically an n-channel metal oxide semiconductor field effect transistor (MOSFET). p ) and the secondary side (L S ) of the transformer 206 facilitates the transfer of energy from the input to the output via magnetic coupling. The high side switch (Q 1 ) 202 is coupled to the secondary side (L S ). Low voltage side switch (Q 2 ) 204 is coupled to the primary side (L p ) first terminal.

[0039] High-side switch (Q 1 )202 and low voltage side switch (Q 2) 204 are the main switches in the dual-switch flyback converter 200. Their synchronous operation (simultaneous switching on and off) manages the primary side (L p ) current.

[0040] The first diode (D 1 )208 and the second diode (D 2 ) 210 acts as a recirculation diode to direct energy from the leakage inductance of transformer 206 back to the input capacitor (C IN )218. This efficient energy utilization (especially in the case of severe transformer leakage) improves the overall efficiency of the dual-switch flyback converter 200. The input capacitor (C IN )218 is used to adjust the input voltage (V IN ) for filtering and stabilization. The output diode (D OUT )212 is used as an output rectifier diode to ensure that current flows only in the high-side switch (Q 1 )202 and low voltage side switch (Q 2 )204 flows to the output when it is in the off state.

[0041] The sensing resistor (R S )214 is coupled to the low voltage side switch (Q 2 ) 204 and is used to ensure safe operation of the dual switch flyback converter 200 and is typically used for current mode control. 2 )204 is activated, the current flowing through it also passes through the sensing resistor (R S ) 214. This results in a S )214, which is related to the voltage drop across the low-voltage side switch (Q 2 )204. By monitoring this voltage, the control circuit system 216 can accurately measure the magnitude of the inductor current in real time. This sensed voltage combined with the feedback signal from the secondary side allows the control circuit system 216 to adjust the high side switch (Q 1 )202 and low voltage side switch (Q 2 )204 on time to ensure that the peak primary current is the current required to provide the power required by the load while keeping the output voltage regulated at the desired value. As a result, by providing a fast response to load and line changes, improving transient behavior, and by preventing potential over-current conditions to ensure safer operation, the sense resistor (R S )214 promotes current mode control to improve the performance of the dual-switch flyback converter 200.

[0042] The control circuit system 216 includes an input terminal coupled to the output of the bootstrap diode 110 and is configured to drive the high side switch (Q) using the high side gate control signal (HVG). 1 )202. High-voltage side switch (Q 1 The operation of )202 is based on the use of bootstrap diode 110 and bootstrap capacitor (C BOOT ) 114 to drive the high side transistor 104 of the DC-DC converter 100. The control circuit system 216 is configured to use the low side gate control signal (LVG) to drive the low side switch (Q 2 )204.

[0043] In operation, when the high side switch (Q 1 )202 and low voltage side switch (Q 2 ) 204 is in an active state (ie, switched on state), energy is accumulated on the primary side (L P ) in the winding. At this time, the output diode (D OUT )212 remains inactive to prevent any energy from being transferred to the output side. 1 )202 and low voltage side switch (Q 2 )204 is disabled (ie, turned off), the operation changes. The voltage stored on the primary side (L P ) is moved to the secondary side (L S ) to activate the output diode (D OUT )212 and drives the energy to the output.

[0044] Due to the non-ideal characteristics of transformer 206, leakage inductance is generated because it is not supplied by the primary winding (L P ) are all magnetic fields generated by the secondary winding (L S ) coupling. Instead, some of these magnetic fields are “leaked” to the outside, which can be detected by coupling with the primary side (L P ) in series with the winding. Leakage inductance can pose a challenge to the operation of a flyback converter, especially during the turn-off phase.

[0045] The dual-switch flyback converter 200 is an improvement over the standard flyback converter. In a standard flyback converter with a single switch, when the switch is turned off, the energy stored in the leakage inductance has nowhere to go, resulting in voltage spikes. These spikes can exceed the voltage ratings of the components, potentially damaging them. To address this problem, the resistor in the resistor-diode-capacitor (RDC) clamp circuit (often called a “snubber resistor”) provides a safe path for the energy stored in the leakage inductance to dissipate, thereby protecting the circuit components from potentially harmful voltage spikes. By connecting the RDC clamp across the primary side (L P ) winding, when the switch is turned off, the energy stored in the leakage inductance can be "burned" or dissipated as heat in the snubber resistor.

[0046] However, while this approach effectively suppresses voltage spikes and protects the circuit, it is not the most efficient solution because the energy in the leakage inductance is not reused but simply wasted as heat. This results in increased thermal load and reduces the overall efficiency of the standard flyback converter.

[0047] In the dual-switch flyback converter 200, the high-side switch (Q 1 )202 and low voltage side switch (Q 2 During the deactivated state of )204, additional energy is stored in the input capacitor (C IN )218, rather than using a resistor-diode-capacitor (RDC) clamp circuit to dissipate the extra energy as heat. 1 )202 and low voltage side switch (Q 2 During the off state of )204, the additional voltage across the leakage inductance typically exceeds the input voltage (V IN ), so that the first diode (D 1 )208 and the second diode (D 2 )210 becomes forward biased. This causes the energy stored in the leakage inductance to be transferred to the input capacitor (C IN )218. During different cycles of the dual-switch flyback converter 200, the input capacitor (C IN )218 charging and discharging improves efficiency by avoiding the waste as heat in a standard flyback converter with a single switch.

[0048] In addition, compared with a single-switch flyback converter design, the 1 )202 and low voltage side switch (Q 2 ) 204 is effectively halved, so the capacitive switching losses in the dual-switch flyback converter 200 (ie, equal to CV 2) is minimized.

[0049] As mentioned above, the high side switch (Q 1 )202 and low voltage side switch (Q 2 )204 is disabled, across the primary side (L P ) of the winding, the voltage offset is equal to the reflected voltage (V R ) and leakage inductance (V x ) is the sum of the voltage spikes caused by the input voltage. Therefore, if the combined value is lower than the input voltage (V IN ), the voltage at the floating ground (FGND) node (V FGND ) cannot reach zero. When the leakage inductance is not enough to raise the voltage (V FGND ) is driven to near zero, the bootstrap capacitor (C BOOT )114 can no longer be charged. For some cycles, this results in the inability to activate the high-side switch (Q 1 )202, thereby interrupting the operation of the dual-switch flyback converter 200.

[0050] Figure 3 A set of waveforms 300 corresponding to an example operation of the two-switch flyback converter 200 are illustrated, wherein the bootstrap capacitor (C BOOT ) 114 is recharged. Waveform 300 includes a high-side gating signal 302, a high-side switch (Q 1 )202 source voltage 304 and the bootstrap capacitor (C BOOT )The charging voltage 306 at 114.

[0051] The high-side selection signal 302 drives the high-side switch (Q 1 )202. In an embodiment, when the high-side switch (Q 1 )202 is in the on state, the high-side selection signal 302 is in the logic level high, and when the high-side switch (Q 1 )202 is in the off state, the high-side selection signal 302 is in a logic low level.

[0052] At time t 0 , the high-side selection signal 302 changes from a logic low to a logic high. Therefore, the high-side switch (Q 1 )202 is activated (it is worth noting that at the same time, the low-voltage side switch (Q 2 )204 is also turned on). The bootstrap capacitor (C BOOT ) The value of the charging voltage 306 at time t 0 Since the bootstrap capacitor (C BOOT )114 is transferred to the high-voltage side switch (Q 1)202 gate capacitance charge, bootstrap capacitor (C BOOT )114 is slightly discharged to drive the high side switch (Q 1 )202.

[0053] At time t 1 , the high-side selection signal 302 changes from a logic level high to a logic level low. Therefore, the high-side switch (Q 1 )202 is disabled. The bootstrap capacitor (C BOOT ) The value of the charging voltage 306 at time t 1 This is because when the high-side switch (Q 1 )202 is turned off, there is enough energy to make the voltage at the floating ground (FGND) node (V FGND ) becomes zero so that the bootstrap capacitor (C BOOT )114Recharge.

[0054] Figure 4 A set of waveforms 400 corresponding to an example operation of the two-switch flyback converter 200 are illustrated, wherein the bootstrap capacitor (C BOOT ) 114 is not recharged. Waveform 400 includes a high side gating signal 402, a high side switch (Q 1 )202 source voltage 404 and the bootstrap capacitor (C BOOT )The charging voltage 406 at 114.

[0055] The high side selection signal 402 drives the high side switch (Q 1 )202. In an embodiment, when the high-side switch (Q 1 )202 is in the on state, the high-side selection signal 402 is in the logic level high, and when the high-side switch (Q 1 )202 is in the off state, the high-side selection signal 402 is in a logic low level.

[0056] At time t 0 , the high-side selection signal 402 changes from a logic low to a logic high. Therefore, the high-side switch (Q 1 )202 is activated. Similarly, due to the bootstrap capacitor (C BOOT )114 is transferred to the high-voltage side switch (Q 1 )202 gate capacitance charge, bootstrap capacitor (C BOOT )114 is slightly discharged to drive the high side switch (Q 1 )202.

[0057] At time t 1 , the high-side selection signal 302 changes from a logic level high to a logic level low. Therefore, the high-side switch (Q1 )202 is disabled. With the bootstrap capacitor (C BOOT )114, the charging voltage 306 at the bootstrap capacitor (C BOOT )114 does not increase. This is because the high-side switch (Q 1 )202 has a different power supply voltage 304, the high-side switch (Q 1 )202 power supply voltage 404 will not reach zero. Therefore, the bootstrap capacitor (C BOOT )114 will be discharged cycle by cycle until it reaches the time t 0 Cannot provide enough voltage, and the high side switch (Q 1 )202 Unable to connect.

[0058] Conventional solutions to this problem include (i) using an auxiliary transformer winding and (ii) using a drive transformer instead of a bootstrap topology. In the first case, a bootstrap capacitor (C BOOT )114, but the auxiliary winding is coupled to the primary side (L P ) winding. When the low voltage side switch (Q 2 )204 is turned on, the voltage across the auxiliary winding is positive, which allows the bootstrap capacitor (C BOOT )114 recharge. While the auxiliary winding technique offers some benefits, it also presents a number of challenges. On the plus side, not having a drive transformer simplifies the design. However, the first approach results in higher power dissipation, which can lead to system inefficiencies. Additionally, the first conventional solution has poor standby performance. The higher complexity of the transformer in this setup can complicate the design process and potentially impact reliability. Finally, this design finds it difficult to manage a wide range of output voltages (V OUT ) is challenging, which may limit its application in meeting modern power requirements, such as Universal Serial Bus (USB) Power Delivery (PD) requirements.

[0059] In the second solution, a drive transformer is used with a standard flyback controller, with the winding connected to its gate drive output, and the winding is added to the gate side of each of the high-side switch and the low-side switch, along with the few passive components required for normal operation. On the positive side, this approach has low power consumption, making the system more energy-efficient. The standby performance of this setup is also improved compared to the first solution, ensuring that the system remains reliable even in idle or low-load conditions. However, while providing these advantages, the addition of a drive transformer also represents an increase in the number of components, which can complicate assembly and maintenance.

[0060] Figure 5A flow chart of an embodiment method 500 for operating a dual-switch flyback converter 200 is illustrated. In an embodiment, to ensure that the voltage (V FGND ) becomes zero, the high-side switch (Q 1 )202 is deactivated with a delay, the low-voltage side switch (Q 2 )204 is deactivated. It should be noted that all steps listed in the flow chart are not necessarily required, but may be optional. In addition, it is possible to similarly consider changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections.

[0061] Typically, when the low-side switch (Q 2 )204 and the high-side switch (Q 1 )202 are disabled at the same time, across the primary side (L P ) winding voltage is reversed. This causes the high-side switch (Q 1 )202 drops in voltage at the source terminal and the low side switch (Q 2 ) The voltage at the drain terminal of 204 increases. The primary side (L P ) of the winding, the reverse voltage between the two terminals is equal to the reflected voltage (V R ) and leakage inductance (V x ) is the sum of the voltage spikes caused by the low-voltage side switch (Q 2 )204 and high-voltage side switch (Q 1 )202 are disabled at the same time, each terminal is Move to the center Where V IN is the input voltage.

[0062] In response to the low-side switch (Q 2 )204 On the high voltage side switch (Q 1 )202 remains activated for a period of time after being deactivated, the input current becomes zero (ie, there is no operation alternation), and the low-side switch (Q 2 )204 remains at zero drain voltage. This causes the entire voltage swing to 1 ) 202 source terminal (ie, floating ground (FGND) node), which in turn causes the voltage (V FGND ) drops below zero. Therefore, the bootstrap capacitor (C BOOT )114 is recharged. When the low voltage side switch (Q 2 )204 is a forward biased first diode (D 1 ) is disabled, the voltage at the floating ground (FGND) node (V FGND) stops going too low, which will float the voltage at the ground (FGND) node (V FGND ) is clamped to, for example, -1V.

[0063] Advantageously, this allows the bootstrap capacitor (C BOOT )114 is recharged regardless of the operating conditions. In addition, the solution does not require a drive transformer or additional external pins, reducing the number of components and costs compared to conventional solutions.

[0064] In order to intelligently control the high-side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 to allow the voltage at the floating ground (FGND) node (V FGND ) is only slightly below zero, a closed-loop regulation operation is added to the dual-switch flyback converter 200. This solves the problem of circuit parameters (e.g., parasitic capacitance, reverse voltage (V R ), leakage inductance, etc.) and the load condition of the converter, since it is not feasible to set a fixed delay for all variations.

[0065] At step 502, closed loop regulation operation begins. At step 504, one or more conditions are checked. The first condition (condition A) corresponds to a voltage across the bootstrap capacitor (C BOOT )114 is greater than the first threshold voltage (V TH1 ). This can be expressed as: if Where V BST is the voltage across the bootstrap capacitor.

[0066] The second condition (condition B) corresponds to the regulated voltage (V cc ) and across the bootstrap capacitor (C BOOT )114 is less than the second threshold voltage (V TH2 ). This can be expressed as: if

[0067] The third condition (condition C) corresponds to the high side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is less than the third threshold voltage (V TH3 ). This can be expressed as: if Where V FGND is τ 2 τ in seconds 1 The voltage at the floating ground (FGND) within seconds. In an embodiment, τ1 =100 nanoseconds (ns). In an embodiment, τ 2 Equal to 300ns.

[0068] In an embodiment, the first threshold voltage (V TH1 ), the second threshold voltage (V TH2 ) and the third threshold voltage (V TH3 ) is predetermined and stored in a memory of a host device coupled to the controller circuit system 216. In an embodiment, the first threshold voltage (V TH1 ), the second threshold voltage (V TH2 ) and the third threshold voltage (V TH3 ) is determined using machine learning techniques based on load and component variation conditions. In an embodiment, the first threshold voltage (V TH1 ) is set to 8 volts. In an embodiment, the second threshold voltage (V TH2 ) is set to 2 volts. In an embodiment, the third threshold voltage (V TH3 ) is set to 1 volt.

[0069] In an embodiment, the satisfaction of condition A, condition B, condition C, or any combination thereof is used to satisfy step 504. Therefore, if condition A, condition B, condition C, or any combination thereof is satisfied, the operation moves to step 506; otherwise, the operation moves to step 508. In an embodiment, the satisfaction of one of these conditions depends on the implementation used in the control IC. In an embodiment, condition A, condition B, and condition C are alternative conditions.

[0070] At step 506, the end of count (EoC) counter is decremented by one step. At step 508, the end of count (EoC) counter is incremented by k steps, where k is an integer greater than 1. In an embodiment, the value of k is between 2 and 6, inclusive.

[0071] After setting the value of the end-of-count (EoC) counter at step 506 or 508, at step 510, the high-side switch (Q 1 )202 and low voltage side switch (Q 2 )204.

[0072] At step 512, the high side switch (Q 1 ) 202. In an embodiment, when the peak inductor current reaches a value programmed by the control loop, the high side switch (Q 1 )202 is disabled. In an embodiment, the control loop adjusts the high side switch (Q 1 )202 and low voltage side switch (Q 2 )204 duty cycle to adjust the output voltage (V OUTIn an embodiment, a current sensor is used to measure the inductor current in real time, which is fed into a control loop. After the inductor current reaches a predetermined peak value set by the control loop, the high side switch (Q 1 )202 is turned off. This action terminates the primary side (L P ) in the winding and initiates the energy storage phase to the secondary side (L S ) of the winding energy transfer.

[0073] At step 514, the counter circuit starts until the end of count (EoC) counter value is reached. At step 516, when the counter circuit ends, the low side switch (Q 2 )204 is disabled. For the next cycle, steps 504 to 516 are repeated. After several cycles, the end of count (EoC) counter value is set to a near fixed value, which allows the voltage (V FGND ) reaches zero.

[0074] Figure 6 A schematic diagram of an embodiment closed-loop regulation circuit 600 that may be implemented in the two-switch flyback converter 200 for condition A of the method 500 is illustrated.

[0075] The closed-loop regulation circuit 600 detects condition A and automatically adjusts the high-side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204. If the bootstrap capacitor (C BOOT )114 is greater than the first threshold voltage (V TH1 ), then the delay is reduced. This can be expressed as: if And, if the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), then increase the delay. This can be expressed as: if

[0076] The output of the closed-loop regulation circuit 600 (LVG A ) is coupled to the low side switch (Q) via, for example, a gate driver (not shown) 2 )204's gate terminal to effectively turn off the low side switch after a delay adjusted by the closed-loop regulation circuit 500 based on condition A.

[0077] The closed-loop regulation circuit 600 includes a first comparator (COMP 1 )602, adder circuit 604, first inverter 606, level shifter circuit 608, first flip-flop (FF 1)610, a second inverter 612, a first AND gate 614, a reverse current timer programming circuit 625, a reverse current timer circuit 631, a second AND gate 640 and a second flip-flop (FF 2 )842, which may or may not be arranged as shown. The closed-loop regulation circuit 600 may include additional components not shown, such as filter circuits. The input of the closed-loop regulation circuit 600 is coupled to a bootstrap capacitor (C BOOT )114 terminal.

[0078] The first comparator (COMP 1 )602 is configured to effectively connect the bootstrap capacitor (C BOOT )114 and the first threshold voltage (V TH1 ) is compared. As described in method 500, a check can be performed to determine whether the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 is based on the first condition (condition A) of the delay between the turn-off of the bootstrap capacitor (C BOOT )114 and the first threshold voltage (V TH1 )

[0079] The first comparator (COMP 1 ) 602 is configured with hysteresis - its past state affects its output due to the feedback connection made via adder circuit 604. Adder circuit 604 has a first threshold voltage (V TH1 ) and a second input configured to receive the output of the comparator. The first comparator (COMP 1 )602 is configured to receive a first threshold voltage (V TH1 ) and the sum of the comparator outputs provided at the output of adder circuit 604. The first comparator (COMP 1 ) 602 is configured to generate an output signal which is fed to the input of a first inverter 606. It should be noted that in embodiments, other techniques besides adder circuits may be used to implement hysteresis.

[0080] In an embodiment, the first comparator (COMP 1 )602 is based on the bootstrap capacitor (C BOOT )114 and the first threshold voltage (V TH1 ) to provide an output signal to the first inverter 606. In response to the first threshold voltage (V TH1 ) and the comparator output is greater than the value across the bootstrap capacitor (C BOOT ) 114, the voltage of the first comparator (COMP 1) 602 will output a logic level high (eg, '1'). In response to the first threshold voltage (V TH1 ) and the sum of the comparator output is less than the value across the bootstrap capacitor (C BOOT ) 114, the voltage of the first comparator (COMP 1 ) 602 will output a logic level low (eg, '0'). The first comparator (COMP 1 )602 is inverted by a first inverter 606 and fed to a level shifter circuit 608.

[0081] In response to the bootstrap capacitor (C BOOT )114 has a voltage greater than or equal to a first threshold voltage (V TH1 ) and the sum of the comparator outputs, at step 504, the output of the first inverter 606 is set to a logic level high (eg, '1'), which indicates that as the voltage at the floating ground (FGND) node (V FGND ) is below zero, the delay needs to be reduced. In response to the BOOT )114 is less than the first threshold voltage (V TH1 ) and the sum of the comparator outputs, at step 504, the output of the first inverter 606 is set to a logic level low (eg, '0'), which indicates that as the voltage at the floating ground (FGND) node (V FGND ) is above zero, the delay needs to be increased.

[0082] The level shifter circuit 608 transfers the digital value at the output of the first inverter 606 from the first portion of the closed-loop regulation circuit 600 (referred to as a floating ground) to the second portion of the closed-loop regulation circuit 600 (having a reference ground). Common methods for implementing the level shifter circuit 608 include optical isolators (i.e., optocouplers), transformers, and cascode structures. Thus, the level shifter circuit 608 transfers the digital value at the output of the first inverter 606 to the first flip-flop (FF 1 )610's reset (R) input.

[0083] In an embodiment, the first flip-flop (FF 1 ) 610 is a reset-dominated level-sensitive set-reset (SR) flip-flop. 1 )610 is reset dominant, and the reset (R) input takes precedence over the set (S) input. This means that if both the set (S) input and the reset (R) input are at a high level, the first flip-flop (FF 1 )610 will enter the "reset" state to ignore the set (S) input. The high-side signal (HVG) is on the first flip-flop (FF 1) is provided at the set (S) input of 610. Therefore, when the high side switch (Q 1 )202 is activated, the first trigger (FF 1 ) is “set”.

[0084] In addition, since the first trigger (FF 1 )610 is level sensitive, so the first trigger (FF 1 ) 610 reacts to the level of the input signal rather than its edge transitions. Therefore, as long as the set (S) input or the reset (R) input remains at a specific logic level (high or low), the output will maintain its corresponding state. Therefore, if the output of the first inverter 606 is set to a logic level high (e.g., '1'), indicating that the delay needs to be reduced, the reset signal is on the first flip-flop (FF 1 ) 610 is asserted at the reset (R) input of the first flip-flop (FF). Conversely, if the output of the first inverter 606 is set to a logic level low (eg, '0'), indicating that an increase in delay is required, the reset signal is asserted at the reset (R) input of the first flip-flop (FF 1 )The reset (R) input of 610 is not asserted.

[0085] When the reset (R) input is at logic level high (i.e., the bootstrap capacitor (C BOOT )114 exceeds the first threshold voltage (V TH1 )) When the high-voltage side switch (Q 1 )202 is activated or deactivated, the first trigger (FF 1 ) are at a logic level low. This is because the reset (R) input dominates and will override the state of the set (S) input and force the output (Q) low.

[0086] When (i) the high-side switch (Q 1 ) 202 is activated and (ii) the reset (R) input is at a logic level low (i.e., the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 )) When the first trigger (FF 1 ) is at a logic level high. This is because the reset (R) input is low and the set (S) input affects the output (Q) to set it to a high state.

[0087] If the set (S) input and the reset (R) input are at logic low, the high side switch (Q 1 )202 is disabled and the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), the output (Q) will maintain its last value (high or low).

[0088] The first input of the first AND gate 614 is coupled to the first flip-flop (FF 1 ) output (Q). The second inverter 612 inverts the logic signal of the high-voltage side signal (HVG) to generate an inverted high-voltage side signal (HVG N ), when the high-side switch (Q 1 )202 is disabled, the signal is at logic level high, and when the high side switch (Q 1 )202 is activated, the signal is at a logic level low.

[0089] Therefore, when (i) the high-side switch (Q 1 ) 202 is disabled and (ii) the first trigger (FF 1 ) is at a logic level high, the output of the first AND gate 614 provides a positive edge signal to the input of the reverse current timer programming circuit 625, which indicates that the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ).

[0090] The reverse current timer programming circuit 625 includes a first mono-flop (MF 1 )616, the second monostable trigger (MF 2 )618, a first current generator 620, a first capacitor (C 1 ) 622 and a second current generator 624, which may or may not be arranged as shown. Alternatively, in an embodiment, the reverse current timer programming circuit 625 is implemented digitally as an up-down counter.

[0091] The reverse current timer circuit 631 includes a fixed current generator 626, a switch (SW) 628, a second capacitor (C 2 )630, XNOR gate 638 and a second comparator (COMP 2 ) 632. Alternatively, in an embodiment, the reverse current timer circuit 631 is digitally implemented as an up counter.

[0092] In an embodiment, when the reverse current timer programming circuit 625 and the reverse current timer circuit 631 are implemented in a digital manner, the second comparator (COMP 2 )632 is implemented as a digital comparator.

[0093] The end of count (EoC) counter is implemented in the closed-loop regulation circuit 600 by the reverse current timer programming circuit 625, the reverse current timer circuit 631 and the second AND gate 640. The first monostable trigger (MF1 ) 616 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, the first monostable trigger (MF 1 )616 is arranged as a positive edge triggered monostable trigger.

[0094] In response to the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), the positive edge signal (the signal that changes from logic level low to logic level high) from the first AND gate 614 triggers the first monostable trigger (MF 1 )616, resulting in the first monostable trigger (MF 1 ) 616 changes in state and the duration (Δt 1 ) generates a charging pulse (CHP) within the circuit, thereby activating the first current generator 620.

[0095] Activation of the first current generator 620 causes charge to flow into the first capacitor (C 1 )622. Added to the first capacitor (C 1 )622 charge (ΔQ) can be expressed by the following formula: ΔQ = I × Δt 1 , where I is a constant current generated by the first current generator 620. In an embodiment, the current added to the first capacitor (C 1 ) 622 has a charge (ΔQ) of 60 to 360 pico-Coulombs (pC). In an embodiment, the first capacitor (C 1 ) 622 is integrated in the closed-loop regulation circuit 600. In an embodiment, the first capacitor (C 1 )622 is 10 picofarads (pF).

[0096] When the high-side switch (Q 1 )202 is activated (corresponding to the high voltage side signal (HVG) changing from logic level low to logic level high), the positive edge signal is provided to the second monostable trigger (MF 2 )618 input. The positive edge signal triggers the second monostable trigger (MF 2 )618, resulting in the second monostable trigger (MF 2 ) 618 changes in state and the duration (Δt 2 ) generates a discharge pulse (DISCHP) in the first capacitor (C ), thereby activating the second current generator 624. The second current generator 624 is a negative current generator. The activation of the second current generator 624 causes the first capacitor (C 1) 622. In an embodiment, the first current generator 620 and the second current generator 624 have different charging ramp speeds and discharging ramp speeds, respectively.

[0097] Since the first capacitor (C 1 ) 622 is charged only during the period when the output of the first AND gate 614 is at a logic level high, and the first capacitor (C 1 )622 discharges during each cycle, so the closed-loop regulation circuit 600 determines a balance at which the output of the first AND gate 614 is at a logic level high for a certain number of cycles and at a logic level low for a certain number of cycles.

[0098] Therefore, over multiple cycles, across the first capacitor (C 1 )622 generates a DC voltage with small ripple. The first capacitor (C 1 The size of )622 is such that the ripple is negligible compared to the DC voltage. The DC voltage is provided as a reference voltage to the second comparator (COMP 2 )632's inverting input.

[0099] The fixed current generator 626 and the second capacitor (C 2 )630 to the second comparator (COMP 2 )632 provides a ramp voltage to the non-inverting input. When provided to the second comparator (COMP 2 ) 632 reaches the DC voltage level, the first input of the second AND gate 640 is at a logic high level. N ) is at logic level high (i.e., the high-side switch (Q 1 )202 is disabled), the second input of the second AND gate 640 is also at a logic level high. Therefore, the output of the second AND gate 640 is at a logic level high, which causes the reset signal to be on the second flip-flop (FF 2 )The “reset” (R) input of 642 is asserted.

[0100] In an embodiment, the second flip-flop (FF 2 )642 is an edge-sensitive set-reset (SR) type flip-flop. Therefore, the second flip-flop (FF 2 The state of the output (Q) of )642 changes based on the set (S) input and the reset (R) input, but only when a triggering edge occurs on the clock signal. The triggering edge can be the rising edge or the falling edge of the clock signal.

[0101] In an embodiment, in response to the high side signal (HVG) being at a logic level high (ie, the high side switch (Q1 )202 is activated), by asserting to the second flip-flop (FF 2 )642's "set" (S) input sets the second flip-flop (FF 2 )642.

[0102] When the trigger edge occurs, if the set (S) input is at a logic level high and the reset (R) input is at a logic level low, the second flip-flop (FF 2 )642 will transition to a logic high. Conversely, if the reset (R) input is high and the set (S) input is low at the trigger edge, the output (Q) will transition to a logic low. This is because the second flip-flop (FF 2 )642 "latches" the states of the set (S) and reset (R) inputs at the clock edge and updates its output accordingly. During the trigger edge, if both the set (S) and reset (R) inputs are low, the output (Q) will generally remain in its last state. This means that the second flip-flop (FF 2 )642 maintains its previous output value, whether high or low, until another triggering edge occurs that causes a change.

[0103] Therefore, when the high-side switch (Q 1 )202 is disabled (ie, the set (S) input is set to a logic low), the second flip-flop (FF 2 )642 will cause the second flip-flop (FF 2 )642 output (Q) is logic level low, which disables the low side switch (Q 2 )204, because the second flip-flop (FF 2 )642 output (Q) to the low voltage side switch (Q 2 ) The gate terminal of 204 provides a low voltage side signal (LVG A ).

[0104] The control signal of the switch (SW) 628 is provided by an XNOR gate 638. The first input of the XNOR gate 638 is the high voltage side signal (HVG), and the second input is the second flip-flop (FF 2 )642 output (Q). When the high voltage side signal (HVG) and the low voltage side signal (LVG A ) is at logic level high (i.e., the high-side switch (Q 1 )202 and low voltage side switch (Q 2 )204 is in the on state) or in the logic level low (ie, the high side switch (Q 1 )202 and low voltage side switch (Q 2) 204 is in the off state), the output of the XNOR gate 638 is at a logic level high, which closes the switch (SW) 628 and resets the closed-loop regulation circuit 600. Otherwise, the switch (SW) 628 remains open.

[0105] Therefore, at step 516, after the counter of the closed-loop regulation circuit 600 reaches the end-of-count (EoC) counter value, the low-side switch (Q 2 )204 is disabled. Therefore, for consecutive cycles, in response to the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), the end of count (EoC) counter value increases, and in response to the bootstrap capacitor (C BOOT )114 is greater than the first threshold voltage (V TH1 ), the end of count (EoC) counter value decreases. Advantageously, this process allows the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 and the duration of the delay between the turn-off of the bootstrap capacitor (C BOOT )114Recharge.

[0106] Figure 7 FIG. 1 is a schematic diagram of an embodiment closed-loop regulation circuit 700 that can be implemented in the dual-switch flyback converter 200 for condition B of the method 500. In an embodiment, the closed-loop regulation circuit 700 is configured to 1 )202 is deactivated and then condition B is checked to determine the delay until the low-voltage side switch (Q 2 )204 disabled.

[0107] The closed-loop regulation circuit 700 checks condition B and automatically adjusts the high-side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 is turned off. If the regulated voltage (V cc ) and across the bootstrap capacitor (C BOOT )114 is greater than the second threshold voltage (V TH2 ), then increase the delay. This can be expressed as: if And, if the regulated voltage (V cc ) and across the bootstrap capacitor (C BOOT )114 is less than the second threshold voltage (V TH2 ), then the delay is reduced. This can be expressed as: if

[0108] The output of the closed-loop regulation circuit 700 (LVG B) is coupled to the low side switch (Q) via, for example, a gate driver (not shown) 2 )204's gate terminal to effectively turn off the low side switch after a delay adjusted by the closed loop regulation circuit 700 based on condition B.

[0109] The closed-loop regulation circuit 700 includes a first comparator (COMP 1 ) 702, an optional differential amplifier 704, an adder circuit 706, a first inverter 708, a first AND gate 710, a reverse current timer programming circuit 711, a reverse current timer circuit 712, a second AND gate 732 and a flip-flop (FF) 734, which may or may not be arranged as shown. The closed-loop regulation circuit 700 may include additional components not shown, such as a filter circuit. The input of the closed-loop regulation circuit 700 is coupled to a bootstrap capacitor (C BOOT )114.

[0110] In an embodiment, the differential amplifier 704 has a unity gain and its non-inverting input is coupled to a regulated voltage (V cc ) and its inverting input is coupled to a second threshold voltage (V TH2 ). The first comparator (COMP 1 ) 702 is configured to effectively provide a regulated voltage (V cc ) and across the bootstrap capacitor (C BOOT )114 and the second threshold voltage (V TH2 ) is compared. As described in method 500, a check can be performed to determine whether the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 is based on the second condition (condition B) of the delay between the turn-off of the regulated voltage (V cc ) and across the bootstrap capacitor (C BOOT )114 is less than the second threshold voltage (V TH2 In an embodiment, the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is provided to the adder circuit 706. In this embodiment, the regulated voltage (V cc ) is provided to the non-inverting input of the adder circuit 706, and the second threshold voltage (V TH2 ) is provided to the inverting input of adder circuit 706.

[0111] The first comparator (COMP 1 ) 702 is configured with hysteresis - its past state affects its output due to the feedback connection made via adder circuit 706. Adder circuit 706 has a circuit configured to receive a regulated voltage (Vcc ) and the second threshold voltage (V TH2 ) is a first input of the difference between . A second input of the adder circuit 706 is configured to receive the comparator output. The first comparator (COMP 1 )702 is configured to generate an output signal which is fed to a first input of a first AND gate 710.

[0112] In an embodiment, the first comparator (COMP 1 )702 based on (i) across the bootstrap capacitor (C BOOT ) 114 voltage and (ii) regulated voltage (V cc ) and the second threshold voltage (V TH2 ) to provide an output signal to the first AND gate 710. In response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is greater than the difference across the bootstrap capacitor (C BOOT ) 114, the voltage of the first comparator (COMP 1 ) 702 will output a logic level high (eg, '1'). In response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is less than the difference across the bootstrap capacitor (C BOOT ) 114, the voltage of the first comparator (COMP 1 ) 702 will output a logic level low (eg, '0').

[0113] In response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is less than the difference across the bootstrap capacitor (C BOOT ) 114, at step 504, the first comparator (COMP 1 ) 702 is set to a logic level low (eg, '0'), which indicates that as the voltage at the floating ground (FGND) node (V FGND ) is below zero, the delay needs to be reduced. In response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is greater than the difference across the bootstrap capacitor (C BOOT ) 114, at step 504, the first comparator (COMP 1 ) 702 is set to a logic level high (eg, '1'), indicating that as the voltage at the floating ground (FGND) node (V FGND ) is above zero, the delay needs to be increased.

[0114] The second input of the first AND gate 710 is coupled to the high side signal (HVG). 1 ) 202 is activated and (ii) the first comparator (COMP 1 ) 702 is set to a logic level high (eg, '1'), the output of the first AND gate 710 provides a positive edge signal to the input of the reverse current timer programming circuit 711, which indicates that the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is greater than the difference across the bootstrap capacitor (C BOOT )114 voltage.

[0115] The reverse current timer programming circuit 711 includes a first monostable trigger (MF 1 )712, the second monostable trigger (MF 2 )720, the first current generator 714, the first capacitor (C 1 ) 716 and a second current generator 718, which may or may not be arranged as shown. Alternatively, in an embodiment, the reverse current timer programming circuit 711 is implemented digitally as an up-down counter.

[0116] The reverse current timer circuit 713 includes a fixed current generator 722, a switch (SW) 724, a second capacitor (C 2 )726, XNOR gate 728 and the second comparator (COMP 2 ) 730. Alternatively, in an embodiment, the reverse current timer circuit 713 is digitally implemented as an up-counter.

[0117] In an embodiment, when the reverse current timer programming circuit 625 and the reverse current timer circuit 631 are implemented in a digital manner, the second comparator (COMP 2 )730 is implemented as a digital comparator.

[0118] The end of count (EoC) counter is implemented in the closed-loop regulation circuit 700 by the reverse current timer programming circuit 711, the reverse current timer circuit 713 and the second AND gate 732. 1 ) 712 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, the first monostable trigger (MF 1 )712 is arranged as a positive edge triggered monostable trigger.

[0119] In response to (i) the high side switch (Q 1 ) 202 is activated and (ii) the first comparator (COMP1 ) 702 is set to a logic level high (eg, '1'), which indicates that the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is greater than the difference across the bootstrap capacitor (C BOOT ) 114, the positive edge signal (the signal when the logic level changes from low to high) from the first AND gate 710 triggers the first monostable trigger (MF 1 )712, resulting in the first monostable trigger (MF 1 ) 712 changes its state and its output (Q) is at a duration (Δt 1 ) generates a charging pulse (CHP) within the circuit, thereby activating the first current generator 714.

[0120] Activation of the first current generator 714 causes charge to flow into the first capacitor (C 1 )716. Added to the first capacitor (C 1 )716 charge (ΔQ) can be expressed by the following formula: ΔQ = I × Δt 1 , where I is a constant current generated by the first current generator 714. In an embodiment, the current added to the first capacitor (C 1 ) 716 has a charge (ΔQ) of 60 to 360 pico-Coulombs (pC). In an embodiment, the first capacitor (C 1 ) 716 is integrated in the closed-loop regulation circuit 700. In an embodiment, the first capacitor (C 1 )716 is 10 picofarads (pF).

[0121] In an embodiment, the second monostable trigger (MF 1 )720 is arranged as a negative edge triggered monostable trigger. When the high side switch (Q 1 )202 is disabled (corresponding to the high voltage side signal (HVG) changing from logic level high to logic level low), the negative edge signal is provided to the second monostable trigger (MF 2 )720 input. The negative edge signal triggers the second monostable trigger (MF 2 )720, resulting in the second monostable trigger (MF 2 ) 720 changes its state and its output (Q) is at a duration (Δt 2 ) generates a discharge pulse (DISCHP) in the first capacitor (C ), thereby activating the second current generator 718. The second current generator 718 is a negative current generator. The activation of the second current generator 718 causes the first capacitor (C 1 ) 716. In an embodiment, the first current generator 714 and the second current generator 720 have different charging ramp speeds and discharging ramp speeds, respectively.

[0122] Since the first capacitor (C 1 ) 716 is charged only during the period when the output of the first AND gate 710 is at a logic level high, and the first capacitor (C 1 )716 discharges during each cycle, so the closed-loop regulation circuit 700 determines a balance at which the output of the first AND gate 710 is at a logic level high for a certain number of cycles and at a logic level low for a certain number of cycles.

[0123] Therefore, over multiple cycles, across the first capacitor (C 1 )716 generates a DC voltage with small ripple. The first capacitor (C 1 ) 716 is sized so that the ripple is negligible compared to the DC voltage. The DC voltage is provided as a reference voltage to the second comparator (COMP 2 )The inverting input of 730.

[0124] The fixed current generator 722 and the second capacitor (C 2 )726 to the second comparator (COMP 2 )730 provides a ramp voltage to the non-inverting input. When provided to the second comparator (COMP 2 )When the ramp voltage at the non-inverting input of 730 reaches the DC voltage level, the first input of the second AND gate 732 is at a logic level high.

[0125] The first inverter 708 inverts the logic signal of the high-voltage side signal (HVG) to generate an inverted high-voltage side signal (HVG N ), when the high-side switch (Q 1 )202 is disabled, the signal is at logic level high, and when the high side switch (Q 1 )202 is activated, the signal is at logic level low. N ) is at logic level high (i.e., the high-side switch (Q 1 )202 is disabled), the second input of the second AND gate 732 is also at a logic level high. Therefore, the output of the second AND gate 732 is at a logic level high, which causes the reset signal to be asserted at the "reset" (R) input of the flip-flop (FF) 734.

[0126] In an embodiment, the flip-flop (FF) 734 is an edge-sensitive set-reset (SR) type flip-flop. Therefore, the state of the output (Q) of the flip-flop (FF) 734 changes based on the set (S) input and the reset (R) input, but only changes when a trigger edge appears on the clock signal. The trigger edge can be the rising edge or the falling edge of the clock signal.

[0127] In an embodiment, in response to the high side signal (HVG) being at a logic level high (ie, the high side switch (Q 1 )202 is activated), the flip-flop (FF) 734 is set by asserting a set signal to the “set” (S) input of the flip-flop (FF) 734.

[0128] When the trigger edge occurs, if the set (S) input is at a logic level high and the reset (R) input is at a logic level low, the output (Q) of the flip-flop (FF) 734 will transition to a logic level high. Conversely, if the reset (R) input is high and the set (S) input is low at the time of the trigger edge, the output (Q) will transition to a logic level low. This is because the flip-flop (FF) 734 "latches" the states of the set (S) input and the reset (R) input at the time of the clock edge and updates its output accordingly. During the trigger edge, if both the set (S) input and the reset (R) input are low, the output (Q) will generally remain in its last state. This means that the flip-flop (FF) 734 maintains its previous output value, whether high or low, until another trigger edge occurs that causes a change.

[0129] Therefore, when the high-side switch (Q 1 )202 is disabled (i.e., the set (S) input is set to a logic level low), resetting the flip-flop (FF) 734 causes the output (Q) of the flip-flop (FF) 734 to be at a logic level low, which disables the low-side switch (Q 2 )204, because the output (Q) of the flip-flop (FF) 734 is switched to the low voltage side switch (Q 2 ) The gate terminal of 204 provides a low voltage side signal (LVG B ).

[0130] The control signal of switch (SW) 724 is provided by XNOR gate 728. The first input of XNOR gate 728 is the high voltage side signal (HVG), and the second input is the output (Q) of flip-flop (FF) 734. B ) is at logic level high (i.e., the high-side switch (Q 1 )202 and low voltage side switch (Q 2 )204 is in the on state) or in the logic level low (ie, the high side switch (Q 1 )202 and low voltage side switch (Q 2 )204 is in the off state), the output of the XNOR gate 728 is at a logic level high, which closes the switch (SW) 724 and resets the closed-loop regulation circuit 700. Otherwise, the switch (SW) 724 remains open.

[0131] Therefore, at step 516, after the counter of the closed-loop regulation circuit 700 reaches the end-of-count (EoC) counter value, the low-side switch (Q 2 )204 is disabled. Therefore, for consecutive cycles, in response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is less than the difference across the bootstrap capacitor (C BOOT ) 114, the end of count (EoC) counter value increases, and in response to the regulated voltage (V cc ) and the second threshold voltage (V TH2 ) is greater than the difference across the bootstrap capacitor (C BOOT ) 114, the end of count (EoC) counter value decreases. Advantageously, this process allows dialing in the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 and the duration of the delay between the turn-off of the bootstrap capacitor (C BOOT )114Recharge.

[0132] Figure 8 A schematic diagram of an embodiment closed-loop regulation circuit 800 that may be implemented in the two-switch flyback converter 200 for condition C of the method 500 is illustrated.

[0133] The closed-loop regulation circuit 800 checks condition C and automatically adjusts the high-side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204. If the high-side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is greater than the third threshold voltage (V TH3 ), then increase the delay. This can be expressed as: if Where V FGND is 2 τ in seconds 1 The voltage at the floating ground (FGND) within seconds. If the high-side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is less than the third threshold voltage (V TH3 ), the delay is reduced.

[0134] This can be expressed as: If

[0135] The output of the closed-loop regulation circuit 800 is coupled to the low-side switch (Q 2 )204's gate terminal to effectively turn off the low side switch after a delay adjusted by the closed loop regulation circuit 800 based on condition C.

[0136] The closed-loop regulation circuit 800 includes a first resistor (R 1 )802, the second resistor (R 2 )804, adder circuit 806, first comparator (COMP 1 )808, the first monostable trigger (MF 1 )810, a first AND gate 812, a second AND gate 814, a second monostable trigger (MF 2 )816, first trigger (FF 1 )818, a first inverter 820, a third AND gate 822, a reverse current timer programming circuit 823, a reverse current timer circuit 825, a fourth AND gate 824 and a second flip-flop (FF 2 )826, which may or may not be arranged as shown. The closed-loop regulation circuit 800 may include additional components not shown, such as filter circuits. The input of the closed-loop regulation circuit 800 is coupled to the high-side transistor (Q 1 )104's source terminal.

[0137] The first comparator (COMP 1 )808 is configured to pass through a voltage divider (ie, including a first resistor (R 1 )802 and the second resistor (R 2 )804) effectively divides the voltage at the floating ground (FGND) node (V FGND ) and the third threshold voltage (V TH3 ) is compared. As described in method 500, a check can be performed to determine whether the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 is based on the delay between the turn-off of the high-side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is less than the third threshold voltage (V TH3 ).

[0138] The first comparator (COMP 1) 808 is configured with hysteresis - the hysteresis is provided from the output of the first AND gate 812. The first comparator (COMP 1 ) 808 is configured to receive a voltage (V FGND ) is the inverting input (-). The first comparator (COMP 1 )The non-inverting input of 808 is coupled to the output of adder circuit 806.

[0139] The adder circuit 806 has a circuit configured to receive a third threshold voltage (V TH3 ). A second input of the adder circuit 806 is configured to receive the output of the first AND gate 812. The first comparator (COMP 1 ) 808 is configured to generate a first monostable trigger (MF 1 ) 810 and the output signal of the first input of the first AND gate 812. The second input of the first AND gate 812 is coupled to the first monostable trigger (MF 1 )810 non-Q Output.

[0140] The first monostable trigger (MF 1 )810 is configured to switch from a stable state to an unstable state in response to being triggered 1 seconds, and then automatically returns to a stable state. In an embodiment, the first monostable trigger (MF 1 )810 is arranged as an edge-triggered (positive or negative) monostable trigger.

[0141] In response to the first comparator (COMP 1 ) The output of 808 changes from a logic level high to a logic level low or from a logic level low to a logic level high, and the first monostable trigger (MF 1 )810 is triggered, resulting in a change of state and a first monostable trigger (MF 1 )810 non-Q Output at τ 1 A set signal is generated to the second input of the first AND gate 812 for a duration of 10 seconds.

[0142] In response to the first comparator (COMP 1 )808 output and the first monostable trigger (MF 1 )810 non-Q The output of the first AND gate 812 is at a logic level high, and the first AND gate 812 provides a logic level high signal to the first input of the second AND gate 814. The second input of the second AND gate 814 is controlled by a second monostable trigger (MF 2 )The output (Q) of 816 is provided.

[0143] The second monostable trigger (MF 2 )816 is configured to switch from a stable state to an unstable state in response to being triggered 2 seconds, and then automatically returns to a stable state. In an embodiment, the second monostable trigger (MF 2 )816 is arranged as a negative edge triggered monostable trigger. In particular, the second monostable trigger (MF 2 )816 responds to the high side signal (HVG) changing from a logic level high to a logic level low (i.e., the high side switch (Q 1 )202 is disabled), which is provided to the input of the second AND gate 814 as a logic high signal.

[0144] In response to the high side signal (HVG) changing from logic level high to logic level low and the output of the first AND gate 812 being at logic level high, the second AND gate 814 supplies the first flip-flop (FF 1 )818 provides a reset signal at its reset (R) input. In an embodiment, the first flip-flop (FF 1 )818 is an edge sensitive trigger. When the high voltage side signal (HVG) is at a logic high level, the first trigger (FF 1 )The set (S) input of 818 is set.

[0145] Therefore, when the high-side switch (Q 1 )202 is disabled and the first AND gate 812 is at a logic high level, the second AND gate resets the first flip-flop (FF 1 )818 and provides a logic level high to a first input of a third AND gate 822. A second input of the third AND gate 822 is coupled to the output of the first inverter 820. The first inverter 820 inverts the high-side signal (HVG) to generate an inverted high-side signal (HVG N ). Therefore, when the high-side switch (Q 1 )202 is disabled, the inverted high-voltage side signal (HVG N ) is at a logic level high. The third input of the third AND gate 822 is coupled to the second monostable trigger (MF 2 )816 non-Q Output.

[0146] The reverse current timer programming circuit 823 includes a third monostable trigger (MF 3 )828, the fourth monostable trigger (MF 4 )830, a first current generator 832, a first capacitor (C 1) 834 and a second current generator 836, which may or may not be arranged as shown. Alternatively, in an embodiment, the reverse current timer programming circuit 823 is digitally implemented as an up-down counter.

[0147] The reverse current timer circuit 825 includes a fixed current generator 838, a switch (SW) 840, a second capacitor (C 2 )842, XNOR gate 844 and the second comparator (COMP 2 ) 846. Alternatively, in an embodiment, the reverse current timer circuit 825 is digitally implemented as an up-counter.

[0148] In an embodiment, when the reverse current timer programming circuit 823 and the reverse current timer circuit 825 are implemented in a digital manner, the second comparator (COMP 2 )846 is implemented as a digital comparator.

[0149] The end of count (EoC) counter is implemented in the closed-loop regulation circuit 800 by the reverse current timer programming circuit 823, the reverse current timer circuit 825 and the fourth AND gate 824. 3 ) 828 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, the third monostable trigger (MF 3 )828 is arranged as a positive edge triggered monostable trigger.

[0150] In response to the three inputs of the third AND gate 822 being turned into logic level high, the positive edge trigger is provided to the third monostable trigger (MF) of the reverse current timer programming circuit 823. 3 The positive edge signal (the signal that changes from logic level low to logic level high) from the third AND gate 822 triggers the third monostable trigger (MF 3 )828, resulting in a change of state and a duration (Δt 3 ) generates a charge pulse (CHP) within the circuit, thereby activating the first current generator 832.

[0151] Activation of the first current generator 832 causes charge to flow into the first capacitor (C 1 )834. Added to the first capacitor (C 1 )834's charge (ΔQ) can be expressed by the following formula: ΔQ = I × Δt 2 , where I is a constant current generated by the first current generator 832. In an embodiment, the current added to the first capacitor (C 1)834 has a charge (ΔQ) of 60 to 360 pico-Coulombs (pC). In an embodiment, the first capacitor (C 1 ) 834 is integrated in the closed-loop regulation circuit 800. In an embodiment, the first capacitor (C 1 )834 is 10 picofarads (pF).

[0152] In an embodiment, the fourth monostable trigger (MF 4 )830 is arranged as a positive edge triggered monostable trigger. When the high side switch (Q 1 )202 is activated (corresponding to the high voltage side signal (HVG) changing from logic level low to logic level high), the positive edge signal is provided to the fourth monostable trigger (MF 4 )830 input. The positive edge signal triggers the fourth monostable trigger (MF 4 )830, resulting in a change of state and a duration (Δt 4 ) generates a discharge pulse (DISCHP) in the first capacitor (C ), thereby activating the second current generator 836. The second current generator 836 is a negative current generator. The activation of the second current generator 836 causes the first capacitor (C 1 ) 834. In an embodiment, the first current generator 832 and the second current generator 836 have different charging ramp speeds and discharging ramp speeds, respectively.

[0153] Since the first capacitor (C 1 )834 is charged only during the period when the output of the third AND gate 822 is at a logic level high, and the first capacitor (C 1 )834 discharges within each cycle, so the closed-loop regulation circuit 800 determines a balance at which the output of the third AND gate 822 is at a logic level high for a certain number of cycles and at a logic level low for a certain number of cycles.

[0154] Therefore, over multiple cycles, across the first capacitor (C 1 )834 generates a DC voltage with small ripple. The first capacitor (C 1 )834 is sized so that the ripple is negligible compared to the DC voltage. The DC voltage is the second comparator (COMP 2 )The reference voltage of the inverting input of 846.

[0155] The fixed current generator 838 and the second capacitor (C 2 )842 to the second comparator (COMP 2 )846 provides a ramp voltage to the non-inverting input. When supplied to the second comparator (COMP 2) When the ramp voltage at the non-inverting input of 846 reaches the DC voltage level, the first input of the fourth AND gate 824 is at a logic level high.

[0156] Due to the inverted high-voltage side signal (HVG N ) is at logic level high (i.e., the high-side switch (Q 1 )202 is disabled), the second input of the fourth AND gate 824 is also at a logic level high. Therefore, the output of the fourth AND gate 824 is at a logic level high, which causes the reset signal to be on the second flip-flop (FF 2 )The “reset” (R) input of 826 is asserted.

[0157] In an embodiment, the second flip-flop (FF 2 )826 is an edge-sensitive set-reset (SR) type flip-flop. Therefore, the second flip-flop (FF 2 The state of the output (Q) of )826 changes based on the set (S) input and the reset (R) input, but only when a triggering edge appears on the clock signal. The triggering edge can be the rising edge or the falling edge of the clock signal.

[0158] In an embodiment, in response to the high side signal (HVG) being at a logic level high (ie, the high side switch (Q 1 )202 is activated), by asserting to the second flip-flop (FF 2 )826 to set the second flip-flop (FF 2 )826.

[0159] When the trigger edge occurs, if the set (S) input is at a logic level high and the reset (R) input is at a logic level low, the second flip-flop (FF 2 )826 will transition to a logic high. Conversely, if the reset (R) input is high and the set (S) input is low at the trigger edge, the output (Q) will transition to a logic low. This is because the second flip-flop (FF 2 )826 "latches" the states of the set (S) and reset (R) inputs at the clock edge and updates its output accordingly. During the trigger edge, if both the set (S) and reset (R) inputs are low, the output (Q) will generally remain in its last state. This means that the second flip-flop (FF 2 )826 maintains its previous output value, whether high or low, until another triggering edge occurs that causes a change.

[0160] Therefore, when the high-side switch (Q 1 )202 is disabled (ie, the set (S) input is set to a logic low), the second flip-flop (FF2 )826 causes the second flip-flop (FF 2 )826 output (Q) is logic level low, which disables the low side switch (Q 2 )204, because the second flip-flop (FF 2 )826 output (Q) to the low voltage side switch (Q 2 ) The gate terminal of 204 provides a low voltage side signal (LVG C ).

[0161] The control signal of the switch (SW) 840 is provided by an XNOR gate 844. The first input of the XNOR gate 844 is the high voltage side signal (HVG), and the second input is the second flip-flop (FF 2 )826 output (Q). When the high voltage side signal (HVG) and the low voltage side signal (LVG) are at logic level high (i.e., the high voltage side switch (Q 1 )202 and low voltage side switch (Q 2 )204 is in the on state) or in the logic level low (ie, the high side switch (Q 1 )202 and low voltage side switch (Q 2 ) 204 is in the off state), the output of the XNOR gate 844 is at a logic level high, which closes the switch (SW) 840 and resets the closed-loop regulation circuit 800. Otherwise, the switch (SW) 840 remains open.

[0162] Therefore, at step 516, after the counter of the closed-loop regulation circuit 800 reaches the end-of-count (EoC) counter value, the low-side switch (Q 2 )204 is disabled. Therefore, for consecutive cycles, in response to the high side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is higher than the third threshold voltage (V TH3 ), the end of count (EoC) counter value increases. And, in response to the high side switch (Q 1 )202 immediately after the shutdown τ 2 τ in seconds 1 The voltage at the floating ground (FGND) node (V FGND ) is less than the third threshold voltage (V TH3 ), the end of count (EoC) counter value decreases. Advantageously, this process allows the high side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204 and the duration of the delay between the turn-off of the bootstrap capacitor (CBOOT )114Recharge.

[0163] Fig. 9 A flow chart of an embodiment method 900 for operating a dual-switch flyback converter 200 based on direct delay setting (DDS) is illustrated. It should be noted that all steps listed in the flow chart are not necessarily required, but may be optional. In addition, changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections may similarly be considered.

[0164] In an embodiment, to ensure that the voltage at the floating ground (FGND) node (V FGND ) becomes zero, the high-side switch (Q 1 )202 is deactivated with a delay, the low-voltage side switch (Q 2 )204 is disabled. In an embodiment, based on DDS, the delay is only the voltage (V FGND ) drops to the fourth threshold voltage (V TH4 ) is introduced later. 1 )202 is turned off and then the low voltage side switch (Q 2 )204 is set to sufficiently allow the voltage at the floating ground (FGND) node (V FGND ) drops to the fourth threshold voltage (V TH4 ) to allow the bootstrap capacitor (C BOOT )114Recharge.

[0165] To implement DDS, either monitor the voltage at the floating ground (FGND) node (V FGND ) until it reaches zero, or monitor the bootstrap capacitor (C BOOT )114 until it drops to the regulated voltage (V cc ) below. After detecting one or both conditions, the low-voltage side switch (Q 2 )204 before shutting down to allow the bootstrap capacitor (C BOOT )114Recharge.

[0166] At step 902, the DDS operation starts. At step 904, the high side switch (Q 1 )202 and low voltage side switch (Q 2 ) 204. At step 906, the high side switch (Q 1 ) 202. In an embodiment, when the peak inductor current reaches a value programmed by the control loop, the high side switch (Q 1 )202 is disabled. In an embodiment, the control loop adjusts the high side switch (Q 1)202 and low voltage side switch (Q 2 )204 duty cycle to adjust the output voltage (V OUT In an embodiment, the current sensor measures the inductor current in real time which is fed into the control loop. After the inductor current reaches a predetermined peak value set by the control loop, the high side switch (Q 1 )202 is turned off. This action terminates the primary side (L P ) in the winding and initiates the energy storage phase to the secondary side (L S ) of the winding energy transfer.

[0167] At step 908, the fourth threshold voltage (V TH4 ) monitors the voltage (V FGND ). Alternatively, monitoring the bootstrap capacitor (C BOOT ) The voltage at 114 (V BOOT ) until it drops to the regulation voltage (V cc )the following.

[0168] At step 910, in response to the voltage (V FGND ) drops to the fourth threshold voltage (V TH4 ) or a bootstrap capacitor (C BOOT ) The voltage at 114 (V BOOT ) down to the regulated voltage (V cc ) below, after a predetermined delay, the low-side switch (Q 2 ) 204 is disabled. In an embodiment, the predetermined delay is provided by an internal delay (e.g., 100 ns) from, for example, a delay introduced by a comparator for checking a condition, a delay for turning off the switch, or a combination thereof. For subsequent cycles of the dual-switch flyback converter 200, steps 904 to 910 are repeated.

[0169] Fig.10 A flow chart of an embodiment method 1000 for operating a dual-switch flyback converter 200 using an open-loop control algorithm is illustrated. It should be noted that all steps listed in the flow chart are not necessarily required, but may be optional. In addition, changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections may similarly be considered.

[0170] Generally, the leakage inductance energy depends on the peak inductor current. A larger peak inductor current (e.g., heavy load) will result in higher leakage inductance energy, which will require a shorter delay. Conversely, a smaller peak inductor current (e.g., light load) will result in lower leakage inductance energy, which will require a longer delay.

[0171] In an embodiment, the load condition (e.g., heavy load or light load) can be monitored using peak current mode control because the control voltage (V C ) is associated with (ie, proportionally related to) the peak inductor current. Thus, in an embodiment, the delay corresponds to the control voltage (V C ). Therefore, for heavy loads, the control voltage (V C ) is higher, while for light loads, the control current (V C ) is smaller.

[0172] At step 1002, the open loop regulation operation begins. At step 1004, the high side switch (Q 1 )202 and low voltage side switch (Q 2 ) 204. At step 1006, the high side switch (Q 1 ) 202. In an embodiment, when the peak inductor current reaches a value programmed by the control loop, the high side switch (Q 1 )202 is disabled. In an embodiment, the control loop adjusts the high side switch (Q 1 )202 and low voltage side switch (Q 2 )204 duty cycle to adjust the output voltage (V OUT In an embodiment, the current sensor measures the inductor current in real time which is fed into the control loop. After the inductor current reaches a predetermined peak value set by the control loop, the high side switch (Q 1 )202 is turned off. This action terminates the primary side (L P ) in the winding and initiates the energy storage phase to the secondary side (L S ) of the winding energy transfer.

[0173] At step 1008, a counter is used based on a programmable delay. In an embodiment, the high side switch (Q 1 )202 after the low-voltage side switch (Q 2 )204 is used to adjust the output voltage (V OUT ) of the feedback loop control voltage (V C ). Therefore, for heavy loads, the control voltage (V C ) is higher and the delay is shorter, while for light loads, the control voltage (V C ) is smaller and the delay is longer. In an embodiment, an external pin is provided for the dual-switch flyback converter 200 to allow the user to modify the programmable delay.

[0174] At step 1010, in response to the passage of a fixed or programmable delay, the low side switch (Q 2 ) 204 is disabled. For subsequent cycles of the dual-switch flyback converter 200, steps 1004 to 1010 are repeated.

[0175] Fig.11 A schematic diagram of an embodiment DDS circuit 1100 that can be implemented in a dual-switch flyback converter 200 based on the method 900 is shown. The DDS circuit 1100 includes a first resistor (R 1 )1102, the second resistor (R 2 ) 1104, adder circuit 1106, comparator (COMP) 1108, AND gate 1110, inverter 1112 and flip-flop (FF) 1114, which may or may not be arranged as shown. DDS circuit 1100 may include additional components not shown, such as filter circuits. The input of DDS circuit 1100 is coupled to the floating ground (FGND) node of the dual-switch flyback converter 200.

[0176] The comparator (COMP) 1108 is configured to provide a voltage divider (i.e., a first resistor (R 1 )1102 and the second resistor (R 2 ) The voltage divider 1104 effectively divides the voltage at the floating ground (FGND) node (V FGND ) and the fourth threshold voltage (V TH4 ) is compared. As described in method 900, the fourth threshold voltage (V TH4 ) monitors the voltage (V FGND ), and in response to detecting the voltage (V FGND ) drops to the fourth threshold voltage (V TH4 ) below, after an internal delay from, for example, the delay introduced by comparator (COMP) 1108, the low side switch (Q 2 ) 204 is disabled. In an embodiment, the fourth threshold voltage (V TH4 ) is 1V.

[0177] The comparator (COMP) 1108 is configured with hysteresis provided from the output of the comparator (COMP) 1108. The comparator (COMP) 1108 has a voltage (V FGND The non-inverting input of comparator (COMP) 1108 is coupled to the output of adder circuit 1106.

[0178] The adder circuit 1106 has a circuit configured to receive a fourth threshold voltage (VTH4 ). A second input of adder circuit 1106 is configured to receive an output of comparator (COMP) 1108. Comparator (COMP) 1108 generates an output signal that is fed to a first input of AND gate 1110.

[0179] The inverter 1112 inverts the high-side signal (HVG) to generate an inverted high-side signal. 1 )202 is disabled, the inverted high-voltage side signal (HVG N ) is at a logic level high. The second input of AND gate 1110 is coupled to the inverted high-side signal (HVG N ).

[0180] Therefore, when (i) the high-side switch (Q 1 ) 202 is disabled and (ii) the voltage at the floating ground (FGND) node (V FGND ) drops to the fourth threshold voltage (V TH4 ), the output of AND gate 1110 is at a logic level high, which is provided to the reset (R) input of flip-flop (FF) 1114. Since the set (S) input of flip-flop (FF) 1114 is at a logic level low (i.e., the high-side signal (HVG) is at a logic level low), flip-flop (FF) 1114 is reset, and the output (Q) of flip-flop (FF) 1114 becomes low. The output (Q) of flip-flop (FF) 1114 is provided to the low-side switch (Q) as the low-side signal (LVG). 2 )204 control terminal.

[0181] Fig.12 FIG. 1 is a schematic diagram of another embodiment of a DDS circuit 1200 that can be implemented in a dual-switch flyback converter 200 based on the method 900. In the DDS circuit 1200, a voltage (V FGND )’s swing corresponds to the differential voltage.

[0182] The DDS circuit 1200 includes a capacitor (C) 1202, a first diode (D 1 )1204, the second diode (D 1 )1206, sensing resistor (R S) 1208, comparator (COMP) 1210, adder circuit 1212, monostable flip-flop (MF) 1214, inverter 1216, AND gate 1218, and flip-flop (FF) 1220, which may or may not be arranged as shown. DDS circuit 1200 may include additional components not shown, such as filter circuits. The input of DDS circuit 1200 is coupled to the floating ground (FGND) node of the dual-switch flyback converter 200.

[0183] The comparator (COMP) 1210 is configured to connect the capacitor (C) 1202, the first diode (D 1 )1204, the second diode (D 2 )1206, sensing resistor (R S ) 1208 effectively sets the voltage at the floating ground (FGND) node (V FGND ) and the fourth threshold voltage (V TH4 ) is compared. As described in method 900, the fourth threshold voltage (V TH4 ) monitors the voltage (V FGND ), and in response to detecting the voltage (V FGND ) drops to the fourth threshold voltage (V TH4 ) below, after an internal delay from, for example, the delay introduced by comparator (COMP) 1210, the low side switch (Q 2 )204 disabled.

[0184] The comparator (COMP) 1210 is configured with hysteresis provided from the output of the comparator (COMP) 1210. The comparator (COMP) 1210 has a voltage (V FGND The non-inverting input of comparator (COMP) 1210 is coupled to the output of adder circuit 1212.

[0185] The adder circuit 1212 has a circuit configured to receive a fourth threshold voltage (V TH4 ). A second input of adder circuit 1212 is configured to receive the output of comparator (COMP) 1210. Comparator (COMP) 1210 generates an output signal which is fed to monostable flip-flop (MF) 1214.

[0186] The monostable trigger (MF) 1214 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, the monostable trigger (MF) 1214 is arranged as a negative edge triggered monostable trigger.

[0187] In response to the voltage at the floating ground (FGND) node (V FGND ), the negative edge signal (a signal that changes from a logic level high to a logic level low) from the comparator (COMP) 1210 triggers the monostable trigger (MF) 1214, resulting in a change of its state and the generation of a logic level high signal at its output (Q) for a duration (Δt).

[0188] The inverter 1216 inverts the high-voltage side signal (HVG) to generate an inverted high-voltage side signal (HVG N ). Therefore, when the high-side switch (Q 1 )202 is disabled, the inverted high-voltage side signal (HVG N ) is at a logic level high. The second input of AND gate 1218 is coupled to the inverted high-side signal (HVG N ).

[0189] Therefore, when (i) the high-side switch (Q 1 ) 202 is disabled and (ii) the output (Q) of the monostable flip-flop (MF) 1214 is at a logic level high, the output of the AND gate 1218 is at a logic level high, which is provided to the reset (R) input of the flip-flop (FF) 1220. Since the set (S) input of the flip-flop (FF) 1220 is at a logic level low (i.e., the high-side signal (HVG) is at a logic level low), the flip-flop (FF) 1220 is reset, and the output (Q) of the flip-flop (FF) 1220 becomes low. The output (Q) of the flip-flop (FF) 1220 is provided as the low-side signal (LVG) to the low-side switch (Q 2 )204 control terminal.

[0190] Fig.13 FIG. 1 is a schematic diagram of an embodiment DDS circuit 1300 that can be implemented in a dual-switch flyback converter 200 based on the method 900. In the DDS circuit 1300, the voltage across the auxiliary winding is sensed to set the high-side switch (Q 1 )202 is turned off and the low-voltage side switch (Q 2 )204's shutdown delay.

[0191] The DDS circuit 1300 includes an auxiliary winding 1302, a first resistor (R 1 )1304, the second resistor (R 2) 1306, adder circuit 1308, comparator (COMP) 1310, AND gate 1312, inverter 1314 and flip-flop (FF) 1316, which may or may not be arranged as shown. DDS circuit 1300 may include additional components not shown, such as filter circuits.

[0192] Typically, the transformer 206 includes an auxiliary winding 1302 for powering the control loop and other components on the primary side of the transformer 206. The comparator (COMP) 1310 is configured to provide a voltage divider (ie, a first resistor (R 1 )1304 and the second resistor (R 2 ) 1306) senses the voltage across the auxiliary winding 1302. The comparator (COMP) 1310 is configured with hysteresis - the hysteresis is provided from the output of the comparator (COMP) 1310. The comparator (COMP) 1310 has an inverting input (-) configured to sense the voltage across the auxiliary winding 1302 through the voltage divider. The non-inverting input of the comparator (COMP) 1310 is coupled to the output of the adder circuit 1308.

[0193] The adder circuit 1308 has a first input coupled to a reference ground. A second input of the adder circuit 1308 is configured to receive the output of a comparator (COMP) 1310. The comparator (COMP) 1310 generates an output signal that is fed to a first input of an AND gate 1312.

[0194] The inverter 1314 inverts the high-voltage side signal (HVG) to generate an inverted high-voltage side signal (HVG N ). Therefore, when the high-side switch (Q 1 )202 is disabled, the inverted high-voltage side signal (HVG N ) is at a logic level high. The second input of AND gate 1312 is coupled to the inverted high-side signal (HVG N ).

[0195] Therefore, when (i) the high-side switch (Q 1 ) 202 is disabled and (ii) comparator (COMP) 1310 generates a logic level high signal, AND gate 1312 provides a logic level high signal to the reset (R) input of flip-flop (FF) 1316. Since the set (S) input of flip-flop (FF) 1316 is at a logic level low (i.e., the high-side signal (HVG) is at a logic level low), flip-flop (FF) 1316 is reset and the output (Q) of flip-flop (FF) 1316 becomes low. The output (Q) of flip-flop (FF) 1316 is provided to the low-side switch (Q) as the low-side signal (LVG). 2 )204 control terminal.

[0196] Fig.14 FIG. 1 is a schematic diagram of an embodiment of an open-loop regulation circuit 1400 that can be implemented in a dual-switch flyback converter 200 based on the method 1000. The open-loop regulation circuit 1400 is a circuit for regulating an output voltage (V OUT ) of the feedback loop control voltage (V C ) provides a timing circuit with a programmable delay as a function of the control voltage (V C ) has a maximum value (V CMAX ) and minimum value (V CMIN ).

[0197] Maximum delay value MAX ) corresponds to the control voltage (V C ) minimum value (V CMIN ), and the minimum delay value (Delay MIN ) corresponds to the control voltage (V C ) maximum value (V CMAX ). and minimum value (V CMIN ) and maximum value (V CMAX ) between the control voltage (V C ) corresponds to the maximum delay value (Delay MAX ) and the minimum delay value (Delay MIN ) can be determined using a linear function, a piecewise linear function, a lookup table, an analog timer using an incrementing counter, and a logic gate circuit that generates a blanking signal at the input of AND gate 1408, etc. In an embodiment, the maximum delay value (Delay MAX ) and the minimum delay value (Delay MIN ) can be programmed based on the application. In an embodiment, one or more parameters associated with the programmable delay are stored in a memory of the host device.

[0198] The open-loop regulation circuit 1400 includes a function circuit 1402, an inverter 1404, a reverse current timer circuit 1406, an AND gate 1408, and a flip-flop (FF) 1410, which may or may not be arranged as shown. The open-loop regulation circuit 1400 may include additional components not shown, such as a filter circuit.

[0199] Function circuit 1402 is a control voltage (V C ) minimum value (V CMIN ) and maximum value (V CMAX ) is a monotonically decreasing function in the interval between .

[0200] The reverse current timer circuit 1406 includes a fixed current generator 1412, a switch (SW) 1414, a capacitor (C) 1416, an XNOR gate 1418, and a comparator (COMP) 1420. Alternatively, in an embodiment, the reverse current timer circuit 1406 is digitally implemented as an up-counter. In an embodiment, the comparator (COMP) 1420 is implemented as a digital comparator.

[0201] The fixed current generator 1412 and the capacitor (C) 1416 provide a ramp voltage to the non-inverting input of the comparator (COMP) 1420. When the ramp voltage provided to the non-inverting input of the comparator (COMP) 1420 reaches the voltage level of X 1402, the first input of the AND gate 1408 is at a logic level high. In an embodiment, the relationship between the current (I) provided by the fixed current generator 1412 and the capacitor (C) 1416 can be expressed as: C / I=1μs / V.

[0202] The inverter 1404 inverts the high-voltage side signal (HVG) to generate an inverted high-voltage side signal (HVG N ). Therefore, when the high-side switch (Q 1 )202 is disabled, the inverted high-voltage side signal (HVG N ) is at a logic level high. The second input of AND gate 1408 is coupled to the inverted high-side signal (HVG N ).

[0203] Therefore, when (i) the high-side switch (Q 1 ) 202 is disabled and (ii) comparator (COMP) 1420 generates a logic level high signal corresponding to the output of function circuit 1402, AND gate 1408 provides a logic level high signal to the reset (R) input of flip-flop (FF) 1410. Since the set (S) input of flip-flop (FF) 1410 is at a logic level low (i.e., the high-side signal (HVG) is at a logic level low), flip-flop (FF) 1410 is reset and the output (Q) of flip-flop (FF) 1410 becomes low. The output (Q) of flip-flop (FF) 1410 is provided to the low-side switch (Q) as the low-side signal (LVG). 2 )204 control terminal.

[0204] Fig.15A block diagram of an embodiment system 1500 is illustrated. In an embodiment, the system 1500 includes a filter and rectifier circuit 1502, an optional power factor correction (PFC) stage circuit 1504, a dual-switch flyback converter 1506, and a USB PD control stage circuit 1508, which may or may not be arranged as shown. The system 1500 may include additional components not shown. In an embodiment, the system 1500 is a high-density USB-C charger for charging, for example, mobile devices.

[0205] The filter and rectifier circuit 1502 is configured to receive an alternating current (AC) input from a power source. The filter and rectifier circuit 1502 filters noise and unwanted frequencies from the AC input and converts it to direct current (DC).

[0206] The PFC stage 1504 ensures that the voltage and current waveforms are aligned to maximize power transfer efficiency. The PFC stage 1504 is typically required for input power levels greater than 75 Watts (W).

[0207] The two-switch flyback converter 1506 converts the DC output from the PFC stage circuit 1504 to another DC level suitable for the USB PD control stage circuit 1508. In an embodiment, the two-switch flyback converter 1506 is implemented as a two-switch flyback converter 200 with a closed-loop regulation circuit 600, 700, 800, and operates using the method 500. In an embodiment, the two-switch flyback converter 1506 is implemented as a two-switch flyback converter 200 with a DDS circuit 1100, 1200, 1300, and operates using the method 900. In an embodiment, the two-switch flyback converter 1506 is implemented as a two-switch flyback converter 200 with an open-loop regulation circuit 1400, and operates using the method 1000.

[0208] The USB PD control stage circuit 1508 transmits the output voltage (V OUT ) to regulate and control the power supply.

[0209] A first aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal to turn off the low-side switch is delayed after a duration from a transition of the first control signal to turn off the high-side switch, wherein the delay is automatically adjusted by detecting a condition associated with the converter, wherein the delay begins in response to a voltage at the floating ground node being less than zero.

[0210] In a first implementation form of the converter according to the first aspect, the converter further comprises a closed-loop regulation circuit configured to monitor the voltage across the bootstrap capacitor.

[0211] In a second implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the delay is reduced in response to detecting that the voltage across the bootstrap capacitor is greater than a threshold voltage using the closed-loop regulation circuit, and wherein the delay is increased in response to detecting that the voltage across the bootstrap capacitor is less than the threshold voltage using the closed-loop regulation circuit.

[0212] In a third implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the converter also includes a diode having a cathode terminal coupled to the bootstrap capacitor; and a closed-loop regulation circuit configured to monitor the difference between the regulated voltage at the anode terminal of the diode and the voltage across the bootstrap capacitor.

[0213] In a fourth implementation of the converter according to the first aspect or any previous implementation of the first aspect, in response to detecting, using the closed-loop regulation circuit, that the difference between the regulated voltage and the voltage across the bootstrap capacitor is less than a threshold voltage, the delay is reduced. In response to detecting, using the closed-loop regulation circuit, that the difference between the regulated voltage and the voltage across the bootstrap capacitor is greater than the threshold voltage, the delay is increased.

[0214] In a fifth implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the converter further comprises a closed-loop regulation circuit configured to regulate the current at the next τ after the high-side switch is turned off. 2 τ in seconds 1 The voltage at the floating ground node is monitored within seconds.

[0215] In a sixth implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, in response to detecting by the closed-loop regulation circuit that the high-side switch is turned off immediately after τ 2 τ in seconds1 The voltage at the floating ground node is less than the threshold within seconds, the delay is reduced, and in response to detecting by the closed-loop regulation circuit that the high-side switch is turned off immediately after τ 2 τ in seconds 1 The voltage at the floating ground node is greater than the threshold within seconds, increasing the delay.

[0216] A second aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal to turn off the low-side switch is based on detecting a condition related to the converter after a transition of the first control signal to turn off the high-side switch.

[0217] In a first implementation form of the converter according to the second aspect, the converter further comprises a circuit configured to monitor the voltage at the floating ground node.

[0218] In a second implementation of the converter according to the second aspect or any previous implementation of the second aspect, the controller is configured to set the second control signal to turn off the low side switch in response to detecting through the circuit that the voltage at the floating ground node is less than a threshold.

[0219] In a third implementation of the converter according to the second aspect or any previous implementation of the second aspect, the converter also includes a diode having a cathode terminal coupled to the bootstrap capacitor; and a circuit configured to monitor the voltage across the bootstrap capacitor and the regulated voltage at the anode terminal of the diode.

[0220] In a fourth implementation of the converter according to the second aspect or any previous implementation of the second aspect, the controller is configured to set the second control signal to turn off the low side switch in response to detecting through the circuit that the voltage across the bootstrap capacitor is less than the regulation voltage.

[0221] In a fifth implementation form of the converter according to the second aspect or any previous implementation form of the second aspect, the controller is configured to set the first control signal and the second control signal to turn on the high side switch and the low side switch simultaneously.

[0222] In a sixth implementation form of the converter according to the second aspect or any previous implementation form of the second aspect, the converter also includes an auxiliary winding for controlling a feedback loop of the converter based on the output voltage of the converter; and a circuit configured to sense the voltage of the auxiliary winding, wherein the controller is configured to set a second control signal to turn off the low-voltage side switch in response to detecting through the circuit that the voltage at the auxiliary winding is less than a threshold.

[0223] A third aspect relates to a converter. The converter includes a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch, a source terminal of the high-side switch coupled to the bootstrap capacitor through the floating ground node; a low-side switch; and a controller. The controller is configured to provide a first control signal to a control terminal of the high-side switch and a second control signal to a control terminal of the low-side switch, wherein a transition of the second control signal for turning off the low-side switch is based on a programmable delay after a transition of the first control signal for turning off the high-side switch, the programmable delay being a function of a maximum current flowing through a transformer of the converter.

[0224] In a first implementation form of the converter according to the third aspect, the maximum current flowing through the transformer is related to the load at the output of the converter.

[0225] In a second implementation of the converter according to the third aspect or any previous implementation of the third aspect, a first duration of the programmable delay responsive to a first load is greater than a second duration of the programmable delay responsive to a second load greater than the first load.

[0226] In a third implementation form of the converter according to the third aspect or any previous implementation form of the third aspect, the converter further comprises an open-loop regulation circuit configured to set a programmable delay as a function of a control voltage in a feedback loop mechanism for controlling operation of the converter based on a lookup table.

[0227] In a fourth implementation form of the converter according to the third aspect or any previous implementation form of the third aspect, a maximum value of the programmable delay corresponds to a minimum value of the control voltage, and wherein the minimum value of the programmable delay corresponds to a maximum value of the control voltage.

[0228] In a fifth implementation of the converter according to the third aspect or any previous implementation of the third aspect, the value of the programmable delay is based on a value of the control voltage between a minimum value of the control voltage and a maximum value of the control voltage using a lookup table, a linear relationship or a piecewise linear relationship.

[0229] Although the description has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In each figure, the same elements are represented by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because those of ordinary skill in the art will easily understand from the present disclosure that the processes, machines, manufactures, material components, means, methods or steps currently existing or developed later can perform functions substantially the same as the corresponding embodiments described herein or achieve substantially the same results. Therefore, the appended claims are intended to include these processes, machines, manufactures, material components, means, methods or steps within their scope.

[0230] Accordingly, the specification and drawings should be regarded as a brief description of the disclosure as defined by the appended claims, and any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure should be covered.

Claims

1. A converter, comprising: a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch having a source terminal coupled to the bootstrap capacitor through the floating ground node; Low voltage side switch; as well as The controller is configured as: providing a first control signal to a control terminal of the high-voltage side switch, and A second control signal is provided to a control terminal of the low side switch, wherein a transition of the second control signal to turn off the low side switch is delayed after a duration from a transition of the first control signal to turn off the high side switch, wherein the delay is automatically adjusted by detecting a condition associated with the converter, wherein the delay begins in response to a voltage at the floating ground node being less than zero. 2 . The converter of claim 1 , further comprising a closed-loop regulation circuit configured to monitor a voltage across the bootstrap capacitor.

3. The converter of claim 2 , wherein the delay is reduced in response to detecting, using the closed-loop regulation circuit, that the voltage across the bootstrap capacitor is greater than a threshold voltage, and wherein the delay is increased in response to detecting, using the closed-loop regulation circuit, that the voltage across the bootstrap capacitor is less than the threshold voltage.

4. The converter according to claim 1, wherein the converter further comprises: a diode having a cathode terminal coupled to the bootstrap capacitor; as well as A closed-loop regulation circuit is configured to monitor a difference between a regulated voltage at an anode terminal of the diode and a voltage across the bootstrap capacitor.

5. The converter of claim 4 , wherein the delay is reduced in response to detecting, using the closed-loop regulation circuit, that the difference between the regulated voltage and the voltage across the bootstrap capacitor is less than a threshold voltage, and wherein the delay is increased in response to detecting, using the closed-loop regulation circuit, that the difference between the regulated voltage and the voltage across the bootstrap capacitor is greater than the threshold voltage.

6. The converter of claim 1 , further comprising a closed-loop regulation circuit configured to monitor the voltage at the floating ground node within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

7. The converter of claim 6 , wherein the delay is reduced in response to detecting by the closed-loop regulation circuit that the voltage at the floating ground node is less than a threshold value within τ1 second within the τ2 second period immediately after the high-side switch is turned off, and wherein the delay is increased in response to detecting by the closed-loop regulation circuit that the voltage at the floating ground node is greater than a threshold value within τ1 second within the τ2 second period immediately after the high-side switch is turned off.

8. A converter comprising: a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch having a source terminal coupled to the bootstrap capacitor through the floating ground node; Low voltage side switch; as well as The controller is configured as: providing a first control signal to a control terminal of the high-voltage side switch, and A second control signal is provided to a control terminal of the low side switch, wherein a transition of the second control signal to turn off the low side switch is based on detecting a condition associated with the converter after a transition of the first control signal to turn off the high side switch.

9. The converter of claim 8, further comprising circuitry configured to monitor a voltage at the floating ground node. 10 . The converter of claim 9 , wherein the controller is configured to set the second control signal to turn off the low-side switch in response to detecting, by the circuit, that the voltage at the floating ground node is less than a threshold.

11. The converter according to claim 10, further comprising: a diode having a cathode terminal coupled to the bootstrap capacitor; as well as A circuit is configured to monitor a voltage across the bootstrap capacitor and a regulated voltage at an anode terminal of the diode. 12 . The converter of claim 11 , wherein the controller is configured to set the second control signal to turn off the low side switch in response to detecting by the circuit that the voltage across the bootstrap capacitor is less than the regulation voltage. 13 . The converter of claim 8 , wherein the controller is configured to set the first control signal and the second control signal to turn on the high-side switch and the low-side switch simultaneously.

14. The converter according to claim 8, further comprising: an auxiliary winding for controlling a feedback loop of the converter based on an output voltage of the converter; as well as The circuit is configured to sense the voltage of the auxiliary winding, wherein the controller is configured to: in response to detecting through the circuit that the voltage at the auxiliary winding is less than a threshold, set the second control signal to turn off the low-side switch.

15. A converter comprising: a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch having a source terminal coupled to the bootstrap capacitor through the floating ground node; Low voltage side switch; as well as The controller is configured as: providing a first control signal to a control terminal of the high-voltage side switch, and A second control signal is provided to a control terminal of the low side switch, wherein a transition of the second control signal for turning off the low side switch is based on a programmable delay after a transition of the first control signal for turning off the high side switch, the programmable delay being a function of a maximum current flowing through a transformer of the converter.

16. The converter of claim 15, wherein the maximum current flowing through the transformer is related to the load at the output of the converter. 17 . The converter of claim 15 , wherein a first duration of the programmable delay in response to a first load is greater than a second duration of the programmable delay in response to a second load, the second load being greater than the first load.

18. The converter of claim 15, further comprising an open loop regulation circuit configured to set the programmable delay as a function of a control voltage in a feedback loop mechanism for controlling operation of the converter based on a lookup table.

19. The converter of claim 18, wherein a maximum value of the programmable delay corresponds to a minimum value of the control voltage, and wherein a minimum value of the programmable delay corresponds to a maximum value of the control voltage.

20. The converter of claim 19, wherein the value of the programmable delay is based on a value of the control voltage between a minimum value of the control voltage and a maximum value of the control voltage using a lookup table, a linear relationship, or a piecewise linear relationship.

Images