Half-bridge driver circuit, related integrated circuit, half-bridge circuit and method

Abstract

The invention relates to a half-bridge driver circuit, a related integrated circuit, a half-bridge circuit and a method. A half-bridge driver circuit periodically repeats a switching cycle by closing a first FET via a first drive signal, detecting a moment at which a current flowing through the first FET reaches a threshold, and then opening the first FET and closing a second FET via a second drive signal. The error amplifier generates a control voltage by comparing a feedback signal with a reference signal, and the variable current generator generates a first current according to the control voltage. The error amplifier includes a proportional-integral controller and a slope compensation circuit that generates a second current as a ramp signal. The threshold value is generated by subtracting the second current from the first current. In response to detecting the instant, a second current is sampled and a signal indicative of a threshold is generated by subtracting the sampled second current from the first current.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000023145 filed on November 3, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments of the present disclosure relate to solutions for driving, for example, a half-bridge of an electronic converter such as a buck converter. Background Art

[0004] Power supply circuits, such as AC / DC or DC / DC switched mode power supplies, are well known in the art. There are many types of electronic converters, mainly divided into isolated and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. Alternatively, isolated converters are, for example, "flyback", "forward", "half-bridge" and "full-bridge" type converters. These types of converters are well known to those skilled in the art, as evidenced, for example, by the application note AN513 / 0393 "Topologies for switched-mode power supplies", L. Wuidart, 1999, STMicroelectronics (incorporated herein by reference).

[0005] Figure 1 2 is a schematic diagram of a DC / DC electronic converter 20. In particular, the universal electronic converter 20 includes a circuit for receiving a DC voltage V in The two input terminals 200a and 200b, and the DC voltage V out For example, the input voltage V in It may be supplied by a DC voltage source 10 such as a battery, or may be obtained from an AC voltage with the aid of a rectifier circuit such as a bridge rectifier and possibly a filtering circuit. Alternatively, the output voltage V out Can be used to power the load 30 .

[0006] For example, Figure 2 FIG. 2 shows a circuit diagram of a buck converter 20. In particular, the buck converter 20 includes a circuit for receiving a DC input voltage V in The two input terminals 200a and 200b, and the regulated voltage V out The two output terminals 202a and 202b, where the output voltage is equal to or lower than the input voltage V in .

[0007] In the example considered, the buck converter 20 includes two electronic switches Q1 and Q2 (and their current paths) connected in series (e.g., directly connected) between input terminals 200a and 200b, wherein the intermediate node between the electronic switches Q1 and Q2 represents the switching node Lx. Specifically, the electronic switch Q1 is a high-side switch connected (e.g., directly connected) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch connected (e.g., directly connected) between the switching node Lx and the (negative) terminal 200b, which often represents the ground GND. Therefore, the (high-side) switch Q1 and the (low-side) switch Q2 represent a half-bridge, which is configured to connect the switching node Lx to the terminal 200a (voltage V in ) or terminal 200b (ground GND).

[0008] Switches Q1 and / or Q2 are often transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs), for example, n-channel FETs, such as NMOS. The second electronic switch Q2 is also often implemented with just a diode, with the anode connected to terminal 200b and the cathode connected to the switch node Lx.

[0009] In the example considered, an inductor L, such as an inductor, is connected (e.g., directly connected) between the switching node Lx and the (positive) output terminal 202a. Alternatively, the (negative) output terminal 202b is connected (e.g., directly connected) to the (negative) input terminal 200b. The converter 20 often includes a capacitor C connected (e.g., directly connected) between the output terminals 202a and 202b. out To stabilize the output voltage V out .

[0010] In this context, Figures 3A-3E Exemplary waveforms of signals of such an electronic converter are shown, where: Figure 3A A signal DRV1 for switching the electronic switch Q1 is shown; Figure 3B shows a signal DRV2 for switching the second electronic switch Q2; Figure 3C shows the current I through the electronic switch Q1 Q1 ; Figure 3D shows the voltage V at the switch node Lx Lx (ie, the voltage at the second switch Q2); and Figure 3E The current I through the inductor L is shown L .

[0011] Specifically, when the electronic switch Q1 is closed (ON state) at time t1, the current I in the inductor L L(Substantially) linear increase. At the same time, the electronic switch Q2 is turned off. Instead, when the electronic switch Q1 is in the interval T ON1 After that, at time t2, when it is disconnected (OFF state), the electronic switch Q2 is closed, and the current I L Finally, the switch Q1 is in the interval T OFF1 and then closes again. In the example considered, therefore, when switch Q1 is open, switch Q2 is closed, and vice versa. Therefore, the current I L can be used to charge capacitor C, which supplies a voltage V at terminals 202a and 202b. out .

[0012] In the embodiment considered, the electronic converter 20 therefore comprises a control circuit 22 configured to drive the switching of the switches Q1 and Q2 for periodically repeating the interval T ON1 and T OFF1 For example, the buck converter 20 also typically includes a feedback circuit (FBC) 24, such as a voltage divider, which is configured to generate a signal indicating the output voltage V out The control circuit 22 is configured to generate a feedback signal FB (and preferably proportional thereto) by comparing the feedback signal FB with a reference signal (such as a reference voltage V ref ) are compared to generate driving signals DRV1 and DRV2.

[0013] Generally speaking, a buck converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM).

[0014] For example, Figure 4 As shown in FIG. 1 , when the control circuit 22 operates the converter in CCM, when the switching cycle T SW At the end, the current I flowing through the inductor L L has a value different from zero. In this case, the control circuit 22 uses two switching phases T1 and T2, where T SW =T1+T2, where: In stage T1 (T1=T ON1 =T OFF2 ), the switch Q1 is closed and the switch / diode Q2 is open; and in phase T2 (T2 = T OFF1 =T ON2 ), switch Q1 is open and switch / diode Q2 is closed.

[0015] On the contrary, Figure 5 As shown in FIG. 1 , when the control circuit 22 operates the converter in DCM, when the current I flowing through the inductor L LWhen the electronic switch Q2 is turned off, the control circuit 22 actually uses three switching phases T1, T2 and T3 in this case. SW =T1+T2+T3, where: In stage T1 (T1=T ON1 ), the switch Q1 is closed and the switch / diode Q2 is open; in phase T2 (T2 = T ON2 ), switch Q1 is open and switch / diode Q2 is closed; and in phase T3 (T OFF1 =T2+T3 and T OFF2 =T3+T1), the switch Q1 is turned off and the switch / diode Q2 is turned off.

[0016] A large number of driving schemes are known for generating the driving signals DRV1 and DRV2. These solutions have in common that the interval T ON1 and / or interval T OFF1 The duration of the regulation of the output voltage V out For example, the control circuit 22 often generates a pulse width modulation (PWM) signal DRV1, where the duty cycle D=T ON1 / (T ON1 +T OFF1 ) is variable. For example, the control circuit 22 often uses constant frequency PWM modulation. For example, in this case, the time t1 can be at a constant time T SW On the contrary, time t2 can be based on the feedback signal FB and the reference signal V ref For example, in this regard, a well-known control method is the peak current mode (PCM), in which the control circuit 22 is configured to control the current I flowing through the inductor L when the current I L (or indicates the value of this current) reaches the threshold I LPK The on-time interval T ends ON1 (Time t2), that is, the current I L The maximum value of I max With threshold I LPK Corresponding, that is, I max =I LPK , wherein the control circuit 22 includes a proportional-integral (PI) or proportional-integral-derivative (PID) regulator configured to change the threshold value I LPK In order to adjust the feedback signal FB to the reference signal V ref .

[0017] This peak current mode is also often used in other half-bridge circuits. For example, Figure 6 and Figure 7 An example of a half-bridge circuit 20 is shown.

[0018] Specifically, the half-bridge circuit 20 includes a half-bridge including two electronic switches Q1 and Q2 connected in series between input terminals 200a and 200b. Moreover, the half-bridge circuit 20 includes an inductor 28 connected to an intermediate node between the electronic switches Q1 and Q2, i.e., a switch node Lx, wherein the half-bridge is configured to selectively connect the input voltage V in The energy is transferred to the inductor 28. Specifically, the inductor 28 is Figure 6 The inductor L and Figure 7 Generally speaking, the inductor 28 is connected between the switch node Lx and the ground 200b, or between the inductor 28 and the capacitor C out is connected in series between the switch node Lx and the ground 200b. Thus, due to the inductive load, when the electronic switch Q1 is closed (and the electronic switch Q2 is open), the current supplied to the inductive load 28 increases (substantially) linearly, and when the electronic switch Q2 is closed (and the electronic switch Q1 is open), the current supplied to the inductive load 28 decreases (substantially) linearly. In this regard, when the capacitor C is used out When compared with the switching frequency of the electronic switches Q1 and Q2, the inductor 28 and the capacitor C out The resonant frequency of a resonant tank is usually large.

[0019] For example, about Figure 6 , the inductor L can be directly the load, such as a motor winding. In contrast, in the case of a buck converter, the capacitor C out The voltage at is connected to the output terminals 202a and 202b of the buck converter.

[0020] On the contrary, Figure 7 As shown in , in a typical half-bridge electronic converter, the inductor 28 comprises a transformer, wherein the primary winding T1 is connected to the switching node Lx (i.e., the primary winding T1 is connected between the switching node Lx and the ground 200b, or the primary winding T1 and the capacitor C are connected in series between the switching node Lx and the ground 200b), and the secondary winding T2 is usually connected to the output terminals 202a and 202b of the electronic converter via the rectifier circuit 27. For example, U.S. Patent No. 10,770,980 discloses various types of half-bridge converters and corresponding rectifier circuits, the contents of which are incorporated herein by reference. In a typical half-bridge converter, the resonant frequency of the resonant tank (including the transformer 28 and possible other reactive components, such as the capacitor C) is usually large compared to the switching frequency of the electronic switches Q1 and Q2.

[0021] Also in this case, the half bridge 20 comprises a control circuit 22 configured to generate drive signals DRV1 and DRV2 for the electronic switches Q1 and Q2 so as to control the switching of the half bridge 20 from the input voltage V in Specifically, when using the peak current mode, the control circuit 22 receives a signal indicating the current provided to the inductive load 28 during the on-period T1 of the electronic switch Q1, such as a signal CS1 provided by the current sensor 26a, which is configured to directly monitor the current I provided to the inductive load 28. L The current sensor 26a may also be replaced by a current sensor 26b, which is configured to provide an indication of the current I flowing through the switch Q1. Q1 (and preferably proportional to) the signal CS2, the current I Q1 The period T1 corresponds to the current supplied to the inductive load 28 .

[0022] Moreover, as mentioned above, the control circuit 22 includes a PI or PID regulator, which is configured to convert the feedback signal FB into a reference voltage V ref The comparison is made to generate a threshold value for signal CS1 or CS2. Generally speaking, the feedback signal FB indicates the output amount to be regulated (and is preferably proportional to it). For example, in an electronic converter configured as a voltage source, the feedback signal FB indicates the output voltage V at terminals 202a and 202b. out In contrast, in the case of a current source, the feedback signal FB indicates the output current i provided via terminals 202a and 202b. out Conversely, in the case of a motor, the feedback signal FB may be indicative of the rotational speed of the motor.

[0023] As mentioned above, the control circuit can drive the electronic switches Q1 and Q2 in CCM or DCM. Therefore, the control circuit 22 can be configured to: SW A new switching cycle is then periodically started, for example, by closing the switch Q1 and opening the switch Q2 (time t1) in response to the clock signal; in response to determining the current I flowing through the inductor 28 L (or a value indicating this current, such as signal C2) reaches the threshold I LPK , opening switch Q1 and closing switch Q2 (time t2); and optionally (ie, when DCM is used), in response to determining current I L reaches zero, the switch Q1 remains turned off and the switch Q2 is turned off (time t3).

[0024] Thus, when using DCM, the control circuit 22 may further include or be connected to a zero current detection circuit (ZCDC) 26, which is configured to generate a zero current signal ZC indicating (at least) the time t3 when the current supplied to the inductor 28 reaches zero, in particular at least during the interval T2. For example, such a zero current detection circuit 26 may receive a signal CS1 provided by a current sensor 26a. Alternatively, the current sensor 26a may be replaced by a current sensor 26c, which is configured to provide a signal indicating the current I flowing through the switch Q2. Q2 (and preferably proportional to) the signal CS3, the current I Q2 Corresponds to the current supplied to the inductor 28 during the interval T2. For example, the zero current signal ZC can be determined via a comparator 26 (a so-called zero current comparator), for example, which is configured to determine whether the monitored signal CS1 or CS3 falls below a given threshold value (which is usually close to zero). For example, at Figure 5 An example of a zero current signal ZC is shown in FIG. 8 , which is set high when the measured current is less than a threshold value (close to zero).

[0025] Often a (usually fixed) dead time may also be introduced between the switching of the drive signals, for example between the falling edge of signal DRV1 and the rising edge of signal DRV2, and similarly (in CCM mode) between the falling edge of signal DRV2 and the rising edge of signal DRV1. ON1 and T OFF1 These intervals are usually shorter than these and will therefore not be considered in detail in the following.

[0026] The peak value of the current flowing through the (high-side) electronic switch Q1 (which in turn indicates the peak value of the current flowing through the inductor 28) may also be useful for other purposes. For example, this value may be useful for determining the operating state of the electronic converter 20, for example, together with other parameters such as the duty cycle D. For example, based on these values, the control circuit 22 may decide whether to operate the electronic converter in a high power mode (e.g., using CCM) or a low power mode (e.g., using DCM or burst mode with PCM).

[0027] Moreover, as described, for example, in U.S. patent application No. 18 / 767,557 (corresponding to Italian patent application No. 102023000014532), the contents of which are incorporated herein by reference, the peak value of the current flowing through the electronic switch can also be used for so-called power stage partitioning or segmenting, in which the electronic switch is replaced by a power stage comprising: a plurality of electronic switches (such as FETs) connected in parallel, and / or FETs in which the width of the active channel can be selectively controlled, thereby actually achieving a plurality of electronic switches connected in parallel.

[0028] For example, Figure 8 An example is shown in which the power stage Q is implemented with a plurality of field effect transistors (FETs) connected in parallel, such as four FETs S1, S2, S3, and S4. In this case, the drain terminals of the plurality of FETs S1-S4 are connected to a first node / terminal N1, and the source terminals of the plurality of FETs S1-S4 are connected to a second node / terminal N2. In contrast, each of the gate terminals of the plurality of FETs S1-S4 is connected to a corresponding terminal to receive a corresponding drive signal, for example, drive signals D1, D2, D3, and D4. In general, any other number of electronic switches connected in parallel with corresponding drive signals, such as 2, 3, 5, 6, 7, 8, or more electronic switches, may also be used.

[0029] Thus, in this case, the control circuit 22 of the half-bridge circuit can be configured to generate drive signals D1-D4 for the electronic switches S1-S4 so as to select the number of electronic switches that should be closed simultaneously. In fact, the main loss sources of the FETs typically vary with different load currents. For example, at high currents, the dominant loss source is the power converted into heat across the resistance of the FET, i.e., ohmic losses. At low currents, the dominant source comes from the switching on and off of the FETs, i.e., dynamic losses such as switching and driving. For example, at any load, the power required to switch the gate of the FET on and off is typically fairly constant, but as the load draws more current, the power used to switch the gate becomes a less significant part of the total power converted. Therefore, when the power stage Q is split into multiple (physical and / or virtual) parallel FETs, the effective size of the power switch can be controlled, and the control circuit of the electronic converter can balance: the total on-resistance R ds,ON , which decreases when increasing the number of closed electronic switches; and switching losses, which decreases when decreasing the number of closed electronic switches.

[0030] For example, the control circuit 22 may be configured to close more electronic switches S1 - S4 when a high current flows, thereby reducing the on-resistance R ds,ONThe power loss in the circuit is reduced, and when low current flows, fewer electronic switches S1-S4 are closed, thereby reducing the switching loss required to close the electronic switches S1-S4.

[0031] For example, in order to decide the number of electronic switches S1-S4 (i.e., partitions or segments of the power stage Q) that should be closed, the control circuit may determine a value indicative of (and preferably proportional to) the peak value of the current flowing through the power stage Q, i.e., the total current flowing through the electronic switches S1-S4. For example, in known solutions, the control circuit is configured to monitor the peak current flowing through the power stage Q and set the number of active FETs using a given current threshold, which may be static or determined according to operating conditions.

[0032] In view of the above, there is a need in the art to provide a solution for obtaining the peak value of the current. Summary of the invention

[0033] One or more embodiments include a half-bridge driver circuit.

[0034] Furthermore, embodiments relate to related integrated circuits, half-bridge circuits, and methods.

[0035] Various embodiments of the present disclosure relate to a half-bridge driver circuit for a half-bridge configured to supply power to an inductive load. For example, the half-bridge circuit may include a first FET and a second FET connected in series between two input terminals configured to receive an input voltage, wherein an intermediate node between the first FET and the second FET represents a switch node configured to supply power to the inductive load.

[0036] Specifically, in various embodiments, a half-bridge driver circuit (e.g., implemented in an integrated circuit) includes a first terminal configured to provide a first drive signal to a gate terminal of a first FET representing a high-side electronic switch of the half-bridge, and a second terminal configured to provide a second drive signal to a gate terminal of a second FET representing a low-side electronic switch of the half-bridge. Moreover, the half-bridge driver circuit includes a feedback terminal configured to receive a feedback signal indicating an amount to be adjusted. For example, when the half-bridge circuit is an electronic converter (such as a buck converter), the feedback signal can indicate an output voltage or an output current generated by the electronic converter.

[0037] In various embodiments, the half-bridge driver circuit is configured to periodically repeat a switching cycle by closing the first FET via a first drive signal at the beginning of each switching cycle, detecting a time when the current flowing through the first FET reaches a threshold, and disconnecting the first FET via the first drive signal and closing the second FET via a second drive signal in response to detecting the time. Moreover, when operating in CCM, the half-bridge driver circuit disconnects the second FET via the second drive signal at the beginning of each switching cycle. Conversely, when operating in DCM, the half-bridge driver circuit detects another time when the current flowing through the second FET reaches zero, and disconnects the second FET via the second drive signal in response to detecting the other time.

[0038] In various embodiments, the half-bridge driver circuit includes a variable current generator configured to generate a first current according to a control voltage, and an error amplifier configured to generate the control voltage by comparing a feedback signal with a reference signal, wherein the error amplifier includes a regulator having a proportional and an integral component. In various embodiments, the half-bridge driver circuit also includes a slope compensation circuit configured to generate a second current, wherein the second current is a ramp signal that is reset at the beginning of each switching cycle, and wherein the threshold is generated by subtracting the second current from the first current. Thus, in various embodiments, the half-bridge driver circuit uses a peak current mode.

[0039] For example, in order to detect the moment when the current flowing through the first FET reaches a threshold, the half-bridge driver circuit may include a reference FET configured to be passed through by a third current corresponding to the difference between the first current and the second current, and a comparator configured to generate a signal indicating the moment by comparing the voltage drop at the reference FET with the voltage drop at the first FET.

[0040] In various embodiments, the half-bridge driver circuit is configured to, in response to detecting a time when the current flowing through the first FET reaches a threshold, sample the second current at that time, and generate a signal indicating the threshold by subtracting the sampled second current from the first current. Thus, instead of directly monitoring the peak value of the current flowing through the first FET, various embodiments of the present disclosure generate a signal indicating the peak value of the current flowing through the first FET by sampling the current provided by the slope compensation circuit and subtracting the sampled current from the current generated via the variable current generator by the error amplifier.

[0041] For example, in various embodiments, the half-bridge driver circuit samples the second current by obtaining a voltage indicating the second current at the moment, and storing the obtained voltage in the capacitor in response to detecting the moment. Thus, the half-bridge driver circuit can generate a fourth current according to the voltage at the capacitor. For example, in various embodiments, the slope compensation circuit includes a current source configured to generate a ramp signal, and the half-bridge driver circuit includes a FET configured to be passed through by the ramp signal, wherein the gate terminal of the FET is connected to the drain terminal of the FET. Thus, in this case, the voltage indicating the second current can correspond to the voltage at the gate terminal of the FET. Thus, the half-bridge driver circuit can include another FET configured to provide a fourth current, wherein the gate terminal of the other FET is driven via the voltage at the capacitor.

[0042] In various embodiments, the variable current generator includes a current source configured to generate a fifth current proportional to the control voltage, and a current mirror configured to generate the first current by mirroring the fifth current. In this case, the current mirror can also generate a sixth current corresponding to the first current, and the half-bridge driver circuit can generate a signal indicating the threshold by subtracting the fourth current (i.e., the sampled current) from the sixth current.

[0043] Additionally or alternatively, the half-bridge driver circuit may include an operational amplifier, wherein an inverting input of the operational amplifier is connected to the fourth current, a non-inverting input of the operational amplifier is connected to the control voltage, and an output terminal of the operational amplifier is connected to the inverting input of the operational amplifier via a resistor, wherein a voltage at the output terminal of the operational amplifier corresponds to a signal indicating a threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting examples only and in which:

[0045] Figure 1 An example of an electronic converter is shown;

[0046] Figure 2 An embodiment of a buck converter is shown;

[0047] Figures 3A-3E Shows Figure 2 Exemplary waveforms of operation of an electronic converter;

[0048] Figure 4 shows exemplary waveforms when the electronic converter is operated in CCM;

[0049] Figure 5 shows exemplary waveforms when the electronic converter is operated in DCM;

[0050] Figure 6 An example of a half-bridge circuit including an inductor is shown;

[0051] Figure 7 An embodiment of a half-bridge circuit including a transformer is shown;

[0052] Figure 8 An example of an implementation of a power stage with multiple parallel FETs is shown;

[0053] Fig. 9 An embodiment of a half-bridge circuit is shown;

[0054] Fig.10 An embodiment of a half-bridge circuit including a slope compensation circuit is shown;

[0055] Fig.11 Shows Fig.10 Exemplary waveforms of the operation of a half-bridge circuit;

[0056] Fig.12 An embodiment of a measurement circuit is shown;

[0057] Fig.13 Shows Fig.12 A first embodiment of a sample-and-hold circuit of a measurement circuit;

[0058] Fig.14 Shows Fig.12 A second embodiment of the sample-and-hold circuit of the measurement circuit;

[0059] Fig.15 Shows Fig.12 , Fig.13 and Fig.14 Exemplary waveforms of the operation of a sample and hold circuit;

[0060] Fig.16 Shows Fig.12 An embodiment of a measurement circuit of; and

[0061] Fig.17 Further embodiments of measurement circuits are shown. DETAILED DESCRIPTION

[0062] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or several of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0063] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0065] In the following Figures 9 to 17 In, reference has been made Figures 1 to 8 Described parts, elements or components are indicated with the same reference numerals used previously in these figures; in order not to unduly burden this detailed description, the description of these previously described elements will not be repeated below.

[0066] As mentioned previously, various embodiments of the present disclosure relate to solutions for obtaining a peak value of a current flowing through a high-side electronic switch of a half-bridge circuit operating in PCM.

[0067] Fig. 9 An embodiment of a half-bridge circuit 20a is shown.

[0068] Specifically, consistent with the above description, the half-bridge circuit 20a includes a circuit for receiving a DC input voltage V in A positive input terminal 200a and a negative input terminal 200b (e.g., representing ground) of the embodiment of the present invention, and two electronic switches Q1 and Q2 connected in series between the positive input terminal 200a and the negative input terminal / ground 200b. For example, in various embodiments, the electronic switches Q1 and Q2 are n-channel FETs, such as NMOS, wherein the drain terminal of FET Q1 is connected (e.g., directly connected) to the positive input terminal 200a, the source terminal of FET Q1 is connected (e.g., directly connected) to the switching node Lx, and the gate terminal of FET Q1 receives the drive signal DRV1, and wherein the drain terminal of FET Q2 is connected (e.g., directly connected) to the switching node Lx, the source terminal of FET Q2 is connected (e.g., directly connected) to the negative input terminal / ground 200b, and the gate terminal of FET Q2 receives the drive signal DRV2. As described with respect to Figure 8 As described, each of the n-channel FETs Q1 and Q2 may actually be implemented with a corresponding power stage Q comprising a plurality of (physical and / or virtual) parallel-connected n-channel FETs.

[0069] In the embodiment considered, the half-bridge circuit is configured to power an inductor 28 (such as an inductor L or a transformer T) via a switching node Lx. For example, the inductor 28 can be connected between the switching node Lx and the negative input terminal / ground 200b, or between the inductor 28 and an optional capacitor C out It can be connected in series between the switch node Lx and the negative input terminal / ground 200b. For possible embodiments of the inductor 28, reference can be made to the above description, especially with regard to Figure 6 and Figure 7 For example, in the embodiment considered, the half-bridge circuit is a buck converter, in which the inductor L is connected between the switching node Lx and the positive output terminal 202a, and the capacitor C out is connected between the positive output terminal 202a and the negative output terminal 202b, and the negative output terminal 202b can be connected to the negative input terminal 200b. Therefore, a general description of such a half-bridge circuit can refer to Figures 1 to 8 , all of which apply to the half-bridge circuit 20a.

[0070] Moreover, the half-bridge circuit 20a includes a half-bridge driver circuit. Specifically, the half-bridge driver circuit includes a high-side driver (HSD) 226 configured to generate a drive signal DRV1 for the electronic switch Q1, a low-side driver (LSD) 228 configured to generate a drive signal DRV2 for the electronic switch Q2, and a control circuit 22a configured to control the operation of the driver circuits 226 and 228 according to a feedback signal FB indicating an output quantity to be regulated. For example, in the embodiment considered, the half-bridge circuit includes a feedback circuit 24 configured to generate a feedback signal FB. For example, in the embodiment considered, the feedback signal FB indicates the output voltage V at the output terminals 202a and 202b. out (and preferably proportional thereto). For example, such feedback circuit 24 may include two resistors, such as resistors R1 and R2, connected in series between terminals 202a and 202b, wherein the voltage at resistor R2 corresponds to the feedback signal FB and is therefore proportional to the output voltage. However, as previously mentioned, the feedback signal FB may also indicate other output quantities.

[0071] Specifically, in the embodiment under consideration, the control circuit 22a is configured to generate the PWM signal DRV. For example, in various embodiments, the high-side driver circuit 226 is configured to: in response to detecting that the signal DRV changes from deassertion to assertion (e.g., a rising edge in the signal DRV), set the signal DRV1 (e.g., immediately when using DCM, or after a first dead time when using CCM) to a first voltage to close the electronic switch Q1; and in response to detecting that the signal DRV changes from assertion to deassertion (e.g., a falling edge in the signal DRV), set the signal DRV1 (e.g., immediately) to a second voltage to open the electronic switch Q1.

[0072] For example, in various embodiments, and as is well known in the art, based on the input voltage V in The first voltage can be in The corresponding or control circuit 20a can obtain (eg, receive or generate) a lower supply voltage Vdd, and the driver circuit 226 can include or have an associated bootstrap circuit configured to generate a voltage Vdc relative to the voltage Vdc at the switch node Lx based on the supply voltage Vdd. Lx In the former case, the second voltage usually corresponds to ground, ie, terminal HS is connected to ground. In the latter case, on the other hand, the second voltage may correspond to the voltage V at the switching node Lx. Lx Correspondingly, ie, terminal HS is connected to the switching node Lx.

[0073] In various embodiments, when operating in CCM, the low-side driver circuit 228 is configured to: in response to detecting that the signal DRV changes from assertion to de-assertion (e.g., a falling edge in the signal DRV), set the signal DRV2 (e.g., after the second dead time) to a third voltage to close the electronic switch Q2; and in response to detecting that the signal DRV changes from de-assertion to assertion (e.g., a rising edge in the signal DRV), set the signal DRV2 (e.g., immediately) to a fourth voltage to open the electronic switch Q2.

[0074] For example, in various embodiments and as is well known in the art, based on the input voltage V in The third voltage can be in Or the additional voltage Vdd. In contrast, the fourth voltage usually corresponds to ground, ie the terminal LS is connected to ground.

[0075] Conversely, when operating in DCM, the low-side driver circuit 228 may also receive a signal CS indicating a current supplied to the inductor 28 when the electronic switch Q2 is closed, such as the signal CS1 or CS3, and the low-side driver circuit 228 may be configured to: in response to detecting that the signal DRV changes from assertion to deassertion, for example, a falling edge in the signal DRV, set the signal DRV2 (for example, after the second dead time) to a third voltage to close the electronic switch Q2; and in response to detecting that the signal CS indicates that the current I supplied to the inductor 28 L When zero is reached, the signal DRV2 is set to a fourth voltage (eg, immediately) to turn off the electronic switch Q2.

[0076] Thus, in the embodiment considered, the half-bridge driver circuit includes the control circuit 22a and the driver circuits 226 and 228. Moreover, the half-bridge driver circuit includes a first terminal HS configured to provide a signal DRV1 to drive the gate terminal of the FET Q1, a second terminal LS configured to provide a signal DRV2 to drive the gate terminal of the FET Q2, and a third terminal configured to receive a feedback signal FB from the feedback circuit 24. For example, such a half-bridge driver circuit can be implemented in an integrated circuit, wherein the terminals HS, LS and FB are implemented via corresponding pads (of the IC die) or pins (of the package die). In general, such an IC may also include electronic switches Q1 and Q2, and / or the feedback circuit 24. For example, when electronic switches are included, the terminals 200a, 200b, Lx and FB may be implemented with pads or pins of the IC.

[0077] Fig. 9 An embodiment of the control circuit 22a is also shown. In particular, in the embodiment considered, the control circuit 22a is again operated in PCM. In particular, in the embodiment considered, the control circuit 22a is configured to SW The PWM signal DRV is then periodically asserted (e.g., set to high). For example, in the embodiment under consideration, the control circuit 22a includes a flip-flop 223 (such as a set-reset flip-flop) and an oscillator (OSC) 222. Specifically, the oscillator 222 and the flip-flop 223 are configured to reset the PWM signal DRV at time T. SW Flip-flop 223 is then periodically asserted.

[0078] Furthermore, the control circuit 22a is configured to determine the current I flowing through the electronic switch Q1 in response to Q1 (ie, the current I supplied to the inductor 28 during the on period of the electronic switch Q1 L ) reaches the threshold I LPK Instead, the PWM signal DRV is de-asserted (eg, set to low).

[0079] For example, in the embodiment under consideration, the control circuit 22a includes a voltage comparator 224 configured to convert the voltage drop at the FET Q1 (ie, the input voltage V in The voltage V at the switch node Lx Lx The difference between the threshold voltage I LPK Specifically, to generate the threshold voltage, the control circuit 22a includes a reference FET M3 corresponding to a scaled version of the FET Q1 according to a given scaling factor K, wherein the drain terminal of the reference FET M3 is connected to the terminal 200a, i.e., the drain terminal of the FET Q1, and the gate terminal of the reference FET M3 is connected to the drive signal DRV1, i.e., the gate terminal of the FET Q1, wherein the variable current generator 230 is configured to convert the current I COPY is applied to the source terminal of the reference FET M3, also indicated as node A in the following. Thus, the current I COPY A voltage drop is generated at FET M3, which is proportional to the input voltage V in and the voltage V at the source terminal of FET M3 COPY For example, in various embodiments and also as Fig.10 As schematically shown in FIG. 1 , the comparator 224 is connected to a voltage V Lx and V COPY , where comparator 224 is the internal reference input voltage V in However, an arrangement for measuring and comparing the drain-source voltages at FETs Q1 and M3 may also be used.

[0080] Thus, in the embodiment considered, when the drain-source voltage of FET Q1 reaches or exceeds the drain-source voltage of FET M3, that is, when:

[0081] I Q1 =I L =K·I COPY =I LPK (1)

[0082] When , comparator 224 asserts its output.

[0083] Therefore, by changing the current I COPY , the control circuit 22a can set the current flowing through the FET Q1 (i.e., the current I provided via the switch node Lx) during the on period of the FET Q1 (i.e., when the signal DRV1 is set to the first voltage to close the electronic switch Q1) L ) of the peak value I LPK .

[0084] As mentioned above, in the embodiment considered, the current ICOPY is provided by the variable current generator 230. For example, in the embodiment under consideration, the variable current generator 230 is configured to generate a current proportional to the control voltage V according to a given proportionality factor g. C (Approximately) proportional to the current I C ,Right now,

[0085] I C = g·V C (2)

[0086] The current I C Applied to node A, that is, I COPY =I CM .

[0087] Thus, in various embodiments, to implement PCM, the control circuit 22a includes an error amplifier 220 implemented via a regulator (preferably a PI or PID regulator), which is configured to vary the voltage V C Until the feedback signal FB and the reference voltage V ref Correspondingly, the reference voltage V ref Indicates the requested value of the output quantity to be regulated, such as the output voltage V out For example, in the embodiment under consideration, the regulator 220 includes a circuit that receives the feedback signal FB and the reference voltage V at the input terminal. ref An operational amplifier 2220 and a feedback or compensation network (NT) 2222 configured to implement the P, I, and optionally D components of the regulator. Specifically, in this case, the control voltage V C Corresponding to the voltage at the output terminal of operational amplifier 2220.

[0088] Thus, in the embodiment under consideration, the variable current generator 230 is configured as a voltage-to-current converter. For example, in the embodiment under consideration, the current generator 230 comprises a current generator configured to generate a current corresponding to the voltage V C Proportional current I' C The voltage to current conversion circuit 2300:

[0089] I′ C = gm·V C (3)

[0090] Furthermore, in order to apply the current to the source terminal of the reference FET M3, in various embodiments, the current generator 230 includes a current generator configured to generate a current I′ corresponding to the current I′ according to a given scaling factor M. C Proportional current I C The current mirror 2302 is:

[0091] I C =M·I′C =M·gm·V C = g·V C (4)

[0092] Here, g=M·gm corresponds to the proportionality coefficient of the current generator 230 .

[0093] For example, in the embodiment considered, the current mirror 2302 is implemented with two n-channel FETs M1 and M2, where the input stage / FET M1 is configured to be driven by the current I' C , where FET M2 is a scaled version of FET M1 according to a scaling factor M, whereby the output stage / FET M2 is configured to be traversed by a current M·I'C. Specifically, in the embodiment considered, the source terminals of FETs M1 and M2 are connected to ground, and the drain terminal of FET M1 is connected to the output of the voltage-to-current conversion circuit 2300 and thus receives a current I' C , the drain terminal of FET M2 is connected to node A, ie, the source terminal of reference FET M3, and the gate terminals of FETs M1 and M2 are connected to the drain terminal of FET M1.

[0094] Therefore, in Fig. 9 In the embodiment shown in FIG. 1 , the comparator 224 is configured to L The output of flip-flop 223 is deasserted when a threshold corresponding to the following equation is reached:

[0095] I LPK =K·g·V C (5)

[0096] The control voltage V C With peak current I LPK Proportional:

[0097] Fig.10 Another embodiment of the half-bridge circuit 20a is shown. Fig. 9 In contrast, the current generator 230 has an associated slope compensation circuit (SCC) 234, which is useful for preventing subharmonic oscillations when the duty cycle of the PWM signal DRV1 is higher than 50%. Specifically, the slope compensation circuit 234 is configured to convert the current I generated by the current generator 230 to C Reduce the compensation current I slope ,Right now:

[0098] I COPY =I C -I slope = g·V C -I slope (6)

[0099] For example, in the embodiment considered, the slope compensation circuit 234 is connected to the node A, i.e., the output of the current generator 230 / the source terminal of the reference FET M3, and is a linearly increasing sawtooth signal, wherein the sawtooth signal increases at each switching cycle T SW Specifically, in various embodiments: when FET Q1 is closed, that is, when terminal HS is set to the first voltage, current I slope corresponding to the linearly increasing ramp signal; and when the FET Q1 is turned off, that is, when the terminal HS is set to the second voltage, the current I slope Corresponds to zero.

[0100] In general, equation (5) can also be implemented by adding a decreasing (negative) ramp signal instead of subtracting an increasing (positive) signal.

[0101] For example, in Fig.10 In the embodiment shown in FIG. , the slope compensation circuit 234 includes a circuit configured to generate a slope compensation circuit 234 at each switching cycle T SW Increment from zero to I ramp,PK The (positive) peak value of the ramp signal I ramp A current generator 2340, and an electronic switch 2342 connected between the current generator 2340 and the output terminal of the current generator 230 / the source terminal of the reference FET M3, wherein the electronic switch 2342 is arranged to be closed when the electronic switch Q1 is closed and to be opened when the electronic switch Q1 is opened, for example, by driving the electronic switch 2342 via a drive signal DRV1. Instead of using the signal DRV1, the electronic switch 2342 can also be driven via the signal DRV.

[0102] Also in this case, when the current I Q1 (i.e., I L ) reaches the peak value I LPK Specifically, when FET Q1 is turned off at time t2, the current I slope The given value corresponding to the following equation has been reached:

[0103] I slope (t2) = D·I ramp,PK (7)

[0104] Among them I ramp,PK With the slope signal I ramp corresponds to the peak value of , and D is the duty cycle of the signal DRV1 , which approximately corresponds to the duty cycle of the signal DRV.

[0105] Thus, according to equation (5), in the embodiment considered, the current I Q1 (i.e., I L) corresponds to the following formula:

[0106] I LPK =K·(g·V C -D.I ramp,PK ) (8)

[0107] However, this means that the control voltage V C No longer directly indicates the peak current I LPK For example, this Fig.11 Specifically, as mentioned above, the electronic switch Q1 is switched in each switching cycle T SW The switch is closed at time t1 at the beginning of the switching operation (eg, in response to a rising edge in the clock signal CLK). Conversely, in response to determining that the current I provided via the switch node Lx L Reaching a given threshold I LPK , the electronic switch Q1 is turned off at time t2. Specifically, in the waveform shown, it is assumed that even if the duty cycle D increases from 0 to 1, the threshold I LPK Also, in parallel, the slope compensation circuit 234 generates a current I slope , the current I slope At time t2, it increases from zero to a given peak value I slope (t2), the peak value I slope (t2) can be determined according to equation (6). Fig.11 As shown in , in order to obtain the same threshold I LPK , which includes the contribution of both the current generator 230 and the slope compensation circuit 234, the error amplifier / regulator 220 must increase the control voltage V C , that is, the control voltage V C Depends on the current I LPK and duty cycle D.

[0108] In fact, for V C Solving equation (7) provides:

[0109]

[0110] where K and g are constants.

[0111] Therefore, when the threshold I LPK When using slope compensation, the voltage V C (or the corresponding current I C ) can be used to determine the peak I LPK To this end, an additional current sensor is usually used to provide a signal proportional to the current flowing through the electronic switch Q1, such as a shunt resistor connected in series with the electronic switch Q1. However, such an additional current sensor, in particular the corresponding sensing circuit, is usually complex and therefore large.

[0112] Therefore, an embodiment of a control circuit will be described below, which can provide a control circuit that indicates the current I provided via the switching node Lx. L The peak value I LPK signal, which requires only minor additional circuitry.

[0113] Specifically, in order to obtain the peak value I LPK The control circuit can adjust the signal I at time t2 to COPY However, it will be noted that directly measuring the current I COPY A large area will be required, for example, to achieve a voltage suitable for supporting V in Also, the current consumption will be high, resulting in lower efficiency.

[0114] In contrast, in various embodiments, the control circuit 22a is configured to control the current I slope Sampling is then done either from the current I C remove this current from the control voltage V after the current-to-voltage conversion C Thus, the solution disclosed herein allows additional operations to be performed in the low voltage domain, for example, the additional FETs can be small.

[0115] Fig.12 An embodiment of such a circuit system is shown. Specifically, in the embodiment considered, the current source 230 is again configured to generate a voltage V C Proportional current I C , that is, I C = g·V C Furthermore, the slope compensation circuit generates a current I slope , where these currents are used to generate the current I flowing through the reference FET M3 COPY , that is, I COPY =I C -Is lope This is schematically shown, for example, via the subtraction node A. However, as mentioned before, when currents are used, it is sufficient to supply these currents (with the correct polarity) to the node A, whereby the resulting current I COPY flows through reference FET M3.

[0116] In the embodiment considered, the current source 230 is configured to also generate a current I C The second current I corresponding to the copy CC , that is, I CC =I C = g·V CFor example, as will be described below, when using the current mirror 2302, it is sufficient that this current mirror includes an additional branch.

[0117] In the embodiment considered, the slope compensation circuit (SLOPE) 234 is configured to provide a further signal S having a value indicative of the current I slope (and preferably proportional to) a (voltage or current) value. For example, Fig.12 The current sensor 2344 is schematically shown in FIG. slope To generate the signal S. However, the slope compensation circuit 234 can also directly provide the current I slope and has the same current I slope Specifically, the signal S is provided to a sample-and-hold (S / H) circuit 236, which is configured to generate a current signal S of the same value at time t2 (i.e., when the current I Q1 (I L ) reaches the threshold I LPK When the signal S is sampled, the current I SH , where signal I SH with I slope (t2) corresponds to:

[0118] I SH =I slope (t2) = D·I ramp,PK (10)

[0119] For example, in the embodiment under consideration, the sample-and-hold circuit 236 is configured to sample the signal S in response to the sampling signal SAMPLE. Thus, in various embodiments, the signal SAMPLE may include a trigger / pulse indicating the time t2. For example, the control circuit 22a may be configured to generate the signal SAMPLE by generating a pulse in the signal SAMPLE in response to detecting a rising edge of the comparison signal at the output of the comparator 224 or a falling edge of the signal DRV.

[0120] Equation (10) also emphasizes that the signal S can be related to the ramp current I ramp is proportional to, because when the electronic switch Q1 is closed, that is, until time t2, the current I slope With ramp current I ramp They are basically identical, namely:

[0121] I SH =I slope (t2) = I ramp (t2) (11)

[0122] In the embodiment considered, the control circuit 22a is therefore configured toCC Subtract the sampled current I from SH To generate the current I L The peak value I LPK Proportional current I S ,Right now:

[0123] I S =I CC -I SH =I C -D.I ramp,PK (12)

[0124] It can be solved according to equations (2) and (9):

[0125] I S =(I LPK / K+D·I ramp,PK )-D·I ramp,PK =I LPK / K (13)

[0126] Fig.13 A first embodiment of blocks 234, 2344 and 236 is shown. Specifically, in the embodiment considered, the slope compensation circuit again comprises a ramp generator 2340 and an electronic switch 2342. However, instead of providing a current I directly to node A via the electronic switch 2342 ramp , the slope compensation circuit 234 comprises a current mirror including two FETs M4 and M5. For example, in the embodiment considered, the FETs M4 and M5 are p-channel FETs, wherein the source terminals of the FETs are connected to a supply voltage (such as Vdd), and the drain terminal of the FET M4 is connected to the output terminal of the current source 2340, i.e., the input stage M4 of the current mirror is driven by the current I ramp The drain terminal of FET M5 is connected to node A via electronic switch 2342, thereby providing a current I to node A when electronic switch 2342 is closed via signal DRV1 (or DRV). ramp , that is, the output stage M5 of the current mirror and the electronic switch 2342 provide a current I to node A slope , and the gate terminals of FETs M4 and M5 are connected to the drain terminal of FET M4. In various embodiments, FET M5 may also be a scaled version of FET M4. However, this embodiment will not be considered in detail below because it results in a ramp current I ramp Relative to the current I slope of scaling.

[0127] Therefore, when using current mirror M4 / M5 to generate current I ramp When a copy of the current mirror M4 / M5 is generated, a signal S can be generated via an additional branch of the current mirror M4 / M5, thereby supplying a current Iramp However, it is considered here that instead of storing a current, it is easier to store a voltage and the gate voltage of FET M5 (and similarly M4) already indicates the current I ramp Thus, in various embodiments, the signal S corresponds to the voltage at the gate terminal of FET M5, i.e., the sample-and-hold circuit 236 is configured to store the voltage at the gate terminal of FET M5 (i.e., the gate voltage of FET M4) to the capacitor C in response to the signal SAMPLE. S (such as a capacitor). For example, in the embodiment considered, the capacitor C S The first terminal of is connected to the gate terminal of FET M5 via electronic switch 2360, and capacitor C S The second terminal of is connected to a reference voltage (such as ground or Vdd). Thus, when the signal SAMPLE is asserted at time t2, the electronic switch 2360 is closed and the capacitor C S Storage indication current I slope (t2). Furthermore, once the signal SAMPLE is deasserted (after a short time), the capacitor C S Just maintain its voltage.

[0128] Thus, in the embodiment under consideration, the sample-and-hold circuit 236 may include a circuit configured to store the current stored in the capacitor C S The voltage in is converted into a current i SH For example, in the embodiment considered, the capacitor C S The first terminal of the FET M5 is also connected to the gate terminal of another FET M6 having the same scaling as the FET M5, whereby the FET M6 provides the sampled current I SH =I slope (t2). For example, in the embodiment under consideration, FET M6 is a p-channel FET, wherein the source terminal of FET M6 is connected to the source terminal of FET M5, and the drain terminal of FET M6 provides the current I SH .

[0129] Thus, in the embodiment considered, the current sensor 2344 is also implemented with the current mirror M4 / M5, wherein the signal S corresponds to the voltage at the gate terminal of the FET M5, and the sample-and-hold circuit 236 is configured to store the gate voltage of the FET M5 (e.g., at the capacitor C in response to the signal SAMPLE). S In addition, the sample-and-hold circuit 236 includes a circuit configured to generate a current I based on the stored gate voltage. SH The voltage to current converter M6.

[0130] Fig.13The solution shown in also has the advantage that it is sufficient to add one or more further FETs, the respective gate terminals of which are connected to the capacitor C S The first terminal provides a current I slope (t2) corresponds to another signal. For example, as described above, an additional current I' can be generated by another FET M7. SH , where the current I' SH Provided to overcurrent protection circuit.

[0131] In various embodiments, the capacitor C S The first terminal can be connected via a voltage follower ( Fig.13 ) is connected to the gate terminal of FET M6.

[0132] Fig.14 A second embodiment of the circuit blocks 234, 2344 and 236 is shown. Specifically, in the embodiment considered, the slope compensation circuit 234 comprises, in addition to the ramp generator 2340, a circuit generating a current I ramp Copy I rampC Thus, in this case, FET M4 can again be configured to provide an indication current I rampC =I ramp The current sensor (especially the current to voltage conversion circuit) of the signal S. For example, in Fig.14 , FET M4 is a p-channel FET with a source terminal connected to a supply voltage (such as Vdd), a drain terminal connected to the output of current generator 2340a, and a gate terminal connected to the drain terminal. Thus, the sample-and-hold circuit 236 may have the same Fig.13 The sample and hold circuit has the same structure as described.

[0133] Fig.15 Shows Fig.12 , Fig.13 and Fig.14 . Specifically, as previously described, the half-bridge driver circuit asserts the signal DRV1 at time t1 and de-asserts the signal DRV1 at time t2. In this regard, the sample-and-hold circuit 236 is configured to store the signal I at time t2. ramp t2 (eg, in response to a signal SAMPLE including a pulse at time t2) to generate a current I SH .

[0134] For example, in various embodiments, the control circuit 22a includes for this purpose a circuit configured to provide an indication current I slope The voltage S (eg, via the signal I slopeC) of a current-to-voltage conversion circuit (eg, M4), a capacitor C configured to store a voltage S at time t2, for example, in response to a signal SAMPLE S , and is configured to provide a current I SH The additional voltage-to-current converter (e.g., M6) is provided, wherein the current-to-voltage conversion circuit and the voltage-to-current converter are sized such that the current I SH The value of the current I at time t2 slope The value corresponds to .

[0135] Fig.16 shows a configuration to generate a peak current I LPK The estimated signal corresponding to I S Specifically, as described above, the sample-and-hold circuit 234 provides a current I slope (t2) The corresponding current I SH As mentioned above, the current I C The current corresponding to the copy I CC Subtract the current I SH .

[0136] For example, in various embodiments, the current source 230 includes a current mirror 2302. In this case, the current I CC It can be generated by providing an additional output stage / FET M8 of the current mirror 2302, wherein FET M8 has the same scaling factor M as FET M2, so that the same current is passed through FET M2 and M8. For example, in the embodiment considered, FET M8 is an n-channel FET, wherein the source terminal is connected to ground, the gate terminal is connected to the gate terminal of FET M1 (gate terminal of FET M2), and the drain terminal provides the current I CC Thus, in the embodiment considered, the current I SH and I CC can be provided to node B, node B provides current I S =I CC -I SH (See also the description of Equations 12 and 13).

[0137] As previously described, in various embodiments, the sample-and-hold circuit 236 may also provide one or more additional currents I′ having the same value as the current I SH . SHFor example, in the embodiment under consideration, the current mirror 2302 comprises an additional output stage / FET M9, wherein FET M9 has the same scaling factor M as FET M2, whereby FET M2 and M9 are traversed by the same current. For example, in the embodiment under consideration, FET M9 is an n-channel FET, wherein the source terminal is connected to ground, the gate terminal is connected to the gate terminal of FET M1 (gate terminal of FET M2), and the drain terminal provides the current I' CC Therefore, in the embodiment under consideration, the current I' can also be SH and I' CC Provided to node C, which provides current I' S =I' CC -I' SH , where I' S =I S For example, in this case, the current I SH can be used to determine the partitioning of power stages Q1 and Q2, and the current I' SH Can be used to verify the current I L If the maximum threshold is exceeded, over-current protection (OCP) is implemented. Fig.16 In the current I' SH is provided to a current comparator (COMP) 238, which is configured to convert the current I' SH and the current I indicating an overcurrent condition OCP For example, the current I OCP can be provided by the current source 2380. Thus, in various embodiments, when the current I' SH Exceeding current I OCP When , comparator 238 may assert signal OCP.

[0138] Fig.17 shows a configuration to generate a peak current I LPK Specifically, instead of generating a current I S , the circuit is configured to generate an indication peak current I LPK (and preferably proportional to) the voltage V S .

[0139] Moreover, in this case, the sample-and-hold circuit 234 provides a current I slope (t2) The corresponding current I SH As mentioned above, the current I C The current corresponding to the copy I CC Subtract the current I SH In this regard, as shown in equation (2), the current I CWith voltage V C Thus, in the embodiment under consideration, the summing circuit B is implemented with a current-to-voltage conversion circuit and a subtraction circuit, the current-to-voltage conversion circuit being configured to generate a current proportional to the current I SH Proportional voltage V SH , and the subtraction circuit is configured to generate a voltage V C With voltage V SH The difference between the corresponding signals V S .

[0140] For example, in Fig.17 In the embodiment, the summing circuit B is implemented by an operational amplifier 240, which receives the current I at the inverting input terminal. SH and receives the voltage V at the non-inverting input C , where the output of the operational amplifier is connected via resistor R sense Thus, in the embodiment considered, the output of the operational amplifier 240 provides a voltage V corresponding to the following equation: S :

[0141] V S =V C -V SH =V C -I SH ·R sense (14)

[0142] Therefore, equation (14) can be rewritten according to equations (9) and (10) as:

[0143]

[0144] Specifically, in various embodiments, the resistor R is selected sense With compensation gain g, that is:

[0145]

[0146] Therefore, the voltage V S With peak I LPK Proportional, that is:

[0147] V S =I LPK / K·g (17)

[0148] Thus, in various embodiments, the summing circuit C can be implemented using similar circuits. Fig.17 In the embodiment, the summing circuit C is implemented by an operational amplifier 242, which receives the current I' at the inverting input terminal. SH and receives the voltage V at the non-inverting input C, where the output of the operational amplifier is connected via resistor R OCP Connected to the inverting input terminal. Therefore, in various embodiments, the resistor R OCP The output of the operational amplifier 242 provides a compensation gain g, which is equal to the peak value I LPK Proportional voltage V' S .

[0149] Therefore, in this case, the voltage V' S and threshold voltage V OCP can be provided to the voltage comparator 238a, which is configured to generate a voltage V' when the voltage V S Exceeding voltage V OCP In various embodiments, instead of generating an additional voltage V' S , the comparator 238a can also be configured to be when the voltage V (generated by the summing circuit B) S Exceeding voltage V OCP The over-current signal OCP is asserted.

[0150] Of course, without prejudice to the principle of the invention, the details of construction and of the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without departing from the scope of the invention as defined by the appended claims.

[0151] The claims are an integral part of the technical teaching of the disclosure provided herein.

Claims

1. A half-bridge driver circuit for a half-bridge configured to power an inductive load, the half-bridge driver circuit comprising: a first terminal configured to provide a first drive signal to a gate terminal of a first field effect transistor (FET) representing a high-side electronic switch of the half-bridge; a second terminal configured to provide a second drive signal to a gate terminal of a second FET representing a low-side electronic switch of the half-bridge; a feedback terminal configured to receive a feedback signal indicative of an amount to be adjusted; The half-bridge driver circuit is configured to periodically repeat a switching cycle by: closing the first FET via the first drive signal at the beginning of each switching cycle; as well as detecting a time when the current flowing through the first FET reaches a threshold value, and, in response thereto, opening the first FET via the first drive signal and closing the second FET via the second drive signal; The half-bridge driver circuit comprises: a variable current generator configured to generate a first current according to a control voltage; an error amplifier configured to generate the control voltage by comparing the feedback signal to a reference signal, wherein the error amplifier comprises a regulator having proportional and integral components; and a slope compensation circuit configured to generate a second current, wherein the second current is a ramp signal that is reset at the beginning of each switching cycle, and wherein the threshold is generated by subtracting the second current from the first current; The half-bridge driver circuit is configured as follows: sampling the second current in response to detecting the instant; and A signal indicative of the threshold is generated by subtracting the sampled second current from the first current.

2. The half-bridge driver circuit according to claim 1, wherein the half-bridge driver circuit is configured as: turning off the second FET via the second drive signal at the beginning of each switching cycle; or A further moment at which the current through the second FET reaches zero is detected and, in response to detecting the further moment, the second FET is turned off via the second drive signal.

3. The half-bridge driver circuit according to claim 1 or claim 2, further comprising: a reference FET configured to be passed through by a third current corresponding to a difference between the first current and the second current; as well as A comparator is configured to generate a signal indicative of the time by comparing a voltage drop at the reference FET with a voltage drop at the first FET.

4. The half-bridge driver circuit according to claim 1 , wherein the sampling of the second current at the time instant comprises: obtaining a voltage indicative of the second current at the time; In response to detecting the moment, storing the obtained voltage in a capacitor; as well as A fourth current is generated according to the voltage at the capacitor.

5. The half-bridge driver circuit of claim 4 , wherein the slope compensation circuit comprises a current source configured to generate a ramp signal, and wherein the half-bridge driver circuit comprises: a third FET configured to be passed through by the ramp signal, wherein a gate terminal of the third FET is connected to a drain terminal of the third FET, wherein the voltage indicative of the second current corresponds to a voltage at the gate terminal of the third FET; as well as A fourth FET is configured to provide the fourth current, wherein a gate terminal of the fourth FET is driven via the voltage at the capacitor.

6. The half-bridge driver circuit according to claim 1, wherein the variable current generator comprises: a current source configured to generate a fifth current proportional to the control voltage; as well as A current mirror is configured to generate the first current by mirroring the fifth current.

7. The half-bridge driver circuit according to claim 1 , wherein the sampling of the second current at the time comprises: obtaining a voltage indicative of the second current at the time; In response to detecting the moment, storing the obtained voltage in a capacitor; as well as generating a fourth current according to the voltage at the capacitor; The variable current generator comprises: a current source configured to generate a fifth current proportional to the control voltage; and a current mirror configured to generate the first current by mirroring the fifth current; wherein the current mirror is configured to generate a sixth current corresponding to the first current, and wherein the half-bridge driver circuit is configured to generate the signal indicative of the threshold by subtracting the fourth current from the sixth current.

8. The half-bridge driver circuit according to claim 7, comprising: an operational amplifier, wherein an inverting input terminal of the operational amplifier is connected to the fourth current, a non-inverting input terminal of the operational amplifier is connected to the control voltage, and an output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier via a resistor, wherein a voltage at the output terminal of the operational amplifier corresponds to the signal indicating the threshold value.

9. An integrated circuit comprising: The half-bridge driver circuit according to claim 1.

10. A half-bridge circuit, comprising: A first FET and a second FET connected in series between two input terminals configured to receive an input voltage, wherein an intermediate node between the first FET and the second FET represents a switch node configured to supply power to an inductive load; and The half-bridge driver circuit according to claim 1.

11. A half-bridge circuit according to claim 10, wherein the half-bridge circuit is an electronic converter providing a buck converter, and wherein the feedback signal is indicative of an output voltage or an output current generated by the electronic converter.

12. A method of operating a half-bridge circuit configured to supply power to an inductive load, the method comprising: The on-off cycle is repeated periodically by: closing a first FET representing a high-side electronic switch of the half-bridge at the beginning of each switching cycle; detecting a moment when the current flowing through the first FET reaches a threshold value, and, in response to detecting the moment, opening the first FET and closing a second FET representing a low-side electronic switch of the half-bridge; generating a first current according to a control voltage; generating said control voltage via a regulator having proportional and integral components by comparing a feedback signal indicative of the quantity to be regulated with a reference signal; generating a second current, wherein the second current is a ramp signal that is reset at the beginning of each switching cycle, generating the threshold by subtracting the second current from the first current; The method further comprises: In response to detecting the time instant, sampling the second current at the time instant, and A signal indicative of the threshold is generated by subtracting the sampled second current from the first current.

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