Current Harmonic Suppression Method, Device and Equipment for T-Type Three-Phase Three-Level Inverter

Abstract

The present application discloses a method, device, equipment and readable storage medium for suppressing current harmonics of a T-type three-phase three-level inverter, which relates to the field of power electronics technology. It includes: obtaining the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determining a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage; calculating the cost value corresponding to each candidate vector voltage for each candidate vector voltage in the target control set; using the candidate vector voltage corresponding to the minimum cost value as the target vector voltage. The method in the present application effectively suppresses the current harmonics of the T-type three-phase three-level inverter.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a method, device, equipment and readable storage medium for suppressing current harmonics of a T-type three-phase three-level inverter. Background Art

[0002] Compared with traditional two-level inverters, T-type three-phase three-level inverters have received more extensive attention due to their advantages such as high power density and low voltage stress. However, due to factors such as DC-side voltage fluctuations and characteristics of switching devices, there are still significant harmonics in the output current of three-phase T-type inverters. Harmonics are high-frequency components in the power grid and can cause various hazards to the power system and equipment. They can cause devices such as transformers, motors, and capacitors to heat up, increase losses, shorten their service life, and even be damaged. Harmonics can also cause grid voltage distortion, increase power losses, and may lead to resonance phenomena, endangering power supply safety. In addition, harmonics interfere with electronic devices, which may cause problems such as misoperation of automatic control systems and computer data errors, affecting production and communication. Seriously, harmonics can also cause cable overheating and grid instability problems.

[0003] However, the current research on suppressing the output current harmonics of T-type three-phase three-level inverters is still very limited, and it is unable to effectively suppress the current harmonics output by T-type three-phase three-level inverters. Therefore, while enjoying the advantages brought by T-type three-phase three-level inverters, they are still affected and harmed by harmonics. Thus, there is an urgent need for a harmonic suppression method that can effectively reduce the current harmonics of T-type three-phase three-level inverters. Summary of the Invention

[0004] The purpose of the present invention is to provide a method, device, equipment and readable storage medium for suppressing current harmonics of a T-type three-phase three-level inverter. According to the real-time numerical relationship between the upper capacitor voltage and the lower capacitor voltage, a suitable target control set is selected. In this process, the vector voltage is filtered for the first time. Subsequently, the cost values of each candidate vector voltage in the target control set are calculated, and the candidate vector voltage corresponding to the minimum cost value is the target vector voltage. In this process, the vector voltage is filtered for the second time, and the vector voltage with the minimum cost value can be selected. The minimum cost value corresponds to the minimum output current harmonics. This method can make the vector voltage with the minimum output current harmonics of the T-type three-phase three-level inverter, realizing the effective suppression of current harmonics.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] In the first aspect, the present invention provides a method for suppressing current harmonics of a T-type three-phase three-level inverter, the method comprising:

[0007] Obtain the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determine the target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage;

[0008] For each candidate vector voltage in the target control set, calculate the cost value corresponding to each candidate vector voltage;

[0009] Take the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

[0010] In some embodiments, calculating the cost value corresponding to each candidate vector voltage in the target control set includes:

[0011] For each candidate vector voltage in the target control set, calculate the weight coefficient corresponding to each candidate vector voltage;

[0012] Substitute the weight coefficient into the cost function to calculate the cost value corresponding to each candidate vector voltage.

[0013] In some embodiments, calculating the weight coefficient corresponding to each candidate vector voltage in the target control set includes:

[0014] According to each candidate vector voltage, respectively construct a current prediction model;

[0015] Based on the current prediction model, calculate the current harmonics corresponding to each candidate vector voltage;

[0016] Based on the current harmonics, calculate the weight coefficient corresponding to each candidate vector voltage.

[0017] In some embodiments, constructing the current prediction model according to each candidate vector voltage respectively includes:

[0018] According to each candidate vector voltage, respectively construct an output-side current equation;

[0019] Perform Clarke transformation and discretization processing on the output-side current equation to obtain the current prediction model.

[0020] In some embodiments, calculating the current harmonics corresponding to each candidate vector voltage based on the current prediction model includes:

[0021] According to the current prediction model, extract the fundamental current through a low-pass filter;

[0022] According to the fundamental current, calculate the current harmonics corresponding to each candidate vector voltage.

[0023] In some embodiments, calculating the weight coefficient corresponding to each candidate vector voltage based on the current harmonics includes:

[0024] Set a cost function;

[0025] Based on the cost function, perform a partial derivative process on the current harmonics to obtain the weight coefficients corresponding to each candidate vector voltage.

[0026] In a second aspect, the present invention also provides a device for suppressing current harmonics of a T-type three-phase three-level inverter, and the device includes:

[0027] A set determination module, configured to obtain the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determine a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage;

[0028] A cost calculation module, configured to calculate the cost values corresponding to each candidate vector voltage for each candidate vector voltage in the target control set;

[0029] A target determination module, configured to use the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

[0030] In a third aspect, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the method for suppressing current harmonics of the T-type three-phase three-level inverter provided in the first aspect.

[0031] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the method for suppressing current harmonics of the T-type three-phase three-level inverter provided in the first aspect.

[0032] In a fifth aspect, the present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the method for suppressing current harmonics of the T-type three-phase three-level inverter provided in the first aspect.

[0033] The beneficial effects of the present invention are as follows:

[0034] The method for suppressing current harmonics of a T-type three-phase three-level inverter provided in the present invention obtains the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determines a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage; for each candidate vector voltage in the target control set, calculates the cost value corresponding to each candidate vector voltage; takes the candidate vector voltage corresponding to the minimum cost value as the target vector voltage. According to the real-time numerical relationship between the upper capacitor voltage and the lower capacitor voltage, a suitable target control set is selected. This process filters the vector voltage for the first time. Subsequently, the cost values of each candidate vector voltage in the target control set are calculated, and the candidate vector voltage corresponding to the minimum cost value is the target vector voltage. This process filters the vector voltage for the second time, and can select the vector voltage with the minimum cost value, and the minimum cost value corresponds to the minimum output current harmonics. This method can make the T-type three-phase three-level inverter output the vector voltage with the minimum current harmonics, and effectively suppresses the current harmonics.

[0035] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it according to the content of the specification, the following describes in detail with preferred embodiments of the present invention and accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic flow chart of a method for suppressing current harmonics of a T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0037] Figure 2 It is a topological structure diagram of a T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0038] Figure 3 It is a schematic diagram of 27 voltage vectors that can be output by a T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0039] Figure 4 It is the waveform diagram of the upper capacitor voltage on the DC side under the traditional harmonic suppression method shown in an embodiment of the present invention ;

[0040] Figure 5 It is the waveform diagram of the upper capacitor voltage on the DC side under the method for suppressing current harmonics of the T-type three-phase three-level inverter proposed in the present invention shown in an embodiment of the present invention ;

[0041] Figure 6 It is the waveform of the output current of phase a and the analysis diagram of its fast Fourier transform under condition 1 and the traditional harmonic suppression method shown in an embodiment of the present invention ;

[0042] Figure 7 Under Condition 1 shown in an embodiment of the present invention, the waveform of the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention and the analysis diagram of its fast Fourier transform;

[0043] Figure 8 Under Condition 2 shown in an embodiment of the present invention, the waveform of the output current of phase a under the traditional harmonic suppression method and the schematic diagram of the corresponding vector selection;

[0044] Figure 9 Under Condition 2 shown in an embodiment of the present invention, the waveform of the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention and the schematic diagram of the corresponding vector selection;

[0045] Figure 10 Under Condition 2 shown in an embodiment of the present invention, the waveform of the output current of phase a under the traditional harmonic suppression method and the enlarged schematic diagram of the corresponding vector selection;

[0046] Figure 11 Under Condition 2 shown in an embodiment of the present invention, the waveform of the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention and the enlarged schematic diagram of the corresponding vector selection;

[0047] Figure 12 The result of the neutral point voltage balance test of the traditional harmonic suppression method shown in an embodiment of the present invention;

[0048] Figure 13 The result of the neutral point voltage balance test of the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention shown in an embodiment of the present invention;

[0049] Figure 14 The flow schematic diagram of another current harmonic suppression method of the T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0050] Figure 15 The structural schematic diagram of a current harmonic suppression device of a T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0051] Figure 16 The structural schematic diagram of another current harmonic suppression device of a T-type three-phase three-level inverter shown in an embodiment of the present invention;

[0052] Figure 17 The structural schematic diagram of the electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0053] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0054] It should be noted that the references to "one embodiment", "embodiment", "example embodiment", etc. in this specification mean that the described embodiment may include specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. In addition, such expressions do not refer to the same embodiment. Further, when combining an embodiment to describe a specific feature, structure, or characteristic, whether or not there is an explicit description, it has been shown that it is within the knowledge of those skilled in the art to combine such features, structures, or characteristics into other embodiments.

[0055] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0056] In some embodiments, as Figure 1 shown, a flow schematic diagram of a method for suppressing current harmonics of a T-type three-phase three-level inverter is provided. The specific method includes:

[0057] S101, obtaining the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determining a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage.

[0058] Specifically, as Figure 2 shown, Figure 2 is a topological structure diagram of a T-type three-phase three-level inverter. Each bridge arm of the T-type three-phase three-level inverter is composed of four controllable switching devices and can output three different voltages. Among them, is the DC side voltage; and are the upper capacitor voltage and the lower capacitor voltage respectively; , and are the current passing through the upper capacitor , the current passing through the lower capacitor and the neutral point current respectively; is the filter inductor on the output side; is the output current of the T-type three-phase three-level inverter; , and Linear resistive loads for three phases A, B, and C respectively. Each leg of the T-type three-level three-phase inverter contains 4 controllable switching devices, namely: , , and , where , and always conduct complementarily; and also always conduct complementarily. According to different switching combinations of the three-level three-phase inverter, a single-phase leg can generate 3 switching states, defined as , where , can have values of "1", "0", and "-1", defined as "P", "O", and "N". When the midpoint potential is balanced, , the output voltage of a single-phase leg is defined as , where , and the output voltage of a single-phase leg can be expressed by formula (1), and the corresponding switching combinations are shown in Table 1.

[0059] ;

[0060] The synthesized output vector voltage can be expressed by formula (2):

[0061] ;

[0062]

[0063] As Figure 3 shown, Figure 3 shows the 27 voltage vectors that the T-type three-level three-phase inverter can output. A single-phase leg of the T-type three-level three-phase inverter can output 3 different switching states, and there are a total of 27 (3 3 ) possible output states. According to the magnitude of each voltage vector, they can be divided into 4 types of vectors: zero vector, small vector, medium vector, and large vector. Among the voltage vectors of the T-type three-level three-phase inverter, small vectors have an obvious influence on the midpoint voltage offset, and the action effects of paired small vectors are opposite. According to this characteristic, the upper capacitor voltage and the lower capacitor voltage of the T-type three-level three-phase inverter at the kth moment can be obtained first by the voltage sensor. When the upper capacitor voltage is less than the lower capacitor voltage, that is, when V p is less than V n , the target control set is determined as { V 0, V 1, V 2, V 3, V 4,V 5, V 6, V 7, V 14 , V 15 , V 16 , V 17 , V 18 , V 19 , V 20 , V 21 , V 22 , V 23 , V 24 , V 25 , V 26}, when the voltage of the upper capacitor is greater than the voltage of the lower capacitor, that is, when V p is greater than V n, determine the target control set as { V 0, V 7, V 8, V 9, V 10 , V 11 , V 12 , V 13 , V 14 , V 15 , V 16 , V 17 , V 18 , V 19 , V 20 , V 21 , V 22 , V 23 , V 24 , V 25 , V 26}.

[0064] S102. For each candidate vector voltage in the target control set, calculate the cost value corresponding to each candidate vector voltage.

[0065] Specifically, each candidate vector voltage can be calculated according to the above formula (2), and then each candidate vector voltage is substituted into the cost value calculation formula respectively to obtain the cost value corresponding to each candidate vector voltage.

[0066] Optionally, the method for calculating the cost value corresponding to each candidate vector voltage can also be: for each candidate vector voltage in the target control set, calculate the weight coefficient corresponding to each candidate vector voltage; substitute the weight coefficient into the cost function to calculate the cost value corresponding to each candidate vector voltage.

[0067] Optionally, the method for calculating the weight coefficient corresponding to each candidate vector voltage includes: respectively constructing a current prediction model according to each candidate vector voltage; calculating the current harmonics corresponding to each candidate vector voltage based on the current prediction model; calculating the weight coefficient corresponding to each candidate vector voltage based on the current harmonics.

[0068] Specifically, according to each candidate vector voltage, an output-side current equation is respectively constructed; the Clarke transform and discretization processing are performed on the output-side current equation to obtain a current prediction model; according to the current prediction model, the fundamental current is extracted through a low-pass filter; according to the fundamental current, the current harmonics corresponding to each candidate vector voltage are calculated; a cost function is set; based on the cost function, the partial derivative processing is performed on the current harmonics to obtain the weight coefficient corresponding to each candidate vector voltage.

[0069] Exemplarily, an output-side current equation can be constructed according to the topological structure diagram of the T-type three-phase three-level inverter in Figure 2 and the determined candidate vector voltage. See the following formula (3):

[0070] ;

[0071] Perform the Clarke transform on the above formula (3) to obtain formula (4):

[0072] ;

[0073] Then, perform the discretization processing on formula (4) through the forward Euler formula to obtain the predicted value formula of the current at the k + 1 moment on the Figure 3 axis (as shown in

[0074] ), that is, the current prediction model (5):

[0075] The predicted value of the output current at the k + 1 moment and The fundamental current is extracted through a low-pass filter (LPF). and , as shown in Equation (6):

[0076] ;

[0077] where and are the actual values of the fundamental output current at time k, A is the filtering coefficient, is the cut-off frequency, is the calculation period.

[0078] The current harmonics at time k+1 are calculated through the following Equation (7):

[0079] ;

[0080] It should be noted that, to achieve efficient low-pass filtering of the inverter output current, the present invention has conducted a comprehensive and in-depth experimental exploration on the selection of the cut-off frequency. By gradually changing the cut-off frequency, starting from 50 Hz and increasing step by step in 100 Hz increments to higher frequency bands, the total harmonic distortion of the output current at different cut-off frequencies is analyzed. After multiple rounds of repeated experiments, it is finally determined that when the cut-off frequency is set to 3000 Hz, the output current harmonics can be most effectively reduced to the minimum value, and at this time, the filtering coefficient A is 0.5409.

[0081] The set cost function is as follows in Equation (8):

[0082] ;

[0083] Taking the partial derivatives of Equation (8) with respect to and respectively, the weight coefficients and are obtained, as shown in Equation (9):

[0084] ;

[0085] Substituting the obtained weight coefficients and each candidate vector voltage calculated in Equation (2) back into the cost function, i.e., Equation (8), the cost values corresponding to each candidate vector voltage can be obtained.

[0086] S103. Take the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

[0087] Specifically, numerically compare the cost values of each candidate vector voltage, and select the candidate vector voltage with the minimum cost value as the target vector voltage.

[0088] The method for suppressing current harmonics of the T-type three-phase three-level inverter in the above embodiments obtains the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determines the target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage; for each candidate vector voltage in the target control set, calculates the cost value corresponding to each candidate vector voltage; and takes the candidate vector voltage corresponding to the minimum cost value as the target vector voltage. According to the real-time numerical relationship between the upper capacitor voltage and the lower capacitor voltage, a suitable target control set is selected. This process filters the vector voltage for the first time. Subsequently, the cost values of each candidate vector voltage in the target control set are calculated, and the candidate vector voltage corresponding to the minimum cost value is the target vector voltage. This process filters the vector voltage for the second time, and can select the vector voltage with the minimum cost value, and the minimum cost value corresponds to the minimum output current harmonics. This method can make the T-type three-phase three-level inverter output the vector voltage with the minimum current harmonics, and effectively suppresses the current harmonics.

[0089] In another embodiment, in order to verify the effectiveness of the method for suppressing current harmonics of the above T-type three-phase three-level inverter, the present invention builds a simulation experiment of the T-type three-phase three-level inverter on the Simulink platform, and the experimental parameters are shown in Table 2 for details.

[0090] Among them, the experimental conditions are as follows: Condition 1: The reference current amplitude and frequency are set to 3A and 50Hz respectively. Condition 2: The reference current frequency is set to 50Hz, and the amplitude steps from 2A to 3A. Condition 3: A 50Ω resistor R is connected in parallel at the upper capacitor on the DC side under the condition of Condition 2. p .

[0091]

[0092] Figure 4 Shows the waveform of the upper capacitor voltage on the DC side under the traditional harmonic suppression method . Figure 5 Shows the waveform of the upper capacitor voltage on the DC side under the method for suppressing current harmonics of the T-type three-phase three-level inverter proposed by the present invention . It can be seen that the neutral point voltage can be well balanced under both the traditional harmonic suppression method and the method for suppressing current harmonics of the T-type three-phase three-level inverter proposed by the present invention.

[0093] Figure 6 Shows the waveform of the output current of phase a under Condition 1 and the traditional harmonic suppression method, as well as the analysis diagram of its fast Fourier transform (FFT). Among them, the upper figure is the waveform, and the lower figure is the FFT analysis diagram. Figure 7Shows the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention under Condition 1 The waveform and its Fast Fourier Transform (FFT) analysis diagram, where the upper figure is The waveform, and the lower figure is The FFT analysis diagram of. According to the FFT analysis results, under the traditional harmonic suppression method, the total harmonic distortion (THD) of the phase-a current is 3.32%. Under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention, the total harmonic distortion (THD) of the phase-a current is 2.73%, which is 0.59% smaller than the traditional method, and the sinusoidality is better.

[0094] To verify the dynamic performance of the current harmonic suppression method of the T-type three-phase three-level inverter proposed in this paper Figure 8 Shows the waveform of the output current of phase a under the traditional harmonic suppression method under Condition 2 And the corresponding vector selection situation; Figure 9 Shows the waveform of the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention under Condition 2 And the corresponding vector selection situation. When the amplitude of the reference current jumps, the currents under both algorithms can quickly track the reference current. After locally magnifying the waveforms of Figure 8 And Figure 9 As shown in Figure 10 And Figure 11 Shown, Figure 10 Shows the waveform of the output current of phase a under the traditional harmonic suppression method under Condition 2 And the corresponding vector selection situation; Figure 11 Shows the waveform of the output current of phase a under the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention under Condition 2 And the corresponding vector selection situation. The two algorithms have similar dynamic performance when the amplitude of the reference current jumps, and the selected vectors are also similar. This shows that compared with the traditional harmonic suppression method, under the condition of eliminating the weight coefficient of the neutral point potential and having fewer alternative vectors, the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention can still achieve similar dynamic performance to the traditional harmonic suppression method, further verifying the effectiveness of the current harmonic suppression method of the T-type three-phase three-level inverter proposed by the present invention.

[0095] Figure 12 Shows the results of the neutral point voltage balance test of the traditional harmonic suppression method under Condition 3 Figure 13The neutral point voltage balance test results of the current harmonic suppression method for the T-type three-phase three-level inverter proposed by the present invention under Condition 3 are shown. The results show that the oscillation of the midpoint potential under both algorithms remains within 0.5 V. After connecting a resistor in parallel with the upper capacitor on the DC side, the voltage of the upper capacitor drops. The voltage of this capacitor drops by 0.107 V under the traditional harmonic suppression method, while the voltage of this capacitor drops by 0.096 V under the current harmonic suppression method for the T-type three-phase three-level inverter proposed by the present invention. It can be considered that the current harmonic suppression method for the T-type three-phase three-level inverter proposed by the present invention has better performance than the traditional harmonic suppression method in balancing the midpoint potential.

[0096] To more comprehensively demonstrate this solution, this embodiment gives an alternative of the current harmonic suppression method for the T-type three-phase three-level inverter, as Figure 14 shown below:

[0097] S201. Obtain the voltages of the upper capacitor and the lower capacitor of the T-type three-phase three-level inverter, and determine the target control set according to the relationship between the voltages of the upper capacitor and the lower capacitor.

[0098] S202. Respectively construct the output-side current equations according to each candidate vector voltage.

[0099] S203. Perform Clarke transformation and discretization processing on the output-side current equations to obtain a current prediction model.

[0100] S204. Extract the fundamental current through a low-pass filter according to the current prediction model.

[0101] S205. Calculate the current harmonics corresponding to each candidate vector voltage according to the fundamental current.

[0102] S206. Set a cost function.

[0103] S207. Based on the cost function, perform partial derivative processing on the current harmonics to obtain the weight coefficients corresponding to each candidate vector voltage.

[0104] S208. Substitute the weight coefficients into the cost function and calculate the cost values corresponding to each candidate vector voltage.

[0105] S209. Use the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

[0106] The specific processes of the above S201-S209 can refer to the description of the above method embodiment, and their implementation principles and technical effects are similar, which will not be elaborated here.

[0107] Based on the same inventive concept, an embodiment of this application also provides a current harmonic suppression device for a T-type three-phase three-level inverter for implementing the current harmonic suppression method of the T-type three-phase three-level inverter involved above. The implementation solutions provided by this device to solve problems are similar to those recorded in the above method. Therefore, the specific limitations in one or more embodiments of the current harmonic suppression device for the T-type three-phase three-level inverter provided below can refer to the limitations on the current harmonic suppression method for the T-type three-phase three-level inverter in the above text, and will not be elaborated here.

[0108] In one embodiment, as Figure 15 shown, a current harmonic suppression device for a T-type three-phase three-level inverter is provided. The device includes:

[0109] A set determination module 30, configured to obtain the upper capacitor voltage and the lower capacitor voltage of the T-type three-phase three-level inverter, and determine a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage;

[0110] A cost calculation module 31, configured to calculate the cost values corresponding to each candidate vector voltage in the target control set;

[0111] A target determination module 32, configured to use the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

[0112] In another embodiment, as Figure 16 shown, the above Figure 15 cost calculation module 31 includes:

[0113] A weight calculation unit 310, configured to calculate the weight coefficients corresponding to each candidate vector voltage in the target control set;

[0114] A cost calculation unit 311, configured to substitute the weight coefficients into the cost function to calculate the cost values corresponding to each candidate vector voltage.

[0115] In another embodiment, the above Figure 16 weight calculation unit 310 includes:

[0116] A model construction subunit, configured to respectively construct a current prediction model according to each candidate vector voltage;

[0117] A harmonic calculation subunit, configured to calculate the current harmonics corresponding to each candidate vector voltage based on the current prediction model;

[0118] A weight calculation subunit, configured to calculate the weight coefficients corresponding to each candidate vector voltage based on the current harmonics.

[0119] In another embodiment, the model construction subunit in the above embodiment is specifically configured to: construct an output-side current equation according to each candidate vector voltage; perform Clarke transformation and discretization processing on the output-side current equation to obtain a current prediction model.

[0120] In another embodiment, the harmonic calculation subunit in the above embodiment is specifically configured to: extract the fundamental current through a low-pass filter according to the current prediction model; calculate the current harmonics corresponding to each candidate vector voltage according to the fundamental current.

[0121] In another embodiment, the weight calculation subunit in the above embodiment is specifically configured to: set a cost function; perform a partial derivative process on the current harmonics based on the cost function to obtain the weight coefficients corresponding to each candidate vector voltage.

[0122] An embodiment of the present application further provides an electronic device. In some embodiments, referring to Figure 17 as shown, the electronic device 700 includes an input unit 710, a memory 720, a processor 730, and an output unit 740. The memory 720 stores program instructions that can be run on the processor 730. The processor 730 can execute the current harmonic suppression method and / or technical solution based on the T-type three-phase three-level inverter in the foregoing embodiment by invoking the program instructions. The electronic device 700 can be a mobile terminal device such as a mobile phone or a computer.

[0123] In addition, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program for executing the current harmonic suppression method of the T-type three-phase three-level inverter. For example, computer program instructions, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. The program instructions for calling the method of the present application may be stored in a fixed or removable storage medium, and / or transmitted and / or stored in a storage medium that runs according to the program instructions through a data stream in a broadcast or other signal-bearing medium.

[0124] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present application can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program code executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module to implement. In this way, the present application is not limited to any specific combination of hardware and software.

[0125] The technical features of the above embodiments can be arbitrarily integrated. For the sake of concise description, not all possible integrations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the integration of these technical features, it should be considered as the scope described in this specification.

[0126] The above embodiments only express several implementation manners of the present invention, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A method for suppressing current harmonics of a T-type three-phase three-level inverter, characterized in that, The method includes: Obtaining the upper capacitor voltage and the lower capacitor voltage of a T-type three-phase three-level inverter, and determining a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage; Respectively constructing current prediction models according to the candidate vector voltages in the target control set; calculating the current harmonics corresponding to the candidate vector voltages based on the current prediction models; calculating the weight coefficients corresponding to the candidate vector voltages based on the current harmonics; substituting the weight coefficients into a cost function to calculate the cost values corresponding to the candidate vector voltages; Taking the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

2. The method for suppressing current harmonics of the T-type three-phase three-level inverter according to claim 1, characterized in that Respectively constructing current prediction models according to the candidate vector voltages, including: Respectively constructing output-side current equations according to the candidate vector voltages; Performing Clarke transformation and discretization processing on the output-side current equations to obtain current prediction models.

3. The method for suppressing current harmonics of the T-type three-phase three-level inverter according to claim 2, wherein, Calculating the current harmonics corresponding to the candidate vector voltages based on the current prediction models, including: Extracting the fundamental current through a low-pass filter according to the current prediction models; Calculating the current harmonics corresponding to the candidate vector voltages according to the fundamental current.

4. The method for suppressing current harmonics of the T-type three-phase three-level inverter according to claim 3, characterized in that, Calculating the weight coefficients corresponding to the candidate vector voltages based on the current harmonics, including: Setting a cost function; Performing partial derivative processing on the current harmonics based on the cost function to obtain the weight coefficients corresponding to the candidate vector voltages.

5. A current harmonic suppression device for a T-type three-phase three-level inverter, characterized in that, The device includes: A set determination module, configured to obtain the upper capacitor voltage and the lower capacitor voltage of a T-type three-phase three-level inverter, and determine a target control set according to the relationship between the upper capacitor voltage and the lower capacitor voltage; A cost calculation module, configured to respectively construct current prediction models according to the candidate vector voltages in the target control set; calculate the current harmonics corresponding to the candidate vector voltages based on the current prediction models; calculate the weight coefficients corresponding to the candidate vector voltages based on the current harmonics; substitute the weight coefficients into a cost function to calculate the cost values corresponding to the candidate vector voltages; A target determination module, configured to take the candidate vector voltage corresponding to the minimum cost value as the target vector voltage.

6. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method for suppressing current harmonics of a T-type three-phase three-level inverter according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, A computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, it implements the method for suppressing current harmonics of a T-type three-phase three-level inverter according to any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method for suppressing current harmonics of a T-type three-phase three-level inverter according to any one of claims 1 to 4.

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