Grid protection circuit

Abstract

The invention discloses a grid protection circuit. The protection circuit comprises a capacitor protection unit, a voltage comparison unit, a voltage setting unit, a positive power supply VDD and a negative power supply VSS. The output end of the voltage setting unit is connected with the first input end of the voltage comparison unit; the second input end of the voltage comparison unit is connected with the output end of the gate drive circuit, and the output end of the voltage comparison unit is connected with the control end of the capacitor protection unit; the input end of the capacitor protection unit is connected with the output end of the gate drive circuit, and the output end of the capacitor protection unit is connected with the gate of the gallium nitride power device GANHEMT; and the positive power supply VDD and the negative power supply VSS supply power to the capacitor protection unit, the voltage comparison unit and the voltage setting unit. The circuit effectively solves the problem of grid oscillation of the gallium nitride power device GANHEMT.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and more particularly to a gate protection circuit. Background Art

[0002] Nowadays, due to the increasing power density of various switching power supplies, it is necessary to continuously increase the switching frequency of the switching power supply in order to further reduce the size of the inductor and other filter components in the switching power supply. Under today's high switching frequency conditions, silicon-based power MOSFETs have gradually reached their theoretical limits, and their switching performance has reached a bottleneck. Gallium nitride (GaN) is called a wide bandgap semiconductor because of the relatively large bonding energy of the atomic components in its crystal structure. The stronger chemical bonds also lead to higher voltage resistance of gallium nitride devices than silicon-based devices. At the same time, the on-resistance of gallium nitride devices is also smaller. Therefore, gallium nitride devices are increasingly used in the field of switching power supplies. However, the increasing switching frequency and faster switching speed make the gate voltage oscillation and interference of gallium nitride power devices very serious, and the gate voltage resistance of most gallium nitride power devices GAN_HEMT is only 6 to 7V. Therefore, the gallium nitride power device GAN_HEMT needs to be connected to a gate protection circuit to ensure the normal operation of the switch.

[0003] Traditional gate protection circuits generally connect Zener diodes or Schottky diodes to the gate of power devices. These passive devices turn on when the gate voltage exceeds the set value, absorb excess energy, and stabilize the gate voltage. However, these methods have limited effects and cannot fundamentally solve the problem of gate voltage oscillation.

[0004] The prior art discloses a driving control circuit, method, device, and medium of a gallium nitride transistor, wherein an ADriver pin and an electronic switch are added to the existing flyback power supply circuit, wherein the first end of the electronic switch is connected to the ADriver pin, the second end is connected between the driving resistor and the gallium nitride transistor, and the third end is connected between the current detection resistor and the CS pin. The control circuit does not protect the gate. Summary of the invention

[0005] The present invention aims at the defect of the switch gate voltage oscillation at the moment of turning on and off of the gallium nitride power device GAN_HEMT in the prior art, and provides a gate protection circuit. The circuit effectively solves the gate oscillation problem of the gallium nitride power device GAN_HEMT.

[0006] The primary purpose of the present invention is to solve the above technical problems. The technical solution of the present invention is as follows:

[0007] A gate protection circuit is connected to a gate driving circuit and a gate of a gallium nitride power device GAN_HEMT, comprising: a capacitor protection unit, a voltage comparison unit, a voltage setting unit, a positive power supply VDD, and a negative power supply VSS;

[0008] The output terminal of the voltage setting unit is connected to the first input terminal of the voltage comparison unit;

[0009] The second input terminal of the voltage comparison unit is connected to the output terminal of the gate driving circuit, and the output terminal of the voltage comparison unit is connected to the control terminal of the capacitor protection unit;

[0010] The input end of the capacitor protection unit is connected to the output end of the gate driving circuit, and the output end of the capacitor protection unit is connected to the gate of the gallium nitride power device GAN_HEMT;

[0011] The positive power supply VDD and the negative power supply VSS are used to supply power to the capacitor protection unit, the voltage comparison unit and the voltage setting unit.

[0012] Further, the capacitor protection unit includes: a first transistor Q1, a second transistor Q2, a first capacitor C1, and a second capacitor C2;

[0013] One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, the source of the gallium nitride power device GAN_HEMT, and the first output end of the gate driving circuit; the other end of the first capacitor C1 is respectively connected to the drain of the first transistor Q1 and the positive output end of the positive power supply VDD; the other end of the second capacitor C2 is connected to the drain of the second transistor Q2 and the negative output end of the negative power supply VSS; the source of the first transistor Q1 is connected to the gate of the gallium nitride power device GAN_HEMT, the source of the second transistor Q2, and the second output end of the gate driving circuit; the first output end of the voltage comparison unit is connected to the gate of the first transistor Q1; and the second output end of the voltage comparison unit is connected to the gate of the second transistor Q2.

[0014] Furthermore, the capacitor protection unit further includes: a first resistor R1 and a second resistor R2;

[0015] The other end of the first resistor R1 is connected to the positive output end of the positive power supply VDD, and the other end of the second resistor R2 is connected to the negative output end of the negative power supply VSS; one end of the first resistor R1 is connected to the other end of the first capacitor C1, and one end of the second resistor R2 is connected to the other end of the second capacitor C2.

[0016] Further, the voltage comparison unit includes a second comparator U2, a third comparator U3, an AND gate U4, and an OR gate U5;

[0017] The output end of the second comparator U2 is connected to the first input end of the AND gate U4, the output end of the third comparator U3 is connected to the first input end of the OR gate U5, the second input end of the AND gate U4 inputs the PWM input signal, the second input end of the OR gate U5 inputs the PWM input signal, the output end of the AND gate U4 is connected to the gate of the first transistor Q1, the output end of the OR gate U5 is connected to the gate of the second transistor Q2, the second output end of the gate drive circuit is respectively connected to the positive input end of the second comparator U2 and the positive input end of the third comparator U3, the negative input end of the second comparator U2 is connected to the first output end of the voltage setting unit, and the negative input end of the third comparator U3 is connected to the second output end of the voltage setting unit.

[0018] Further, the voltage setting unit includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0019] One end of the third resistor R3 is connected to one end of the fourth resistor R4 and the negative input end of the second comparator U2, one end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the negative input end of the third comparator U3, the other end of the third resistor R3 is connected to the positive output end of the positive power supply VDD, the other end of the sixth resistor R6 is connected to the positive output end of the positive power supply VDD, the other end of the fourth resistor R4 is connected to the negative output end of the negative power supply VSS, and the other end of the fifth resistor R5 is connected to the negative output end of the negative power supply VSS.

[0020] Further, the gate drive circuit includes: a gate driver U1, a gate parasitic inductance LG, and a gate drive resistor RG;

[0021] The input end of the gate driver U1 inputs a PWM input signal, the positive power supply end of the gate driver U1 is connected to the positive output end of the positive power supply VDD, the negative power supply end of the gate driver U1 is connected to the negative output end of the negative power supply VSS, the output end of the gate driver U1 is connected to one end of the gate drive resistor RG, the other end of the gate drive resistor RG is connected to one end of the gate parasitic inductance LG, the other end of the gate parasitic inductance LG is connected to the gate of the gallium nitride power device GAN_HEMT, and the negative output end of the positive power supply VDD is connected to the positive output end of the negative power supply VSS and the source of the gallium nitride power device GAN_HEMT.

[0022] Furthermore, the capacitance of the capacitor C1 and / or the capacitor C2 is greater than ten times the capacitance of the input capacitance of the gallium nitride power device GAN_HEMT.

[0023] Furthermore, the first transistor Q1 is an N-channel transistor, and the second transistor Q2 is a P-channel transistor.

[0024] A gate protection method, a turn-on process of a gallium nitride power device GAN_HEMT includes:

[0025] The PWM input signal changes from a low level to a high level, and the output of the OR gate U5 changes synchronously to a high level, and the second transistor Q2 is turned off; the gate drive circuit outputs a high level, the gate capacitance of the GaN power device GAN_HEMT is charged, and the gate voltage rises; until the gate voltage of the GaN power device GAN_HEMT is higher than the negative input voltage of the second comparator U2, the second comparator U2 outputs a high level, the AND gate U4 outputs a high level, and the first transistor Q1 is turned on; the first capacitor C1 is connected to the gate of the GaN power device GAN_HEMT.

[0026] The shutdown process of the GaN power device GAN_HEMT includes:

[0027] The PWM input signal changes from a high level to a low level, and changes to a low level synchronously with the output of the gate U4, and the first transistor Q1 is turned off; the gate drive circuit outputs a low level, the gate capacitance of the gallium nitride power device GAN_HEMT is discharged, and the gate voltage begins to decrease; until the gate voltage of the gallium nitride power device GAN_HEMT is lower than the negative input voltage of the third comparator U3, the third comparator U3 outputs a low level, or the gate U5 outputs a low level, and the second transistor Q2 is turned on; the second capacitor C2 is connected to the gate of the gallium nitride power device GAN_HEMT.

[0028] A charging method for a gallium nitride power device comprises the gate protection method.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides a capacitor protection unit, a voltage comparison unit, and a voltage setting unit, so that the gallium nitride power device GAN_HEMT can be connected to a large capacitor at specific stages of turning on and off, thereby effectively solving the gate oscillation problem of the gallium nitride power device GAN_HEMT. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a structural diagram of a gate protection circuit provided in Example 1.

[0032] Figure 2 A circuit diagram of a gate protection circuit provided in Example 1.

[0033] Figure 3 A schematic circuit diagram of the principle of a gate protection circuit provided in Example 1. DETAILED DESCRIPTION

[0034] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0035] In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0036] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0037] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0038] Example 1

[0039] like Figure 1 , Figure 2 As shown, a gate protection circuit is connected to the gate driving circuit and the gate of the gallium nitride power device GAN_HEMT, including: a capacitor protection unit, a voltage comparison unit, a voltage setting unit, a positive power supply VDD, and a negative power supply VSS;

[0040] The output terminal of the voltage setting unit is connected to the first input terminal of the voltage comparison unit;

[0041] The second input terminal of the voltage comparison unit is connected to the output terminal of the gate driving circuit, and the output terminal of the voltage comparison unit is connected to the control terminal of the capacitor protection unit;

[0042] The input end of the capacitor protection unit is connected to the output end of the gate driving circuit, and the output end of the capacitor protection unit is connected to the gate of the gallium nitride power device GAN_HEMT;

[0043] The positive power supply VDD and the negative power supply VSS are used to supply power to the capacitor protection unit, the voltage comparison unit and the voltage setting unit.

[0044] Further, the capacitor protection unit includes: a first transistor Q1, a second transistor Q2, a first capacitor C1, and a second capacitor C2;

[0045] One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, the source of the gallium nitride power device GAN_HEMT, and the first output end of the gate driving circuit; the other end of the first capacitor C1 is respectively connected to the drain of the first transistor Q1 and the positive output end of the positive power supply VDD; the other end of the second capacitor C2 is connected to the drain of the second transistor Q2 and the negative output end of the negative power supply VSS; the source of the first transistor Q1 is connected to the gate of the gallium nitride power device GAN_HEMT, the source of the second transistor Q2, and the second output end of the gate driving circuit; the first output end of the voltage comparison unit is connected to the gate of the first transistor Q1; and the second output end of the voltage comparison unit is connected to the gate of the second transistor Q2.

[0046] Furthermore, the capacitor protection unit further includes: a first resistor R1 and a second resistor R2;

[0047] The other end of the first resistor R1 is connected to the positive output end of the positive power supply VDD, and the other end of the second resistor R2 is connected to the negative output end of the negative power supply VSS; one end of the first resistor R1 is connected to the other end of the first capacitor C1, and one end of the second resistor R2 is connected to the other end of the second capacitor C2.

[0048] It should be noted that the first resistor R1 is used to charge the first capacitor C1 before the protection circuit operates, so that the voltage across the first capacitor C1 reaches VDD. The second resistor R2 is used to charge the second capacitor C2 before the protection circuit operates, so that the voltage across the second capacitor C2 reaches VSS.

[0049] Further, the voltage comparison unit includes a second comparator U2, a third comparator U3, an AND gate U4, and an OR gate U5;

[0050] The output end of the second comparator U2 is connected to the first input end of the AND gate U4, the output end of the third comparator U3 is connected to the first input end of the OR gate U5, the second input end of the AND gate U4 inputs the PWM input signal, the second input end of the OR gate U5 inputs the PWM input signal, the output end of the AND gate U4 is connected to the gate of the first transistor Q1, the output end of the OR gate U5 is connected to the gate of the second transistor Q2, the second output end of the gate drive circuit is respectively connected to the positive input end of the second comparator U2 and the positive input end of the third comparator U3, the negative input end of the second comparator U2 is connected to the first output end of the voltage setting unit, and the negative input end of the third comparator U3 is connected to the second output end of the voltage setting unit.

[0051] Further, the voltage setting unit includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0052] One end of the third resistor R3 is connected to one end of the fourth resistor R4 and the negative input end of the second comparator U2, one end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the negative input end of the third comparator U3, the other end of the third resistor R3 is connected to the positive output end of the positive power supply VDD, the other end of the sixth resistor R6 is connected to the positive output end of the positive power supply VDD, the other end of the fourth resistor R4 is connected to the negative output end of the negative power supply VSS, and the other end of the fifth resistor R5 is connected to the negative output end of the negative power supply VSS.

[0053] Further, the gate drive circuit includes: a gate driver U1, a gate parasitic inductance LG, and a gate drive resistor RG;

[0054] The input end of the gate driver U1 inputs a PWM input signal, the positive power supply end of the gate driver U1 is connected to the positive output end of the positive power supply VDD, the negative power supply end of the gate driver U1 is connected to the negative output end of the negative power supply VSS, the output end of the gate driver U1 is connected to one end of the gate drive resistor RG, the other end of the gate drive resistor RG is connected to one end of the gate parasitic inductance LG, the other end of the gate parasitic inductance LG is connected to the gate of the gallium nitride power device GAN_HEMT, and the negative output end of the positive power supply VDD is connected to the positive output end of the negative power supply VSS and the source of the gallium nitride power device GAN_HEMT.

[0055] It should be noted that the gate drive circuit converts the PWM input signal into the gate drive signal of the GaN power device. The gate parasitic inductance LG represents the sum of the parasitic inductance of the gate drive circuit and the gate of the GaN power device. The gate protection circuit operates according to the PWM input signal and the gate voltage to protect the GaN power device, thereby effectively reducing the overshoot and oscillation of the gate voltage of the GaN power device.

[0056] The AND gate U4 includes a gate driving output stage, which can control the switching of the first transistor Q1. The OR gate U5 includes a gate driving output stage, which can control the switching of the second transistor Q2.

[0057] Furthermore, the capacitance of the capacitor C1 and / or the capacitor C2 is greater than ten times the capacitance of the input capacitance of the gallium nitride power device GAN_HEMT.

[0058] Furthermore, the first transistor Q1 is an N-channel transistor, and the second transistor Q2 is a P-channel transistor.

[0059] A gate protection method, a turn-on process of a gallium nitride power device GAN_HEMT includes:

[0060] The PWM input signal changes from a low level to a high level, and the output of the OR gate U5 changes synchronously to a high level, and the second transistor Q2 is turned off; the gate drive circuit outputs a high level, the gate capacitance of the GaN power device GAN_HEMT is charged, and the gate voltage rises; until the gate voltage of the GaN power device GAN_HEMT is higher than the negative input voltage of the second comparator U2, the second comparator U2 outputs a high level, the AND gate U4 outputs a high level, and the first transistor Q1 is turned on; the first capacitor C1 is connected to the gate of the GaN power device GAN_HEMT.

[0061] The shutdown process of the GaN power device GAN_HEMT includes:

[0062] The PWM input signal changes from a high level to a low level, and changes to a low level synchronously with the output of the gate U4, and the first transistor Q1 is turned off; the gate drive circuit outputs a low level, the gate capacitance of the gallium nitride power device GAN_HEMT is discharged, and the gate voltage begins to decrease; until the gate voltage of the gallium nitride power device GAN_HEMT is lower than the negative input voltage of the third comparator U3, the third comparator U3 outputs a low level, or the gate U5 outputs a low level, and the second transistor Q2 is turned on; the second capacitor C2 is connected to the gate of the gallium nitride power device GAN_HEMT.

[0063] A charging method for a gallium nitride power device comprises the gate protection method.

[0064] For the traditional power device gate drive circuit, its drive circuit can be simplified to a series RLC circuit, such as Figure 3 As shown, R represents the gate resistance in the driving circuit, L represents the parasitic inductance of the driving circuit, and C represents the gate capacitance of the power device.

[0065] Therefore, the transfer function of the drive loop can be expressed as

[0066]

[0067] The two extreme points of H(s) are

[0068]

[0069] There are three situations for the positions of the two poles:

[0070] (1) When Right now When 1,2 is an unequal negative real number, and the circuit is in an overdamped state;

[0071] (2) When Right now When 1,2 are equal negative real numbers, and the circuit is in a critical damping state; (3) Right now When 1,2 is a conjugate complex number, and the circuit is underdamped at this time;

[0072] When the loop is in an underdamped state, the loop will oscillate during the switching transient. To address this problem, the general practice in the industry is to increase the gate resistance R to transform the loop into a critical damped state or an overdamped state to suppress the switching oscillation. Although this method can effectively solve the problem of switching oscillation, it also leads to a decrease in the switching speed of the power device and increases the power loss, which is not conducive to further improving the performance of the circuit.

[0073] To address this problem, the present invention proposes a novel gate protection circuit and method, which connects a large-capacity capacitor in parallel between the gate and source of the power device in a specific stage of the power device switching transient, thereby transforming the drive circuit into an over-damped state, effectively suppressing the oscillation of the gate voltage without reducing the switching speed of the power device, thereby fundamentally solving this problem.

[0074] The same or similar reference numerals correspond to the same or similar components;

[0075] The terms used in the drawings to describe positional relationships are only used for illustrative purposes and should not be construed as limiting this patent;

[0076] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A gate protection circuit, characterized in that: Connecting the gate drive circuit and the gate of the GaN power device GAN_HEMT, including: a capacitor protection unit, a voltage comparison unit, a voltage setting unit, a positive power supply VDD, and a negative power supply VSS; The output terminal of the voltage setting unit is connected to the first input terminal of the voltage comparison unit; The second input terminal of the voltage comparison unit is connected to the output terminal of the gate driving circuit, and the output terminal of the voltage comparison unit is connected to the control terminal of the capacitor protection unit; The input end of the capacitor protection unit is connected to the output end of the gate driving circuit, and the output end of the capacitor protection unit is connected to the gate of the gallium nitride power device GAN_HEMT; The positive power supply VDD and the negative power supply VSS are used to supply power to the capacitor protection unit, the voltage comparison unit and the voltage setting unit.

2. A gate protection circuit according to claim 1, characterized in that: The capacitor protection unit includes: a first transistor Q1, a second transistor Q2, a first capacitor C1, and a second capacitor C2; One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, the source of the gallium nitride power device GAN_HEMT, and the first output end of the gate driving circuit; the other end of the first capacitor C1 is respectively connected to the drain of the first transistor Q1 and the positive output end of the positive power supply VDD; the other end of the second capacitor C2 is connected to the drain of the second transistor Q2 and the negative output end of the negative power supply VSS; the source of the first transistor Q1 is connected to the gate of the gallium nitride power device GAN_HEMT, the source of the second transistor Q2, and the second output end of the gate driving circuit; the first output end of the voltage comparison unit is connected to the gate of the first transistor Q1; and the second output end of the voltage comparison unit is connected to the gate of the second transistor Q2.

3. A gate protection circuit according to claim 2, characterized in that: The capacitor protection unit further includes: a first resistor R1 and a second resistor R2; The other end of the first resistor R1 is connected to the positive output end of the positive power supply VDD, and the other end of the second resistor R2 is connected to the negative output end of the negative power supply VSS; one end of the first resistor R1 is connected to the other end of the first capacitor C1, and one end of the second resistor R2 is connected to the other end of the second capacitor C2.

4. A gate protection circuit according to claim 2, characterized in that: The voltage comparison unit includes a second comparator U2, a third comparator U3, an AND gate U4, and an OR gate U5; The output end of the second comparator U2 is connected to the first input end of the AND gate U4, the output end of the third comparator U3 is connected to the first input end of the OR gate U5, the second input end of the AND gate U4 inputs the PWM input signal, the second input end of the OR gate U5 inputs the PWM input signal, the output end of the AND gate U4 is connected to the gate of the first transistor Q1, the output end of the OR gate U5 is connected to the gate of the second transistor Q2, the second output end of the gate drive circuit is respectively connected to the positive input end of the second comparator U2 and the positive input end of the third comparator U3, the negative input end of the second comparator U2 is connected to the first output end of the voltage setting unit, and the negative input end of the third comparator U3 is connected to the second output end of the voltage setting unit.

5. A gate protection circuit according to claim 4, characterized in that: The voltage setting unit includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; One end of the third resistor R3 is connected to one end of the fourth resistor R4 and the negative input end of the second comparator U2, one end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the negative input end of the third comparator U3, the other end of the third resistor R3 is connected to the positive output end of the positive power supply VDD, the other end of the sixth resistor R6 is connected to the positive output end of the positive power supply VDD, the other end of the fourth resistor R4 is connected to the negative output end of the negative power supply VSS, and the other end of the fifth resistor R5 is connected to the negative output end of the negative power supply VSS.

6. A gate protection circuit according to claim 5, characterized in that: The gate drive circuit includes: a gate driver U1, a gate parasitic inductance LG, and a gate drive resistor RG; The input end of the gate driver U1 inputs a PWM input signal, the positive power supply end of the gate driver U1 is connected to the positive output end of the positive power supply VDD, the negative power supply end of the gate driver U1 is connected to the negative output end of the negative power supply VSS, the output end of the gate driver U1 is connected to one end of the gate drive resistor RG, the other end of the gate drive resistor RG is connected to one end of the gate parasitic inductance LG, the other end of the gate parasitic inductance LG is connected to the gate of the gallium nitride power device GAN_HEMT, and the negative output end of the positive power supply VDD is connected to the positive output end of the negative power supply VSS and the source of the gallium nitride power device GAN_HEMT.

7. A gate protection circuit according to any one of claims 2 to 6, characterized in that: The capacitance of the capacitor C1 and / or the capacitor C2 is ten times greater than the input capacitance of the gallium nitride power device GAN_HEMT.

8. A gate protection circuit according to any one of claims 2 to 6, characterized in that: The first transistor Q1 is an N-channel transistor, and the second transistor Q2 is a P-channel transistor.

9. A gate protection method, applied to the protection circuit according to any one of claims 1 to 8, characterized in that: The turn-on process of the GaN power device GAN_HEMT includes: The PWM input signal changes from a low level to a high level, and the output of the OR gate U5 changes synchronously to a high level, and the second transistor Q2 is turned off; the gate drive circuit outputs a high level, the gate capacitance of the GaN power device GAN_HEMT is charged, and the gate voltage rises; until the gate voltage of the GaN power device GAN_HEMT is higher than the negative input voltage of the second comparator U2, the second comparator U2 outputs a high level, the AND gate U4 outputs a high level, and the first transistor Q1 is turned on; the first capacitor C1 is connected to the gate of the GaN power device GAN_HEMT. The shutdown process of the GaN power device GAN_HEMT includes: The PWM input signal changes from a high level to a low level, and changes to a low level synchronously with the output of the gate U4, and the first transistor Q1 is turned off; the gate drive circuit outputs a low level, the gate capacitance of the gallium nitride power device GAN_HEMT is discharged, and the gate voltage begins to decrease; until the gate voltage of the gallium nitride power device GAN_HEMT is lower than the negative input voltage of the third comparator U3, the third comparator U3 outputs a low level, or the gate U5 outputs a low level, and the second transistor Q2 is turned on; the second capacitor C2 is connected to the gate of the gallium nitride power device GAN_HEMT.

10. A method for charging a gallium nitride power device, characterized in that: Including the gate protection method as described in claim 9.

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