Bootstrap recharging system in dual-switch flyback converter

Abstract

The embodiment of the invention relates to a bootstrap recharging system in a dual-switch flyback converter. According to one embodiment, a converter includes a bootstrap capacitor, a high side switch, a low side switch, an auxiliary switch, and a controller. The bootstrap capacitor has a first terminal coupled with the floating ground node. The high side switch has a source terminal coupled to the bootstrap capacitor via a floating node. The auxiliary switch has a drain terminal coupled to the bootstrap capacitor via a floating node. The controller provides a first control signal to the control terminal of the high-side switch, provides a second control signal to the control terminal of the low-side switch, and provides a third control signal to the control terminal of the auxiliary switch. The third control signal is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high side switch and the low side switch, respectively.

Description

Technical Field

[0001] The present disclosure relates generally to circuits and, in specific embodiments, to a bootstrap recharging system in a dual-switch flyback converter. Background Art

[0002] The two-switch flyback converter is a design topology used in power electronics. However, just like any other electronic system, it struggles with specific technical challenges that need to be addressed to achieve optimal performance. One of the most prominent issues is ensuring that the bootstrap capacitor maintains sufficient charge under all operating conditions, especially to drive the high-side switch of the converter.

[0003] To initiate charging of the bootstrap capacitor, the low-side switch can be turned on for a specific duration, which is a mirroring technique used in a half-bridge configuration. By activating the low-side switch, the potential at the floating ground (FGND) node is essentially zero. This facilitates charging of the bootstrap capacitor via the low-side switch and the primary winding of the converter transformer.

[0004] When the converter is operating and switching, the recharging of the bootstrap capacitor comes into play. The presence of a large amount of energy generated by the leakage inductance of the transformer can make the potential at the floating ground (FGND) close to zero, resulting in the recharging of the bootstrap capacitor. This situation is further amplified when the recirculation diode of the converter is activated during the OFF state of the high-side switch and the low-side switch. When the high-side switch and the low-side switch are deactivated, the voltage excursion across the primary winding is equivalent to the reflected voltage (V R ) and the voltage spike due to leakage inductance (V x ) is the sum of the reflected voltage (V R ) and the voltage spike due to leakage inductance (V x ) is lower than the input voltage (V IN ), a potential challenge arises when the potential at the floating ground (FGND) node does not reach zero.

[0005] The integrity of the converter's operation depends on adequate recharging of the bootstrap capacitor. When the energy from the leakage inductance is insufficient to drive the potential at the floating ground (FGND) node close to zero, the bootstrap capacitor can no longer be charged. Over time, this eventually leads to a failure to activate the high-side switch, derailing the converter's operation. Summary of the invention

[0006] Technical advantages are generally achieved by embodiments of the present disclosure, which describes a bootstrap recharging system in a dual-switch flyback converter.

[0007] A first aspect relates to a converter, the converter comprising a bootstrap capacitor, a high-side switch, a low-side switch, an auxiliary switch and a controller. The bootstrap capacitor has a first terminal coupled to a floating node. The high-side switch has a source terminal, the source terminal is coupled to the bootstrap capacitor by means of the floating node. The auxiliary switch has a drain terminal, the drain terminal is coupled to the bootstrap capacitor by means of the floating node. The controller is configured to provide a first control signal to a control terminal of the high-side switch, a second control signal to a control terminal of the low-side switch, and a third control signal to a control terminal of the auxiliary switch. The third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively.

[0008] A second aspect relates to a method of operating a converter. The method includes: generating, by a controller, a first control signal to a control terminal of a high-side switch of the converter, the high-side switch having a source terminal coupled to a bootstrap capacitor via a floating node; generating, by the controller, a second control signal to a control terminal of a low-side switch of the converter; and determining, by the controller, whether to activate an auxiliary switch within a current cycle using a third control signal, the auxiliary switch having a drain terminal coupled to the bootstrap capacitor via a floating node. The determination is based on a condition associated with the converter after the high-side switch and the low-side switch are deactivated by the first control signal and the second control signal, respectively.

[0009] A third aspect relates to a device having a converter. The converter includes a bootstrap capacitor, a high-side switch, a low-side switch, an auxiliary switch, and a controller. The bootstrap capacitor has a first terminal coupled to a floating ground node. The high-side switch has a source terminal, and the source terminal is coupled to the bootstrap capacitor by means of the floating ground node. The auxiliary switch has a drain terminal, and the drain terminal is coupled to the bootstrap capacitor by means of the floating ground node. The controller is configured to provide a first control signal to a control terminal of the high-side switch, a second control signal to a control terminal of the low-side switch, and a third control signal to a control terminal of the auxiliary switch. The third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively.

[0010] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram of a conventional DC-DC converter;

[0013] Figure 2 is a schematic diagram of a conventional two-switch flyback converter;

[0014] Figure 3 is a collection of waveforms corresponding to example operation of a two-switch flyback converter in which the bootstrap capacitor (C BOOT ) is recharged;

[0015] Figure 4 is a collection of waveforms corresponding to example operation of a two-switch flyback converter in which the bootstrap capacitor (C BOOT ) has not been recharged;

[0016] Figure 5 is a schematic diagram of an embodiment of a dual-switch flyback converter;

[0017] Figure 6 is a flow chart of an embodiment method for operating a two-switch flyback converter;

[0018] Figure 7 is possible in a dual-switch flyback converter for Figure 6 A schematic diagram of an embodiment control logic circuit for implementing condition A of the method;

[0019] Figure 8 is possible in a dual-switch flyback converter for Figure 6 A schematic diagram of an embodiment control logic circuit for implementing condition B of the method; and

[0020] Fig. 9 is a block diagram of an embodiment system. DETAILED DESCRIPTION

[0021] The present disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments are merely illustrations of specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments may be combined to form additional embodiments. Various embodiments are illustrated in the accompanying drawings, in which the same components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0022] The changes or modifications described in one embodiment of the embodiments may also be applicable to other embodiments. In addition, various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the present disclosure defined by the appended claims.

[0023] Although aspects of the present invention are primarily described in the context of a dual-switch flyback converter, it should be understood that these inventive aspects may also be applicable to other types of power converters.

[0024] Figure 1 The schematic diagram of a conventional DC-DC converter 100 is shown. The DC-DC converter 100 includes a high-side driving circuit device 102, a high-side transistor 104, a low-side driving circuit device 106, a low-side transistor 108, a bootstrap diode 110, a bootstrap capacitor (C BOOT )114, output capacitor 116, inductor 118 and DC voltage source 120.

[0025] In the DC-DC converter 100, the control circuit device 112 drives the high-side transistor 104 and the low-side transistor 108 alternately ON and OFF via the high-side signal (HVG) and the low-side signal (LVG), respectively, to create a desired output voltage (V out The DC voltage source 120 is configured to generate a stable voltage (V cc ), stable voltage (V cc ) is provided to the bootstrap diode 110 and the low-side driver circuit device 106. In an embodiment, the regulated voltage (V cc ) is generated by a DC voltage source 120 using an auxiliary winding (not shown) coupled to a transformer, a rectifier diode (not shown) and a buffer capacitor (not shown) to obtain a substantially DC voltage.

[0026] Output capacitor 116 and inductor 118 form an LC circuit at the output of DC-DC converter 100 to produce a desired DC output voltage.

[0027] The bootstrap diode 110 and the bootstrap capacitor (C BOOT ) 114 forms a bootstrap circuit to generate a boost voltage (i.e., greater than or equal to the minimum gate-source voltage (V gs )) and the high-side transistor 104 is efficiently driven by the high-side driving circuit device 102.

[0028] Typically, the low-side transistor 108 is directly controlled using a control circuit arrangement 112 coupled to an input of the low-side driver circuit arrangement 106. However, directly controlling the high-side transistor 104 by the control circuit arrangement 112 becomes more challenging because when the high-side transistor 104 is implemented as an n-channel metal oxide semiconductor field effect transistor (MOSFET) in a buck converter, for example, the high-side transistor (Q 1 ) The source terminal of 104 is not connected to the ground reference.

[0029] During the ON state of the low-side transistor 108 (i.e., the OFF phase of the converter), the switching node (SW) is connected to ground. cc ) flows through the bootstrap diode 110, the bootstrap capacitor (C BOOT)114 is charged to a stable voltage (V cc ) and the threshold voltage of the bootstrap diode 110. The bootstrap diode 110 is forward biased and the bootstrap capacitor (C BOOT )114 is charged to a higher than stable voltage (V cc ) slightly lower voltage.

[0030] During the ON state of the high-side transistor 104 (i.e., the ON phase of the converter), the gate voltage of the high-side transistor 104 must be at least the threshold voltage higher than the source voltage level to ensure that it is fully turned on. However, since the source of the high-side transistor 104 is not connected to the ground reference, it is challenging to drive it directly from the control circuit device 112.

[0031] The bootstrap circuit functions during this ON state of the high-side transistor 104. The control circuit device 112 asserts the high-side signal (HVG), which allows the charged bootstrap capacitor (C BOOT ) 114 is applied to the control terminal of the high-side transistor 104 by means of the high-side drive circuit device 102. BOOT ) 114 is applied to the control terminal of the high-side transistor 104, so that the gate-source voltage (V gs ) is sufficient to turn on the high-side transistor 104.

[0032] Once the high-side transistor 104 is turned on, the voltage at the floating ground (FGND) node (V FGND ) is connected to the input supply (V in The cathode of the bootstrap diode 110 (bootstrap power supply) is equal to the input power supply (V in ) and the bootstrap capacitor (C BOOT )114. The bootstrap diode is reverse biased, and the bootstrap capacitor is connected to the stabilization voltage (V cc ) is disconnected. When the high-side transistor 104 is turned off, the cycle continues to repeat and the bootstrap capacitor (C BOOT ) 114 is recharged during the ON state of the low-side transistor 108.

[0033] Figure 2 FIG. 2 is a schematic diagram of a conventional dual-switch flyback converter 200. The dual-switch flyback converter 200 includes a high-side switch (Q 1 )202, low side switch (Q 2 )204, transformer 206, first diode (D 1 )208, the second diode (D 2 )210, output diode (D OUT )212, sensing resistor (R S)214, control circuit device 216, input capacitor (C IN )218, bootstrap diode 110, bootstrap capacitor (C BOOT ) 114 and a DC voltage source 120. As shown in the figure, the stable voltage (V cc ) is provided to the controller circuit device 216.

[0034] High-side switch (Q 1 )202 and the low-side switch (Q 2 Each of the transistors 204 is typically an n-channel metal oxide semiconductor field effect transistor (MOSFET). p ) and the secondary side (L S ) of the transformer 206 facilitates energy transfer from the input to the output via magnetic coupling. The high-side switch (Q 1 ) 202 is coupled to the secondary side (L S ). The low-side switch (Q 2 ) 204 is coupled to the primary side (L p ) first terminal.

[0035] High-side switch (Q 1 )202 and the low-side switch (Q 2 ) 204 are the main switches in the dual-switch flyback converter 200. Their synchronous operation (simultaneous switching on and off) manages the primary side (L P ) in which the current flows.

[0036] The first diode (D 1 )208 and the second diode (D 2 ) 210 acts as a recirculation diode, directing energy from the leakage inductance of transformer 206 back to the input capacitor (C IN ) 218. This efficient energy utilization improves the overall efficiency of the dual-switch flyback converter 200, especially in the case of significant transformer leakage. IN )218 for input voltage (V IN ) for filtering and stabilization. The output diode (D OUT )212 is used as an output rectifier diode to ensure that current flows only in the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 flows to the output when it is in the OFF state.

[0037] The sensing resistor (R S )214 is coupled to the low side switch (Q 2) 204 and is used to ensure safe operation of the dual switch flyback converter 200 and is typically used for current mode control. 2 )204 is activated, the current flowing through it also traverses the sense resistor (R S ) 214. This causes the sensing resistor (R S )214, the voltage drop across the two ends, the voltage drop and the voltage transfer through the low-side switch (Q 2 )204. By monitoring this voltage, the control circuit device 216 can accurately measure the magnitude of the inductor current in real time. This sensed voltage is combined with the feedback signal from the secondary side to allow the control circuit device 216 to control the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is modulated to ensure that the peak primary current is the current required to provide the power required by the load while regulating the output voltage at the desired value. S )214 facilitated current mode control enhances the performance of the dual-switch flyback converter 200 by providing fast response to load and line variations, improving transient behavior, and ensuring safer operation by preventing potential over-current scenarios.

[0038] The control circuit device 216 includes an input terminal coupled to the output of the bootstrap diode 110 and is configured to drive the high-side switch (Q) using the high-side gate control signal (HVG). 1 )202. High-side switch (Q 1 )202 operation is based on the use of bootstrap diode 110 and bootstrap capacitor (C BOOT ) 114 to drive the high-side transistor 104 of the DC-DC converter 100. The control circuit device 216 is configured to drive the low-side switch (Q) using the low-side gate control signal (LVG). 2 )204.

[0039] In operation, when the high-side switch (Q 1 )202 and the low-side switch (Q 2 ) 204 is in the active state (ie, ON state), energy is transferred to the primary side (L P ) is accumulated in the winding. At this time, the output diode (D OUT )212 remains inactive, preventing any energy from being transferred to the output side. When the high-side switch (Q 1 )202 and the low-side switch (Q 2 ) 204 is deactivated (ie, OFF state), the operation is offset. The primary side (L P) is moved to the secondary side (L S ), the output diode (D OUT )212 activates and drives energy to the output.

[0040] Due to the non-ideal characteristics of transformer 206, since the primary winding (L P ) are all magnetic fields generated by the secondary winding (L S ) coupling, so leakage inductance is generated. Instead, some of this field is "leaked" to the outside, which can be connected to the primary side (L P ) is illustrated by a decoupling inductor in series with the winding of the flyback converter. Leakage inductance can present challenges in the operation of a flyback converter, especially during the turn-off phase.

[0041] The dual-switch flyback converter 200 is a modification of a standard flyback converter. In a standard flyback converter with a single switch, when the switch turns off, the energy stored in the leakage inductance has nowhere to go, resulting in voltage spikes. These spikes can exceed the voltage ratings of the components, potentially damaging them. To address this problem, a resistor (often referred to as a "snubber resistor") in a resistor-diode-capacitor (RDC) clamp circuit provides a safe path for the energy stored in the leakage inductance to dissipate, thereby protecting the circuit components from potentially harmful voltage spikes. By connecting the RDC clamp on the primary side (L P ) across the winding, when the switch is turned off, the energy stored in the leakage inductance can be "burned" or dissipated as heat in the snubber resistor.

[0042] However, while this method effectively clamps the voltage spike and protects the circuit, it is not the most efficient solution because the energy in the leakage inductance is not reused but simply wasted as heat. This results in an increase in thermal load and reduces the overall efficiency of the standard flyback converter.

[0043] In the dual-switch flyback converter 200, instead of using a resistor-diode-capacitor (RDC) clamp circuit to dissipate the excess energy as heat, a resistor-diode-capacitor (RDC) clamp circuit is used to dissipate the excess energy in the high-side switch (Q 1 )202 and the low-side switch (Q 2 The additional energy during the deactivated state of )204 is stored in the input capacitor (C IN )218. In the high side switch (Q 1 )202 and the low-side switch (Q 2 During the OFF state of )204, the additional voltage across the leakage inductance usually exceeds the input voltage (V IN ), so that the first diode (D 1 )208 and the second diode (D 2)210 becomes forward biased. This causes the energy stored in the leakage inductance to be transferred to the input capacitor (C IN ) 218. During different cycles of the dual-switch flyback converter 200, the input capacitor (C IN )218 charging and discharging improves efficiency by avoiding the energy wasted as heat in a standard flyback converter with a single switch.

[0044] In addition, compared with a single-switch flyback converter design, the high-side switch (Q 1 )202 and the low-side switch (Q 2 ) 204 effectively splits the voltage swing across the two-switch flyback converter 200 into two halves. In the dual-switch flyback converter 200, the capacitive switch loss (i.e., equal to CV 2 ) is minimized.

[0045] As mentioned above, the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 deactivates, the primary side (L P ) is equivalent to the reflected voltage (V R ) and the voltage spike due to leakage inductance (V x ). Therefore, if the combined value is lower than the input voltage (V IN ), then the voltage at the floating ground (FGND) node (V FGND ) cannot reach zero. When the energy from the leakage inductance is insufficient to raise the voltage (V FGND ) is driven close to zero, the bootstrap capacitor (C BOOT )114 cannot be charged. In some cycles, this results in the failure to activate the high-side switch (Q 1 )202, thereby interrupting the operation of the dual-switch flyback converter 200.

[0046] Figure 3 A set of waveforms 300 are illustrated, corresponding to an example operation of the dual-switch flyback converter 200, wherein the bootstrap capacitor (C BOOT ) 114 is recharged. Waveform 300 includes a high-side gating signal 302, a high-side switch (Q 1 ) 202 source voltage 304, and the bootstrap capacitor (C BOOT )The charging voltage 306 at 114.

[0047] The high-side enable signal 302 drives the high-side switch (Q 1 )202. In an embodiment, when the high-side switch (Q 1 )202 is in the ON state, the high-side enable signal 302 is in the logic level high, and when the high-side switch (Q 1)202 is in the OFF state, the high-side selection signal 302 is in a logic level low.

[0048] At time t 0 At , the high-side enable signal 302 switches from a logic low level to a logic high level. 1 )202 is activated (it is worth noting that at the same time, the low-side switch Q 2 is also turned on). The bootstrap capacitor (C BOOT ) The charging voltage 306 at 114 at time t 0 The value at the bootstrap capacitor (C BOOT )114 The charge from the bootstrap capacitor (C BOOT )114 is passed to the high-side switch (Q 1 )202 gate capacitance, so the bootstrap capacitor (C BOOT )114 is slightly discharged to drive the high-side switch (Q 1 )202.

[0049] At time t 1 At , the high-side enable signal 302 switches from a logic level high to a logic level low. 1 )202 is deactivated. The bootstrap capacitor (C BOOT ) The charging voltage 306 at 114 at time t 1 This is because when the high-side switch (Q 1 )202 is turned off, there is enough energy to make the voltage at the floating ground (FGND) node (V FGND ) becomes zero so that the bootstrap capacitor (C BOOT )114Recharge.

[0050] Figure 4 A set of waveforms 400 are illustrated, corresponding to an example operation of the dual-switch flyback converter 200, wherein the bootstrap capacitor (CBOOT) 114 is not recharged. The waveforms 400 include a high-side enable signal 402, a source voltage 404 of the high-side switch (Q1) 202, and a charge voltage 406 at the bootstrap capacitor (CBOOT) 114.

[0051] The high-side enable signal 402 drives the high-side switch (Q 1 )202. In an embodiment, when the high-side switch (Q 1 )202 is in the ON state, the high-side selection signal 402 is in the logic level high, and when the high-side switch (Q 1 )202 is in the OFF state, the high-side selection signal 402 is in a logic level low.

[0052] At time t 0At , the high-side enable signal 402 switches from a logic low level to a logic high level. 1 )202 is activated. Similarly, because the bootstrap capacitor (C BOOT ) of the charge from the bootstrap capacitor (C BOOT )114 is passed to the high-side switch (Q 1 )202 gate capacitance, so the bootstrap capacitor (C BOOT )114 is slightly discharged to drive the high-side switch (Q 1 )202.

[0053] At time t 1 At , the high-side enable signal 302 switches from a logic level high to a logic level low. 1 )202 is deactivated. With the bootstrap capacitor (C BOOT )114, the charging voltage 306 is opposite, the bootstrap capacitor (C BOOT )114 does not increase. This is because the high-side switch (Q 1 )202 source voltage 404 and the high-side switch (Q 1 )202 has a source voltage 304 that does not reach zero. Therefore, the bootstrap capacitor (C BOOT )114 will be discharged cycle by cycle until it is 0 The high-side switch (Q 1 )202 Unable to connect.

[0054] Conventional solutions to this problem include (i) using an auxiliary transformer winding, and (ii) using a drive transformer instead of a bootstrap topology. In the first case, a bootstrap capacitor (C BOOT )114, but the auxiliary winding is coupled to the primary side (L P ) winding. When the low-side switch (Q 2 )204 is turned on, the voltage across the auxiliary winding is positive, which allows the bootstrap capacitor (C BOOT )114 for recharging. While the auxiliary winding technique provides some benefits, it also presents multiple challenges. On the plus side, not having a drive transformer may simplify the design. However, the first approach results in higher power dissipation, which may result in system inefficiency. In addition, the first conventional solution exhibits poor standby performance. The complexity of the transformer in this setup is higher, which may complicate the design process and may affect reliability. Finally, the design found that managing a wider output voltage range (V OUT ) is challenging, and a wide output voltage range may limit its application to meet modern power requirements, such as Universal Serial Bus (USB) Power Delivery (PD) requirements.

[0055] In the second solution, a drive transformer is used with a standard flyback controller, with a winding connected to its gate drive output, and a winding is added to the gate side of each of the high-side and low-side switches, plus a small number of passive components required for correct operation. On the positive side, this approach has low power consumption, making the system more energy efficient. The standby performance of this setup is also improved compared to the first solution, ensuring that the system remains reliable even in idle or low-load conditions. However, while adding a drive transformer provides these advantages, it also means increasing the number of components, which can complicate assembly and maintenance.

[0056] Figure 5 1 is a schematic diagram of an embodiment of a dual-switch flyback converter 500. The dual-switch flyback converter 500 includes a high-side switch (Q) that may (or may not) be arranged as shown. 1 )202, low side switch (Q 2 )204, transformer 206, auxiliary switch (Q 3 )502, the second diode (D 2 )210, output diode (D OUT )212, sensing resistor (R S )214, control circuit device 216, input capacitor (C IN )218, bootstrap diode 110, bootstrap capacitor (C BOOT ) 114 and a DC voltage source 120. The dual-switch flyback converter 500 may include additional components not shown, such as a high-side switch (Q 1 )202, low side switch (Q 2 )204 and auxiliary switch (Q 3 )502 of each of the gate drive circuit devices.

[0057] In the dual-switch flyback converter 500, the first diode (D 1 )208 Use auxiliary switch (Q 3 )502 to replace. The high-side switch (Q 1 )202 and auxiliary switch (Q 3 ) 502 forms a half-bridge structure 504. The half-bridge structure 504 ensures that the bootstrap capacitor (C BOOT )114 is recharged.

[0058] Auxiliary switch (Q 3 ) 502 has a source terminal coupled to the reference ground. The auxiliary switch (Q 3 ) 502 is coupled to the control terminal (AUXG) of the controller circuit device 216. The auxiliary switch (Q 3) 502 has a drain terminal coupled to a floating ground (FGND) node. In an embodiment, the auxiliary switch (Q 3 )502 is an n-channel MOSFET.

[0059] In an embodiment, the controller circuit device 216 is configured to activate (ie, turn on) the auxiliary switch (Q) for a short duration. 3 )502, while the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is turned off. In the embodiment, the auxiliary switch (Q 3 )502 is in the OFF state for a period of time, the auxiliary switch (Q 3 ) 502 acts as a first diode (D 1 ) similar to the recycling diode.

[0060] Advantageously, this allows the bootstrap capacitor (C BOOT ) 114 is recharged. In addition, compared with conventional solutions, this solution does not require a drive transformer, thereby reducing component count and cost.

[0061] In an embodiment, the control circuit device 216 is configured to control the circuit parameters (e.g., parasitic capacitance, reverse voltage (V R ), leakage inductance, etc.) and the load condition of the converter to adjust the auxiliary switch (Q 3 )502 activation and deactivation, because the auxiliary switch (Q 3 )A fixed delay for activation of 502 is not feasible.

[0062] In an embodiment, the auxiliary switch (Q 3 )502 is activated immediately after the high-side switch (Q 1 )202 and the low-side switch (Q 2 ) 204 after deactivation. However, it should be understood that the auxiliary switch (Q 3 )502 can be activated by the high-side switch (Q 1 )202 and the low-side switch (Q 2 )Occurs at any time after deactivation of 204.

[0063] Figure 6 A flow chart of an embodiment method 600 for operating a dual-switch flyback converter 500 is illustrated. Note that all steps outlined in the flow chart are not necessarily required and may be optional. In addition, changes to the arrangement of steps, deletion of one or more steps and path connections, and addition of steps and path connections are similarly contemplated.

[0064] At step 602, the operation cycle of the dual switch flyback converter 500 begins. At step 604, one or more conditions are checked. The first condition (condition A) corresponds to monitoring the bootstrap capacitor (C BOOT ) The second condition (condition B) corresponds to monitoring the voltage at the floating ground (FGND) node (V FGND ).

[0065] When operating based on condition A, in response to detecting the bootstrap capacitor (C BOOT ) The voltage across 114 is greater than the first threshold voltage (V TH1 ), auxiliary switch (Q 3 )502 remains OFF during the operation cycle. This can be expressed as: Keep OFF, where V BST is the voltage across the bootstrap capacitor.

[0066] In contrast, when operating based on condition A, in response to detecting the bootstrap capacitor (C BOOT ) The voltage across 114 is less than the first threshold voltage (V TH1 ), auxiliary switch (Q 3 )502 is turned on for τ seconds in the operating cycle. This can be expressed as: In an embodiment, τ is equal to 200 ns.

[0067] When operating based on condition B, in response to detecting the voltage (V FGND ) in the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is turned off after τ 2 τ in seconds 1 seconds is greater than the second threshold (VTH2), the auxiliary switch (Q 3 )502 is turned on within the operating cycle. This can be expressed as: On, where V FGND is in τ 2 τ in seconds 1 The voltage at the floating ground (FGND) within seconds. In the embodiment, τ 1 Equal to 100 nanoseconds (ns). In an embodiment, τ2 is equal to 300 ns.

[0068] In contrast, when operating based on condition B, in response to detecting the voltage (V FGND ) in the high-side switch (Q 1 )202 and the low-side switch (Q 2)204 is turned off after τ 2 τ in seconds 1 is less than the second threshold (VTH2) within seconds, the auxiliary switch (Q 3 )502 remains OFF during the operation cycle. This can be expressed as: Keep OFF.

[0069] In an embodiment, the first threshold voltage (V TH1 ) and the second threshold voltage (V TH2 ) is predetermined and stored in a memory in the host device coupled to the controller circuit device 216. In an embodiment, the first threshold voltage (V TH1 ) and the second threshold voltage (V TH2 ) is determined based on load and component variation conditions using machine learning techniques. In an embodiment, the first threshold voltage (V TH1 ) is set to 8 volts. In an embodiment, the second threshold voltage (V TH2 ) is set to 1V.

[0070] In an embodiment, the satisfaction of condition A or condition B is used to satisfy step 604. At step 606, in response to condition A or condition B not being satisfied, the auxiliary switch (Q 3 )502 is turned on for τ seconds in the operating cycle. In step 608, in response to (i) condition A or condition B being satisfied or (ii) the auxiliary switch (Q 3 )502 is turned on at step 606, the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 are turned on simultaneously. In an embodiment, the satisfaction of one of the conditions depends on the implementation used in the control IC. In an embodiment, condition A and condition B are alternative conditions.

[0071] At step 610, the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 are simultaneously deactivated. In an embodiment, when the peak inductor current reaches a value programmed by the control loop, the high-side switch (Q 1 )202 is deactivated. In an embodiment, the control loop adjusts the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 duty cycle to adjust the output voltage (V OUT In an embodiment, a current sensor is used to measure the inductor current in real time, which is fed into the control loop. Once the inductor current reaches a predetermined peak value as set by the control loop, the high-side switch (Q 1 )202 is turned off. This action turns the primary side (LP ) in the winding is terminated and the energy storage phase is initiated to the secondary side (L S Steps 604 to 610 are repeated in the next cycle.

[0072] Figure 7 FIG. 1 is a schematic diagram of an embodiment control logic circuit 700 that can be implemented for condition A of method 600 in a dual-switch flyback converter 500. The control logic circuit 700 checks condition A and switches the auxiliary switch (Q 3 )502 control terminal provides control signal (AUXG A ). In response to detecting the bootstrap capacitor (C BOOT ) The voltage across 114 is greater than the first threshold voltage (V TH1 ), auxiliary switch (Q 3 )502 remains OFF during the operation cycle. In response to detecting the bootstrap capacitor (C BOOT ) The voltage across 114 is less than the first threshold voltage (V TH1 ), auxiliary switch (Q 3 )502 is turned on for τ seconds within the operating cycle.

[0073] The control logic circuit 700 includes a comparator (COMP) 702, an adder circuit 704, a first inverter 706, a level shifter circuit 708, a flip-flop (FF) 710, a second inverter 712, an AND gate 714, a delay circuit 716, and a one-shot (MF) 718, which may or may not be arranged as shown. The control logic circuit 700 may include additional components not shown, such as a filter circuit. The input of the control logic circuit 700 is coupled to a bootstrap capacitor (C BOOT )114 terminal.

[0074] The comparator (COMP) 702 is configured to effectively compare the bootstrap capacitor (C BOOT )114 The voltage across the two ends (V BOOT ) and the first threshold voltage (V TH1 As described in method 600, a check may be performed to determine whether the auxiliary switch (Q 3 The first condition (condition A) of 502 is based on the bootstrap capacitor (C BOOT ) The voltage across 114 and the first threshold voltage (V TH1 )

[0075] The comparator (COMP) 702 is configured with hysteresis - the past state of the comparator (COMP) 702 affects its output due to the feedback connection via the adder circuit 704. The adder circuit 704 has a first threshold voltage (V TH1 ) and a second input configured to receive the comparator output. The comparator (COMP) 702 is configured to receive a first threshold voltage (V TH1 ) and the sum of the comparator output, the sum provided by the output of adder circuit 704. The inverting input of comparator (COMP) 702 is configured to receive the bootstrap capacitor (C BOOT )114 The voltage across the two ends (V BOOT ). The comparator (COMP) 702 is configured to generate an output signal based on comparing the signals at its input terminals, the output signal being fed to the input of the first inverter 706. It should be noted that in embodiments, other techniques besides adder circuits may be used to implement hysteresis.

[0076] In an embodiment, the comparator (COMP) 702 is based on a bootstrap capacitor (C BOOT ) The voltage across 114 and the first threshold voltage (V TH1 ) and provides an output signal to the first inverter 706. In response to the first threshold voltage (V TH1 ) and the comparator output is greater than the bootstrap capacitor (C BOOT ) 114, the comparator (COMP) 702 will output a logic level high (eg, "1"). In response to the first threshold voltage (V TH1 ) and the comparator output is less than the bootstrap capacitor (C BOOT ) 114, the comparator (COMP) 702 will output a logic level low (eg, “0”). The output of the comparator (COMP) 702 is inverted by means of a first inverter 706 and fed to a level shifter circuit 708.

[0077] In response to the bootstrap capacitor (C BOOT ) The voltage across 114 is greater than or equal to the first threshold voltage (V TH1 ) and the sum of the comparator output, the output of the first inverter 706 is set to a logic level high (eg, "1"). BOOT ) The voltage across 114 is less than the first threshold voltage (V TH1 ) and the summed value of the comparator output, the output of the first inverter 706 is set to a logic level low (eg, “0”).

[0078] The level shifter circuit 708 transfers the digital value at the output of the first inverter 706 from the first portion of the control logic circuit 700 (referred to as floating ground) to the second portion of the control logic circuit 700 (with reference ground). Common methods of implementing the level shifter circuit 708 include optical isolators (i.e., optocouplers), transformers, and cascade structures. Thus, the level shifter circuit 708 transfers the digital value at the output of the first inverter 706 to the reset (R) input of the flip-flop (FF) 710.

[0079] In an embodiment, the flip-flop (FF) 710 is a reset-dominated, level-sensitive, set-reset (SR) flip-flop. Since the flip-flop (FF) 710 is reset-dominated, the reset (R) input takes precedence over the set (S) input. This means that if both the set (S) input and the reset (S) input are at a high level, the flip-flop (FF) 710 will enter a "reset" state, ignoring the set (S) input. The high-side signal (HVG) is provided at the set (S) input of the flip-flop (FF) 710. Therefore, when the high-side switch (Q1) 202 is activated, the flip-flop (FF) 710 is "set".

[0080] In addition, since the flip-flop (FF) 710 is level sensitive, the flip-flop (FF) 710 reacts to the level of the input signal rather than their edge transitions. Therefore, as long as the set (S) input or the reset (R) input remains at a specific logic level (high or low), the output will maintain its corresponding state. Therefore, if the output of the first inverter 706 is set to a logic level high (e.g., "1"), the reset signal is asserted at the reset (R) input of the flip-flop (FF) 710. On the contrary, if the output of the first inverter 706 is set to a logic level low (e.g., "0"), the reset signal will not be asserted at the reset (R) input of the flip-flop (FF) 710.

[0081] When the reset (R) input is at logic level high (i.e., the bootstrap capacitor (C BOOT )114 exceeds the first threshold voltage (V TH1 )), regardless of the high-side switch (Q 1 )202 is activated or deactivated, the output (Q) of the flip-flop (FF) 710 is at a logic level low. This is because the reset (R) input dominates and will override the state of the set (S) input and force the output (Q) to be low.

[0082] When (i) the high-side switch (Q 1 ) 202 is activated and (ii) the reset (R) input is at a logic level low (i.e., the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1)), the output (Q) of flip-flop (FF) 710 is at a logic level high. This is because the reset (R) input is low and the set (S) input affects the output (Q), setting it to a high state.

[0083] If the set (S) input and the reset (R) input are at a logic level low, corresponding to the high-side switch (Q1) 202 being deactivated and the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), the output (Q) will hold its last value (high or low).

[0084] The first input of the AND gate 714 is coupled to the output (Q) of the flip-flop (FF) 710. The second inverter 712 inverts the logic signal of the high-side signal (HVG) to generate an inverted high-side signal (HVG N ), the inverted high-side signal (HVG N ) on the high side switch (Q 1 )202 is at logic level high when deactivated and at the high side switch (Q 1 )202 is at logic level low when activated.

[0085] Thus, when (i) high-side switch (Q1) 202 is deactivated and (ii) the output (Q) of flip-flop (FF) 710 is at a logic level high, the output of AND gate 714 provides a positive edge signal to the input of delay circuit 716, indicating that the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ).

[0086] Delay circuit 716 is configured to provide a fixed or programmable delay before the signal at the output of AND gate 714 is provided to the input terminal of one-shot (MF) 718. In an embodiment, delay circuit 716 is configured to provide a delay equal to approximately 100 ns.

[0087] One-shot (MF) 718 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, one-shot (MF) 718 is arranged as a positive edge triggered one-shot.

[0088] In response to the bootstrap capacitor (C BOOT )114 is less than the first threshold voltage (V TH1 ), the delayed positive edge signal (signal transitions from logic level low to logic level high) from AND gate 714 triggers one-shot (MF) 718, causing the state of one-shot (MF) 718 to change and generate a control signal (AUXG) at its output (Q) within τ seconds. A), activate the auxiliary switch (Q 3 )502.

[0089] Figure 8 FIG. 8 is a schematic diagram of an embodiment control logic circuit 800 that can be implemented for condition B of method 600 in a dual-switch flyback converter 500. The control logic circuit 800 checks condition B and switches the auxiliary switch (Q 3 )502 control terminal provides control signal (AUXG B ). In response to detecting the voltage (V FGND ) in the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is turned off after τ 2 τ in seconds 1 is greater than the second threshold (V TH2 ), auxiliary switch (Q 3 ) 502 is turned on during the operation cycle. In response to detecting the voltage (V FGND ) in the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is turned off after τ 2 τ in the period 1 Less than the second threshold (V TH2 ), auxiliary switch (Q 3 )502 remains OFF within the operating cycle.

[0090] The control logic circuit 800 includes a first resistor (R 1 )802, the second resistor (R 2 )804, comparator (COMP) 806, adding circuit 808, first single trigger (MF 1 )810, a first AND gate 812, a second AND gate 814, a second single trigger (MF 2 ) 816, an inverter 818, a flip-flop (FF) 820, a third AND gate 822 and a third single trigger (MF 3 ) 824. The control logic circuit 800 may include additional components not shown, such as filter circuits. The input of the control logic circuit 800 is coupled to a floating ground (FGND) node.

[0091] The comparator (COMP) 806 is configured to use a voltage divider (ie, including a first resistor (R 1 )802 and the second resistor (R 2 )804) to the voltage at the floating ground (FGND) node (VFGND ) and the second threshold voltage (V TH2 ) is compared. As described in method 600, it can be checked to determine whether the auxiliary switch (Q 3 The second condition (condition B) of 502 is based on the voltage (V FGND ) in the high-side switch (Q 1 )202 and the low-side switch (Q 2 )204 is turned off after τ 2 τ in seconds 1 seconds greater than the second threshold voltage (V TH2 ).

[0092] The comparator (COMP) 806 is configured with hysteresis provided by the output of the first AND gate 812. The comparator (COMP) 806 has an inverting input (-) configured to receive a voltage (V FGND ). The non-inverting input of comparator (COMP) 806 is coupled to the output of adder circuit 808.

[0093] Adder circuit 808 has a first input configured to receive a second threshold voltage (V TH2 ). A second input of the adder circuit 808 is configured to receive the output of the first AND gate 812. The comparator (COMP) 806 is configured to generate an output signal which is fed to the first one-shot (MF 1 ) 810 and a first input of a first AND gate 812. A second input of the first AND gate 812 is coupled to a first one-shot trigger (MF 1 )810 non Output.

[0094] The first single trigger (MF 1 )810 is configured to respond to being triggered, at τ 1 The first single trigger (MF) switches from a stable state to an unstable state within a few seconds, and then automatically returns to a stable state. 1 )810 is arranged as an edge-triggered (positive or negative) single trigger.

[0095] In response to the output of the comparator (COMP) 806 transitioning from a logic high level to a logic low level or from a logic low level to a logic high level, the first one-shot trigger (MF 1 )810 is triggered, resulting in a state change and with the help of the first single trigger (MF 1 )810 non Output, at τ 1A set signal is generated to the second input of the first AND gate 812 for a duration of 10 seconds.

[0096] In response to the output of the comparator (COMP) 806 and the first one-shot (MF 1 )810 non The output of the first AND gate 812 is at a logic level high, and the first AND gate 812 provides a logic level high signal to the first input of the second AND gate 814. The second input of the second AND gate 814 is controlled by the second one-shot trigger (MF 2 )The output (Q) of 816 is provided.

[0097] The second single trigger (MF 2 )816 is configured to respond to being triggered, at τ 2 The second single trigger (MF) switches from a stable state to an unstable state within a few seconds, and then automatically returns to a stable state. 2 ) 816 is arranged as a negative edge triggered single trigger. Specifically, the second single trigger (MF 2 ) 816 in response to the high-side signal (HVG) switching from a logic level high to a logic level low (i.e., the high-side switch (Q 1 )202 is deactivated), the high-side signal (HVG) is provided to the input of the second AND gate 814 as a logic high signal.

[0098] In response to the high-side signal (HVG) transitioning from a logic level high to a logic level low and the output of the first AND gate 812 being at a logic level high, the second AND gate 814 provides a reset signal to a reset (R) input of a flip-flop (FF) 820. In an embodiment, the flip-flop (FF) 820 is an edge-sensitive flip-flop. The set (S) input of the flip-flop (FF) 820 is set when the high-side signal (HVG) is at a logic level high.

[0099] Therefore, when the high-side switch (Q 1 )202 is deactivated and the first AND gate 812 is at a logic level high, the second AND gate resets the flip-flop (FF) 820 and provides a logic level high to the first input of the third AND gate 822. The second input of the third AND gate 822 is coupled to the output of the inverter 818. The inverter 818 inverts the high-side signal (HVG) to generate an inverted high-side signal (HVG N ). Therefore, when the high-side switch (Q 1 )202 is deactivated, the inverted high-side signal (HVG N ) is at a logic level high. The third input of the third AND gate 822 is coupled to the second one-shot trigger (MF 2 )816 non Output.

[0100] The third single trigger (MF 3 ) 824 is configured to, in response to being triggered, switch from a stable state to an unstable state within a predetermined period of time, and then automatically return to a stable state. In an embodiment, the third single trigger (MF 3 )824 is arranged as a positive edge triggered one-shot. In response to the three inputs of the third AND gate 822 transitioning to a logic level high, a positive edge trigger is provided to the third one-shot (MF 3 ) 824. The positive edge signal (the signal converted from logic level low to logic level high) from the third AND gate 822 triggers the third one-shot trigger (MF 3 )824, resulting in the third single trigger (MF 3 )824 changes state and generates a control signal (AUXG) at its output (Q) within τ seconds. B ), thereby turning the auxiliary switch (Q 3 )502 activation.

[0101] Fig. 9 A block diagram of an embodiment system 900 is illustrated. In an embodiment, the system 900 includes a filter and rectifier circuit 902, which may or may not be arranged as shown, an optional power factor correction (PFC) stage circuit 904, a dual-switch flyback converter 906, and a USB PD control stage circuit 908. The system 900 may include additional components not shown. In an embodiment, the system 900 is a high-density USB-C charger used to charge, for example, mobile devices.

[0102] The filter and rectifier circuit 902 is configured to receive an alternating current (AC) input from a power source. The filter and rectifier circuit 902 filters out noise and unwanted frequencies from the AC input and converts it to direct current (DC).

[0103] The PFC stage 904 ensures that the voltage and current waveforms are aligned to maximize power transfer efficiency. The PFC stage 904 is typically required for input power levels greater than 75 Watts (W).

[0104] The two-switch flyback converter 906 converts the DC output from the PFC stage circuit 904 to another DC level suitable for the USB PD control stage circuit 908. In an embodiment, the two-switch flyback converter 906 is implemented as the two-switch flyback converter 500 having the control logic circuits 700, 800 and operating using the method 600.

[0105] The USB PD control stage circuit 908 transmits an output voltage (V OUT ) to regulate and control power.

[0106] A first aspect relates to a converter, the converter comprising a bootstrap capacitor, a high-side switch, a low-side switch, an auxiliary switch and a controller. The bootstrap capacitor has a first terminal, the first terminal being coupled to a floating node. The high-side switch has a source terminal, the source terminal being coupled to the bootstrap capacitor by means of the floating node. The auxiliary switch has a drain terminal, the drain terminal being coupled to the bootstrap capacitor by means of the floating node. The controller is configured to provide a first control signal to a control terminal of the high-side switch, a second control signal to a control terminal of the low-side switch, and a third control signal to a control terminal of the auxiliary switch. The third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively.

[0107] In a first implementation form of the converter according to the first aspect, the converter further comprises a control logic circuit configured to monitor the voltage across the bootstrap capacitor.

[0108] In the second implementation of the converter according to the first aspect or any previous implementation of the first aspect, the third control signal is arranged to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value.

[0109] In a third implementation of the converter according to the first aspect or any previous implementation of the first aspect, the third control signal is arranged to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than a threshold.

[0110] In the fourth implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the converter further comprises a control logic circuit configured to monitor τ immediately after the high-side switch is turned off. 2 τ in seconds 1 The voltage at a floating node within one second.

[0111] In the fifth implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the third control signal is set in response to the control logic circuit detecting that the voltage at the floating node is τ immediately after the high-side switch is turned off. 2 τ in seconds 1 is greater than the threshold value for 1 second, activating the auxiliary switch within the current cycle.

[0112] In the sixth implementation form of the converter according to the first aspect or any previous implementation form of the first aspect, the third control signal is set in response to the control logic circuit detecting that the voltage at the floating node is τ immediately after the high-side switch is turned off. 2 τ in seconds 1 If the current is less than the threshold value for 1 second, the auxiliary switch remains deactivated during the current cycle.

[0113] A second aspect relates to a method of operating a converter. The method includes: generating, by a controller, a first control signal to a control terminal of a high-side switch of the converter, the high-side switch having a source terminal, the source terminal being coupled to a bootstrap capacitor via a floating node; generating, by the controller, a second control signal to a control terminal of a low-side switch of the converter; and determining, by the controller, whether to use a third control signal to activate an auxiliary switch within a current cycle, the auxiliary switch having a drain terminal, the drain terminal being coupled to the bootstrap capacitor via a floating node. The determination is based on a condition associated with the converter after the high-side switch and the low-side switch are deactivated by the first control signal and the second control signal, respectively.

[0114] In a first implementation form of the method according to the second aspect, the method further comprises monitoring, by the control logic circuit, the voltage across the bootstrap capacitor.

[0115] In the second implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the third control signal is arranged to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value.

[0116] In a third implementation of the method according to the second aspect or any previous implementation of the second aspect, the third control signal is arranged to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than a threshold.

[0117] In the fourth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the method further comprises monitoring, by the control logic circuit, τ immediately after the high-side switch is turned off. 2 τ in seconds 1 The voltage at a floating node within one second.

[0118] In the fifth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the third control signal is set in response to the control logic circuit detecting that τ immediately after the high-side switch is turned off. 2 The voltage at the floating node is greater than the threshold value for a period of seconds, activating the auxiliary switch in the current cycle.

[0119] In the sixth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the third control signal is set in response to the control logic circuit detecting that the high-side switch is turned off immediately after the τ 2 τ in seconds 1 Within 100 ms, the voltage at the floating node is less than the threshold, keeping the auxiliary switch deactivated during the current cycle.

[0120] A third aspect relates to a device having a converter. The converter includes a bootstrap capacitor, a high-side switch, a low-side switch, an auxiliary switch, and a controller. The bootstrap capacitor has a first terminal coupled to a floating ground node. The high-side switch has a source terminal, and the source terminal is coupled to the bootstrap capacitor by means of the floating ground node. The auxiliary switch has a drain terminal, and the drain terminal is coupled to the bootstrap capacitor by means of the floating ground node. The controller is configured to provide a first control signal to a control terminal of the high-side switch, a second control signal to a control terminal of the low-side switch, and a third control signal to a control terminal of the auxiliary switch. The third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively.

[0121] In a first implementation form according to the third aspect, the converter further comprises a control logic circuit configured to monitor the voltage across the bootstrap capacitor.

[0122] In the second implementation form of the device according to the third aspect or any previous implementation form of the third aspect, the third control signal is arranged to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value. The third control signal is arranged to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than a threshold value.

[0123] In the third implementation form of the device according to the third aspect or any previous implementation form of the third aspect, the converter further comprises a control logic circuit configured to monitor τ immediately after the high-side switch is turned off. 2 τ in seconds 1 The voltage at a floating node within one second.

[0124] In a fourth implementation form of the device according to the third aspect or any previous implementation form of the third aspect, the third control signal is set in response to the control logic circuit detecting that the voltage at the floating node is τ immediately after the high-side switch is turned off. 2 τ in seconds 1 is greater than the threshold value for 1 second, activating the auxiliary switch within the current cycle.

[0125] In the fifth implementation form of the device according to the third aspect or any previous implementation form of the third aspect, the third control signal is set in response to the control logic circuit detecting that the voltage at the floating node is τ immediately after the high-side switch is turned off. 2 τ in seconds 1 If the current is less than the threshold value for 1 second, the auxiliary switch remains deactivated during the current cycle.

[0126] Although the description has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In different figures, the same elements are designated by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because those of ordinary skill in the art will easily understand that the processes, machines, manufactures, material compositions, parts, methods or steps currently existing or to be developed later can perform functions substantially the same as the corresponding embodiments described herein or achieve substantially the same results according to the present disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, parts, methods or steps within their scope.

[0127] Accordingly, the specification and drawings should be regarded simply as illustrative of the present disclosure as defined by the appended claims, and any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure are contemplated to be covered.

Claims

1. A converter, comprising: a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch having a source terminal coupled to the bootstrap capacitor via the floating node; Low-side switch; an auxiliary switch having a drain terminal coupled to the bootstrap capacitor via the floating node; as well as A controller, the controller being configured to: providing a first control signal to a control terminal of the high-side switch; providing a second control signal to a control terminal of the low-side switch; as well as A third control signal is provided to a control terminal of the auxiliary switch, wherein the third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively. 2 . The converter of claim 1 , further comprising a control logic circuit configured to monitor the voltage across the bootstrap capacitor.

3. The converter of claim 2, wherein the third control signal is arranged to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value.

4. The converter of claim 2, wherein the third control signal is arranged to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than a threshold value.

5. The converter of claim 1 further comprising a control logic circuit configured to monitor a voltage at the floating node within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

6. A converter according to claim 5, wherein the third control signal is configured to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is greater than a threshold within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

7. A converter according to claim 5, wherein the third control signal is configured to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is less than a threshold within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

8. A method of operating a converter, the method comprising: generating, by a controller, a first control signal to a control terminal of a high-side switch of the converter, the high-side switch having a source terminal coupled to a bootstrap capacitor via a floating node; generating, by the controller, a second control signal to a control terminal of a low-side switch of the converter; as well as A determination is made by the controller whether to use a third control signal to activate an auxiliary switch within a current cycle, the auxiliary switch having a drain terminal coupled to the bootstrap capacitor via the floating node, wherein the determination is based on conditions associated with the converter after the first control signal and the second control signal respectively deactivate the high-side switch and the low-side switch.

9. The method according to claim 8, further comprising: The voltage across the bootstrap capacitor is monitored by a control logic circuit.

10. The method of claim 9, wherein the third control signal is arranged to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value.

11. The method of claim 10, wherein the third control signal is arranged to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than the threshold.

12. The method according to claim 8, further comprising: The voltage at the floating node is monitored by the control logic circuit within τ1 seconds within a period of τ2 seconds immediately after the high-side switch is turned off.

13. The method of claim 12 , wherein the third control signal is configured to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is greater than a threshold value within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

14. The method of claim 12, wherein the third control signal is configured to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is less than a threshold value within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

15. A device comprising a converter, the converter comprising: a bootstrap capacitor having a first terminal coupled to a floating ground node; a high-side switch having a source terminal coupled to the bootstrap capacitor via the floating node; Low-side switch; an auxiliary switch having a drain terminal coupled to the bootstrap capacitor via the floating node; as well as A controller, the controller being configured to: providing a first control signal to a control terminal of the high-side switch; providing a second control signal to a control terminal of the low-side switch; as well as A third control signal is provided to a control terminal of the auxiliary switch, wherein the third control signal for activating the auxiliary switch within a current cycle is based on a condition associated with the converter after the first control signal and the second control signal deactivate the high-side switch and the low-side switch, respectively.

16. The apparatus of claim 15, wherein the converter further comprises a control logic circuit configured to monitor a voltage across the bootstrap capacitor.

17. The apparatus of claim 16 , wherein the third control signal is configured to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is less than a threshold value, and wherein the third control signal is configured to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage across the bootstrap capacitor is greater than the threshold value.

18. The apparatus of claim 15, wherein the converter further comprises a control logic circuit configured to monitor a voltage at the floating node within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

19. The apparatus of claim 18, wherein the third control signal is configured to activate the auxiliary switch within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is greater than a threshold value within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

20. The apparatus of claim 19, wherein the third control signal is configured to keep the auxiliary switch deactivated within the current cycle in response to detecting by the control logic circuit that the voltage at the floating node is less than the threshold within τ1 seconds within a τ2 second period immediately after the high-side switch is turned off.

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