Novel chopping correlation double-sampling stable multi-path amplification circuit and method

Abstract

The invention discloses a novel chopping correlation double-sampling stable multi-path amplifying circuit and method, and relates to integrated circuit design. A Miller compensation capacitor in a chopping stable multi-path CSMP amplification circuit architecture is utilized to design a chopping correlation double-sampling circuit, and compared with a traditional correlation double-sampling circuit, a group of sampling capacitors and sampling switches are reduced. Large capacitance and large resistance required by a traditional high-pass filter circuit are eliminated, and the layout area and the current required for driving a high-pass filter capacitor are reduced; and thermal noise caused by large resistance in the passive high-pass filter is reduced, and the input equivalent noise density is improved. Through an offset calibration technology, the stability of the CSMP architecture is ensured, and the offset voltage is reduced at the same time; output ripples are suppressed by using the high-pass performance of the novel chopping correlation double-sampling circuit, 1 / f noise is reduced, and input equivalent noise density is reduced. The advantages of the chopping correlation double sampling technology and the stable multi-path amplification circuit are combined, and the advantages of low offset, low output ripple and low input equivalent noise density are achieved.

Description

Technical Field

[0001] The present invention relates to the field of mixed signal integrated circuit design combining analog circuits and calibration circuits, and in particular to a novel chopping-correlated double sampling stable multi-path amplifier circuit and method for reducing offset, output ripple, and input equivalent noise density. Background Art

[0002] Chopper Stabilized Multi-Path Amplifier Circuit (CSMP Amp) is a circuit design that combines chopper stabilization technology and multi-path amplifier architecture. It is used to suppress low-frequency noise and offset and achieve high-precision signal amplification. It is widely used in high-precision sensors, medical electronics, precision instrument signal amplification and other fields. Since the input signal of high-precision sensors is very weak, the signal amplitude ranges from a few microvolts to millivolts, so the amplifier needs to achieve a good balance between noise, offset and bandwidth. The chopper stabilized multi-path amplifier circuit divides the amplifier into a high-frequency path with wide bandwidth and a low-frequency path with high gain, low offset and low noise. The overall gain, offset and noise of the amplifier are determined by the low-frequency path, and the high-frequency path provides high bandwidth and fast dynamic response. At the same time, in order to ensure that the closed-loop feedback of the multi-path amplifier has sufficient gain and phase margin to avoid oscillation, circuit stabilization design methods such as Miller frequency compensation are also used.

[0003] Although the chopper-stabilized multipath amplifier circuit can reduce low-frequency offset voltage and noise through chopper modulation technology, the residual modulation flicker noise and offset will appear at the output of the amplifier in the form of output ripple. How to eliminate the ripple becomes one of the important challenges of the circuit design. The ripple is similar to a square wave superimposed on the desired signal. The ripple at the output end will be superimposed on the target signal, directly affecting the measurement accuracy of the system and the output quality of the amplifier. In addition, the presence of ripple increases the noise level within the bandwidth of the subsequent input signal, reduces the signal-to-noise ratio of precision data acquisition or sensor signal processing, and introduces non-negligible systematic errors in high-sensitivity circuits.

[0004] In order to eliminate the ripple of the chopper-stabilized multipath amplifier circuit, there are mainly the following ripple elimination technologies: (1) After the first-stage amplifier is chopped, a low-pass or notch filter technology is used to selectively filter out the ripple modulated to the chopping frequency, thereby suppressing the output ripple (R. Burt and J. Zhang, "A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2729-2736, Dec. 2006); (2) A ripple reduction loop (RRL) is used to detect ripples and generate offset compensation signals through feedback suppression mechanism to reduce the output ripple of the amplifier (R.Wu, KAA Makinwa and JH Huijsing, "A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz 1 / f Noise Corner and an AC-Coupled Ripple Reduction Loop," in IEEE Journal of Solid-State Circuits, vol.44, no. 12, pp. 3232-3243, Dec. 2009); (3) The low-frequency current caused by the offset is selectively filtered out by a high-pass filter to prevent it from being modulated by chopping, thereby suppressing the output ripple (Qu, Q. Pan, L. Liu, X. Zeng, Z.Hong and J. Xu, "A 1.8–GΩ Input-Impedance 0.15–μV Input-Referred–RippleChopper Amplifier With Local Positive Feedback and SAR-Assisted RippleReduction," in IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp.796-805, March 2023); (4) Calibrate the offset of the first-stage amplifier through digital calibration technology to reduce the offset of the first-stage amplifier and thus reduce the output ripple caused by it (J. Xu, RF Yazicioglu, B. Grundlehner, P. Harpe, KAA Makinwa and C. Van Hoof, "A 160 μW 8-Channel ActiveElectrode System for EEG Monitoring," in IEEE Transactions on BiomedicalCircuits and Systems, vol. 5, no. 6, pp. 555-567, Dec. 2011). .

[0005] At present, similar research and patents on chopper-stabilized multi-path operational amplifier circuits and offset ripple elimination methods are as follows:

[0006] The document "A Micropower Chopper—CDS Operational Amplifier" (IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2521-2529) proposes a single-path amplifier circuit based on chopper-correlated double sampling. The circuit structure combines chopper technology and the Correlated Double Sample (CDS) method, eliminates the offset voltage of the first-stage amplifier through the AC coupling capacitor of CDS and realizes the function of chopper demodulation. The premise is that the offset voltage of the first-stage amplifier will not saturate the output of the amplifier. Compared with it, the present invention combines the chopper-correlated double sampling circuit with the multi-path amplifier circuit, and the multi-path amplifier circuit achieves a better balance between noise, offset and bandwidth compared with the single-path amplifier circuit; at the same time, the present invention redesigns the chopper-correlated double sampling circuit using the Miller compensation capacitor in the CSMP amplifier circuit architecture, and reduces a set of sampling capacitors and sampling switches compared with the traditional correlated double sampling circuit, and the present invention reduces the offset voltage while ensuring the stability of the CSMP architecture through the offset calibration technology.

[0007] The document "A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction" (IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 796-805) proposes a technology combining high-pass filtering and SAR offset calibration. This technology uses an offset calibration circuit to selectively filter out the output ripple caused by the offset through a traditional high-pass filter circuit when the first-stage amplifier is not saturated. Compared with it, the present invention uses a new chopper-related double sampling circuit to replace the traditional high-pass filter circuit to suppress output ripple and 1 / f noise, eliminate the large capacitors and large resistors required by the traditional high-pass filter circuit, reduce the layout area and the current required to drive the high-pass filter capacitor; and reduce the thermal noise caused by the large resistor in the passive high-pass filter, and improve the input equivalent noise density.

[0008] Chinese patent CN119051607A discloses a chopper instrument amplifier circuit with low output ripple, which uses the common-mode rejection characteristics of differential operational amplifiers to reduce the interference of switching noise introduced by chopping on the signal, thereby solving the problem of large output ripple. Compared with it, the present invention uses the high-pass performance of a new chopper-correlated double sampling circuit to suppress output ripple and 1 / f noise, thereby reducing the input equivalent noise density. At the same time, the present invention uses the Miller compensation capacitor in the CSMP amplifier circuit architecture as a sampling capacitor to design a new chopper-correlated double sampling circuit.

[0009] Chinese patent CN118962539A discloses a ripple elimination loop for eliminating Hall offset voltage. In the feedback path, a high-pass filter is used to filter out the low-frequency Hall voltage and retain the offset voltage modulated to a high frequency. The offset DC component is then restored through filtering by a chopper switch and an integrator, and input to the negative end of the instrument amplifier to offset the original offset voltage. It belongs to the ripple suppression loop technology we mentioned above. Compared with it, the present invention does not use a ripple suppression loop, but uses the high-pass performance of a new chopper-related double sampling circuit to suppress output ripple. And through the offset calibration technology, the offset voltage is reduced while ensuring the stability of the CSMP architecture.

[0010] Chinese patent CN109818583A discloses a multi-path stabilized chopper amplifier with a high-pass filter for suppressing chopper ripple. The method generates a corresponding compensation signal and provides it to the first-stage gain circuit by detecting the low-frequency content of the differential signal after amplification, thereby reducing low-frequency noise and input offset voltage. It is similar to the ripple suppression loop technology we mentioned above. Compared with it, the present invention uses the high-pass performance of the new chopper-related double sampling circuit to suppress output ripple and 1 / f noise. At the same time, the present invention uses the Miller compensation capacitor in the CSMP amplifier circuit architecture as the sampling capacitor to design a new chopper-related double sampling circuit, and ensures the stability of the CSMP architecture and reduces the offset voltage through the offset calibration technology.

[0011] In summary, many methods for suppressing the offset ripple of chopper-stabilized multi-path operational amplifier circuits have appeared in recent years, but none of these inventions involve the novel chopper-correlated double sampling multi-path amplifier circuit and method proposed in the present invention. So far, there has been no chopper-correlated double sampling circuit designed using the Miller compensation capacitor in the CSMP amplifier circuit architecture, nor has this novel chopper-correlated double sampling circuit been applied to the design of multi-path amplifier circuits. Summary of the invention

[0012] The purpose of the present invention is to provide a novel chopper-correlated double sampling stabilized multipath amplifier circuit and method for the output ripple problem caused by residual modulation flicker noise and offset in a chopper-stabilized multipath amplifier circuit, and to design a chopper-correlated double sampling circuit by cleverly utilizing the Miller compensation capacitor in the chopper-stabilized multipath amplifier circuit architecture, thereby saving a set of sampling capacitors and sampling switches. This structure eliminates the large capacitors and large resistors required for traditional high-pass filter circuits, reduces the layout area and the current required to drive large capacitors, and reduces power consumption; at the same time, it reduces 1 / f noise and thermal noise, and improves input equivalent noise density. By combining the advantages of chopping technology and correlated double sampling technology, the high-pass performance of the novel chopper-correlated double sampling circuit is utilized to suppress the output ripple, and the output ripple voltage is further reduced while ensuring the stability of the CSMP architecture through offset calibration technology, which has the advantages of low offset, low output ripple, and low input equivalent noise density.

[0013] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions.

[0014] The chopper-correlated double sampling multi-path amplifier circuit has an analog differential input signal V in port, chopper circuit CH1, calibration input common mode voltage V icm1 Port, first stage amplifier G m1 Offset calibration switch SW group (SW c0 ~SW c3 )、G m1 Offset calibration clock signal group ( , )、First stage amplifier G m1 , G m1 Offset calibration circuit, correlated double sampling circuit, second stage amplifier G m2 , output stage amplifier G m4 , the second-stage Miller compensation capacitor group (C M20 , C M21 )、Auxiliary amplifier G m3 and the output signal V out Port; the analog differential input signal V in The port is connected to the input of the chopper circuit CH1 and the auxiliary amplifier G m3 The first stage amplifier G m1 The input is passed through the first stage amplifier G m1 SW in the offset calibration switch SW group c1 and SW c2 The switch is calibrated with the input common-mode voltage V icm1 The first stage amplifier G m1 SW in the offset calibration switch SW group c0 and SW c3 Connected to the output of chopper circuit CH1; G m1 The offset correction clock signal group and As G m1 The working clock of the offset calibration switch SW group controls its switch operation; the first stage amplifier G m1 The output and G m1 The input of the offset calibration circuit is connected to the input of the correlated double sampling circuit, G m1 The output of the offset calibration circuit is connected to the first stage amplifier G m1 The signal V of the correlated double sampling circuit is connected to the Cal port; o1、 V o2 The output of the second stage amplifier G m2 The input of the correlated double sampling circuit is connected to the signal V o3 Output and output signal V out The output stage amplifier G m4 The input and second stage amplifier G m2 The output of the auxiliary amplifier G m3 The output of the second-stage Miller compensation capacitor group C M20、 C M21 The two ends are connected to the output stage amplifier G m4 The input and output are connected; the output stage amplifier G m4 The output and output signal V out The ports are connected.

[0015] The correlated double sampling circuit comprises a double sampling capacitor group (C cds0 ~C cds3 ), sampling switch SW group (SW0~SW7), sampling clock ( , ), sampling common mode voltage V icm2 Input port, and the first-stage Miller capacitor group (C M10 , C M11 ); the input V of the correlated double sampling circuit in 、V ip The ports are connected to the first stage amplifier G m1 The output negative and positive terminals are connected; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds0 The sampling switch SW0 in the sampling switch SW group is connected to the second stage amplifier G m2 The input and the capacitor C in the first-stage Miller capacitor group M11 One end of the dual sampling capacitor group through the capacitor C cds0 and the sampling switch SW4 is connected to the sampling common mode voltage V icm2 The input port constitutes the first path of the correlated double sampling circuit; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds1 and the sampling switch SW1 is connected to the sampling common mode voltage V icm2 The input port and the capacitor C in the double sampling capacitor group cds1 and sampling switch SW5 is connected to the second stage amplifier G m2 The input and first stage Miller capacitor group C M10 One end of the correlated double sampling circuit constitutes the second path; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds2 The sampling switch SW2 is connected to the second stage amplifier G m2 The input and the capacitor C in the first-stage Miller capacitor group M10 One end of the dual sampling capacitor group through the capacitor C cds2 and the sampling switch SW6 is connected to the sampling common mode voltage V icm2 The input port constitutes the third path of the correlated double sampling circuit; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds3 and the sampling switch SW3 is connected to the sampling common mode voltage V icm2 The input port and the capacitor C in the double sampling capacitor group cds3 and sampling switch SW7 is connected to the second stage amplifier G m2The input and the capacitor C in the first-stage Miller capacitor group M11 The first and third paths form a "ping" structure, and the second and fourth paths form a "pong" structure. In the stage, the "ping" structure samples and inputs the signal to the second stage amplifier G m2 ; "Pong" structure and sampling common mode voltage V icm2 The input port is connected to reset. stage, the "ping" structure and the sampling common mode voltage V icm2 The input port is connected to reset, and the "pong" structure is used to sample and input the signal to the second stage amplifier G m2 ; The first-stage Miller capacitor group C M10 One end is connected to the second stage amplifier G m2 The first-stage Miller capacitor group C M10 The other end is connected to the output stage amplifier G m4 Output; C in the first-stage Miller capacitor group M11 One end is connected to the second stage amplifier G m2 The first-stage Miller capacitor group C M11 The other end is connected to ground.

[0016] The G m1 The offset calibration circuit includes a dynamic comparator, a successive comparison logic generation circuit and a current-type DAC; the input of the dynamic comparator is connected to the first-stage amplifier G m1 The output of the successive comparison logic generation circuit receives the output of the dynamic comparator and generates a corresponding calibration code input to the current-type DAC; the output of the current-type DAC is connected to the first-stage amplifier G m1 Cal port of the

[0017] The working sequence of the correlated double sampling circuit is as follows:

[0018] 1. In stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C of the double sampling capacitor group cds2 and sampling switch SW6 and sampling common mode voltage V icm2 The input port is connected, then V ip for:

[0019] (1)

[0020] Among them, V in is the analog input signal, V os 、V n Respectively represent the first stage amplifier G m1Input offset voltage and input equivalent noise, A1 is the first stage amplifier G m1 The gain. Phase C cds2 The charge Q cds2 for:

[0021] (2)

[0022] Where V icm2 For sampling input common-mode voltage.

[0023] 2. In stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C in the double sampling capacitor group cds2 and the sampling switch SW2 and the capacitor C in the first-stage Miller capacitor group M10 One end and the second stage amplifier G m2 Since the capacitor C in the first-stage Miller capacitor group M10 Connected across the second stage amplifier G m2 The input and output stages of the amplifier G m4 The output end of the amplifier can be regarded as the second-stage amplifier G according to Miller's equivalent theorem. m2 The input terminal is connected to C M1a =(1+A2×A4)C M10 The sampling capacitor, output stage amplifier G m4 The output terminal is connected to C M1b =A2×A4 / (1+A2×A4)C M10 The load capacitance of A2 and A4 are respectively the second stage amplifier G m2 and output stage amplifier G m4 Gain. According to the charge conservation theorem, Phase C cds2 and C M1a The sum of the charges on Phase C cds2 The charges on are equal, that is:

[0024] (3)

[0025] in = ,for Stage capacitance C M1a The charge on V cs is the capacitance C M1a The voltage on = for Stage capacitance C cds2Substituting these two charges into equation (3) and rearranging them, we get:

[0026] (4)

[0027] exist stage, the chopper circuit CH1 exchanges V in The polarity of , so we can get:

[0028] (5)

[0029] Combining equations (1), (4) and (5), we can get:

[0030] (6)

[0031] From formula (6), we can see that the input signal V in The transfer function is 1+z -1 , is a low-pass function; the noise V n The transfer function is 1-z -1 , is a high-pass function, so V os are canceled out; thus it is proved that the proposed correlated double sampling circuit can filter out and reduce the input equivalent noise and offset voltage, thereby suppressing the output ripple.

[0032] Compared with the prior art, the outstanding technical effects of the present invention are:

[0033] 1. A novel chopper-correlated double sampling circuit structure uses the Miller compensation capacitor in the CSMP architecture to perform signal-correlated double sampling, thereby saving a set of sampling capacitors and sampling switches. This design reduces the number of sampling capacitors and sampling switches required in traditional correlated double sampling circuits, thereby reducing costs and improving circuit efficiency.

[0034] 2. The high-pass transmission characteristics of this new chopper-related double sampling circuit can filter out 1 / f low-frequency noise and DC offset voltage, thereby reducing the input equivalent noise density and suppressing output ripple; further, it not only eliminates the large capacitors and large resistors required by traditional high-pass filter circuits, reduces the layout area and the current required to drive the high-pass filter capacitor; but also reduces the thermal noise caused by the large resistors in the passive high-pass filter, and improves the input equivalent noise density.

[0035] 3. This new chopper-correlated double sampling multi-path amplifier circuit combines the advantages of chopper-correlated double sampling technology and stable multi-path amplifier circuit, and further reduces the offset voltage while ensuring the stability of the CSMP architecture through offset calibration technology. It has the advantages of low offset, low output ripple, and low input equivalent noise density.

[0036] 4. By combining the chopper-stabilized multipath amplifier circuit with the new correlated double sampling circuit, not only the overall performance of the circuit is improved, but also the circuit achieves a better balance between noise, offset and bandwidth. By optimizing the circuit structure and signal processing flow, the circuit has lower power consumption and smaller layout area. The design of the ping-pong structure ensures the continuity of the signal and improves the reliability and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a block diagram of a novel chopper-correlated double sampling multi-path amplifier circuit described in the present invention.

[0038] Figure 2 It is the working timing diagram of the correlated double sampling circuit described in the present invention and its equivalent circuit analysis diagram.

[0039] Figure 3 G of the present invention m1 Calibration waveform timing diagram of the offset calibration circuit.

[0040] Figure 4 This is a comparison diagram of the output ripple improvement of the correlated double sampling circuit of the present invention and other methods.

[0041] Figure 5 This is a comparison diagram of the correlated double sampling circuit of the present invention in improving the input equivalent offset voltage.

[0042] Figure 6 This is a comparison diagram of the improvement of input equivalent ripple by the correlated double sampling circuit of the present invention.

[0043] Figure 7 This is a comparison diagram of the input equivalent noise density spectrum improved by the correlated double sampling circuit of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the present invention clearer, the following embodiments will further illustrate the method of the present invention in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the circuit structure and method principles of the present invention should be included in the protection scope of the present invention.

[0045] See also Figure 1 The chopper-correlated double sampling multi-path amplifier circuit embodiment has an analog differential input signal V in Port 0, chopper circuit CH1 1, calibration input common mode voltage V icm1 Port 2, first stage amplifier G m1 Offset calibration switch SW group 3, G m1 Offset calibration clock signal group 4, first stage amplifier Gm1 5. G m1 Offset calibration circuit 6, correlated double sampling circuit 7, second stage amplifier G m2 8. Output stage amplifier G m4 9. Second-stage Miller compensation capacitor group, auxiliary amplifier G m3 11 and the output signal V out Port 12; wherein the first stage amplifier G m1 Offset calibration switch SW group 3 includes switches SW c0 , switch SW c1 , switch SW c2 , switch SW c3 ; said G m1 The offset calibration clock signal group includes the clock signal , clock signal The second-stage Miller compensation capacitor group includes capacitor C M20 100. Capacitor C M21 101;

[0046] The analog differential input signal V in Port 0 is used to receive an external analog differential input signal; the chopping circuit CH11 is used to chop the input signal; the analog differential input signal V in Port 0 is connected to the input of the chopper circuit CH1 1 and the auxiliary amplifier G m3 11 is connected to the input end; the first stage amplifier G m1 5 is used to initially amplify the chopped signal. The first-stage amplifier G m1 5 input through G m1 Switch SW in offset calibration switch SW group 3 c1 and switch SW c2 The calibrated input common-mode voltage V icm1 Port 2 is connected to the G m1 Switch SW in offset calibration switch SW group 3 c0 and switch SW c3 Connected to the output of the chopper circuit CH1 1; calibrated input common-mode voltage V icm1 Port 2 is used to provide the common mode voltage required for calibration; G m1 Clock signal in offset correction clock signal group 4 and clock signal As G m1 The working clock of the offset calibration switch SW group 3 controls its switch operation; the first stage amplifier G m1 5 output and G m1 The input of the offset calibration circuit 6 is connected to the input of the correlated double sampling circuit 7.m1 The output of the offset calibration circuit 6 is connected to the first stage amplifier G m1 5 Cal port connected; G m1 The offset calibration circuit 6 is used to detect and calibrate the first stage amplifier G m1 5 offset voltage; the correlated double sampling circuit 7 signal V o1 、V o2 The output of the second stage amplifier G m2 8 is connected to the input of the correlated double sampling circuit 7. o3 Output and output V out The output stage amplifier G m4 9 input and the second stage amplifier G m2 8 output and auxiliary amplifier G m3 The output of 11 is connected to the second stage amplifier G m2 8 is used to further amplify the sampled signal; the capacitor C in the second-stage Miller compensation capacitor group M20 100. Capacitor C M21 101 has two output stage amplifiers G m4 9 is connected to the input and output; the output stage amplifier G m4 9 output and output signal V out Port 12 is connected. Output stage amplifier G m4 9 is used to provide the final amplified output signal; the output signal V out Port 12 outputs the final amplified signal.

[0047] The correlated double sampling circuit 7 includes a double sampling capacitor group, a sampling switch SW group, a sampling clock group, a sampling common mode voltage V icm2 Input port 714 and the first-stage Miller capacitor group; the double sampling capacitor group includes capacitor C cds0 700, Capacitor C cds1 701. Capacitor C cds2 702, C cds3 703; the sampling switch SW group includes sampling switch SW0 706, sampling switch SW1 707, sampling switch SW2 708, sampling switch SW3 709, sampling switch SW4 710, sampling switch SW5 711, sampling switch SW6 712, sampling switch SW7 713; the sampling clock group includes sampling clock 704, Sampling Clock 705; The first-stage Miller capacitor group includes capacitor C M10 715. Capacitor C M11 716;

[0048] The input V of the correlated double sampling circuit 7in Port, V ip The ports are connected to the first stage amplifier G m1 5 output negative and positive terminals are connected; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds0 700 and the sampling switch SW0 706 in the sampling switch SW group connect the second stage amplifier G m2 8 input and the capacitor C in the first-stage Miller capacitor group M11 One end of 716 and through the capacitor C in the double sampling capacitor group cds0 700 and sampling switch SW4 710 are connected to the sampling common mode voltage V icm2 The input port 714 constitutes the first path of the correlated double sampling circuit; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds1 701 and sampling switch SW1 707 are connected to the sampling common mode voltage V icm2 Input port 714 and through the capacitor C in the double sampling capacitor group cds1 701 and sampling switch SW5 711 are connected to the second stage amplifier G m2 8 input and the capacitor C in the first-stage Miller capacitor group M10 One end of 715 constitutes the second path of the correlated double sampling circuit; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds2 702 and sampling switch SW2 708 connect the second stage amplifier G m2 8 input and the capacitor C in the first-stage Miller capacitor group M10 One end of 715 and through the capacitor C in the double sampling capacitor group cds2 702 and sampling switch SW6 712 are connected to the sampling common mode voltage V icm2 The input port 714 constitutes the third path of the correlated double sampling circuit; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds3 703 and sampling switch SW3 709 are connected to the sampling common mode voltage V icm2 Input port 714 and through the capacitor C in the double sampling capacitor group cds3 703 and sampling switch SW7 713 are connected to the second stage amplifier G m2 8 input and the capacitor C in the first-stage Miller capacitor group M11 One end of 716 constitutes the fourth path of the correlated double sampling circuit; the first path and the third path constitute a "ping" structure, and the second path and the fourth path constitute a "pong" structure. In stage 704, the "ping" structure performs sampling and inputs the signal to the second stage amplifier G m2 8. "Pong" structure and sampling common mode voltage V icm2 Input port 714 is connected to reset. 705 stage, the "ping" structure and the sampling common mode voltage V icm2 The input port 714 is connected to reset, and the "pong" structure is sampled, and the signal is input to the second stage amplifier G m2 8; This alternating working mode ensures that the continuity of the signal can be guaranteed even in the process of sampling and charge transfer, thereby improving the accuracy and stability of the entire amplifier circuit; the capacitor C in the first-stage Miller capacitor group M10 One end of 715 is connected to the second stage amplifier G m2 8 input, the capacitor C in the first-stage Miller capacitor group M10 The other end of 715 is connected to the output stage amplifier G m4 9 output; capacitor C in the first-stage Miller capacitor group M11 One end of 716 is connected to the second stage amplifier G m2 8 input, the capacitor C in the first-stage Miller capacitor group M11 The other end of 716 is connected to ground.

[0049] The G m1 The offset calibration circuit 6 comprises a dynamic comparator 61, a successive comparison logic generation circuit 62 and a current-type DAC 63; the input of the dynamic comparator 61 is connected to the first-stage amplifier G m1 The successive comparison logic generating circuit 62 receives the output of the dynamic comparator 61 and generates a corresponding calibration code input to the current type DAC 63; the output of the current type DAC63 is connected to the first stage amplifier G m1 5 Cal port.

[0050] The present invention utilizes Miller compensation capacitors in a CSMP architecture to perform correlated double sampling, that is, utilizes Miller compensation capacitors to perform signal sampling and transmission, thereby reducing a group of sampling capacitors and sampling switches, and provides a novel chopper-correlated double sampling multi-path amplifier circuit and method; this circuit structure not only eliminates large capacitors and large resistors required for a traditional high-pass filter circuit, reduces the layout area and the current required to drive the high-pass filter capacitor; it also reduces the thermal noise caused by the large resistor in the passive high-pass filter, and improves the input equivalent noise density; at the same time, the high-pass performance of the novel chopper-correlated double sampling circuit is utilized to suppress output ripple, reduce 1 / f noise and reduce input equivalent noise density; in addition, the novel chopper-correlated double sampling multi-path amplifier circuit combines the advantages of chopper-correlated double sampling technology and a stable multi-path amplifier circuit, and reduces the offset voltage while ensuring the stability of the CSMP architecture through an offset calibration technology; based on the above-mentioned novel chopper-correlated double sampling circuit and calibration method, a novel chopper-correlated double sampling multi-path amplifier circuit and method with low offset, low output ripple and low input equivalent noise density are realized.

[0051] Figure 2 The working timing diagram of the correlated double sampling circuit of the present invention and its equivalent circuit analysis diagram, wherein V in is the analog input signal, CH1 is the chopper circuit, V os 、V n Respectively represent the first stage amplifier G m1 Input offset voltage and input equivalent noise, A1 is the first stage amplifier G m1 Gain, V ip is the input voltage at one end of the correlated double sampling circuit, C cds0 is the capacitance in the correlated double sampling capacitor group, V cs is the capacitance C M1a The voltage on the second stage amplifier G m2 and output stage amplifier G m4 Gain, C M10 is the capacitance of the first-stage Miller capacitor group, V icm2 is the sample input common mode voltage, V out The output stage amplifier G m4 The output voltage, and is the sampling clock signal; the working sequence of the correlated double sampling circuit is as follows:

[0052] 1. In stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C of the double sampling capacitor group cds2 and Figure 1 The sampling switch SW6 in the sampler and the sampling common mode voltage V icm2 The input port is connected, then Vip for:

[0053] (1)

[0054] At this time C cds2 The charge Q cds2 for:

[0055] (2)

[0056] 2. In stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C in the double sampling capacitor group cds2 and Figure 1 The sampling switch SW2 in the first stage and the capacitor C in the Miller capacitor group M10 One end and the second stage amplifier G m2 Since the capacitor C in the first-stage Miller capacitor group M10 Connected across the second stage amplifier G m2 The input and output stages of the amplifier G m4 The output end of the amplifier can be regarded as the second-stage amplifier G according to Miller's equivalent theorem. m2 The input terminal is connected to C M1a =(1+A2×A4)C M10 The sampling capacitor, output stage amplifier G m4 The output terminal is connected to C M1b =A2×A4 / (1+A2×A4)C M10 The load capacitance of A2 and A4 are respectively the second stage amplifier G m2 and output stage amplifier G m4 Gain. According to the charge conservation theorem, Phase C cds2 and C M1a The sum of the charges on Phase C cds2 The charges on are equal, that is:

[0057] (3)

[0058] in = ,for Stage capacitance C M1a The charge on = for Stage capacitance C cds2 Substituting these two charges into equation (3) and rearranging them, we get:

[0059] (4)

[0060] exist stage, the chopper circuit CH1 exchanges V in The polarity of

[0061] (5)

[0062] Combining equations (1), (4) and (5), we can get:

[0063] (6)

[0064] From formula (6), we can see that the input signal V in The transfer function is 1+z -1 , is a low-pass function; the first-stage amplifier G m1 The input equivalent noise V n The transfer function is 1-z -1 , is a high-pass function, so the first-stage amplifier G m1 The input offset voltage V os are canceled out; thus it is proved that the proposed correlated double sampling circuit can filter out and reduce the input equivalent noise and offset voltage, thereby suppressing the output ripple.

[0065] Figure 3 G of the present invention m1 Offset calibration circuit calibration waveform timing diagram, where Figure 3 (a) shows the first stage amplifier G m1 The positive and negative output voltage V ip and V in , Figure 3 (b) shows the offset calibration clock signal CLK, Figure 3 (c) in FIG. 1 shows the dynamic comparator output signal COMP. Figure 3 (d) in the figure shows the calibration codes D0~D7; during the calibration phase , Figure 1 The switch SW in c1 and SW c2 Closed, input shorted to calibrate input common-mode voltage V icm1 voltage, dynamic comparator at CLK calibration clock ( Figure 3 The falling edge of (b) compares the first stage amplifier G m1 The output voltage V ip and V in The difference reflects the first stage amplifier G m1 The output offset voltage is compared and the result is used to set the calibration code D7. Figure 3 As shown in (c); at the next CLK calibration clock falling edge, the dynamic comparator compares the first stage amplifier G againm1 The output voltage V ip and V in The comparison result is used to set the calibration code D6; and so on, the calibration codes D0~D7 are output as follows Figure 3 As shown in (d); the first stage amplifier G m1 The output offset voltage can be determined by the two output voltages V ip and V in The difference is reflected by Figure 3 As shown in (a), the output offset voltage is reduced from 4.19V-821.51mV=3.37V before calibration to 2.78V-2.21V=0.57V after calibration through calibration code D7-D0; this result shows that the G m1 The offset correction circuit can significantly reduce the first stage amplifier G m1 The offset voltage of the first stage amplifier G m1 No saturation and normal operation.

[0066] Figure 4 This is a comparison diagram of the output ripple improvement of the correlated double sampling circuit of the present invention and other methods, wherein the closed-loop gain of the simulation circuit is set to 100, and the input first-stage amplifier G m1 The offset voltage is set to 500nV; Figure 4 (a) is the ripple waveform of the output signal of the chopper-correlated double sampling multi-path amplifier circuit of the present invention, the output ripple is about 12.05 μV, and the input equivalent ripple is about 12.05 μV / closed-loop gain=120.5 nV; Figure 4 (b) is the ripple waveform of the output signal of the circuit described in the literature (T. Qu, Q.Pan, L. Liu, X. Zeng, Z. Hong and J. Xu, "A 1.8–GΩ Input-Impedance 0.15-μVInput-Referred–Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction," in IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 796-805, March 2023), where the output ripple is approximately 15.71μV and the input equivalent ripple is approximately 15.71μV / closed-loop gain = 157.1nV; Figure 4(c) is the ripple waveform of the output signal of the chopper-stabilized multi-path amplifier circuit when the ripple elimination technology is not used. The output ripple is about 101.48μV, and the input equivalent ripple is about 101.48μV / closed-loop gain=1.01μV. By comparison, it can be seen that the input equivalent ripple of the present invention is reduced by about 8.5 times compared with that of the circuit and method described in the literature. Figure 4 The comparison results show that the chopper-correlated double sampling multi-path amplifier circuit of the present invention can effectively suppress the output ripple.

[0067] Figure 5 A comparison diagram of the improvement of the input equivalent offset voltage by the correlated double sampling circuit of the present invention, wherein the closed-loop gain of the simulation circuit is set to 100, and 200 Monte Carlo simulations are performed on the input equivalent offset voltage; Figure 5 (a) is an input equivalent offset voltage histogram of the chopping-correlated double sampling multi-path amplifier circuit of the present invention. The distribution range of the input equivalent offset voltage is in the interval [-9.15μV, 7.28μV], the average value is about 829.26nV, and the standard deviation is about 2.77μV; Figure 5 (b) is an input equivalent offset voltage histogram of the chopper-stabilized multi-path amplifier circuit when the chopper-correlated double sampling technology is not used. The distribution range of the input equivalent offset voltage is in the interval [-1.79mV, 1.79mV], the average value is about 4.16μV, and the standard deviation is about 597.29μV; compared with the input equivalent offset voltage without the chopper-correlated double sampling technology, the average value of the input equivalent offset voltage of the present invention is reduced from 4.16μV to 0.83μV, which is improved by about 5 times; the standard deviation is reduced from 597.29μV to 2.77μV, and the standard deviation is improved by about 215 times, indicating that the chopper-correlated double sampling multi-path amplifier circuit described in the present invention can well reduce the offset voltage.

[0068] Figure 6 This is a comparison diagram of the improvement of input equivalent ripple by the correlated double sampling circuit of the present invention, wherein the closed-loop gain of the simulation circuit is set to 100, and the input equivalent ripple is subjected to 200 Monte Carlo simulations; Figure 6 (a) is an input equivalent ripple histogram of the chopping-correlated double sampling multi-path amplifier circuit of the present invention, and the distribution range of the input equivalent ripple is in the interval of (0V, 499.5nV], the average value is about 129.14nV, and the standard deviation is about 100.18nV; Figure 6(b) is an input equivalent ripple histogram of the chopper-stabilized multi-path amplifier circuit when the ripple elimination technology is not adopted. The distribution range of the input equivalent ripple is in the interval of (0V, 2.45mV], the average value is about 601.72 μV, and the standard deviation is about 450.46 μV; compared with the input equivalent ripple without the ripple elimination technology, the input equivalent ripple average value of the present invention is reduced from 601.72 μV to 129.14 nV, which is improved by about 4659 times; the standard deviation is reduced from 450.46 μV to 100.18 nV, which is improved by about 4500 times, indicating that the chopper-correlated double sampling multi-path operational amplifier circuit of the present invention can greatly suppress the ripple.

[0069] Figure 7 A comparison diagram of the input equivalent noise density spectrum improved by the correlated double sampling circuit of the present invention; Figure 7 The dashed line in the middle represents the input equivalent noise curve when the chopping-correlated double sampling technology is not used, and the solid line represents the input equivalent noise curve after the chopping-correlated double sampling technology is used. When the chopping-correlated double sampling technology is not used, the input equivalent noise at a frequency of 10Hz is about 355.30nV / √Hz; when the chopping-correlated double sampling technology is added to the circuit, the input equivalent noise at 10Hz is reduced from 355.30nV / √Hz to about 12.09nV / √Hz, which is improved by about 30 times. Figure 7 The input equivalent noise peak at the mid-20kHz frequency is caused by the chopping-correlated double sampling moving the noise at the mid-low frequency to the chopping-correlated double sampling frequency of 20kHz, which does not affect the significant reduction of the noise in the mid-low frequency band; the comparison results of the input equivalent noise density curves with and without the chopping-correlated double sampling technology show that the chopping-correlated double sampling circuit described in the present invention can effectively reduce the input equivalent noise density.

[0070] The present invention proposes a novel chopper-correlated double sampling multi-path amplifier circuit and method; the novel chopper-correlated double sampling multi-path amplifier circuit and method combine the respective advantages of chopper-correlated double sampling technology and stable multi-path amplifier circuit, and have the advantages of low offset, low output ripple, and low input equivalent noise density; the present invention uses the Miller compensation capacitor in the CSMP amplifier circuit architecture to design a chopper-correlated double sampling circuit, and compared with the traditional correlated double sampling circuit, a group of sampling capacitors and sampling switches are reduced; this structure not only eliminates the large capacitors and large resistors required by the traditional high-pass filter circuit, reduces the layout area and the current required to drive the high-pass filter capacitor; and reduces the large resistor in the passive high-pass filter. thermal noise, and improved the input equivalent noise density; in addition, the present invention reduces the offset voltage while ensuring the stability of the CSMP architecture through the offset calibration technology; the high-pass performance of the new chopper-related double sampling circuit is used to suppress the output ripple, reduce 1 / f noise and reduce the input equivalent noise density; the results of theoretical analysis and circuit simulation verify the advantages of the above-mentioned present invention; in addition, the present invention reduces the offset voltage while ensuring the stability of the CSMP architecture through the offset calibration technology. This new chopper-related double sampling multi-path amplifier circuit combines the respective advantages of the chopper-related double sampling technology and the stable multi-path amplifier circuit, and has the advantages of low offset, low output ripple and low input equivalent noise density.

[0071] The above embodiments are only preferred embodiments of the present invention and cannot be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A novel chopper-correlated double sampling stabilized multi-path amplifier circuit, characterized in that: include: With an analog differential input signal V in port, chopper circuit CH1, calibration input common mode voltage V icm1 Port, first stage amplifier G m1 Offset calibration switch SW group, G m1 Offset calibration clock signal group, first stage amplifier G m1 , G m1 Offset calibration circuit, correlated double sampling circuit, second stage amplifier G m2 , output stage amplifier G m4 , the second-stage Miller compensation capacitor group, auxiliary amplifier G m3 and the output signal V out port; The first stage amplifier G m1 The offset calibration switch SW group includes a switch SW c0 , switch SW c1 , switch SW c2 , switch SW c3 ; said G m1 The offset calibration clock signal group includes the clock signal , clock signal The second-stage Miller compensation capacitor group includes capacitor C M20 , capacitor C M21 ; The analog differential input signal V in The port is connected to the input of the chopper circuit CH1 and the auxiliary amplifier G m3 The first stage amplifier G m1 The input is passed through the first stage amplifier G m1 The switch SW in the offset calibration switch SW group c1 and switch SW c2 The calibrated input common-mode voltage V icm1 The first amplifier G m1 The switch SW in the offset calibration switch SW group c0 and switch SW c3 Connected to the output of chopper circuit CH1; G m1 Clock signals in the offset correction clock signal group and clock signal As G m1 The working clock of the offset calibration switch SW group controls its switch operation; the first stage amplifier G m1 The output and G m1 The input of the offset calibration circuit is connected to the input of the correlated double sampling circuit, G m1 The output of the offset calibration circuit is connected to the first stage amplifier G m1 The Cal port of the correlated double sampling circuit is connected; the signal V o1、 V o2 The output of the second stage amplifier G m2 The input of the correlated double sampling circuit is connected to the signal V o3 Output and output signal V out The output stage amplifier G m4 The input and second stage amplifier G m2 The output of the auxiliary amplifier G m3 The output of the second-stage Miller compensation capacitor group is connected; the capacitor C M20 and capacitor C M21 The two ends are connected to the output stage amplifier G m4 The input and output are connected; the output stage amplifier G m4 The output and output signal V out The ports are connected.

2. A novel chopper-correlated double sampling stabilized multi-path amplifier circuit as claimed in claim 1, characterized in that: The correlated double sampling circuit includes a double sampling capacitor group, a sampling switch SW group, a sampling clock , sample common mode voltage V icm2 Input port and first-stage Miller capacitor bank; The dual sampling capacitor group includes a capacitor C cds0 , capacitor C cds1 , capacitor C cds2 and capacitor C cds3 The sampling switch SW group includes sampling switches SW0-SW7, and the first-stage Miller capacitor group includes capacitors C M10 , capacitor C M11 ; The input V of the correlated double sampling circuit in 、V ip The ports are connected to the first stage amplifier G m1 The output negative and positive terminals are connected; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds0 The sampling switch SW0 in the sampling switch SW group is connected to the second stage amplifier G m2 The input and the capacitor C in the first-stage Miller capacitor group M11 One end of the dual sampling capacitor group through the capacitor C cds0 and the sampling switch SW4 is connected to the sampling common mode voltage V icm2 The input port constitutes the first path of the correlated double sampling circuit; the input V in The port passes through the capacitor C in the dual sampling capacitor group cds1 and the sampling switch SW1 is connected to the sampling common mode voltage V icm2 The input port and the capacitor C in the double sampling capacitor group cds1 and sampling switch SW5 is connected to the second stage amplifier G m2 The input and first stage Miller capacitor group C M10 One end of the correlated double sampling circuit constitutes the second path; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds2 The sampling switch SW2 is connected to the second stage amplifier G m2 The input and the capacitor C in the first-stage Miller capacitor group M10 One end of the dual sampling capacitor group through the capacitor C cds2 and the sampling switch SW6 is connected to the sampling common mode voltage V icm2 The input port constitutes the third path of the correlated double sampling circuit; the input V ip The port passes through the capacitor C in the dual sampling capacitor group cds3 and the sampling switch SW3 is connected to the sampling common mode voltage V icm2 The input port and the capacitor C in the double sampling capacitor group cds3 and sampling switch SW7 is connected to the second stage amplifier G m2 The input and the capacitor C in the first-stage Miller capacitor group M11 One end of the clock forms the fourth path of the correlated double sampling circuit; the first path and the third path form a "ping" structure, and the second path and the fourth path form a "pong" structure; In the stage, the "ping" structure performs sampling and inputs the signal to the second stage amplifier G m2 ; "Pong" structure and sampling common mode voltage V icm2 The input port is connected to reset; stage, the "ping" structure and the sampling common mode voltage V icm2 The input port is connected to reset, the "pong" structure is sampled, and the signal is input to the second stage amplifier G m2 ; C in the first-stage Miller capacitor group M10 One end is connected to the second stage amplifier G m2 The first-stage Miller capacitor group C M10 The other end is connected to the output stage amplifier G m4 Output; C in the first-stage Miller capacitor group M11 One end is connected to the second stage amplifier G m2 The first-stage Miller capacitor group C M11 The other end is connected to ground.

3. A novel chopper-correlated double sampling stabilized multi-path amplifier circuit as claimed in claim 1, characterized in that: The G m1 The offset calibration circuit includes a dynamic comparator, a successive comparison logic generation circuit and a current-type DAC; the input of the dynamic comparator is connected to the first-stage amplifier G m1 The output of the successive comparison logic generation circuit receives the output of the dynamic comparator and generates a corresponding calibration code input to the current-type DAC; the output of the current-type DAC is connected to the first-stage amplifier G m1 Cal port of the 4. According to claim 2, a novel chopper-correlated double sampling stabilized multi-path amplifier circuit is characterized in that: The working timing of the correlated double sampling circuit includes: Stage and stage, in stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C of the double sampling capacitor group cds2 and sampling switch SW6 and sampling common mode voltage V icm2 The input port is connected, then V ip for: （1） Among them, V in is the analog input signal, V os 、V n Respectively represent the first stage amplifier G m1 Input offset voltage and input equivalent noise, A1 is the first stage amplifier G m1 gain; Phase C cds2 The charge Q cds2 for: （2） Where V icm2 is the sampling input common mode voltage; stage, the input of the correlated double sampling circuit is V ip The signal of the port passes through the capacitor C in the double sampling capacitor group cds2 and the sampling switch SW2 and the capacitor C in the first-stage Miller capacitor group M10 One end and the second stage amplifier G m2 The input is connected; due to the capacitor C in the first-stage Miller capacitor group M10 Connected across the second stage amplifier G m2 The input and output stages of the amplifier G m4 The output end of the amplifier is regarded as the second-stage amplifier G according to Miller's equivalent theorem. m2 The input terminal is connected to C M1a =(1+A2×A4)C M10 The sampling capacitor, output stage amplifier G m4 The output terminal is connected to C M1b =A2×A4 / (1+A2×A4)C M10 The load capacitance of A2 and A4 are respectively the second stage amplifier G m2 and output stage amplifier G m4 Gain; According to the charge conservation theorem, Phase C cds2 and C M1a The sum of the charges on Phase C cds2 The charges on are equal, that is: （3） in = ,for Stage Capacitor C M1a The charge on V cs is the capacitance C M1a The voltage on = for Stage Capacitor C cds2 Substituting these two charges into equation (3), we can get: （4） exist stage, the chopper circuit CH1 exchanges V in The polarity of , therefore: （5） Combining equations (1), (4) and (5), we get: （6） From the numerator of formula (6), we can see that the input signal V in The transfer function is 1+z -1 , is a low-pass function; input equivalent noise V n The transfer function is 1-z -1 , is a high-pass function; input offset voltage V os are canceled out; thus it is proved that the proposed correlated double sampling circuit can filter out and reduce the input equivalent noise and offset voltage, thereby suppressing the output ripple.

5. A novel chopper-correlated double sampling stabilized multi-path amplifier circuit as claimed in claim 1, characterized in that: By combining the advantages of chopping technology and correlated double sampling technology, the high-pass performance of the new chopping correlated double sampling circuit is used to suppress the output ripple, and the offset calibration technology is used to further reduce the output ripple voltage while ensuring the stability of the CSMP architecture.

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