System capable of achieving impedance matching

Abstract

The invention provides a system capable of achieving impedance matching. The system comprises a primary coil, a second bonding wire and a secondary coil, wherein the primary coil comprises a series combination of a first bonding wire and a first capacitor which are connected in series; the first end of the series combination is coupled to the first end of the primary coil. The first end of the second bonding wire is coupled with the first end of the primary coil, and the second end of the second bonding wire is coupled with the second end of the series combination. The first end of the secondary coil is coupled to an output end.

Description

Technical Field

[0001] The present invention relates to a system capable of achieving impedance matching, and in particular to a bonding wire system capable of achieving impedance matching. Background Art

[0002] A transformer is a device that transfers energy from one circuit to another through electromagnetic coupling. Its main purpose is to transform voltage, change impedance and separate circuits. In power transmission, transformers play an important role. For example, in radio frequency circuits, transformers are often used for impedance matching between differential circuits.

[0003] The transformer usually includes two separate and corresponding inductors, which can be implemented on a semiconductor chip and coupled to the system load (such as an amplifier) ​​through bonding wires. However, the bonding wires will generate additional inductive impedance, thereby increasing the impedance matching requirements of the system. Summary of the invention

[0004] The present invention provides a system (or "system") capable of achieving impedance matching, which includes a primary coil, a series combination including a first bonding wire and a first capacitor connected in series, a second bonding wire, and a secondary coil. The primary coil has a first end and a second end. A first end of the first series combination is coupled to the first end of the primary coil. A first end of the second bonding wire is coupled to the first end of the primary coil, and a second end of the second bonding wire is coupled to a second end of the first series combination. The secondary coil has a first end and a second end, and the first end of the secondary coil is coupled to an output end.

[0005] The present invention further provides a system (or "system") capable of achieving impedance matching, which includes a primary coil, a first bonding wire, a first series combination including a second bonding wire and a first capacitor connected in series, a second series combination including a third wire and a second capacitor connected in series, a fourth bonding wire, and a secondary coil. The primary coil has a first end and a second end. A first end of the first bonding wire is coupled to the first end of the primary coil. A first end of the first series combination is coupled to the first end of the primary coil. A first end of the second series combination is coupled to the second end of the primary coil, and a second end of the second series combination is coupled to a second end of the first bonding wire. A first end of the fourth bonding wire is coupled to the second end of the primary coil, and a second end of the fourth bonding wire is coupled to the second end of the first series combination. The secondary coil has a first end and a second end, and the first end of the secondary coil is coupled to an output end.

[0006] The present invention further provides a system (or "system") capable of achieving impedance matching, which includes a primary coil, a first series combination including a first wiring and a first capacitor connected in series, a second wiring, and a secondary coil. The primary coil has a first end and a second end. A first end of the first series combination is coupled to the first end of the primary coil. A first end of the second wiring is coupled to the first end of the primary coil, and a second end of the second wiring is coupled to a second end of the first series combination. The secondary coil has a first end and a second end, and the first end of the secondary coil is coupled to an output end.

[0007] The present invention further provides a system (or "system") capable of achieving impedance matching, which includes a primary coil, a first routing line, a first series combination including a second routing line and a first capacitor connected in series, a second series combination including a third routing line and a second capacitor connected in series, a fourth routing line, and a secondary coil. The primary coil has a first end and a second end. A first end of the first routing line is coupled to the first end of the primary coil. A first end of the first series combination is coupled to the first end of the primary coil. A first end of the second series combination is coupled to the second end of the primary coil, and a second end of the second series combination is coupled to a second end of the first routing line. A first end of the fourth routing line is coupled to the second end of the primary coil, and a second end of the fourth routing line is coupled to the second end of the first series combination. The secondary coil has a first end and a second end, and the first end of the secondary coil is coupled to an output end. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of a system in an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a schematic diagram of a system in another embodiment of the present invention.

[0010] Figure 3A-3C FIG. 4 is a schematic diagram of a system in another embodiment of the present invention.

[0011] Figure 4A-4D FIG. 4 is a schematic diagram of a system in another embodiment of the present invention.

[0012] Explanation of symbols:

[0013] 10: First chip

[0014] 20: Second chip

[0015] 22, 24: Routing

[0016] 30: Amplifier

[0017] 100, 200, 301-303, 401-404: System

[0018] BW1-BW4: Bonding wires

[0019] C1, C2: capacitors

[0020] P1-P4, Q1-Q4: Solder pads

[0021] O1-O2: Solder pad / output terminal

[0022] TR: Transformer

[0023] L1: Primary coil

[0024] L2: Secondary coil

[0025] CT: Center tap

[0026] SW1, SW2: switches DETAILED DESCRIPTION

[0027] Figure 1 FIG. 1 is a schematic diagram of a system 100 according to an embodiment of the present invention. Figure 2 FIG. 2 is a schematic diagram of a system 200 according to another embodiment of the present invention. Figure 3A-3C Schematic diagram of systems 301 - 303 in another embodiment of the present invention. Figure 4A-4D Schematic diagram of systems 401 - 404 in another embodiment of the present invention.

[0028] like Figure 1 As shown, the system 100 includes a primary coil L1, a secondary coil L2, a first series combination and a bonding wire BW2, wherein the first series combination includes a bonding wire BW1 and a capacitor C1 connected in series. A first end of the first series combination is coupled to a first end of the primary coil L1, a first end of the bonding wire BW2 is also coupled to a first end of the primary coil L1, a second end of the bonding wire BW2 is coupled to a second end of the first series combination, and a first end of the secondary coil L2 is coupled to an output terminal O1. In terms of the configuration of the bonding wire BW1 and the capacitor C1 in the first series combination, Figure 1 In an embodiment, a first end of the bonding wire BW1 is coupled to a first end of the primary coil L1, a second end of the bonding wire BW1 is coupled to a first end of the capacitor C1, and a second end of the capacitor C1 is coupled to a second end of the bonding wire BW2. Thus, the bonding wire BW1 and the capacitor C1 in the first series combination can jointly generate a capacitive impedance, and this capacitive impedance can reduce an inductive impedance generated by the bonding wire BW2. In some embodiments, the capacitive impedance jointly generated by the bonding wire BW1 and the capacitor C1 in the first series combination can offset the inductive impedance generated by the bonding wire BW2.

[0029] In some embodiments, Figure 1The system 100 shown may also include a bonding wire BW3 and a second series combination, wherein the second series combination includes a bonding wire BW4 and a capacitor C2 connected in series. A first end of the bonding wire BW3 is coupled to a second end of the primary coil L1, a first end of the second series combination is coupled to a second end of the primary coil L1, and a second end of the second series combination is coupled to a second end of the bonding wire BW3. Figure 1 In the embodiment of the present invention, the first end of the bonding wire BW4 is coupled to the second end of the primary coil L1, the second end of the bonding wire BW4 is coupled to the first end of the capacitor C2, and the second end of the capacitor C2 is coupled to the second end of the bonding wire BW3. In this way, the bonding wire BW4 and the capacitor C2 in the second series combination can jointly generate a capacitive impedance, and this capacitive impedance can reduce an inductive impedance generated by the bonding wire BW3. In some embodiments, the capacitive impedance jointly generated by the bonding wire BW4 and the capacitor C2 in the second series combination can offset the inductive impedance generated by the bonding wire BW3.

[0030] In the present invention, Figure 1 The system 100 shown in the figure includes a first chip 10 and a second chip 20. A transformer TR is disposed on the first chip 10, which includes the primary coil L1 and the secondary coil L2. The primary coil L1 has a middle tap CT. Figure 1 As shown, the middle tap CT is drawn from the middle of the primary coil L1. In addition, the middle tap CT can be coupled to a power supply voltage (not shown). The secondary coil L2 is disposed near the primary coil L1 so that the primary coil L1 and the secondary coil L2 are mutually inductive, thereby outputting an induced current. In addition, the bonding wires BW1, BW2, BW3, and BW4 are respectively connected between the first chip 10 and the second chip 20. Further, in Figure 1In the illustrated system 100, the first wafer 10 may include two pads P1 and P2, and the second wafer 20 may include four pads Q1-Q4, wherein the first end and the second end of the bonding wire BW1 are respectively connected to the bonding pad P1 of the first wafer 10 and the bonding pad Q1 of the second wafer 20, the first end and the second end of the bonding wire BW2 are respectively connected to the bonding pad P1 of the first wafer 10 and the bonding pad Q2 of the second wafer 20, the first end and the second end of the bonding wire BW3 are respectively connected to the bonding pad P2 of the first wafer 10 and the bonding pad Q3 of the second wafer 20, and the first end and the second end of the bonding wire BW4 are respectively connected to the bonding pad P2 of the first wafer 10 and the bonding pad Q4 of the second wafer 20. In other words, the bonding wires BW1 and BW2 share the bonding pad P1 when connected to the first wafer 10, the bonding wires BW3 and BW4 share the bonding pad P2 when connected to the first wafer 10, and the bonding wires BW1-BW4 are respectively connected to the second wafer 20 via dedicated bonding pads Q1-Q4. In other embodiments, the bonding wires BW1 and BW2 may respectively use two separate pads connected by routing when connected to the first chip 10, instead of the common pad P1, and the bonding wires BW3 and BW4 may respectively use two other separate pads connected by routing when connected to the first chip 10, instead of the common pad P2.

[0031] exist Figure 1 In the system 100 shown, the first chip 10 further includes two pads O1 and O2 as output terminals O1 and O2, a first end of the primary coil L1 is coupled to the first ends of the bonding wires BW1 and BW2 through the pad P1, a second end of the primary coil L1 is coupled to the first ends of the bonding wires BW3 and BW4 through the pad P2, a first end of the secondary coil L2 is coupled to the pad O1, and a second end of the secondary coil L2 is coupled to the pad O2. Figure 1 In the embodiment, the first end of capacitor C1 is coupled to pad Q1 of second chip 20 (that is, coupled to pad P1 of first chip 10 through bonding wire BW1), the second end of capacitor C1 is coupled to pad Q2 of second chip 20 (that is, coupled to pad P1 of first chip 10 through bonding wire BW2), the first end of capacitor C2 is coupled to pad Q4 of second chip 20 (that is, coupled to pad P2 of first chip 10 through bonding wire BW4), and the second end of capacitor C2 is coupled to pad Q3 of second chip 20 (that is, coupled to pad P2 of first chip 10 through bonding wire BW3). Pad Q1 of second chip 20 is coupled to pad Q2 through capacitor C1, and pad Q3 of second chip 20 is coupled to pad Q4 through capacitor C2.

[0032] In some embodiments, Figure 1The system 100 shown in the figure can be applied to an architecture using differential signals, for example. Therefore, the system 100 can also include a trace 22 and a trace 24. The trace 22 and the trace 24 can be coupled to a load of the system 100. Figure 1 For the embodiment of the present invention, the load of the system 100 is, for example, an amplifier 30, the first end of the trace 22 is coupled to the second end of the bonding wire BW1, and the second end of the trace 22 is coupled to the amplifier 30, the first end of the trace 24 is coupled to the second end of the bonding wire BW4, and the second end of the trace 24 is coupled to the amplifier 30. In other words, the system 100 is coupled to the amplifier 30 via the trace 22 and the trace 24, and the amplifier 30 is, for example, a differential amplifier, and the differential signal is transmitted via the trace 22 and the trace 24. The first end of the amplifier 30 is coupled to the second end of the bonding wire BW1 via the trace 22, and the second end of the amplifier 30 is coupled to the second end of the bonding wire BW4 via the trace 24. Further, in Figure 1 In the system 100 shown, the trace 22 is coupled to the bonding wire BW1 through the capacitor C1, for example, and the trace 24 is coupled to the bonding wire BW4 through the capacitor C2, for example. In this way, the bonding wires and capacitors in the system 100 can be symmetrically arranged, and the impedance from the second end of the trace 22 to the first end of the trace 22 is equal to the impedance from the second end of the trace 24 to the first end of the trace 24, so that the system 100 can operate smoothly when applied to an architecture using differential signals. In addition, Figure 2 The system 200 shown can also be applied to a structure using differential signals, that is, the system 200 can also be coupled to the amplifier 30 via the traces 22 and 24. Further, the second ends of the bonding wires BW1, BW2, BW3, and BW4 can receive the RF signal from the amplifier 30, that is, the second ends of the bonding wires BW1, BW2, BW3, and BW4 can serve as the input ends of the RF signal.

[0033] Figure 2 The system 200 shown is Figure 1 The system 100 shown in FIG. 1 is similar, with the main difference being that, in terms of the configuration of the bonding wire BW1 and the capacitor C1 in the first series combination, Figure 2 In the embodiment, the first end of the capacitor C1 is coupled to the first end of the primary coil L1, the second end of the capacitor C1 is coupled to the first end of the bonding wire BW1, and the second end of the bonding wire BW1 is coupled to the second end of the bonding wire BW2. In this way, the capacitor C1 and the bonding wire BW1 in the first series combination can jointly generate a capacitive impedance, and this capacitive impedance can reduce an inductive impedance generated by the bonding wire BW2. In some embodiments, the capacitive impedance jointly generated by the capacitor C1 and the bonding wire BW1 in the first series combination can offset the inductive impedance generated by the bonding wire BW2. In addition, with respect to the configuration of the bonding wire BW4 and the capacitor C2 in the second series combination, in Figure 2In the embodiment of the present invention, the first end of the capacitor C2 is coupled to the second end of the primary coil L1, the second end of the capacitor C2 is coupled to the first end of the bonding wire BW4, and the second end of the bonding wire BW4 is coupled to the second end of the bonding wire BW3. In this way, the capacitor C2 and the bonding wire BW4 in the second series combination can jointly generate a capacitive impedance, and this capacitive impedance can reduce an inductive impedance generated by the bonding wire BW3. In some embodiments, the capacitive impedance jointly generated by the capacitor C2 and the bonding wire BW4 in the second series combination can offset the inductive impedance generated by the bonding wire BW3.

[0034] On the other hand, Figure 2 In the illustrated system 200, the first chip 10 may include four pads P1-P4, and the second chip 20 may include two pads Q1 and Q2, wherein the first end and the second end of the bonding wire BW1 are respectively connected to the bonding pad P1 of the first chip 10 and the bonding pad Q1 of the second chip 20, the first end and the second end of the bonding wire BW2 are respectively connected to the bonding pad P2 of the first chip 10 and the bonding pad Q1 of the second chip 20, the first end and the second end of the bonding wire BW3 are respectively connected to the bonding pad P3 of the first chip 10 and the bonding pad Q2 of the second chip 20, and the first end and the second end of the bonding wire BW4 are respectively connected to the bonding pad P4 of the first chip 10 and the bonding pad Q2 of the second chip 20. In other words, the bonding wires BW1-BW4 are connected to the first chip 10 via the dedicated pads P1-P4, respectively, the bonding wires BW1 and BW2 share the bonding pad Q1 when connected to the second chip 20, and the bonding wires BW3 and BW4 share the bonding pad Q2 when connected to the second chip 20. In other embodiments, the bonding wires BW1 and BW2 may respectively use two separate pads connected by routing when connected to the second chip 20, instead of the common pad Q1, and the bonding wires BW3 and BW4 may respectively use two other separate pads connected by routing when connected to the second chip 20, instead of the common pad Q2.

[0035] exist Figure 2 In the system 200 shown, the first chip 10 further includes two pads O1 and O2 as output terminals O1 and O2, the first end of the primary coil L1 is coupled to the first end of the bonding wire BW1 through the pad P1 and to the first end of the bonding wire BW2 through the pad P2, the second end of the primary coil L1 is coupled to the first end of the bonding wire BW3 through the pad P3 and to the first end of the bonding wire BW4 through the pad P4, the first end of the secondary coil L2 is coupled to the pad O1, and the second end of the secondary coil L2 is coupled to the pad O2. In addition, Figure 2In the embodiment, the first end of the capacitor C1 is coupled to the pad P2 of the first chip 10 (that is, it can be coupled to the pad Q1 of the second chip 20 through the bonding wire BW2), the second end of the capacitor C1 is coupled to the pad P1 of the first chip 10 (that is, it can be coupled to the pad Q1 of the second chip 20 through the bonding wire BW1), the first end of the capacitor C2 is coupled to the pad P3 of the first chip 10 (that is, it can be coupled to the pad Q2 of the second chip 20 through the bonding wire BW3), and the second end of the capacitor C2 is coupled to the pad P4 of the first chip 10 (that is, it can be coupled to the pad Q2 of the second chip 20 through the bonding wire BW4).

[0036] Figure 3A-3C The systems 301-303 and Figure 4A-4D The systems 401-404 shown are compared to Figure 1 The system 100 shown has the following differences: Figure 3A-3C The systems 301-303 and Figure 4A-4D The bonding wire BW2 and capacitor C1, bonding wire BW3 and capacitor C2 in the systems 401-404 are arranged in a cross-shaped manner, so that the impedance matching result can be changed to meet specific impedance requirements, which will be further described below. Figure 3A-3C and Figure 4A-4D As shown, systems 301-303 and systems 401-404 respectively include a primary coil L1, a secondary coil L2, a bonding wire BW1, a first series combination, a second series combination, and a bonding wire BW4, wherein the first series combination includes a bonding wire BW2 and a capacitor C1 connected in series, and the second series combination includes a bonding wire BW3 and a capacitor C2 connected in series. A first end of the bonding wire BW1 is coupled to a first end of the primary coil L1, a first end of the first series combination is coupled to a first end of the primary coil L1, a first end of the second series combination is coupled to a second end of the primary coil L1, a second end of the second series combination is coupled to a second end of the bonding wire BW1, a first end of the bonding wire BW4 is coupled to a second end of the primary coil L1, and a second end of the bonding wire BW4 is coupled to a second end of the first series combination, and a first end of the secondary coil L2 is coupled to an output end O1.

[0037] Among them, Figure 3A In the system 301 shown, with respect to the configuration of the bonding wire BW2 and the capacitor C1 in the first series combination, and the configuration of the bonding wire BW3 and the capacitor C2 in the second series combination, the first end of the bonding wire BW2 is coupled to the first end of the primary coil L1, the second end of the bonding wire BW2 is coupled to the first end of the capacitor C1, the second end of the capacitor C1 is coupled to the second end of the bonding wire BW4, the first end of the bonding wire BW3 is coupled to the second end of the primary coil L1, the second end of the bonding wire BW3 is coupled to the first end of the capacitor C2, and the second end of the capacitor C2 is coupled to the second end of the bonding wire BW1, so as to form a transmission line crossing configuration.

[0038] Furthermore, in Figure 3A In the system 301 shown, the first end of the capacitor C1 is coupled to the pad Q2 of the second chip 20 (that is, coupled to the pad P1 of the first chip 10 through the bonding wire BW2), the second end of the capacitor C1 is coupled to the pad Q4 of the second chip 20 (that is, coupled to the pad P2 of the first chip 10 through the bonding wire BW4), the first end of the capacitor C2 is coupled to the pad Q3 of the second chip 20 (that is, coupled to the pad P2 of the first chip 10 through the bonding wire BW3), and the second end of the capacitor C2 is coupled to the pad Q1 of the second chip 20 (that is, coupled to the pad P1 of the first chip 10 through the bonding wire BW1). In addition, the pad Q1 of the second chip 20 is coupled to the pad Q3 through the capacitor C2, and the pad Q2 of the second chip 20 is coupled to the pad Q4 through the capacitor C1.

[0039] In some embodiments, Figure 3A The system 301 shown can be applied to an architecture using differential signals, for example. Therefore, the system 301 can also include a trace 22 and a trace 24. The trace 22 and the trace 24 can be coupled to a load of the system 301. Figure 3A For the embodiment of the present invention, the load of the system 301 is, for example, an amplifier 30, the first end of the trace 22 is coupled to the second end of the bonding wire BW1, and the second end of the trace 22 is coupled to the amplifier 30, the first end of the trace 24 is coupled to the second end of the bonding wire BW4, and the second end of the trace 24 is coupled to the amplifier 30. In other words, the system 301 is coupled to the amplifier 30 through the traces 22 and 24, and the amplifier 30 is, for example, a differential amplifier, and the differential signal is transmitted through the traces 22 and 24. The first end of the amplifier 30 is coupled to the second end of the bonding wire BW1 through the trace 22, and the second end of the amplifier 30 is coupled to the second end of the bonding wire BW4 through the trace 24. In this way, the bonding wires and capacitors in the system 301 can be symmetrically arranged, and the impedance from the second end of the trace 22 to the first end of the trace 22 is equal to the impedance from the second end of the trace 24 to the first end of the trace 24, so that the system 301 can operate smoothly when applied to an architecture using differential signals. Figure 4A-4D The systems 401-404 shown can also be applied to the architecture using differential signals, that is, the systems 302-303 and the systems 401-404 can also be coupled to the amplifier 30 via the traces 22 and 24. Further, the second ends of the bonding wires BW1, BW2, BW3, and BW4 can receive the RF signal from the amplifier 30, that is, the second ends of the bonding wires BW1, BW2, BW3, and BW4 can serve as the input ends of the RF signal.

[0040] Figure 3B The system 302 shown is Figure 3A The system 301 is similar to the system 302 shown in FIG. 3 , but the main difference is that the system 302 further includes a switch SW1 and a switch SW2, wherein the switch SW1 is connected in series with a capacitor C1, and the switch SW2 is connected in series with a capacitor C2, so that the conduction degree of the switch SW1 and the switch SW2 can be adjusted to change the impedance in the system 302. Figure 3B In the system 302 shown, capacitor C1 is connected in series between bonding wire BW2 and switch SW1, and capacitor C2 is connected in series between bonding wire BW3 and switch SW2. Figure 3B In the system 302 shown, the first end of the capacitor C1 is coupled to the bonding pad Q2 of the second chip 20 (that is, coupled to the bonding pad P1 of the first chip 10 through the bonding wire BW2), the second end of the capacitor C1 is coupled to the bonding pad Q4 of the second chip 20 through the switch SW1 (that is, coupled to the bonding pad P2 of the first chip 10 through the switch SW1 and the bonding wire BW4), the first end of the capacitor C2 is coupled to the bonding pad Q3 of the second chip 20 (that is, coupled to the bonding pad P2 of the first chip 10 through the bonding wire BW3), and the second end of the capacitor C2 is coupled to the bonding pad Q1 of the second chip 20 through the switch SW2 (that is, coupled to the bonding pad P1 of the first chip 10 through the switch SW2 and the bonding wire BW1). In addition, the bonding pad Q1 of the second chip 20 is coupled to the bonding pad Q3 through the switch SW2 and the capacitor C2, and the bonding pad Q2 of the second chip 20 is coupled to the bonding pad Q4 through the capacitor C1 and the switch SW1.

[0041] Figure 3C The system 303 shown is Figure 3B The system 302 shown is similar, the main difference is that the configuration positions of the switch SW1 and the capacitor C1 can be swapped, and the configuration positions of the switch SW2 and the capacitor C2 can be swapped. Figure 3C In the system 303 shown, the switch SW1 is connected in series between the bonding wire BW2 and the capacitor C1, and the switch SW2 is connected in series between the bonding wire BW3 and the capacitor C2. Figure 3CIn the system 303 shown, the first end of the capacitor C1 is coupled to the bonding pad Q2 of the second chip 20 through the switch SW1 (that is, coupled to the bonding pad P1 of the first chip 10 through the switch SW1 and the bonding wire BW2), the second end of the capacitor C1 is coupled to the bonding pad Q4 of the second chip 20 (that is, coupled to the bonding pad P2 of the first chip 10 through the bonding wire BW4), the first end of the capacitor C2 is coupled to the bonding pad Q3 of the second chip 20 through the switch SW2 (that is, coupled to the bonding pad P2 of the first chip 10 through the switch SW2 and the bonding wire BW3), and the second end of the capacitor C2 is coupled to the bonding pad Q1 of the second chip 20 (that is, coupled to the bonding pad P1 of the first chip 10 through the bonding wire BW1). In addition, the bonding pad Q1 of the second chip 20 is coupled to the bonding pad Q3 through the capacitor C2 and the switch SW2, and the bonding pad Q2 of the second chip 20 is coupled to the bonding pad Q4 through the switch SW1 and the capacitor C1.

[0042] Figure 4A The system 401 shown is Figure 3A The system 301 shown is similar, with the main difference being that, with respect to the configuration of the bonding wire BW2 and the capacitor C1 in the first series combination, and the configuration of the bonding wire BW3 and the capacitor C2 in the second series combination, the first end of the capacitor C1 is coupled to the first end of the primary coil L1, the second end of the capacitor C1 is coupled to the first end of the bonding wire BW2, the second end of the bonding wire BW2 is coupled to the second end of the bonding wire BW4, the first end of the capacitor C2 is coupled to the second end of the primary coil L1, the second end of the capacitor C2 is coupled to the first end of the bonding wire BW3, and the second end of the bonding wire BW3 is coupled to the second end of the bonding wire BW1 to form a transmission line crossing configuration.

[0043] Furthermore, in Figure 4A In the system 401 shown, the first end of the capacitor C1 is coupled to the bonding pad P1 of the first chip 10 (that is, coupled to the bonding pad Q1 of the second chip 20 through the bonding wire BW1), the second end of the capacitor C1 is coupled to the bonding pad P2 of the first chip 10 (that is, coupled to the bonding pad Q2 of the second chip 20 through the bonding wire BW2), the first end of the capacitor C2 is coupled to the bonding pad P4 of the first chip 10 (that is, coupled to the bonding pad Q4 of the second chip 20 through the bonding wire BW4), and the second end of the capacitor C2 is coupled to the bonding pad P3 of the first chip 10 (that is, coupled to the bonding pad Q3 of the second chip 20 through the bonding wire BW1). In addition, the bonding pads Q1 and Q3 of the second chip 20 are coupled to each other, and the bonding pads Q2 and Q4 of the second chip 20 are coupled to each other.

[0044] Figure 4B The system 402 shown is Figure 4AThe system 402 is similar to the system 401 shown in the figure, and the main difference is that the system 402 further includes a switch SW1 and a switch SW2, wherein the switch SW1 is connected in series with a capacitor C1, and the switch SW2 is connected in series with a capacitor C2, so that the conduction degree of the switch SW1 and the switch SW2 can be adjusted to change the impedance in the system 402. Figure 4B In the system 402 shown, capacitor C1 is connected in series between bonding wire BW2 and switch SW1, and capacitor C2 is connected in series between bonding wire BW3 and switch SW2. Figure 4B In the system 402 shown, the first end of the capacitor C1 is coupled to the bonding pad P1 of the first chip 10 through the switch SW1 (that is, coupled to the bonding pad Q1 of the second chip 20 through the switch SW1 and the bonding wire BW1), the second end of the capacitor C1 is coupled to the bonding pad P2 of the first chip 10 (that is, coupled to the bonding pad Q2 of the second chip 20 through the bonding wire BW2), the first end of the capacitor C2 is coupled to the bonding pad P4 of the first chip 10 through the switch SW2 (that is, coupled to the bonding pad Q4 of the second chip 20 through the switch SW2 and the bonding wire BW4), and the second end of the capacitor C2 is coupled to the bonding pad P3 of the first chip 10 (that is, coupled to the bonding pad Q3 of the second chip 20 through the bonding wire BW3). In addition, the bonding pads Q1 and Q3 of the second chip 20 are coupled to each other, and the bonding pads Q2 and Q4 of the second chip 20 are coupled to each other.

[0045] Figure 4C The system 403 shown is Figure 4B The system 402 shown is similar, the main difference is that the configuration positions of the switch SW1 and the capacitor C1 can be swapped, and the configuration positions of the switch SW2 and the capacitor C2 can be swapped. Figure 4C In the system 403 shown, the switch SW1 is connected in series between the bonding wire BW2 and the capacitor C1, and the switch SW2 is connected in series between the bonding wire BW3 and the capacitor C2. Figure 4C In the system 403 shown, the first end of the capacitor C1 is coupled to the bonding pad P1 of the first chip 10 (that is, coupled to the bonding pad Q1 of the second chip 20 through the bonding wire BW1), the second end of the capacitor C1 is coupled to the bonding pad P2 of the first chip 10 through the switch SW1 (that is, coupled to the bonding pad Q2 of the second chip 20 through the switch SW1 and the bonding wire BW2), the first end of the capacitor C2 is coupled to the bonding pad P4 of the first chip 10 (that is, coupled to the bonding pad Q4 of the second chip 20 through the bonding wire BW4), and the second end of the capacitor C2 is coupled to the bonding pad P3 of the first chip 10 through the switch SW2 (that is, coupled to the bonding pad Q3 of the second chip 20 through the switch SW2 and the bonding wire BW3). In addition, the bonding pads Q1 and Q3 of the second chip 20 are coupled to each other, and the bonding pads Q2 and Q4 of the second chip 20 are coupled to each other.

[0046] Figure 4D The system 404 shown is Figure 4A The system 404 is similar to the system 401 shown, with the main difference being that the system 404 further includes a switch SW1 and a switch SW2, wherein a first end of the switch SW1 is coupled to a second end of BW1, and a second end of the switch SW1 is coupled to a second end of BW3, a first end of the switch SW2 is coupled to a second end of BW4, and a second end of the switch SW2 is coupled to a second end of BW2, so that the conduction degree of the switch SW1 and the switch SW2 can be adjusted to change the impedance in the system 404. Figure 4D In the system 404 shown, the first end of the capacitor C1 is coupled to the bonding pad P1 of the first chip 10 (that is, coupled to the bonding pad Q1 of the second chip 20 via the bonding wire BW1), the second end of the capacitor C1 is coupled to the bonding pad P2 of the first chip 10 (that is, coupled to the bonding pad Q2 of the second chip 20 via the bonding wire BW2), the first end of the capacitor C2 is coupled to the bonding pad P4 of the first chip 10 (that is, coupled to the bonding pad Q4 of the second chip 20 via the bonding wire BW4), and the second end of the capacitor C2 is coupled to the bonding pad P3 of the first chip 10 (that is, coupled to the bonding pad Q3 of the second chip 20 via the bonding wire BW3). In addition, the bonding pad Q1 of the second chip 20 is coupled to the bonding pad Q3 via the switch SW1, and the bonding pad Q2 of the second chip 20 is coupled to the bonding pad Q4 via the switch SW2.

[0047] The systems 302-303 and 402-404 shown in FIGS. 3B-3C and 4B-4D form a symmetrical structure at both ends of the primary coil L1, and when the systems 302-303 and 402-404 shown in FIGS. 3B-3C and 4B-4D are applied to a structure using a differential signal, in an operation mode, the conduction degree of the switch SW1 is the same as the conduction degree of the switch SW2. Further, in this operation mode, the impedance viewed from the second end of the trace 22 to the first end of the trace 22 and the impedance viewed from the second end of the trace 24 to the first end of the trace 24 can be changed as the conduction degrees of the switches SW1 and SW2 are adjusted. In this way, by making the conduction degree of switch SW1 the same as the conduction degree of switch SW2, the impedance seen from the second end of trace 22 to the first end of trace 22 is equal to the impedance seen from the second end of trace 24 to the first end of trace 24, thereby allowing systems 302-303 and 402-404 to operate smoothly when applied to an architecture using differential signals.

[0048] In the embodiments shown in FIGS. 1, 2, 3A-3C and 4A-4D of the present invention, bonding wires BW1-BW4 are connected across the first chip 10 and the second chip 20, so that the transformer TR and the amplifier 30 can communicate. In other embodiments of the present invention, when the first chip 10 and the second chip 20 are disposed on the same circuit board, the bonding wires BW1-BW4 in the embodiments shown in FIGS. 1, 2, 3A-3C and 4A-4D can also be replaced with routing wires to provide a signal path between the first chip 10 and the second chip 20.

[0049] In summary, the present invention provides a first signal path between two chips in the system through a series combination including a first bonding wire / line and a capacitor, and provides a second signal path between two chips in the system through a second bonding wire / line, so that the capacitive impedance of the first signal path can reduce the inductive impedance of the second signal path, thereby achieving the purpose of impedance matching. In addition, in the case of a specific impedance requirement, the bonding wire / line and the capacitor are configured in a cross manner, and the impedance matching result can be changed to meet the specific impedance requirement.

[0050] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the scope of the claims of the present invention should fall within the scope of the present invention.

Claims

1. A system capable of achieving impedance matching, characterized in that: It contains: A primary coil having a first end and a second end; A first series combination, comprising a first bonding wire and a first capacitor connected in series, wherein a first end of the first series combination is coupled to the first end of the primary coil; a second bonding wire, a first end of the second bonding wire coupled to the first end of the primary coil, and a second end of the second bonding wire coupled to a second end of the first series combination; and A secondary coil has a first end and a second end. The first end of the secondary coil is coupled to an output end.

2. The system according to claim 1, characterized in that A first end of the first bonding wire is coupled to the first end of the primary coil, a second end of the first bonding wire is coupled to a first end of the first capacitor, and a second end of the first capacitor is coupled to the second end of the second bonding wire.

3. The system according to claim 1, characterized in that A first end of the first capacitor is coupled to the first end of the primary coil, a second end of the first capacitor is coupled to a first end of the first bonding wire, and a second end of the first bonding wire is coupled to the second end of the second bonding wire.

4. The system according to claim 1, characterized in that It also includes: a third bonding wire, a first end of the third bonding wire being coupled to the second end of the primary coil; and A second series combination includes a fourth bonding wire and a second capacitor connected in series, a first end of the second series combination is coupled to the second end of the primary coil, and a second end of the second series combination is coupled to a second end of the third bonding wire.

5. The system according to claim 4, characterized in that A first end of the fourth bonding wire is coupled to the second end of the primary coil, a second end of the fourth bonding wire is coupled to a first end of the second capacitor, and a second end of the second capacitor is coupled to the second end of the third bonding wire.

6. The system according to claim 4, characterized in that A first end of the second capacitor is coupled to the second end of the primary coil, a second end of the second capacitor is coupled to a first end of the fourth bonding wire, and a second end of the fourth bonding wire is coupled to the second end of the third bonding wire.

7. The system according to claim 1, characterized in that The primary coil has a middle tap, and the middle tap is coupled to a power supply voltage.

8. The system according to claim 1, characterized in that The first bonding wire and the first capacitor jointly generate a capacitive impedance, and the second bonding wire generates an inductive impedance, and the capacitive impedance reduces the inductive impedance.

9. The system according to claim 1, characterized in that in: The first bonding wire is connected across a first chip and a second chip; Two first bonding pads are respectively located on the first chip and the second chip, and are respectively connected to a first end and a second end of the first bonding wire; and The second bonding wire is connected across the first chip and the second chip.

10. A system capable of achieving impedance matching, characterized in that: It contains: A primary coil having a first end and a second end; a first bonding wire, a first end of the first bonding wire being coupled to the first end of the primary coil A first series combination, comprising a second bonding wire and a first capacitor connected in series, wherein a first end of the first series combination is coupled to the first end of the primary coil; a second series combination, comprising a third bonding wire and a second capacitor connected in series, a first end of the second series combination coupled to the second end of the primary coil, and a second end of the second series combination coupled to a second end of the first bonding wire; a fourth bonding wire, a first end of the fourth bonding wire being coupled to the second end of the primary coil, and a second end of the fourth bonding wire being coupled to the second end of the first series combination; and A secondary coil has a first end and a second end. The first end of the secondary coil is coupled to an output end.

11. The system according to claim 10, characterized in that in: A first end of the second bonding wire is coupled to the first end of the primary coil, and a second end of the second bonding wire is coupled to a first end of the first capacitor; A second end of the first capacitor is coupled to the second end of the fourth bonding wire; A first end of the third bonding wire is coupled to the second end of the primary coil, and a second end of the third bonding wire is coupled to a first end of the second capacitor; and A second end of the second capacitor is coupled to the second end of the first bonding wire.

12. The system according to claim 11, characterized in that It also includes: a first switch connected in series with the first capacitor; and A second switch is connected in series with the second capacitor.

13. The system according to claim 10, characterized in that in: A first end of the first capacitor is coupled to the first end of the primary coil, and a second end of the first capacitor is coupled to a first end of the second bonding wire; A second end of the second bonding wire is coupled to the second end of the fourth bonding wire; A first end of the second capacitor is coupled to the second end of the primary coil, and a second end of the second capacitor is coupled to a first end of the third bonding wire; and A second end of the third bonding wire is coupled to the second end of the first bonding wire.

14. The system according to claim 13, characterized in that It also includes: a first switch connected in series with the first capacitor; and A second switch is connected in series with the second capacitor.

15. The system according to claim 13, characterized in that It also includes: a first switch, a first end of the first switch coupled to the second end of the first bonding wire, and a second end of the first switch coupled to the second end of the third bonding wire; and A second switch, wherein a first end of the second switch is coupled to the second end of the fourth bonding wire, and a second end of the second switch is coupled to the second end of the second bonding wire.

16. The system according to any one of claims 12, 14 and 15, characterized in that In one operation mode, the first switch and the second switch have the same conduction degree.

17. The system according to any one of claims 12, 14 and 15, characterized in that It also includes: a first trace, a first end of the first trace being coupled to the second end of the first bonding wire, and a second end of the first trace being coupled to an amplifier; a second routing line, wherein a first end of the first routing line is coupled to the second end of the fourth bonding wire, and a second end of the first routing line is coupled to the amplifier, wherein, in an operation mode, a first impedance viewed from the second end of the first routing line to the first end, and a second impedance viewed from the second end of the second routing line to the first end change as the conduction degree of the first switch and the second switch are adjusted.

18. The system according to claim 17, characterized in that The first impedance is equal to the second impedance.

19. A system capable of achieving impedance matching, characterized in that: It contains: A primary coil having a first end and a second end; A first series combination, comprising a first trace and a first capacitor connected in series, wherein a first end of the first series combination is coupled to the first end of the primary coil; a second wiring, a first end of the second wiring coupled to the first end of the primary coil, and a second end of the second wiring coupled to a second end of the first series combination; and A secondary coil has a first end and a second end. The first end of the secondary coil is coupled to an output end.

20. A system capable of achieving impedance matching, characterized in that: It contains: A primary coil having a first end and a second end; a first wiring, a first end of which is coupled to the first end of the primary coil; A first series combination, comprising a second trace and a first capacitor connected in series, wherein a first end of the first series combination is coupled to the first end of the primary coil; A second series combination, comprising a third wiring and a second capacitor connected in series, a first end of the second series combination coupled to the second end of the primary coil, and a second end of the second series combination coupled to a second end of the first wiring; a fourth wiring, a first end of the fourth wiring being coupled to the second end of the primary coil, and a second end of the fourth wiring being coupled to the second end of the first series combination; and A secondary coil has a first end and a second end. The first end of the secondary coil is coupled to an output end.

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