Multipath reference voltage generation circuit, analog-to-digital converter and receiver

Abstract

The embodiment of the invention provides a multi-channel reference voltage generation circuit, an analog-to-digital converter using the multi-channel reference voltage generation circuit and a receiver. The multi-path reference voltage generation circuit comprises a main-stage circuit and a copy-stage circuit, the main-stage circuit comprises a main-stage reference voltage generation module and a main-stage bias voltage filtering module, and the main-stage reference voltage generation module receives input reference voltage and generates first bias voltage and second bias voltage; the replica-stage circuit comprises a plurality of replica-stage reference voltage generation modules and a plurality of replica-stage bias voltage filtering modules, and each replica-stage reference voltage generation module receives the first bias voltage and the second bias voltage provided by the main-stage circuit and outputs a path of replica reference voltage, so that the replica-stage circuit can output multiple paths of reference voltages. According to the multi-path reference voltage generation circuit, one path of reference voltage can be copied into multiple paths of reference voltage, and meanwhile, the response time of the reference voltage of the sub analog-to-digital converter can be shortened.

Description

Technical Field

[0001] The present disclosure relates to high-speed communication, and in particular to a multi-channel reference voltage generating circuit and a time-interleaved analog-to-digital converter and a receiver using the multi-channel reference voltage generating circuit. Background Art

[0002] As data centers grow in their demand for high-speed communications, the communication rates of serial interfaces continue to increase, and the requirements for receiver performance are also getting higher and higher. Traditional receivers based on analog structures are difficult to meet the needs of current high-data-rate applications. Therefore, new receivers based on high-speed time-interleaved analog-to-digital converters are gradually becoming mainstream, and are generally used in high-speed communication systems of 10Gbps and above.

[0003] High-speed time-interleaved ADCs work together through multiple sub-ADCs to increase the overall sampling rate. Each sub-ADC samples the same analog signal at a different time phase and compares it with a reference voltage to generate a corresponding digital bit stream. Currently, the most advanced high-speed time-interleaved ADC solutions have adopted 64 or even 128 sub-ADCs.

[0004] In this architecture, the existing sub-ADCs use the same reference voltage. In order to avoid mutual interference between the sub-ADCs during the sampling process, each sub-ADC needs to be equipped with an additional reference voltage buffer to isolate the reference voltage used by it from the common reference voltage. This increases the design complexity and also leads to an increase in power consumption and area. Summary of the invention

[0005] In order to meet the requirements of sub-ADCs for reference voltage, it is necessary to design a reference voltage generating circuit which can suppress the interference of the reference voltage during the sampling and comparison process between sub-ADCs while reducing power consumption and area consumption, and is easy to implement and manufacture.

[0006] In view of the problems existing in the prior art, the embodiments of the present disclosure provide a multi-channel reference voltage generating circuit and a time-interleaved analog-to-digital converter and a receiver using the multi-channel reference voltage generating circuit.

[0007] According to a first aspect of the present disclosure, a multi-channel reference voltage generating circuit is provided, which includes a main-stage circuit and a replica-stage circuit, wherein the main-stage circuit includes a main-stage reference voltage generating module and a main-stage bias voltage filtering module, wherein the main-stage reference voltage generating module is used to receive an input reference voltage and generate a first bias voltage and a second bias voltage, and the main-stage bias voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage; and a replica-stage circuit, which includes a plurality of replica-stage reference voltage generating modules and a plurality of replica-stage bias voltage filtering modules, wherein each replica-stage reference voltage generating module receives the first bias voltage and the second bias voltage sent by the main-stage circuit, and outputs a replicated reference voltage, so that the replica-stage circuit outputs multiple replicated reference voltages, each replica-stage bias voltage filtering module is connected to the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage, and each replica-stage reference voltage generating module includes a source follower of an open-loop structure, wherein the multiple replicated reference voltages are the same as the input reference voltage. In addition, the primary reference voltage generating module can output a primary reference voltage which is the same as the input reference voltage.

[0008] In the multi-channel reference voltage generating circuit of the embodiment of the present disclosure, each sub-analog-to-digital converter can generate a separate reference voltage by replicating the bias voltage through a source follower, thereby preventing interference with the reference voltage. By setting a bias voltage filtering module for the bias voltage, the interference of the sub-analog-to-digital converter with the bias voltage is suppressed, thereby obtaining a more accurate replicated reference voltage.

[0009] Optionally, the primary reference voltage generation module includes an amplifier, whose in-phase input terminal receives the input reference voltage and whose output terminal outputs a first bias voltage; a source follower, which receives the first bias voltage and outputs a primary reference voltage, the primary reference voltage being a copy of the reference voltage, and the output primary reference voltage is input to the inverting input terminal of the amplifier. The above structure of the primary reference voltage generation module enables the amplifier to form a closed-loop control structure, ensuring that the primary reference voltage is the same as the input reference voltage.

[0010] Optionally, the source follower includes a first NMOS transistor (N-type metal oxide field effect transistor) and a second NMOS transistor, the gates of the first NMOS transistor and the second NMOS transistor are connected to the first bias voltage, the source of the second NMOS transistor is connected to the inverting input of the amplifier, and outputs a main reference voltage; a first PMOS transistor (P-type metal oxide field effect transistor) and a second PMOS transistor, the source of the first PMOS transistor is connected to the source of the first NMOS transistor, and its gate and drain are connected together to generate a second bias voltage, and its drain is connected to a current source, the source of the second PMOS transistor is connected to the source of the second NMOS transistor, and its gate is connected to the gate of the first PMOS transistor.

[0011] Through the above circuit structure, the primary reference voltage generating module of the embodiment of the present disclosure can generate a stable first bias voltage and a second bias voltage.

[0012] Optionally, each replica level reference voltage generating module includes a third NMOS transistor and a third PMOS transistor, wherein the gate of the third NMOS transistor is connected to the first bias voltage, its source is connected to the source of the third PMOS transistor and outputs a replicated reference voltage, and the gate of the third PMOS transistor is connected to the second bias voltage.

[0013] Each replica level reference voltage generation module of the disclosed embodiment only needs one NMOS transistor and one PMOS transistor to generate an independent reference voltage, thereby simplifying the circuit design and reducing power consumption and chip area. The first bias voltage and the second bias voltage can be used to determine the DC operating points of the NMOS transistor and the PMOS transistor in the replica level reference voltage generation module, respectively, to ensure that the replica level reference voltage is the same as the main level reference voltage.

[0014] Optionally, the primary bias voltage filter module includes first and second filter capacitors connected to the first and second bias voltages, respectively, and the first and second filter capacitors include capacitors formed by a combination of a MOS (Metal-Oxide-Semiconductor) capacitor and a MOM (Metal-Oxide-Metal) capacitor. This method of constructing capacitors can reduce the capacitor area. The filter capacitor can also use only MOS capacitors or MOM capacitors, but compared to using a combination of MOS and MOM capacitors, this method will increase the area of ​​the integrated circuit.

[0015] Optionally, each of the plurality of replica-level bias voltage filter modules comprises a third and a fourth filter capacitor respectively connected to the first and second bias voltages, and the third and the fourth filter capacitor comprise capacitors formed by a combination of a MOS capacitor and a MOM capacitor.

[0016] Optionally, the third and fourth filter capacitors are placed on a layout of a device for receiving multi-channel replicated reference voltages generated by the multi-channel reference voltage generating circuit.

[0017] Optionally, the multi-channel reference voltage generating circuit also includes a first overvoltage protection circuit, which includes a first comparator, whose non-inverting input terminal is connected to a reference power supply voltage, and whose inverting input terminal is connected to a first bias voltage, and the reference power supply voltage is less than the power supply voltage and is a certain proportion of the power supply voltage; a fourth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power supply voltage, and whose drain is connected to the drain of the second NMOS transistor; a fourth NMOS transistor, whose drain is connected to the drain of the second NMOS transistor, and whose gate is connected to the output terminal of the comparator, when the first bias voltage is lower than the reference power supply voltage, the fourth NMOS transistor is turned on and the fourth PMOS transistor is turned off.

[0018] Optionally, the multi-channel reference voltage generating circuit also includes a second overvoltage protection circuit, which includes a second comparator, whose non-inverting input terminal is connected to a reference power supply voltage, and whose inverting input terminal is connected to a first bias voltage, and the reference power supply voltage is less than the power supply voltage and is a certain proportion of the power supply voltage; a fifth PMOS transistor, whose gate is connected to the output terminal of the comparator, whose source is connected to the power supply voltage, and whose drain is connected to the drain of the third NMOS transistor; a fifth NMOS transistor, whose drain is connected to the drain of the third NMOS transistor, and whose gate is connected to the output terminal of the comparator, and when the first bias voltage is lower than the reference power supply voltage, the fifth NMOS transistor is turned on and the fifth PMOS transistor is turned off.

[0019] Optionally, the second NMOS transistor and the third NMOS transistor may use low-voltage MOS transistors. The fourth and fifth NMOS transistors may use high-voltage MOS transistors. The overvoltage protection circuit may enable the source follower to use a MOS transistor with a lower threshold voltage, increase the adjustment range of the reference voltage, and prevent the gate-drain voltage and gate-source voltage of the NMOS transistor from exceeding the maximum voltage required by the process.

[0020] Optionally, the ratio of the reference power supply voltage to the power supply voltage is between 0.35-0.8, for example, about two-thirds of the power supply voltage.

[0021] A second aspect of the present disclosure provides a time-interleaved analog-to-digital converter, which includes: one or more buffers for dividing an input high-speed data signal into multiple sub-data signals; multiple sub-analog-to-digital converters, each of which receives one of the multiple sub-data signals output by the one or more buffers and performs analog-to-digital conversion on it; and a multiple reference voltage generating circuit as described above, which generates multiple replicated reference voltages for providing a separate reference voltage for each of the multiple sub-analog-to-digital converters.

[0022] A third aspect of the present disclosure provides a receiver comprising a terminal for matching transmission line impedance, a continuous time linear equalizer, a variable gain amplifier, a time interleaved analog-to-digital converter as described above, and a digital back end.

[0023] It is not necessary to achieve all the advantages described above at the same time for any device implementing the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be realized and obtained by the structures indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0025] Figure 1 is a circuit block diagram of a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure;

[0026] Figure 2 is a circuit diagram of a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of an overvoltage protection circuit according to an embodiment of the present disclosure;

[0028] Figure 4 is a structural schematic diagram of an analog-to-digital converter using a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram of the structure of a receiver using a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not necessarily indicate a quantity restriction. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] Figure 1 The circuit block diagram of a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure is shown. The main stage circuit includes a main stage reference voltage generating module 101 and a main stage bias voltage filtering module 102. The main stage reference voltage generating module 101 receives the input of the reference voltage VREF, generates and sends a first bias voltage VNBIAS (indicating the bias voltage of NMOS) and a second bias voltage VPBIAS (indicating the bias voltage of PMOS) to the replica stage circuit. In addition, the first bias voltage VNBIAS and the second bias voltage VPBIAS are connected to the main stage bias voltage filtering module 102, which can be placed near the device receiving the multi-channel reference voltage, that is, located at its layout position for close coupling, which can refer to the layout position of the sub-analog-to-digital converter in this embodiment to suppress sampling noise. The main stage reference voltage generating module 101 may include an amplifier feedback module and a source follower. The amplifier feedback module forms a closed-loop control to generate a first bias voltage VNBIAS. The source follower generates a main stage reference voltage VREF0, which accurately replicates the reference voltage VREF and is transmitted to the amplifier feedback module. The amplifier feedback module enables the circuit to automatically adjust the first bias voltage to ensure the stability of the output primary reference voltage.

[0033] The replica stage circuit includes a plurality of replica stage reference voltage generating modules 111 and a plurality of replica stage bias voltage filtering modules 112. Each replica stage reference voltage generating module 111 includes a source follower of an open-loop structure, which is connected to a replica stage bias voltage filtering module 112. Each replica stage reference voltage generating module 111 receives a first bias voltage VNBIAS and a second bias voltage VPBIAS, and outputs a replicated reference voltage, so that N replica stage reference voltage generating modules 111 can output N reference voltages, namely VREF1 to VREFN.

[0034] The main bias voltage filter module 102 and the replica bias voltage filter module 112 may each include a filter capacitor, which filters the first bias voltage VNBIAS and the second bias voltage VPBIAS to reduce the ripple and interference of the bias voltage. The bias voltage filter module may be placed near a device that receives a reference voltage, such as at its layout position, so as to suppress the interference of the device to the bias voltage. For example, when the reference voltage output by the replica circuit is used to drive the sub-analog-to-digital converter, the main circuit, the replica circuit, and the sub-analog-to-digital converter are tightly coupled in the layout in sequence. If the output reference voltage of the main circuit is also used to drive the sub-analog-to-digital converter, it is similarly placed near the sub-analog-to-digital converter circuit.

[0035] Figure 2The circuit structure of a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure is more specifically shown. In the main circuit, a single reference voltage VREF is input to the non-inverting input terminal of the amplifier Amp1, and the first bias voltage output by the amplifier is represented by VNBIAS, which is connected to the gates of NMOS M1 and NMOS M2. The source of NMOS M1 is connected to the source of PMOS M3, and the source of NMOS M2 is connected to the source of PMOS M4, forming a push-pull source follower structure. The source of NMOS M2 is connected to the inverting input terminal of the amplifier Amp1. The source voltage of NMOS M2 is the copied main reference voltage VREF0. The gate and drain of PMOS M3 are connected together, and the second bias voltage here is represented by VPBIAS. The drain of PMOS M3 is connected to the common ground terminal via a current source, and the current source is used to provide a bias current to PMOS M3 to determine the DC operating point of PMOS M3. This DC operating point is also used for PMOS M4, PMOS M41 to PMOS M4N to ensure the stable operation of the MOS tube. The drain of PMOS M4 is connected to the common ground terminal. The gate of PMOS M3 is connected to the gate of PMOS M4. The input and output connection of amplifier Amp1 forms an amplifier feedback circuit, which adjusts the gate voltage of NMOS M2 through negative feedback. NMOS M1, NMOS M2, PMOS M1 and PMOS M2 form a push-pull source follower, which combines closed-loop control to ensure that the source voltage VREF0 accurately follows the input reference voltage VREF.

[0036] In the circuit of replica stage 1, the gate of NMOS M21 is connected to the first bias voltage VNBIAS, the source of NMOS M21 is connected to the source of PMOS M41, and the first reference voltage VREF1 is replicated here. The gate of PMOS M41 is connected to the second bias voltage. The circuits of other replica stages are the same as the circuit of replica stage 1. For example, the gate of NMOS M2N is connected to the first bias voltage VNBIAS, the source of NMOS M2N is connected to the source of PMOS M4N, and the Nth reference voltage VREFN is replicated here. The gate of PMOS M4N is connected to the second bias voltage. Different from the main stage circuit, the reference voltage in the circuits of replica stages 1 to N is an open-loop configuration. The replicated multiple reference voltages VREF1 to VREFN are provided to sub-ADC 1 to sub-ADC N for use, respectively.

[0037] When each analog-to-digital converter uses a reference voltage to convert an input analog signal, there will be sampling noise, which affects the first bias voltage VNBIAS and the second bias voltage VPBIAS. Therefore, near the sub-analog-to-digital converter, in order to suppress the interference of sampling noise to the first bias voltage VNBIAS and the second bias voltage VPBIAS, the first and second bias voltages VNBIAS and VPBIAS are connected to the filter capacitor respectively. In the main circuit, the filter capacitor C11 is connected between the first bias voltage VNBIAS and the common ground terminal, and the filter capacitor C21 is connected between the second bias voltage VPBIAS and the common ground terminal. Specifically, one end of the filter capacitor C11 can be connected to the output terminal of the amplifier, and one end of the filter capacitor C2 can be connected between the gate of the PMOS M3 and the gate of the PMOS M4.

[0038] Similarly, each replica stage also has filter capacitors respectively connected between the first bias voltage VNBIAS and the second bias voltage VPBIAS and the common ground terminal. For example, for the sub-ADC N, at its corresponding layout position, the filter capacitors C1N and C2N are respectively connected between the first bias voltage VNBIAS and the second bias voltage VPBIAS and the common ground terminal, so that the filter capacitors C1, C11 to C1N are connected in parallel, and C2, C21 to C2N are connected in parallel. The main stage circuit and each replica stage circuit have the same bias voltage, which ensures the consistency of the circuit and avoids output deviation, and is suitable for high-precision ADCs. In order to ensure the consistency of the circuit, the filter capacitors C1, C11 to C1N can use the same configuration, and the filter capacitors C2, C21 to C2N can use the same configuration.

[0039] Optionally, the filter capacitor can be composed of a MOS capacitor and / or a MOM capacitor. A capacitor composed of a MOS capacitor and a MOM capacitor can save chip area.

[0040] The present invention uses a source follower to replicate the bias so that each sub-analog-to-digital converter can generate a separate reference voltage, and the separate reference voltage only needs to be generated by an NMOS tube and a PMOS tube, which greatly simplifies the circuit design of the sub-analog-to-digital converter and reduces the power consumption and area of ​​the sub-analog-to-digital converter. The source follower is not limited to a push-pull source follower, and can be replaced by an NMOS source follower or a PMOS source follower, for example.

[0041] In one embodiment, when the power supply voltage connected to the drains of M2, M21 to M2N is consistent with the process requirement voltage of the NMOS transistor, these drains can be directly connected to the same power supply voltage.

[0042] In another embodiment, in order to increase the voltage range of the reference voltage that can be generated by the circuit, a MOS transistor with a low threshold voltage can be used. However, the gate-source voltage, gate-drain voltage, and source-drain voltage that a MOS transistor with a low threshold voltage can generally withstand are lower. At this time, the power supply voltage connected to the drain may be higher than the process requirement voltage of the MOS transistor, and an additional overvoltage protection circuit is required to ensure that the gate-source voltage and gate-drain voltage of the NMOS transistor do not exceed the process requirements. Figure 3 The present invention is a schematic diagram of an overvoltage protection circuit. The circuit can be used for overvoltage protection of NMOS M2, NMOS M21 to NMOS M2N in the main stage and each replica stage circuit.

[0043] Taking NMOS M2 as an example, in the overvoltage protection circuit, the comparator COMP compares the reference power supply voltage V1 and the first bias voltage VNBIAS. Figure 3 In the embodiment of the present invention, the reference power supply voltage V1 and the first bias voltage VNBIAS are connected to the non-inverting input terminal and the inverting input terminal, respectively. The output terminal of the comparator COMP is connected to the gate of the PMOS M5. The source of the PMOS M5 is connected to the power supply voltage VDDH, and its drain is connected to the drain of the NMOS M2. The gate of the NMOS M2 is connected to the inverting input terminal of the comparator COMP, that is, connected to the first bias voltage VNBIAS, and its drain is connected to the drain of another NMOS M6. The gate of the NMOS M6 is connected to the output of the comparator COMP, and its source is grounded. In this circuit, M5 and M6 can be high-voltage MOS tubes, and M2 can be a low-voltage MOS tube. The high-voltage MOS tube referred to in the present disclosure has a higher threshold voltage than the low-voltage MOS tube. For example, a high-voltage MOS tube can refer to a MOS tube whose gate drive voltage is not less than 1.2V, and a low-voltage MOS tube can refer to a MOS tube whose gate drive voltage does not exceed 0.75V.

[0044] The reference power supply voltage V1 is set to a value less than the power supply voltage VDDH. According to the general design method of MOS transistors, the reference power supply voltage V1 can be determined as a certain proportion of VDDH. Preferably, the ratio of the reference power supply voltage V1 to VDDH can be between 0.35 and 0.8, for example, it can be two-thirds of the size of VDDH. The ratio can be determined according to the difference between VDDH and the first bias voltage. When the anti-overvoltage circuit is working, when the first bias voltage VNBIAS is higher than the reference power supply voltage V1, PD_HV becomes a low level, PMOS M5 is turned on, and NMOS M6 is turned off. At this time, the circuit is in a normal working state, and the gate-source voltage and gate-drain voltage of NMOS M2 are both fixed proportions of the power supply voltage VDDH, which will not exceed the process requirement value. When the first bias voltage VNBIAS is lower than the reference power supply voltage V1, PD_HV becomes a high level, PMOS M5 is turned off, and NMOS M6 is turned on. At this time, the circuit is in a protection state to ensure that NMOS M2 will not be affected by the high level.

[0045] Optionally, the reference power supply voltage V1 is set to two-thirds of the power supply voltage VDDH, so that when the first bias VNBIAS is greater than two-thirds of VDDH, the drain of NMOS M2 will be connected to a higher VDDH voltage, ensuring that the source-drain voltage of NMOS M2 does not exceed the process requirements. The ratio of the reference power supply voltage V1 to the power supply voltage VDDH can be set to other values ​​less than 1 as needed.

[0046] The introduction of the overvoltage protection circuit enables the source follower to use a MOS tube with a lower threshold voltage, thereby expanding the adjustment range of the reference voltage. The above circuit is also applicable to the overvoltage protection of NMOS M21 to NMOS M2N.

[0047] By copying the bias of the source follower, one reference voltage can be copied into multiple reference voltages with high precision, and the response time of the sub-ADC reference voltage can be reduced. By setting a filter capacitor in each sub-ADC, the interference of the reference voltage in the sampling and comparison process between the sub-ADCs can be suppressed. The use of the above-mentioned overvoltage protection circuit can prevent the gate-drain voltage and gate-source voltage of the source follower NMOS tube from exceeding the maximum voltage required by the process. The multi-reference voltage generating circuit of the disclosed embodiment is also applicable to other circuit scenarios requiring multiple reference voltages.

[0048] Figure 4A time-interleaved analog-to-digital converter according to an embodiment of the present disclosure is shown, which includes a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure. The analog-to-digital converter includes a multi-stage buffer, for example, 1 to 3 stages, to divide the high-speed data signal into multiple channels, such as 8 channels, 16 channels, 32 channels, 64 channels, 128 channels, etc., and then perform analog-to-digital conversion on the data divided into multiple channels and then decelerated through a sub-analog-to-digital converter. Preferably, the high-speed data signal can be divided into 64 channels. Figure 4 The embodiment shows a two-stage buffer, which divides the high-speed data signal to the sub-ADC 111 to the sub-ADC NNN. The multi-channel reference voltage generation circuit according to the embodiment of the present disclosure can generate a duplicate reference voltage for each sub-ADC, preventing the mutual interference caused by multiple sub-ADCs reusing the same reference voltage, thereby avoiding the adverse effect on the signal-to-noise ratio of the ADC.

[0049] The high-speed data in the disclosed embodiments may be a data rate of 10 Gbps or more. For NRZ (Non-Return to Zero), the data rate may preferably be above 10 Gbps, more preferably 56 Gbps. For PAM4 (Four-Level Pulse Amplitude Modulation), the data rate may preferably be at least 56 Gbps, more preferably at least 112 Gbps.

[0050] Figure 5 A receiver 50 according to an embodiment of the present disclosure is shown, wherein the analog-to-digital converter includes a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure. The receiver includes a terminal 51, a continuous time linear equalizer (CTLE) 52, a variable gain amplifier (VGA) 53, an analog-to-digital converter (ADC) 54, and a digital back end (DBE) 55. The terminal 51 is used to match the transmission line impedance so that the terminal load impedance matches the transmission line impedance, thereby avoiding or reducing signal reflection and ensuring signal integrity. The terminal can use a differential terminal resistor, for example.

[0051] The continuous time linear equalizer 52 enhances the high frequency signal component by frequency selective amplification, thereby reducing signal distortion. The variable gain amplifier 53 can dynamically adjust the gain of the signal, adjust the gain according to the signal strength, and enhance the signal amplitude with variable frequency, so that the input signal reaches an appropriate level range in the subsequent analog-to-digital converter.

[0052] The analog-to-digital converter 54 converts the received equalized signal into a digital signal for subsequent digital signal processing. The analog-to-digital converter 54 is a time-interleaved analog-to-digital converter having a multi-channel reference voltage generating circuit according to an embodiment of the present disclosure. The structural diagram of the analog-to-digital converter 54 can be found in Figure 4 .

[0053] The digital backend may include but is not limited to a feedforward equalizer (FFE), a decision feedback equalizer (DFE), a clock data recovery module (CDR), and an adaptive equalizer to implement equalization, filtering, symbol recovery, etc. Here, the serializer / deserializer (SerDes) receiver may use an existing digital signal processor as the digital backend.

[0054] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-channel reference voltage generating circuit, characterized in that include: A primary circuit, comprising a primary reference voltage generating module and a primary bias voltage filtering module, wherein the primary reference voltage generating module is used to receive an input reference voltage and generate a first bias voltage and a second bias voltage, and the primary bias voltage filtering module connects the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage; A replica-level circuit includes a plurality of replica-level reference voltage generating modules and a plurality of replica-level bias voltage filtering modules, each replica-level reference voltage generating module receives a first bias voltage and a second bias voltage sent by a main-level circuit, and outputs a replicated reference voltage, so that the replica-level circuit outputs multiple replicated reference voltages, each replica-level bias voltage filtering module connects the first bias voltage and the second bias voltage to suppress external interference to the first bias voltage and the second bias voltage, and each replica-level reference voltage generating module includes a source follower of an open-loop structure, wherein the multiple replicated reference voltages are the same as the input reference voltage.

2. The multi-channel reference voltage generating circuit as claimed in claim 1, characterized in that The primary reference voltage generating module comprises: An amplifier, wherein a non-inverting input terminal receives the input reference voltage, and an output terminal outputs a first bias voltage; A source follower receives a first bias voltage and outputs a primary reference voltage which is a replica of the reference voltage, and the output primary reference voltage is input to an inverting input terminal of the amplifier.

3. The multi-channel reference voltage generating circuit as claimed in claim 2, characterized in that The source follower comprises: a first NMOS transistor and a second NMOS transistor, wherein the gates of the first NMOS transistor and the second NMOS transistor are connected to a first bias voltage, the source of the second NMOS transistor is connected to an inverting input terminal of the amplifier, and outputs a primary reference voltage; A first PMOS transistor and a second PMOS transistor, wherein the source of the first PMOS transistor is connected to the source of the first NMOS transistor, the gate and drain of the first PMOS transistor are connected together to generate a second bias voltage, and the drain of the first PMOS transistor is connected to a current source, the source of the second PMOS transistor is connected to the source of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor.

4. The multi-channel reference voltage generating circuit as claimed in claim 1, characterized in that Each of the replica-level reference voltage generating modules includes a third NMOS transistor and a third PMOS transistor, wherein the gate of the third NMOS transistor is connected to the first bias voltage, the source of the third NMOS transistor is connected to the source of the third PMOS transistor and outputs a replicated reference voltage, and the gate of the third PMOS transistor is connected to the second bias voltage.

5. The multi-channel reference voltage generating circuit as claimed in claim 3, characterized in that Also included is a first overvoltage protection circuit, comprising: A first comparator, a non-inverting input terminal of which is connected to a reference power supply voltage and an inverting input terminal of which is connected to a first bias voltage, wherein the reference power supply voltage is less than the power supply voltage; a fourth PMOS transistor, having a gate connected to the output terminal of the comparator, a source connected to a power supply voltage, and a drain connected to the drain of the second NMOS transistor; a fourth NMOS transistor, a drain of which is connected to the drain of the second NMOS transistor, and a gate of which is connected to the output terminal of the comparator, When the first bias voltage is lower than the reference power supply voltage, the fourth NMOS transistor is turned on and the fourth PMOS transistor is turned off.

6. The multi-channel reference voltage generating circuit as claimed in claim 4, characterized in that Also included is a second overvoltage protection circuit, comprising: A second comparator, wherein the non-inverting input terminal thereof is connected to a reference power supply voltage, and the inverting input terminal thereof is connected to a first bias voltage, wherein the reference power supply voltage is less than the power supply voltage; a fifth PMOS transistor, having a gate connected to the output terminal of the comparator, a source connected to a power supply voltage, and a drain connected to the drain of the third NMOS transistor; a fifth NMOS transistor, a drain of which is connected to the drain of the third NMOS transistor, and a gate of which is connected to the output terminal of the comparator, When the first bias voltage is lower than the reference power supply voltage, the fifth NMOS transistor is turned on and the fifth PMOS transistor is turned off.

7. The multi-channel reference voltage generating circuit as claimed in claim 5 or 6, characterized in that The ratio of the reference power supply voltage to the power supply voltage is between 0.35 and 0.

8.

8. The multi-channel reference voltage generating circuit as claimed in claim 1, characterized in that The main-stage bias voltage filter module includes first and second filter capacitors connected to the first and second bias voltages respectively, and the first and second filter capacitors include capacitors formed by a combination of a MOS capacitor and a MOM capacitor.

9. The multi-channel reference voltage generating circuit as claimed in claim 1, characterized in that Each of the plurality of replica-stage bias voltage filter modules comprises a third and a fourth filter capacitor connected to the first and second bias voltages respectively, and the third and the fourth filter capacitor comprise a capacitor formed by a combination of a MOS capacitor and a MOM capacitor.

10. The multi-channel reference voltage generating circuit as claimed in claim 9, characterized in that The third and fourth filter capacitors are placed on the layout of the device for receiving the multi-channel replicated reference voltages generated by the multi-channel reference voltage generating circuit.

11. A time-interleaved analog-to-digital converter, comprising: One or more buffers for dividing the input high-speed data signal into multiple sub-data signals; A plurality of sub-analog-to-digital converters, each of which receives one channel of the multiple channels of sub-data signals output by one or more buffers, and performs analog-to-digital conversion on the signal; The multi-channel reference voltage generating circuit according to any one of claims 1 to 10, which generates multiple replicated reference voltages for providing a separate reference voltage for each sub-module converter in a plurality of sub-analog-to-digital converters.

12. A receiver comprising a terminal for matching a transmission line impedance, a continuous time linear equalizer, a variable gain amplifier, a time interleaved analog-to-digital converter as claimed in claim 11, and a digital back end.

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