Switched-capacitor comparators, analog-to-digital converters and electronic devices

Abstract

This disclosure provides a switched-capacitor comparator, an analog-to-digital converter, and an electronic device, relating to the field of integrated circuit technology. The switched-capacitor comparator includes a switched-capacitor comparator unit and a common-mode stabilization unit. The switched-capacitor comparator unit integrates a sampling capacitor and a comparator. Its inputs include a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator. Its output is a comparison of the difference between the forward and reverse input voltages, and the difference between the forward and reverse reference voltages. The common-mode stabilization unit simulates the sampling state of the switched-capacitor comparator unit, ensuring that the actual common-mode input voltage of the comparator equals the ideal common-mode input voltage. Its inputs include the common-mode reference voltage, the forward input voltage, the reverse input voltage, and the ideal common-mode input voltage. Its output is the common-mode bias voltage. This switched-capacitor comparator features a wide common-mode input range and fast response.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a switched capacitor comparator, an analog-to-digital converter, and an electronic device. Background Technology

[0002] In high-speed pipelined analog-to-digital converters (ADCs), the sub-ADC often employs switched-capacitor comparators (SC-CMPs). The response speed of the SC-CMP directly determines the conversion speed of the sub-ADC. Therefore, high-performance SC-CMPs remain a key design focus for high-speed pipelined ADCs.

[0003] There are various types of switched-capacitor comparators in related technologies, with the fully differential switched-capacitor comparator being the most widely used. It offers advantages such as high precision, low power consumption, simple circuit structure, and small footprint. The structure of a fully differential switched-capacitor comparator is as follows: Figure 1 As shown, the common-mode input voltage (VCMI) and the actual common-mode input voltage (VCMX) of the comparator (CMP) of this switched-capacitor comparator significantly affect its performance. It is necessary to keep VCMI, the common-mode reference voltage (VCMR), the ideal common-mode input voltage (VCMC) of the CMP, and the common-mode bias voltage (VCMS, which is also the voltage at the top plate of the capacitor) consistent, all at the set value VCM, to achieve VCMX = VCMC. Because the speed and offset of this switched-capacitor comparator are significantly affected by VCMX, it is not suitable for high-speed pipelined ADCs with variable input common-mode, especially in sample-and-hold ADC structures. Other disclosed switched-capacitor comparators, such as those based on thin-film transistor designs, also fail to achieve a wide common-mode input range.

[0004] The structure of a switched-capacitor comparator with a wide common-mode input range disclosed in related technologies is as follows: Figure 2 As shown. Compared to the switched-capacitor comparator described above, a wide input common-mode range design is implemented for the CMP input stage to address the applicability issue of high-speed pipelined ADCs with variable common-mode input. Different pull-up and pull-down circuits are selected based on the different common-mode levels of the input signal to implement comparators applicable to low and high input common-mode inputs. These two comparators are then connected in parallel to achieve a wide common-mode input range (common-mode voltage). This approach increases the design complexity of the switched-capacitor comparator, increases the parasitic capacitance of the CMP, and reduces the response speed of the switched-capacitor comparator. Summary of the Invention

[0005] The main objective of this disclosure is to provide a switched-capacitor comparator, an analog-to-digital converter, and an electronic device to solve the technical problems of increased CMP parasitic capacitance and slower response speed caused by changes in the product structure of switched-capacitor comparators.

[0006] To achieve the above objectives, a first aspect of this disclosure provides a switched-capacitor comparator, comprising:

[0007] A switched-capacitor comparator unit has a built-in sampling capacitor and a comparator connected in series. The inputs of the switched-capacitor comparator unit include a forward reference voltage, a reverse reference voltage, a forward input voltage, a reverse input voltage, and a common-mode bias voltage of the comparator. The output of the switched-capacitor comparator unit is a comparison result of the difference between the forward input voltage and the reverse input voltage, and the difference between the forward reference voltage and the reverse reference voltage.

[0008] A common-mode stabilization unit is used to simulate the sampling state of the switched-capacitor comparator unit, such that the actual common-mode input voltage of the comparator is equal to the ideal common-mode input voltage. The inputs of the common-mode stabilization unit include a common-mode reference voltage, the positive input voltage, the negative input voltage, and the ideal common-mode input voltage. The output of the common-mode stabilization unit is the common-mode bias voltage applied to the top plate of the sampling capacitor. The common-mode reference voltage is related to the positive reference voltage and the negative reference voltage.

[0009] Furthermore, there are multiple switched-capacitor comparator units, and all of the switched-capacitor comparator units are connected in parallel; and,

[0010] The sampling capacitor, the forward input voltage, the reverse input voltage, the common-mode bias voltage, and the common-mode reference voltage are all the same in each of the switched-capacitor comparator units; however, the forward reference voltage and the reverse reference voltage are different in different switched-capacitor comparator units.

[0011] Furthermore, the common-mode bias voltage is adjustable; and the common-mode stabilization unit is configured with an adjustable ideal common-mode input voltage, and generates the common-mode bias voltage based on the adjusted ideal common-mode input voltage, such that the common-mode bias voltage satisfies:

[0012] VCMS = VCMC + VCMR - VCMI

[0013] In the formula, VCMS represents the common-mode bias voltage, VCMC represents the ideal common-mode input voltage, VCMR represents the common-mode reference voltage, VCMR is the average of the forward reference voltage and the reverse reference voltage, VCMI represents the common-mode input voltage, and VCMI is the average of the forward input voltage and the reverse input voltage.

[0014] Furthermore, the common-mode stabilization unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor, and an integrator; wherein,

[0015] The base plate of the first capacitor is divided into two paths: one path is connected to the positive input voltage via the second switch, and the other path is connected to the common-mode reference voltage via the first switch. The base plate of the second capacitor is also divided into two paths: one path is connected to the reverse input voltage via the third switch, and the other path is connected to the common-mode reference voltage via the fourth switch. The top plates of the first and second capacitors are connected in parallel and then divided into two paths: one path is connected to the output terminal of the integrator via the fifth switch, and the other path is connected to the input terminal of the integrator via the sixth switch. The reference terminal of the integrator is connected to the ideal common-mode input voltage, and the output terminal of the integrator serves as the output terminal of the common-mode stabilization unit and is connected to the top plate of the sampling capacitor.

[0016] Furthermore, the integrator includes a third capacitor and an operational amplifier; wherein,

[0017] Inside the integrator, the positive input terminal of the operational amplifier serves as the reference terminal of the integrator and is connected to the ideal common-mode input voltage; the inverting input terminal of the operational amplifier serves as the input terminal of the integrator and is connected to the top plates of the first capacitor and the second capacitor respectively via the sixth switch; the output terminal of the operational amplifier serves as the output terminal of the integrator and is connected to the negative input terminal of the operational amplifier via the third capacitor.

[0018] Furthermore, the first switch and the fourth switch are connected to the first control signal, the second switch and the third switch are connected to the second control signal; the fifth switch is connected to the third control signal, and the sixth switch is connected to the fourth control signal; and,

[0019] Within one control cycle of the switched capacitor comparator, the third control signal exhibits a falling edge indicating turn-off information before the first control signal, and the fourth control signal exhibits a falling edge indicating turn-off information before the second control signal; furthermore, the first control signal, the second control signal, the third control signal, and the fourth control signal are non-overlapping signals; and...

[0020] The capacitance values ​​of the first capacitor and the second capacitor are equal.

[0021] Furthermore, the switched-capacitor comparator also includes a first voltage buffer; wherein,

[0022] The output of the common-mode stabilization unit is connected to the top plate of the sampling capacitor in the switched-capacitor comparator unit via the first voltage buffer.

[0023] Furthermore, within one control cycle of the switched capacitor comparator, the third control signal, the first control signal, the fourth control signal, and the second control signal successively exhibit falling edges representing turn-off information; and the initial states of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all open; the capacitor switch comparator also includes a controller; the controller performs the following steps to complete the voltage comparison function:

[0024] In response to the falling edge of the third control signal representing the shutdown information, the fifth switch is controlled to be turned off, and the output of the common-mode stabilization unit is connected to the top plate of the sampling capacitor.

[0025] In response to the falling edge of the first control signal representing the shutdown information, the first switch and the fourth switch are controlled to be turned off, the base plate of the sampling capacitor is controlled to be connected to the corresponding positive reference voltage and the reverse reference voltage and sampled, the common mode reference voltage is obtained according to the sampling result, and the base plates of the first capacitor and the second capacitor are both controlled to be connected to the common mode reference voltage.

[0026] In response to the falling edge of the fourth control signal representing the shutdown information, the sixth switch is controlled to be turned off, so that the top plates of the first capacitor and the second capacitor are both connected to the input terminal of the integrator.

[0027] In response to the falling edge of the second control signal representing the shutdown information, the second switch and the third switch are controlled to be turned off, and the base plate of the sampling capacitor is controlled to be connected to the corresponding positive input voltage and the reverse input voltage.

[0028] In response to the running time reaching a set threshold time that makes the actual common-mode input voltage of the comparator equal to the ideal common-mode input voltage, the comparison results of the difference between the positive input voltage and the reverse input voltage, and the difference between the positive reference voltage and the reverse reference voltage are obtained through the switched capacitor comparator unit.

[0029] A second aspect of this disclosure provides an analog-to-digital converter including the aforementioned switched-capacitor comparator.

[0030] A third aspect of this disclosure provides an electronic device including the analog-to-digital converter described above.

[0031] The switched-capacitor comparator provided in this disclosure can be applied to high-speed pipelined ADCs with variable common-mode input. It achieves a wide common-mode input range by adding a common-mode stabilization unit to control the common-mode input voltage of the switched-capacitor comparator unit without modifying its product structure. The common-mode stabilization unit simulates the sampling state of the switched-capacitor comparator unit until the actual common-mode input voltage of the comparator equals the ideal common-mode input voltage. The actual common-mode input voltage can be adjusted according to the ideal common-mode input voltage of the input common-mode stabilization unit, ensuring variable common-mode input and a wide common-mode input range (0.5-1.3V). This achieves the technical effects of a wide common-mode input range, low CMP parasitic capacitance, and fast response speed, thereby solving the technical problems of increased CMP parasitic capacitance and slower response speed caused by changing the product structure of the switched-capacitor comparator. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a fully differential switched capacitor comparator.

[0034] Figure 2 A schematic diagram of a switched-capacitor comparator with a wide common-mode input range;

[0035] Figure 3 This is a schematic diagram of a switched capacitor comparator provided in an embodiment of the present disclosure;

[0036] Figure 4 This is a schematic diagram of another switched-capacitor comparator provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of a common-mode stabilization unit provided in an embodiment of this disclosure;

[0038] Figure 6 A schematic diagram of a circuit structure for an integrator provided in an embodiment of this disclosure;

[0039] Figure 7 This is a timing diagram of each control signal within a control cycle;

[0040] Figure 8 This is a complete circuit diagram of a switched capacitor comparator provided in an embodiment of the present disclosure.

[0041] Figure 9 A schematic block diagram of an analog-to-digital converter provided in an embodiment of this disclosure;

[0042] Figure 10 A schematic block diagram of an electronic device provided in an embodiment of this disclosure.

[0043] Figure Labels

[0044] VRP - Forward reference voltage; VRN - Reverse reference voltage; VINP - Forward input voltage; VINN - Reverse input voltage; VCM - Voltage at the top plate of the sampling capacitor; VCMX - Actual common-mode input voltage;

[0045] VCMR - Common-mode reference voltage; VCMC - Ideal common-mode input voltage; VCMS - Common-mode bias voltage; VCMI - Common-mode input voltage; VOP - Comparator positive output node; VON - Comparator negative output node; VXP - Comparator positive input node; VXN - Comparator negative input node; ckh - First control signal; cks - Second control signal; ckha - Third control signal; cksa - Fourth control signal; GND - Ground; VDD - External power supply; OUTP - SR latch positive output node; OUTN - SR latch negative output node Points; 111-Seventh switch; 112-Eighth switch; 113-Ninth switch; 114-Tenth switch; 115-Eleventh switch; 116-Twelfth switch; 117-Fourth capacitor; 118-Fifth capacitor; 119-Comparator; 121-First switch; 122-Second switch; 123-Third switch; 124-Fourth switch; 125-Fifth switch; 126-Sixth switch; 127-First capacitor; 128-Second capacitor; 129a-Third capacitor; 129b-Operational amplifier; 130-First voltage buffer; 131-Second voltage buffer. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] In this disclosure, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are primarily for the purpose of better describing this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0049] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain circumstances to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0050] Furthermore, the terms "set up," "equipped with," "connected," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] To adapt to high-speed pipelined ADCs with variable common-mode input, improvements to existing switched-capacitor comparators often require changes to the comparator's design structure. This leads to a significant increase in design complexity, increased CMP parasitic capacitance, and reduced response speed, among other problems. In other words, existing technologies suffer from the technical issues of increased CMP parasitic capacitance and slower response speed due to changes in the switched-capacitor comparator's design structure.

[0053] To address the aforementioned problems, embodiments of this disclosure provide a switched capacitor comparator. Figure 3 This is a schematic diagram of a switched-capacitor comparator provided in an embodiment of this disclosure. Figure 3 As shown, the switched capacitor comparator 100 includes a switched capacitor comparator unit 110 and a common-mode stabilization unit 120.

[0054] The switched-capacitor comparator unit 110 integrates a sampling capacitor connected in series and a comparator 119. The inputs of the switched-capacitor comparator unit 110 include a forward reference voltage VRP, a reverse reference voltage VRN, a forward input voltage VINP, a reverse input voltage VINN, and the common-mode bias voltage VCMS of the comparator 119. The output of the switched-capacitor comparator unit 110 is a comparison of the differences between the forward input voltage VINP and the reverse input voltage VINN, and the differences between the forward reference voltage VRP and the reverse reference voltage VRN. The switched-capacitor comparator unit 110 is used to implement the voltage comparison function of the forward input voltage VINP and the reverse input voltage VINN.

[0055] The common-mode stabilization unit 120 is used to simulate the sampling state of the switched-capacitor comparator unit 110, ensuring that the actual common-mode input voltage VCMX of the comparator 119 is equal to the ideal common-mode input voltage VCMC. The inputs of the common-mode stabilization unit 120 include the common-mode reference voltage VCMR, the forward input voltage VINP, the reverse input voltage VINN, and the ideal common-mode input voltage VCMC. The output of the common-mode stabilization unit 120 is the common-mode bias voltage VCMS applied to the top plate of the sampling capacitor. The common-mode reference voltage VCMR is related to the forward reference voltage VRP and the reverse reference voltage VRN.

[0056] It should be noted that the common-mode stabilization unit 120 can be implemented through software programming or hardware, with the aim of making the actual common-mode input voltage VCMX of comparator 119 equal to the ideal common-mode input voltage VCMC. The switched-capacitor comparator unit 110 can be a fully differential switched-capacitor comparator or other off-the-shelf switched-capacitor comparator products, such as a switched-capacitor comparator based on a thin-film transistor design; the embodiments of this disclosure are not limited in this regard.

[0057] The common-mode reference voltage VCMR is related to the forward reference voltage VRP and the reverse reference voltage VRN. This means that the common-mode reference voltage VCMR can be set as the average or sum of the forward reference voltage VRP and the reverse reference voltage VRN, or other relationships, such as multiple relationships. The embodiments of this disclosure do not limit this.

[0058] The switched-capacitor comparator of this disclosure is applicable to any existing analog-to-digital converter (ADC) application scenario. For example, in high-speed pipelined ADCs, the switched-capacitor comparator of this disclosure, compared with the prior art, can achieve a wide common-mode input range without changing the product structure of the switched-capacitor comparator, without causing an increase in CMP parasitic capacitance or a slowdown in response speed. It has significant technical advantages over existing switched-capacitor comparators with a wide common-mode input range.

[0059] exist Figure 3 Based on the shown switched-capacitor comparator structure, preferably, the switched-capacitor comparator further includes a first voltage buffer 130. The output terminal of the common-mode stabilization unit 120 is connected to the top plate of the sampling capacitor in the switched-capacitor comparator unit 110 via the first voltage buffer 130. The first voltage buffer 130 is used to prevent load interference to the signal source, maintain the amplitude and shape of the signal, enhance the current of the output signal, improve the driving capability of the output current, and simultaneously increase the bandwidth.

[0060] Figure 4 This is a schematic diagram of another switched-capacitor comparator provided in an embodiment of this disclosure. Figure 4 As shown, there are multiple switched-capacitor comparator units 110, numbered n, and all switched-capacitor comparator units 110 are connected in parallel. Each switched-capacitor comparator unit 110 has the same sampling capacitor, forward input voltage VINP, reverse input voltage VINN, common-mode bias voltage VCMS, and common-mode reference voltage VCMR. However, the forward reference voltage VRP and reverse reference voltage VRN differ between different switched-capacitor comparator units 110 to obtain different output results. For example, VCMR = (VRP + VRN) / 2, but VRP and VRN are different; for example, in the first switched-capacitor comparator unit, VRP = 1.4 and VRN = 0.4, while in the second switched-capacitor comparator unit, VRP = 1.2 and VRN = 0.6.

[0061] In a preferred embodiment, the common-mode stabilization unit 120 outputs an adjustable common-mode bias voltage VCMS. Furthermore, the common-mode stabilization unit 120 is equipped with an adjustable ideal common-mode input voltage VCMC, and generates a target common-mode bias voltage VCMS based on the adjusted ideal common-mode input voltage VCMC, such that the common-mode bias voltage VCMS satisfies:

[0062] VCMS = VCMC + VCMR - VCMI

[0063] In the formula, VCMC represents the ideal common-mode input voltage VCMC, VCMR represents the common-mode reference voltage VCMR, VCMR is the average of the forward reference voltage VRP and the reverse reference voltage VRN, VCMI represents the common-mode input voltage, VCMI is the average of the forward input voltage VINP and the reverse input voltage VINN.

[0064] Using the above formula, the common-mode stabilizing unit 120 achieves the design goal of VCMX = VCMC.

[0065] Figure 5 This is a schematic diagram of a circuit structure for a common-mode stabilization unit 120 provided in an embodiment of this disclosure. Figure 5 As shown, the common-mode stabilization unit 120 includes a first switch 121, a second switch 122, a third switch 123, a fourth switch 124, a fifth switch 125, a sixth switch 126, a first capacitor 127, a second capacitor 128, and an integrator 129. The base plate of the first capacitor 127 is divided into two paths: one path connects to the positive input voltage VINP via the second switch 122, and the other path connects to the common-mode reference voltage VCMR via the first switch 121. The base plate of the second capacitor 128 is also divided into two paths: one path connects to the reverse input voltage VINN via the third switch 123, and the other path connects to the common-mode reference voltage VCMR via the fourth switch 124. The top plates of the first capacitor 127 and the second capacitor 128 are connected in parallel and then divided into two paths: one path connects to the output terminal of the integrator 129 via the fifth switch 125, and the other path connects to the input terminal of the integrator 129 via the sixth switch 126. The reference terminal of integrator 129 is connected to the ideal common-mode input voltage VCMC, and the output terminal of integrator 129 serves as the output terminal of common-mode stabilization unit 120, connected to the top plate of the sampling capacitor. This circuit structure provides advantages such as simple structure and fast response speed for the common-mode stabilization unit 120.

[0066] exist Figure 5 Based on the structure of the switched-capacitor comparator shown, preferably, the switched-capacitor comparator further includes a second voltage buffer 131. The input terminal of the second voltage buffer 131 is connected to the output terminal of the integrator 129, and its output terminal is connected to the fifth switch 125. The purpose of the second voltage buffer 131 is to provide an interface between the input and output to reduce signal loss caused by factors such as resistance and capacitance during transmission, thereby optimizing signal transmission.

[0067] Figure 6 This is a schematic diagram of a circuit structure for an integrator 129 provided in an embodiment of this disclosure. Figure 6As shown, the integrator 129 includes a third capacitor 129a and an operational amplifier 129b. Internally, the positive input terminal of the operational amplifier 129b serves as the reference terminal of the integrator 129, connected to the ideal common-mode input voltage VCMC. Its inverting input terminal serves as the input terminal of the integrator 129, connected via a sixth switch 126 to the top plates of the first capacitor 127 and the second capacitor 128, respectively. The output terminal of the operational amplifier 129b serves as the output terminal of the integrator 129, connected via the third capacitor 129a to its negative input terminal. The capacitance value of the third capacitor 129a determines the step size for establishing the common-mode bias voltage VCMS.

[0068] For the first switch 121 to the sixth switch 126, preferably, the first switch 121 and the fourth switch 124 are connected to the first control signal ckh, the second switch 122 and the third switch 123 are connected to the second control signal cks; the fifth switch 125 is connected to the third control signal ckha, and the sixth switch 126 is connected to the fourth control signal cksa. Furthermore, within one control cycle of the switched-capacitor comparator, the third control signal ckha appears before the first control signal ckh with a falling edge indicating turn-off information, and the fourth control signal cksa appears before the second control signal cks with a falling edge indicating turn-off information. Moreover, the first control signal ckh, the second control signal cks, the third control signal ckha, and the fourth control signal cksa are non-overlapping signals. This setting of control signals ensures the effective control function of the switched-capacitor comparator.

[0069] Preferably, the capacitance values ​​of the first capacitor 127 and the second capacitor 128 are equal, which makes the sampling state effect of the analog switched capacitor comparator unit 110 better.

[0070] It should be noted that integrator 129 is not limited to Figure 6 If the circuit structure in the present disclosure is replaced with other types of integrating devices or integrating circuits to achieve the function of the integrator 129, it is also within the protection scope of the present disclosure.

[0071] Figure 7 This is a timing diagram of each control signal within a control cycle provided in an embodiment of this disclosure. For example... Figure 7 As shown, within one control cycle (dashed box) of the switched capacitor comparator, the third control signal ckha, the first control signal ckh, the fourth control signal cksa, and the second control signal cks successively exhibit falling edges representing turn-off information. The first switch 121, the second switch 122, the third switch 123, the fourth switch 124, the fifth switch 125, and the sixth switch 126 are initially all open, turn off upon receiving the falling edge of the corresponding control signal, and turn on again upon receiving the rising edge of the corresponding control signal.

[0072] Preferably, the switched capacitor comparator further includes a controller. Within one control cycle, the controller performs the following steps to complete the voltage comparison function:

[0073] S1. In response to the falling edge of the third control signal ckha, which represents the turn-off information, the fifth switch 125 is turned off, and the output of the common-mode stabilization unit 120 is connected to the top plate of the sampling capacitor.

[0074] S2. In response to the falling edge of the first control signal ckh representing the turn-off information, control the first switch 121 and the fourth switch 124 to turn off, and control the base plate of the sampling capacitor to be connected to the corresponding forward reference voltage VRP and reverse reference voltage VRN and sample them. Obtain the common mode reference voltage VCMR based on the sampling result, and control the base plates of the first capacitor 127 and the second capacitor 128 to be connected to the common mode reference voltage VCMR.

[0075] S3. In response to the falling edge of the fourth control signal cksa, which represents the turn-off information, the sixth switch 126 is turned off, so that the top plates of the first capacitor 127 and the second capacitor 128 are connected to the input terminal of the integrator 129.

[0076] S4. In response to the falling edge of the second control signal cks representing the turn-off information, control the second switch 122 and the third switch 123 to turn off, and control the base plate of the sampling capacitor to be connected to the corresponding positive input voltage VINP and reverse input voltage VINN.

[0077] S5. In response to the time when the running time reaches the set threshold time that makes the actual common-mode input voltage VCMX of comparator 119 equal to the ideal common-mode input voltage VCMC, the comparison results of the difference between the positive input voltage VINP and the reverse input voltage VINN, and the difference between the positive reference voltage VRP and the reverse reference voltage VRN are obtained through the switched capacitor comparator unit.

[0078] It should be noted that the above steps can be executed in a control system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0079] Figure 8 This is a complete circuit diagram of a switched-capacitor comparator provided in an embodiment of the present disclosure. The switched-capacitor comparator unit is a fully differential switched-capacitor comparator, such as... Figure 8As shown, the switched capacitor comparator unit includes a seventh switch 111, an eighth switch 112, a ninth switch 113, a tenth switch 114, an eleventh switch 115, a twelfth switch 116, a fourth capacitor 117, a fifth capacitor 118, and a comparator 119. The fourth capacitor 117 and the fifth capacitor 118 are both sampling capacitors, and their capacitance values ​​are equal. The base plate of the fourth capacitor 117 is divided into two paths: one path connects to the positive input voltage VINP via the eighth switch 112, and the other path connects to the positive reference voltage VRP via the seventh switch 111. The top plate of the fourth capacitor 117 is also divided into two paths: one path connects to the positive input terminal of comparator 119, and the other path connects to the output terminal of common-mode stabilization unit 110 via the eleventh switch 115. The base plate of the fifth capacitor 118 is divided into two paths: one path connects to the inverted input voltage VINN via the ninth switch 113, and the other path connects to the negative reference voltage VRN via the tenth switch 114. The top plate of the fifth capacitor 118 is also divided into two paths: one path connects to the positive input terminal of comparator 119, and the other path connects to the output terminal of common-mode stabilization unit 110 via the twelfth switch 116. The seventh switch 111 and the tenth switch 114 connect to the first control signal ckh; the eighth switch 112 and the ninth switch 113 connect to the second control signal cks; and the eleventh switch 115 and the twelfth switch 116 connect to the third control signal ckha.

[0080] As can be seen from the above description, this disclosure achieves the following technical effects:

[0081] 1. A common-mode stabilization module 120 is used to detect the common-mode input voltage VCMI (including the positive input voltage VINP and the reverse input voltage VINN) and the common-mode reference voltage VCMR. Based on the ideal input common-mode voltage VCMC required by the comparator's positive input node VXP and the comparator's negative input node VXN, the voltage value of the capacitor top plate when the switched capacitor comparator samples the common-mode reference voltage VCMR is generated, i.e., VCMS. Then, the voltage is output through the first voltage buffer 130 to the sampling circuit of all switched capacitor comparator units 110 in the sub-ADC. The goal of the common-mode stabilization circuit 120 is to make VCMS = VCMC + VCMR - VCMI.

[0082] 2. The common-mode stabilization module 120 simulates the sampling state of the switched-capacitor comparator unit 110, and then achieves the above objective through the integrator 129. In the ckh phase, the switched-capacitor comparator unit 110 samples the reference voltage of the comparator 119. The bottom plate of the sampling capacitor is connected to the positive input node VXP and the negative input node VXN of the comparator, respectively, and the top plate is connected to VCMS. At this time, the bottom plate of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 is connected to VCMR=(VRP+VRN) / 2, and the top plate is also connected to VCMS. In the cks phase, the base plate of the sampling capacitor of the switched capacitor comparator unit 110 and the base plates of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 are both connected to the input. The top plate of the sampling capacitor of the switched capacitor comparator unit 110 is connected to the input of the comparator 119. The top plates of the first capacitor 127 and the second capacitor 128 of the common-mode stabilization module 120 are connected to the negative input terminal of the integrator operational amplifier. According to the virtual short of the operational amplifier input, the charge generated on the capacitor in the ckh phase due to the difference between the various common-mode levels is transferred to the integrating capacitor, i.e., the third capacitor 129a. Therefore, the output of the integrating operational amplifier changes. After several cycles of integration adjustment, VCMS = VCMC + VCMR - VCMI is finally achieved, thereby achieving the design goal of VCMX = VCMC.

[0083] This disclosure also provides an analog-to-digital converter, such as... Figure 9 As shown, the analog-to-digital converter 10 includes the switched-capacitor comparator 100 described above. It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the analog-to-digital converter 10. To achieve the necessary functions of the analog-to-digital converter 10, those skilled in the art can provide and configure other constituent units (not shown) according to specific needs, and this disclosure does not impose any limitations on this.

[0084] This disclosure also provides an electronic device, such as... Figure 10As shown, the electronic device 1 includes a processor 20 and an analog-to-digital converter 10. The processor 20 can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips. The general-purpose processor can be a microprocessor or any conventional processor.

[0085] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the components of the electronic device 1. To achieve the necessary functions of the electronic device 1, those skilled in the art can provide and set other components (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0086] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A switched-capacitor comparator, characterized by, The application relates to a switch capacitor comparator unit, which comprises a sampling capacitor and a comparator in series; wherein the input of the switch capacitor comparator unit comprises a positive reference voltage, a negative reference voltage, a positive input voltage, a negative input voltage and a common mode bias voltage of the comparator; the output of the switch capacitor comparator unit is the comparison result of the difference between the positive input voltage and the negative input voltage and the difference between the positive reference voltage and the negative reference voltage; a common mode stabilization unit is used for simulating the sampling state of the switch capacitor comparator unit, so that the actual common mode input voltage of the comparator is equal to an ideal common mode input voltage; the input of the common mode stabilization unit comprises a common mode reference voltage, the positive input voltage, the negative input voltage and the ideal common mode input voltage; the output of the common mode stabilization unit is the common mode bias voltage applied to the top plate of the sampling capacitor; the common mode reference voltage is related to the positive reference voltage and the negative reference voltage; the common mode reference voltage is the average, sum or multiple of the positive reference voltage and the negative reference voltage; wherein the common mode stabilization unit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor and an integrator; wherein the bottom plate of the first capacitor is divided into two paths, one path is connected to the positive input voltage through the second switch, and the other path is connected to the common mode reference voltage through the first switch; the bottom plate of the second capacitor is also divided into two paths, one path is connected to the negative input voltage through the third switch, and the other path is connected to the common mode reference voltage through the fourth switch; the top plate of the first capacitor is connected in parallel with the top plate of the second capacitor, and then divided into two paths, one path is connected to the output terminal of the integrator through the fifth switch, and the other path is connected to the input terminal of the integrator through the sixth switch; the reference terminal of the integrator is connected to the ideal common mode input voltage, and the output terminal of the integrator is used as the output terminal of the common mode stabilization unit and is connected to the top plate of the sampling capacitor; wherein the first switch and the fourth switch are connected to a first control signal, the second switch and the third switch are connected to a second control signal, the fifth switch is connected to a third control signal, and the sixth switch is connected to a fourth control signal; and, in one control period of the switch capacitor comparator, the third control signal appears a falling edge representing a turn-off information earlier than the first control signal, the fourth control signal appears a falling edge representing a turn-off information earlier than the second control signal, and the first control signal, the second control signal, the third control signal and the fourth control signal are non-overlapping signals; and, the capacitance values of the first capacitor and the second capacitor are equal. The number of the switch capacitor comparator units is plural, and each switch capacitor comparator unit is connected in parallel; and, ​ ​ ​ ​ ​ ​ 2. The switched-capacitor comparator of claim 1, wherein, ​ The sampling capacitor, the positive input voltage, the negative input voltage, the common-mode bias voltage and the common-mode reference voltage of each of the switch capacitor comparator units are the same; but the positive reference voltage and the negative reference voltage of different switch capacitor comparator units are different.

3. The switched-capacitor comparator according to claim 1 or 2, characterized in that The common-mode bias voltage is adjustable; and the common-mode stabilization unit is configured with an adjustable ideal common-mode input voltage, and generates the common-mode bias voltage according to the adjusted ideal common-mode input voltage, so that the common-mode bias voltage satisfies: VCMS=VCMC+VCMR-VCMI In the formula, VCMS represents the common-mode bias voltage, VCMC represents the ideal common-mode input voltage, VCMR represents the common-mode reference voltage, VCMR is the average of the positive reference voltage and the negative reference voltage, and VCMI represents the common-mode input voltage of the switch capacitor comparator, and VCMI is the average of the positive input voltage and the negative input voltage.

4. The switched-capacitor comparator of claim 1, wherein, The integrator comprises a third capacitor and an operational amplifier; wherein, Inside the integrator, the positive input end of the operational amplifier serves as the reference end of the integrator and receives the ideal common-mode input voltage; the negative input end of the operational amplifier serves as the input end of the integrator and is connected to the top plate of the first capacitor and the second capacitor through the sixth switch; and the output end of the operational amplifier serves as the output end of the integrator and is also connected to the negative input end of the operational amplifier through the third capacitor.

5. The switched-capacitor comparator of any of claims 1, 2, 4, wherein, The integrator further comprises a first voltage buffer; wherein, The output end of the common-mode stabilization unit is connected to the top plate of the sampling capacitor through the first voltage buffer.

6. The switched-capacitor comparator of claim 1, wherein, In one control cycle of the switch capacitor comparator, the third control signal, the first control signal, the fourth control signal and the second control signal successively appear falling edges representing turn-off information; and the initial states of the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all open; the switch capacitor comparator further comprises a controller, which performs the following steps to complete the voltage comparison function: In response to the third control signal appearing a falling edge representing turn-off information, the fifth switch is controlled to be turned off, and the output end of the common-mode stabilization unit is controlled to be connected to the top plate of the sampling capacitor; In response to the first control signal appearing a falling edge representing turn-off information, the first switch and the fourth switch are controlled to be turned off, the bottom plate of the sampling capacitor is controlled to be connected to the corresponding positive reference voltage and negative reference voltage for sampling, the common-mode reference voltage is obtained according to the sampling result, and the bottom plates of the first capacitor and the second capacitor are both controlled to be connected to the common-mode reference voltage; In response to the fourth control signal appearing a falling edge representing turn-off information, the sixth switch is controlled to be turned off, so that the top plates of the first capacitor and the second capacitor are both connected to the input end of the integrator. in response to a falling edge of the second control signal representing turn-off information, controlling the second switch and the third switch to turn off, and controlling the bottom plate of the sampling capacitor to be connected to the corresponding positive input voltage and the negative input voltage; in response to a runtime reaching a set threshold time such that an actual common-mode input voltage of the comparator is equal to an ideal common-mode input voltage, obtaining, by the switched-capacitor comparator unit, a comparison result of a difference between the positive input voltage and the negative input voltage, and a difference between the positive reference voltage and the negative reference voltage.

7. An analog-to-digital converter, characterized by The switched-capacitor comparator of any one of claims 1-6.

8. An electronic device, comprising: The analog-to-digital converter of claim 7. The analog-to-digital converter of claim 7.

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