Information processing method and apparatus, and communication device

Abstract

The invention discloses a coding method, a coding device, communication equipment and a communication system. The method comprises: encoding an input bit sequence using a low density parity check (LDPC) matrix; wherein the LDPC matrix is obtained based on a base graph, the base graph comprises sub-matrixes A, B, C, D and E, the sub-matrix A is a matrix with mA rows and nA columns, mA and nA are positive integers, 4 < = mA < = 7, and nA = 10; the sub-matrix B is a matrix of mA rows and mA columns, and the sub-matrix B comprises columns with the weight of 3 and a sub-matrix B'of a double-diagonal structure; the sub-matrix D comprises mD rows in a matrix F, the matrix F is a matrix with mF rows (mA + nA) columns, mD and mF are positive integers, 0 < = mD < = mF, and 35 < = mF < = 38; the sub-matrix C is an all-0 matrix with mA rows and mD columns; the sub-matrix E is a unit matrix with mD rows and mD columns. According to the coding method, the coding device, the communication equipment and the communication system, the coding requirements of information bit sequences with various lengths can be met.

Description

[0001] This application is a divisional application. The application number of the original application is 201710454030.3, and the original application date is June 15, 2017. The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The embodiments of the present invention relate to the field of communications, and in particular to an information processing method and a communication device. Background Art

[0003] Low density parity check (LDPC) code is a type of linear block code with a sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than traditional Turbo codes. LDPC codes can be used as error correction codes in communication systems, thereby improving the reliability and power utilization of channel transmission. LDPC codes can also be widely used in space communications, optical fiber communications, personal communication systems, ADSL and magnetic recording equipment. At present, LDPC codes have been considered as one of the channel coding methods in the fifth generation mobile communications.

[0004] In actual use, an LDPC matrix with special structural characteristics may be used. The LDPC matrix H with special structural characteristics may be expanded from an LDPC base matrix with a quasi cycle (QC) structure.

[0005] Typically, the length of the information bit sequence to be encoded ranges from dozens to hundreds, and the code rate required by the communication system is also flexible. How to support the encoding of information bit sequences of various lengths and meet the system's code rate requirements has become a problem that needs to be solved. Summary of the invention

[0006] The embodiments of the present invention provide an information processing method, a communication device and a system, which can support the encoding and decoding of information bit sequences of various lengths and meet the flexible code length and code rate requirements of the system.

[0007] In a first aspect, a coding method and an encoder are provided, wherein the encoder encodes an input sequence using a low-density parity check (LDPC) matrix.

[0008] In a second aspect, a decoding method and a decoder are provided, wherein the decoder decodes an input sequence using a low-density parity check (LDPC) matrix.

[0009] In a first implementation of the first aspect or the second aspect, the LDPC matrix is ​​obtained based on a base graph, and the base graph includes sub-matrices A, B, C, D and E, wherein:

[0010] The submatrix A is m A Line n A Matrix of columns, m A 、n A is a positive integer, and 4≤m A ≤7, n A =10;

[0011] The submatrix B is m A Line m A A matrix of columns, the submatrix B comprising columns with weights of 3 and a submatrix B' of a dual diagonal structure;

[0012] The submatrix D includes the matrix F in m D rows, the matrix F is m F Row(m A +n A ) columns, m D 、m F is a positive integer, 0≤m D ≤m F , 35≤m F ≤38;

[0013] The submatrix C is m A Line m D A matrix with all zeros in its columns;

[0014] The submatrix E is m D Line m D The identity matrix of the columns.

[0015] Based on the above implementation, in a possible implementation, any two adjacent rows in the last 10 rows of the base graph are orthogonal.

[0016] Based on the above implementation, in a possible implementation, the last 10 rows of the base graph include at least 5 groups, each of the at least 5 groups includes at least 2 rows, and the at least 2 rows are orthogonal.

[0017] Based on any of the above implementations, in a possible implementation, the weights of 9 rows in the matrix F are 3, and the weight of 1 row is 2.

[0018] In one design, in the matrix F, the weight of column 1 is 16, the weight of column 1 is 18, the weight of column 1 is 11, the weight of column 2 is 10, the weight of column 1 is 9, the weight of column 1 is 8, the weight of column 1 is 7, the weight of column 1 is 6, the weight of column 2 is 4, the weight of column 1 is 3, and the weight of column 2 is 2.

[0019] Based on the first implementation, in another possible implementation, the number of rows in the matrix F that conform to the orthogonal structure is greater than or equal to 10, and in the matrix F, the weight of column 1 is 16, the weight of column 1 is 18, the weight of column 1 is 11, the weight of column 2 is 10, the weight of column 1 is 9, the weight of column 1 is 8, the weight of column 1 is 7, the weight of column 1 is 6, the weight of column 2 is 4, the weight of column 1 is 3, and the weight of column 2 is 2.

[0020] In yet another design, in the matrix F, 9 rows have a weight of 3, and 1 row has a weight of 2.

[0021] In yet another design, the matrix F includes at least 10 rows, and any two adjacent rows among the at least 10 rows are orthogonal.

[0022] In another design, the matrix F includes at least 5 groups, each of the at least 5 groups includes at least 2 rows, and the at least 2 rows are orthogonal. Optionally, the at least 2 rows can be consecutive rows. For example, the at least 10 rows can be the last 10 rows of the base graph 30a.

[0023] In any of the above implementations, if m A >4, the weights of the remaining columns in the matrix F are 0.

[0024] For example, the 10 rows in the matrix F that conform to the orthogonal structure may include the rows or columns of the matrix block composed of the 25th to 34th rows and the 0th to 13th columns in the base diagram 30a, or the 10 rows in the matrix F that conform to the orthogonal structure may include the rows or columns of the matrix block composed of the 25th to 34th rows and the 0th to 16th columns in the base diagram 30a. The rows in the matrix F may be interchanged, and the columns may also be interchanged.

[0025] Based on the above implementation, the base matrix of the base graph 30a can be any matrix such as the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7 and 30b-8, or a matrix after row / column transformation of the matrix.

[0026] Based on the above implementation method, the offset matrix of matrix F can be the matrix shown in the 7th to 41st rows and the 0th to 16th columns in any matrix 30b-1 to 30b-8, or the matrix after the row / column transformation of the matrix; or the offset matrix of matrix F can include the matrix shown in the 4th to 41st rows and the 0th to 14th columns in any matrix 30b-1 to 30b-8, or the matrix after the row / column transformation of the matrix.

[0027] In order to support different block lengths, LDPC codes require different expansion factors Z. Based on the above implementation, in one possible implementation, a base matrix corresponding to the different expansion factors Z is used. For example, Z = a × 2 j , a∈{2,3,5,7,9,11,13,15},

[0028] If the expansion factor Z = 2 × 2 j , j=0,1,2,3,4,5,6,7, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-1, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-1, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-1, or the matrix after row / column transformation of the matrix.

[0029] If the expansion factor Z = 3 × 2 j , j=0,1,2,3,4,5,6,7, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-2, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-2, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-2, or the matrix after row / column transformation of the matrix.

[0030] If the expansion factor Z = 5 × 2 j , j=0,1,2,3,4,5,6, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-3, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-3, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-3, or the matrix after row / column transformation of the matrix.

[0031] If the expansion factor Z = 7 × 2 j, j=0,1,2,3,4,5, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-4, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-4, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-4, or the matrix after row / column transformation of the matrix.

[0032] If the expansion factor Z = 9 × 2 j , j=0,1,2,3,4,5, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-5, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-5, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-5, or the matrix after row / column transformation of the matrix.

[0033] If the expansion factor Z = 11 × 2 j , j=0,1,2,3,4,5, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-6, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-6, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-6, or the matrix after row / column transformation of the matrix.

[0034] If the expansion factor Z = 13 × 2 j , j=0,1,2,3,4, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-7, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-7, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-7, or the matrix after row / column transformation of the matrix.

[0035] If the expansion factor Z = 15 × 2 j, j=0,1,2,3,4, then the offset matrix of matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-8, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-8, or the matrix after row / column transformation of the matrix. Correspondingly, the base matrix of base graph 30a can be the matrix shown in 30b-8, or the matrix after row / column transformation of the matrix.

[0036] Further, optionally, based on the above implementation method, for each expansion factor Z, the element Pi,j=f(Vi,j,Z) in the i-th row and j-th column in the basis matrix of Z can also be obtained according to the basis matrix of the above-mentioned sets, where Vi,j is the element in the i-th row and j-th column in the basis matrix of the set where the expansion factor Z is located.

[0037] For example,

[0038]

[0039] In yet another possible implementation, the base image or base matrix may further include at least one column of built-in puncturing bit columns.

[0040] The base graph and base matrix of the LDPC matrix in the above-mentioned implementations can meet the performance requirements of code blocks with a block length of 20 to 2560 bits.

[0041] Based on the above aspects, or any possible implementation of the aspects, in another possible implementation, it further includes: determining an expansion factor Z. For example, the value of the expansion factor Z is determined according to the length K of the input sequence, such as: if the length of the input sequence is K, the minimum value satisfying 10*Z≥K can be determined from the expansion factors defined by multiple systems.

[0042] Optionally, the LDPC matrix can be obtained based on a base matrix corresponding to Z, or based on an offset matrix of Z.

[0043] For a communication device at a transmitting end, encoding the input sequence using an LDPC matrix includes:

[0044] The input sequence is encoded using an LDPC matrix corresponding to the expansion factor Z; or the LDPC matrix corresponding to the expansion factor Z is subjected to a row / column transformation, and the input sequence is encoded using a matrix after the row / column transformation. In the present application, the row / column transformation refers to a row transformation, a column transformation, or a row transformation and a column transformation.

[0045] For the communication device at the receiving end, decoding the input sequence using the LDPC matrix includes:

[0046] The input sequence is decoded using the LDPC matrix corresponding to the expansion factor Z; or the LDPC matrix corresponding to the expansion factor Z is subjected to row / column transformation, and the matrix after the row / column transformation is used to encode the input sequence. In the present application, the row / column transformation refers to row transformation, column transformation, or row transformation and column transformation.

[0047] In a possible implementation, an LDPC matrix may be saved and used to encode an input sequence, or an LDPC matrix that can be used for encoding may be obtained by transforming (row / column transformation) or extending the LDPC matrix.

[0048] In another possible implementation, parameters can be saved, and an LDPC matrix for encoding or decoding can be obtained according to the parameters, so that the input sequence can be encoded or decoded based on the LDPC matrix. The parameters include at least one of the following: a base graph, a base matrix, a transformation matrix after a base graph or base matrix row / column transformation, an extended matrix based on the base graph or base matrix, an offset value of a non-zero element in the base matrix, or any parameter related to obtaining the LDPC matrix.

[0049] In yet another possible implementation, the base matrix of the LDPC matrix may be stored in a memory.

[0050] In yet another possible implementation, a base graph of the LDPC matrix is ​​stored in a memory, and offset values ​​of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.

[0051] Based on the above possible implementation methods, in one possible design, at least one of the base graphs and base matrices used for LDPC encoding or decoding is obtained by performing row exchange, column exchange, or row and column exchange on at least one of the base graphs and base matrices of the above LDPC matrix.

[0052] In a third aspect, a communication device is provided that may include a module for executing the corresponding module in the above method design. The module may be software and / or hardware.

[0053] In one possible design, the communication device provided in the third aspect includes a processor and a transceiver component, which can be used to implement the functions of each part of the above-mentioned encoding or decoding method. In this design, if the communication device is a terminal, a base station or other network equipment, its transceiver component can be a transceiver, and if the communication device is a baseband chip or a baseband board, its transceiver component can be an input / output circuit of the baseband chip or the baseband board, which is used to realize the reception / transmission of input / output signals. The communication device can optionally also include a memory for storing data and / or instructions.

[0054] In one implementation, the processor may include an encoder as described in the first aspect and a determination unit. The determination unit is used to determine an expansion factor Z required for encoding an input sequence. The encoder is used to encode the input sequence using an LDPC matrix corresponding to the expansion factor Z.

[0055] In another implementation, the processor may include a decoder and an acquisition unit as described in the second aspect. The acquisition unit is used to acquire the soft value and expansion factor Z of the LDPC code. The decoder is used to decode the soft value of the LDPC code based on the base matrix HB corresponding to the expansion factor Z to obtain the information bit sequence.

[0056] In a fourth aspect, a communication device is provided, comprising one or more processors.

[0057] In one possible design, one or more of the processors may implement the function of the encoder described in the first aspect. In another possible design, the encoder described in the first aspect may be a part of the processor, and the processor may implement other functions in addition to implementing the function of the encoder described in the first aspect.

[0058] In one possible design, one or more of the processors may implement the functionality of the decoder described in the second aspect. In another possible design, the decoder described in the second aspect may be a part of the processor.

[0059] Optionally, the communication device may further include a transceiver and an antenna.

[0060] Optionally, the communication device may also include a device for generating a transmission block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, or a modulator for modulation processing, etc.

[0061] Optionally, the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, or a device for rate matching, etc. The functions of these devices may be implemented by one or more processors.

[0062] In one possible design, the functions of these devices may be implemented by one or more processors.

[0063] In a fifth aspect, an embodiment of the present invention provides a communication system, which includes the communication device described in the third aspect.

[0064] In a sixth aspect, an embodiment of the present invention provides a communication system, which includes one or more communication devices described in the fourth aspect.

[0065] On the other hand, an embodiment of the present invention provides a computer storage medium on which a program is stored, and when the program is run, the computer executes the method described in the above aspects.

[0066] Another aspect of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods described in the above aspects.

[0067] The information processing method, apparatus, communication device and communication system of the embodiments of the present invention can adapt to the flexible and changeable code length and code rate requirements of the system in terms of coding performance and error level. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 is a schematic diagram of a base graph, a base matrix and a circulant permutation matrix of an LDPC code;

[0069] Figure 2 is a schematic diagram of the structure of a base graph of an LDPC code;

[0070] Figure 3a A schematic diagram of an LDPC code base diagram provided by an embodiment of the present invention;

[0071] Figure 3b for Figure 3a A schematic diagram of the basis matrix of the basis graph shown;

[0072] Figure 4 A performance diagram provided for another embodiment of the present invention;

[0073] Figure 5 A schematic diagram of the structure of an information processing device provided by another embodiment of the present invention;

[0074] Figure 6 A schematic diagram of a communication system provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0075] To facilitate understanding, some terms involved in this application are explained below.

[0076] In this application, the terms "network" and "system" are often used interchangeably, and "device" and "equipment" are also often used interchangeably, but those skilled in the art can understand their meanings. "Communication device" can be a chip (such as a baseband chip, or a data signal processing chip, or a general chip, etc.), a terminal, a base station, or other network equipment. A terminal is a device with communication functions, which may include a handheld device with wireless communication functions, a vehicle-mounted device, a wearable device, a computing device, or other processing devices connected to a wireless modem, etc. In different networks, terminals can be called different names, such as: user equipment, mobile station, user unit, station, cellular phone, personal digital assistant, wireless modem, wireless communication device, handheld device, laptop, cordless phone, wireless local loop station, etc. For the convenience of description, it is referred to as a terminal in this application. A base station (BS), also known as a base station device, is a device deployed in a wireless access network to provide wireless communication functions. The names of base stations may be different in different wireless access systems. For example, in the Universal Mobile Telecommunications System (UMTS) network, the base station is called NodeB, and in the LTE network, the base station is called evolved NodeB (eNB or eNodeB), and in the new radio (NR) network, the base station is called a transmission reception point (TRP) or a next generation nodeB (gNB), or the base stations in various other evolved networks may also use other names. The present invention is not limited to this.

[0077] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0078] LDPC codes can usually be represented by a parity check matrix H. The parity check matrix H of the LDPC code can be obtained through a base graph and a shift value. The base graph can usually include m*n matrix elements (entries), which can be represented in the form of a matrix with m rows and n columns. The values ​​of the matrix elements are 0 or 1. The elements with a value of 0 are sometimes also called zero elements, indicating that the element can be replaced by a Z*Z all-zero matrix (zero matrix). The elements with a value of 1 are sometimes also called non-zero elements, indicating that the element can be replaced by a Z*Z circulant permutation matrix (circulant permutation matrix). In other words, each matrix element represents an all-zero matrix or a circulant permutation matrix. For example Figure 110a shows the elements in the base graph of an exemplary m=4, n=20 LDPC code with a QC structure. It should be noted that in this article, the row and column numbers of the base graph and the matrix are numbered from 0, just for the convenience of understanding. It can be understood that the row and column numbers can also be numbered from 1, and the corresponding row and column numbers are based on the row and column numbers shown in this article plus 1.

[0079] If the value of the element in the i-th row and j-th column of the base graph is 1, its offset value is P i,j , P i,j is an integer greater than or equal to 0, indicating that the element with a value of 1 in the i-th row and j-th column can be i,j The corresponding Z*Z circulant permutation matrix is ​​replaced by the circulant permutation matrix, which can be obtained by P-ing the Z*Z identity matrix i,j It is obtained by cyclic shifting to the right. It can be seen that by replacing each element with a value of 0 in the base graph with a Z*Z all-zero matrix, and replacing each element with a value of 1 with a Z*Z cyclic permutation matrix corresponding to its offset value, the parity check matrix of the LDPC code can be obtained. Z is a positive integer, which can also be called the lifting factor, which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z). For example, if the lifting factor Z=4, each zero element is replaced by a 4*4 all-zero matrix 11a. If P 2,3 =2, then the non-zero elements in the second row and third column are replaced by the 4*4 circulant permutation matrix 11d, which is obtained by 2 right circulant shifts of the 4*4 identity matrix 11b. If P 2,4 =0, then the non-zero element in the 2nd row and the 4th column is replaced by the unit matrix 11b. It should be noted that this is only an example and is not intended to be limiting.

[0080] Because P i,j It can be obtained based on the expansion factor Z. For the element with a value of 1 at the same position, different P values ​​may exist when different expansion factors Z are used. i,j To simplify the implementation, the system usually defines an m*n base matrix. Each element in the base matrix corresponds to each element in the base graph. The zero element in the base graph remains unchanged in the base matrix and is represented by -1. The non-zero element in the base graph with a value of 1 in the i-th row and j-th column remains unchanged in the base matrix and can be represented as V i,j , V i,j It can be an offset value defined relative to a predetermined or specific expansion factor Z, for example, relative to the maximum expansion factor Z in the set of expansion factors Z. max The offset value is, then, where V i,jIt can be to use the maximum expansion factor Z in the set where Z is located max The offset value of the non-zero element in the i-th row and j-th column. In the embodiment of the present application, the base matrix is ​​sometimes referred to as the offset matrix of the base graph matrix.

[0081] P i,j Can be based on V i,j and Z. For example, it can be expressed as P i,j =f(V i,j ,Z), where f(V i,j ,Z) indicates V i,j and Z as parameters. For example,

[0082]

[0083] like Figure 1 10b shows a basis matrix corresponding to the basis graph 10a.

[0084] Usually, the base graph or base matrix of the LDPC code can also include p columns of built-in puncture bit columns, where p can be an integer from 0 to 2. These columns participate in the coding, but the system bits corresponding to their coding are not sent. Then the code rate of the LDPC code base matrix satisfies R = (nm) / (np). For a base matrix of 4 rows and 20 columns (4*20), if there are 2 columns of built-in puncture bit columns, the code rate is (20-4) / (20-2) = 8 / 9.

[0085] The matrix size of the base graph of the LDPC code used in wireless communication systems is m*n, which can include 5 sub-matrices A, B, C, D and E. The weight of the matrix is ​​determined by the number of non-zero elements. The weight of the row (row weight) refers to the number of non-zero elements included in a row, and the weight of the column (column weight) refers to the number of non-zero elements included in a column. Figure 2 As shown in 200, wherein:

[0086] Submatrix A is m A Line n A A matrix of columns, whose size can be m A *n A , where each column corresponds to Z systematic bits in the LDPC code, and the systematic bits are sometimes also called information bits.

[0087] Submatrix B is m A Line m A A square matrix of columns, whose size can be m A *m A, each column corresponds to Z check bits in the LDPC code. The submatrix B includes a dual diagonal submatrix B' and a matrix column with a weight of 3 (referred to as a 3-column column), where the matrix column with a weight of 3 can be located before the submatrix B', such as Figure 2 As shown in 20a; the submatrix B may also include one or more matrix columns with a column weight of 1 (referred to as single column weight), for example, a possible implementation is as follows Figure 2 As shown in 20b or 20c.

[0088] Usually, the matrix generated based on sub-matrices A and B is a core matrix, which can be used to support high-bitrate encoding.

[0089] Submatrix C is an all-zero matrix with a size of m A ×m D .

[0090] Submatrix E is the identity matrix, whose size is m D ×m D .

[0091] The size of the submatrix D is m D ×(n A +m A ), which is usually used to generate low-rate check bits.

[0092] Since the structures of the sub-matrices C and E are relatively certain, the structure of the sub-matrices A, B and D is one of the factors affecting the encoding and decoding performance of the LDPC code.

[0093] Usually, LDPC codes can be obtained based on base graphs and base matrices. The density evolution method can be used to determine the upper limit of the performance of LDPC codes, and the error floor of LDPC codes can be determined based on the offset value in the base matrix. Improving the encoding and decoding performance and reducing the error floor are one of the goals of determining the base graph and base matrix. The code length in wireless communication systems is flexible and variable, for example, it can be 40 bits, 1280 bits, etc. Figure 3a , Figure 3b are examples of a base graph and base matrix of an LDPC code, respectively, which can meet the performance requirements of code blocks with a block length of 20 to 2560 bits. Figure 3b Column numbers and row numbers are shown at the top and left, respectively.

[0094] Figure 4 Given Figure 3a to Figure 3bThe performance diagram of the LDPC code shown in FIG. 1 shows that the LDPC code is obtained by encoding the base matrices corresponding to the base graph 30a, and LDPC 2 shows a commonly used LDPC code for comparison, wherein the horizontal axis shows the length of the information bit sequence in bits, and the vertical axis shows the symbol signal-to-noise ratio (Es / N0). The performance curve shows the performance of the symbol signal-to-noise ratio of LDPC 1 and LDPC 2 at different information bit sequence lengths when the BLER is 0.0001. It can be seen that under the same BLER, the symbol signal-to-noise ratio of LDPC 1 at different information bit sequence lengths is lower than that of LDPC 2, that is, the performance is better than that of LDPC 2.

[0095] Figure 3a The figure shows an example of a base graph 30a of an LDPC code, wherein the top row 0 to 51 in the figure represents column numbers, and the leftmost column 0 to 41 represents row numbers, that is, the matrix size of the base graph 30a is 42 rows and 52 columns.

[0096] Submatrix A corresponds to the system bits and has a size of m A 10 rows and 10 columns, where 4≤m A ≤7, for example, m A =4, which is composed of the elements from row 0 to row 3 and column 0 to column 9 in base graph 30a. For example, m A >4, in m A =7 as an example, in the base graph 30a, it is composed of elements from row 0 to row 6 and column 0 to column 9;

[0097] Submatrix B corresponds to the check bits and has a size of m A Line m A Column, from row 0 to row (m A -1) rows and columns 10 to (10+m A -1) The element composition of the column;

[0098] Submatrix A and submatrix B constitute the core matrix part of the LDPC code base graph, that is, they constitute an m A Row(m A +n A ) columns, can be used for high-rate coding. For the convenience of description, the following uses m A =7 as an example, the core matrix part of the base graph of the LDPC code is 7 rows and 17 columns.

[0099] Among them, the sub-matrix A may include 2 columns of built-in puncturing bit columns, and after puncturing, the code rate that the core matrix can support is 10 / (17-2)=2 / 3.

[0100] Among them, submatrix B includes 1 column and 3 columns of repetition, that is, the 0th column of submatrix B (the 10th column of the core matrix) has a column weight of 3, the 1st to 3rd columns of submatrix B (the 11th to 13th columns of the core matrix), the 0th to 3rd rows are a dual diagonal structure, and submatrix B also includes 3 columns of single column weight.

[0101] m A =7 as an example, the core matrix of the base graph 30a includes 2 rows with a weight of 10, 2 rows with a weight of 8, 2 rows with a weight of 6, and 1 row with a weight of 4. That is, the weights of each row in the core matrix formed by submatrix A and submatrix B are 8, 10, 8, 10, 4, 6 and 6 respectively. It should be noted that the order of the rows in the core matrix can be exchanged, for example, the 0th row and the 2nd row are exchanged, the 1st row and the 3rd row are exchanged, and so on. It can be one of the rows shown in the 0th to 6th rows and the 0th to the 16th columns in the core matrix of the base graph 30a respectively. The order of these rows can be exchanged, and the order of the columns can also be exchanged. For example, the 8th column and the 14th column of the core matrix can be exchanged, etc. It should be noted that this is only an example. In actual applications, the exchange of column order and row order can be flexibly designed according to system requirements.

[0102] It can be understood that since the rows and columns of the matrix can be exchanged, row exchange does not change the weight of the columns in the matrix, and column exchange does not change the weight of the rows in the matrix, the number of non-zero elements in the matrix does not change. The weights of each row of the base graph after row exchange and column exchange do not change. Using a base graph after row exchange, column exchange, or row and column exchange does not affect performance.

[0103] It should be noted that, in this application, not affecting performance means that, overall, the impact is acceptable and within the tolerance range. For example, in some scenarios or within certain ranges, the performance may decrease within the allowable range, but in some scenarios or within certain ranges, the performance is improved, and overall the performance is not significantly affected.

[0104] Generally, for a given base graph or base matrix of an LDPC code, a small modification of the matrix elements has an acceptable impact on performance. For example, in one implementation, a small modification can be made based on the core matrix of the base graph 30a, for example, the weight of one row satisfies greater than or equal to 2 and less than or equal to 5, and the weights of the remaining 6 rows respectively satisfy greater than or equal to 6 and less than or equal to 12. It can be understood that the weights of some rows can also be increased or decreased by 1 to 2 with reference to the solution provided in the present application, and the present application does not limit this.

[0105] In order to obtain a flexible code rate, sub-matrix C, sub-matrix D and sub-matrix E of corresponding sizes can be added based on the core matrix to obtain different code rates. Since sub-matrix C is an all-zero matrix and the sub-matrix is ​​a unit matrix, its size is mainly determined according to the code rate, and the structure is relatively fixed. The core matrix and sub-matrix D parts mainly affect the encoding and decoding performance. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates. For example, the core matrix part of base graph 30a or the core matrix part of base graph 80a can be used as the core matrix, and corresponding sub-matrices C, D and E are added to meet the requirements of encoding or decoding at different code rates.

[0106] The number of columns m of the submatrix D D is the sum of the number of columns of submatrices A and B, and its number of rows is mainly related to the bit rate. Taking base graph 30a as an example, if m A =4, then the number of columns of the corresponding submatrix D is (n A +m A )=14 columns, if m A =7, then the number of columns of the corresponding submatrix D is (n A +m A ) = 17 columns =. If the code rate supported by the LDPC code is R m , then the size of its base graph or base matrix is ​​m*n, where n=n A / R m +p,m=nn A =n A / R m +pn A If the minimum bit rate R m = 1 / 5, the number of built-in puncturing columns p = 2, taking base image 30a as an example, n = 52, m = 42, and the number of rows of submatrix D is m D Maximum size can be mm A =42-m A , if m A =4, then 0≤m D ≤38, if m A =7, then 0≤m D ≤35.

[0107] For the convenience of description, we can define a size of m F Row(m A +n A ) columns of the matrix F, then the submatrix D can include m D row, that is, 0≤m D ≤m F , and 35≤m F ≤38. Still in m A =7 as an example, in base diagram 30a, m A +mD =42. If m D =35, and the corresponding submatrix D is 35 rows and 17 columns, that is, the submatrix D is the matrix F, and the code rate supported by the corresponding LDPC code is 10 / 50=1 / 5. A =7, the matrix composed of rows 7 to 41 and columns 0 to 17 in base graph 30a is the matrix F. A =4, the matrix formed by the 4th to 41st rows and the 0th to 13th columns in the base graph 30a is the matrix F. It should be noted that this is only an example and is not limited to this. A It can also be any integer value from 4 to 7, and the number of columns of the matrix F will change accordingly.

[0108] In the present invention, if the same column of two adjacent rows in the base graph has at most one non-zero element, the two rows are orthogonal to each other. If the same column of two adjacent rows in the base graph has at most one non-zero element in all columns except some columns, the two rows are quasi-orthogonal.

[0109] The matrix F may include multiple rows of quasi-orthogonal structures and at least two rows of orthogonal structures. For example, the matrix F includes at least 15 rows that conform to the quasi-orthogonal structure, and in any two adjacent rows of the 15 rows, except for the built-in punctured bit columns, there is at most one non-zero element in the same column, that is, at least 15 rows in the matrix F, except for the built-in punctured bit columns, constitute a matrix block with the remaining columns having an orthogonal structure. The matrix F may also include 10 to 20 rows that conform to the orthogonal structure, that is, in these rows, there is at most one non-zero element in the same column in any two adjacent rows, that is, there is at most one non-zero element in the built-in punctured bit columns.

[0110] For example, taking base graph 30a as an example, the last 10 rows in matrix F conform to the orthogonal structure, where the weight of 9 rows is 3 and the weight of 1 row is 2. The column redistribution of matrix F can be, where the weight of 1 column is 16, the weight of 1 column is 18, the weight of 1 column is 11, the weight of 2 columns is 10, the weight of 1 column is 9, the weight of 1 column is 8, the weight of 1 column is 7, the weight of 1 column is 6, the weight of 2 columns is 4, the weight of 1 column is 3, and the weight of 2 columns is 2. If m A >4, the weights of the remaining columns in the matrix F are 0.

[0111] m A Taking =7 as an example, in the matrix F illustrated in the base diagram 30a, the row weights are 5, 3, 4, 4, 4, 3, 4, 4, 3, 3, 3, 3, 2, 3, 3, 2, 4, 2, 3, 2, 4, 2, 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3, 3.

[0112] Since the submatrix E is the identity matrix, the weights of each row in the base graph 30a are 8, 10, 8, 10, 4, 6, 6, 6, 4, 5, 5, 5, 4, 5, 5, 4, 4, 4, 4, 3, 4, 4, 3, 5, 3, 4, 3, 5, 3, 4, 4, 4, 4, 3, 4, 4, 4, 4, 4 respectively.

[0113] Still m A =7, for example, if m D =15, the size of the submatrix D in the LDPC code base graph is 15 rows and 17 columns, which can be composed of the 0th to 14th rows of the matrix F in the base graph 30a, that is, the 7th to 21st rows and the 0th to 16th columns of the base graph 30a, and the code rate supported by the corresponding LDPC code is 10 / 30=1 / 3, that is, at this code rate, the base graph of the LDPC code corresponds to the matrix part composed of the 0th to 21st rows and the 0th to 31st columns of the base graph 30a, wherein the submatrix E is a unit matrix of 15 rows and 15 columns, and the submatrix C is a matrix of all 0s of 7 rows and 15 columns;

[0114] If m D =25, the size of the submatrix D in the LDPC code base graph is 25 rows and 17 columns, which can be composed of the 0th to 24th rows of the matrix F in the base graph 30a, that is, the 7th to 31st rows and the 0th to 16th columns of the base graph 30a, and the code rate supported by the corresponding LDPC code is 10 / 40=1 / 4, that is, at this code rate, the base graph of the LDPC code corresponds to the matrix part composed of the 0th to 31st rows and the 0th to 41st columns of the base graph 30a, where the submatrix E is a unit matrix with 25 rows and 25 columns, and the submatrix C is a matrix of all zeros with 7 rows and 25 columns.

[0115] And so on, I won’t elaborate on them one by one.

[0116] It should be noted that the rows and columns in the base graph and base matrix of the LDPC code can be interchanged. For example, the 34th row and the 36th row of the base graph 30a can be interchanged, and the 44th column and the 45th column can be interchanged. For another example, the submatrix D includes the m in the matrix F. D OK, this D The rows can be swapped without swapping, or one or more rows can be swapped. The submatrix E is still a diagonal structure, and rows and columns are not swapped. For example, the 27th and 29th rows of the matrix F are swapped, and the submatrix D includes the m rows in the matrix F. D The submatrix E is still a diagonal structure. The matrix F is a quasi-orthogonal matrix before the row swap, and it is still a quasi-orthogonal matrix after the swap. It can be understood that if the base graph or base matrix includes the submatrix D, then when the columns of the core matrix are swapped, the columns in the corresponding submatrix D also need to be swapped.

[0117] like Figure 3b The illustrated base matrices 30b-1 to 30b-8 are multiple base matrix examples of the base graph 30a. The non-zero elements in the i-th row and j-th column of the base graph 30a remain in the same position in each of the base matrices 30b-1 to 30b-8, and the value is the offset value V i,j , zero elements are represented by -1 or null in the offset matrix. The corresponding part of the submatrix D in the base matrix can include the offset matrix of the matrix F. D You can choose m according to the bit rate. D The offset matrix corresponding to the submatrix D is the m in the offset matrix of the matrix F. D OK.

[0118] In one possible implementation, the offset matrix of matrix F may be the matrix shown in rows 7 to 41 and columns 0 to 16 in any matrix from 30b-1 to 30b-8, or the matrix after row / column transformation of the matrix; or the offset matrix of matrix F may include the matrix shown in rows 4 to 41 and columns 0 to 14 in any matrix from 30b-1 to 30b-8, or the matrix after row / column transformation of the matrix.

[0119] To support different block lengths, LDPC codes require different extension factors Z. For example, for extension factor Z = a × 2 j , a∈{2,3,5,7,9,11,13,15}. It can be divided into 8 sets as shown in Table 1:

[0120] Table 1

[0121] Collection 1 <![CDATA[Z=2×2 j ,j=0,1,2,3,4,5,6,7]]> Collection 2 <![CDATA[Z=3×2 j ,j=0,1,2,3,4,5,6,7]]> Collection 3 <![CDATA[Z=5×2 j ,j=0,1,2,3,4,5,6]]> Collection 4 <![CDATA[Z=7×2 j ,j=0,1,2,3,4,5]]> Collection 5 <![CDATA[Z=9×2 j ,j=0,1,2,3,4,5]]> Collection 6 <![CDATA[Z=11×2 j ,j=0,1,2,3,4,5]]> Collection 7 <![CDATA[Z=13×2 j ,j=0,1,2,3,4]]> Collection 8 <![CDATA[Z=15×2 j ,j=0,1,2,3,4]]>

[0122] In order to ensure the performance of LDPC codes under different block lengths, corresponding base matrices may be adopted based on different sets of expansion factors Z.

[0123] Among them, in one possible implementation:

[0124] If the expansion factor Z is one of the set 1, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-1, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-1, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base graph 30a can be the matrix shown in 30b-1, or the matrix after the row / column transformation of the matrix;

[0125] If the expansion factor Z is one of the set 2, the offset matrix of the matrix F can be the matrix shown in the 7th to 41st rows and the 0th to 16th columns in 30b-2, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in the 4th to 41st rows and the 0th to 14th columns in 30b-2, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base graph 30a can be the matrix shown in 30b-2, or the matrix after the row / column transformation of the matrix;

[0126] If the expansion factor Z is one of the set 3, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-3, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-3, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-3, or the matrix after the row / column transformation of the matrix;

[0127] If the expansion factor Z is one of the set 4, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-4, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-4, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-4, or the matrix after the row / column transformation of the matrix;

[0128] If the expansion factor Z is one of the set 5, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-5, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-5, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-5, or the matrix after the row / column transformation of the matrix;

[0129] If the expansion factor Z is one of the set 6, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-6, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-6, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-6, or the matrix after the row / column transformation of the matrix;

[0130] If the expansion factor Z is one of the set 7, the offset matrix of the matrix F can be the matrix shown in rows 7 to 41 and columns 0 to 16 in 30b-7, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in rows 4 to 41 and columns 0 to 14 in 30b-7, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-7, or the matrix after the row / column transformation of the matrix;

[0131] If the expansion factor Z is one of the set 8, the offset matrix of the matrix F can be the matrix shown in the 7th to 41st rows and the 0th to 16th columns in 30b-8, or the matrix after the row / column transformation of the matrix; or the offset matrix of the matrix F can be the matrix shown in the 4th to 41st rows and the 0th to 14th columns in 30b-8, or the matrix after the row / column transformation of the matrix. Correspondingly, the base matrix of the base diagram 30a can be the matrix shown in 30b-8, or the matrix after the row / column transformation of the matrix.

[0132] For example, the value of the expansion factor Z is determined according to the length K of the input sequence. For example, if the length of the input sequence is K, the minimum value satisfying 10*Z≥K can be determined from the expansion factors defined by multiple systems as the value of the expansion factor of the matrix. Furthermore, the corresponding base matrix can be selected according to the determined expansion factor.

[0133] Similarly, the rows and columns of the basis matrix can be swapped. If the basis graph undergoes at least one of row swapping and column swapping, the corresponding part of the basis matrix will also undergo the same swapping.

[0134] It can be understood that the quasi-orthogonal structure in the present application is not limited to two adjacent rows. The matrix conforming to the quasi-orthogonal structure can also be designed to include multiple groups, each group contains at least 2 rows, such as 3 rows, or 4 rows, etc., and the rows included in each group are quasi-orthogonal.

[0135] Figure 4In the performance curve shown, LDPC 1 indicates that the LDPC code is obtained by encoding a base matrix corresponding to the base graph 30a, and LDPC 2 indicates a commonly used LDPC code for comparison, wherein the horizontal axis indicates the length of the information bit sequence in bits, and the vertical axis indicates the symbol signal-to-noise ratio (Es / N0), and the performance curves are the performance of the symbol signal-to-noise ratio of LDPC 1 and LDPC 2 at different information bit sequence lengths when the BLER is 0.01 and 0.0001 respectively. It can be seen that under the same BLER, the symbol signal-to-noise ratio of LDPC 1 at different information bit sequence lengths is lower than that of LDPC 2, that is, the performance is better than that of LDPC 2.

[0136] In the encoding method provided in one embodiment of the present invention, the encoder uses an LDPC matrix to encode an input sequence; the base graph of the LDPC matrix can be any base graph in the aforementioned examples, and the base matrix of the LDPC matrix can be any base matrix in the aforementioned examples. The input sequence of the encoder can be an information bit sequence.

[0137] Furthermore, it also includes: determining an expansion factor Z; and determining the value of the expansion factor Z according to the length K of the input sequence. The information bit sequence is sometimes also called a code block, which can be obtained by dividing the transmission block into code blocks. If the length of the information bit sequence is K, a minimum value satisfying 10*Z≥K can be determined from the expansion factors defined by multiple systems, for example, K=128, and the expansion factors defined by the system include the expansion factors in each set in the aforementioned Table 1, for example, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, then Z can be determined to be 13, which is in set 7. It should be noted that this is only an example and is not intended to be limiting.

[0138] The encoder uses the LDPC matrix to encode the input sequence, which may be to use the LDPC matrix corresponding to the expansion factor Z to encode the input sequence.

[0139] For example, if Z is 13, in set 7, then the LDPC matrix is ​​obtained based on the basis matrix 3b-7 corresponding to set 7 to encode the input sequence;

[0140] In another design, the basis matrix of the factor Z can also be expanded, and the element P in the i-th row and j-th column is i,j The following relationship is satisfied:

[0141]

[0142] Among them, V i,j It can be the offset value of the element in the i-th row and j-th column in the basis matrix of the set where Z is located, that is, the offset value of the non-zero element in the i-th row and j-th column of the basis matrix of the maximum expansion factor in the set where Z is located.

[0143] For example, taking Z as 13, the element P in the i-th row and j-th column of the basis matrix is i,j satisfy

[0144]

[0145] Among them, V i,j is the offset value of the non-zero element in the i-th row and j-th column in the basis matrix 3b-7.

[0146] It should be noted that this is only an example and the present invention is not limited to this.

[0147] The LDPC matrix base matrix H B It can be any base matrix listed in the aforementioned embodiments or a base matrix with a changed row order, a changed column order, or both a changed row order and a changed column order relative to any base matrix listed in the aforementioned embodiments, and its base graph includes at least submatrix A and submatrix B, and may also include submatrix C, submatrix D and submatrix E. Each part can refer to the description in the aforementioned embodiments and will not be repeated here.

[0148] In one possible implementation, the basis matrix H of the LDPC code is B It can be stored in the memory, and the encoder obtains the LDPC matrix corresponding to the expansion factor Z, thereby encoding the input sequence. In another possible implementation, since the base matrix H of the LDPC code B There are multiple ones, and saving them in a matrix structure will take up a large storage space. The base graph of the LDPC code can also be saved in the memory, and the offset values ​​of the non-zero elements in each base matrix can be saved row by row or column by column. Then, the LDPC matrix is ​​obtained according to the offset value of the base matrix corresponding to the base graph and the expansion factor Z.

[0149] It should be noted that these are just examples and are not intended to be limiting.

[0150] When encoding the information bit sequence, the basis matrix H can be encoded according to Z B The coded LDPC matrix H is obtained by expansion. B Every non-zero element P i,j , determine the circulant permutation matrix h of size Z*Z i,j , where h i,j The identity matrix is ​​P i,jThe cyclic permutation matrix obtained by cyclic shift is h i,j Replace the non-zero elements P i,j , replace the basis matrix H with a Z*Z size all-zero matrix B The zero elements in , thus obtaining the parity check matrix H;

[0151] In a communication system, the above method can be used to encode and obtain an LDPC code. After obtaining the LDPC code, the communication device can also perform one or more of the following operations: rate matching the LDPC code; interleaving the rate-matched LDPC code according to an interleaving scheme; modulating the interleaved LDPC code according to a modulation scheme to obtain a bit sequence B; and sending the bit sequence B.

[0152] In a decoding method provided in another embodiment of the present invention, a decoder uses an LDPC matrix to decode an input sequence; the base graph of the LDPC matrix may be any base graph in the aforementioned examples, and the base matrix H of the LDPC matrix B It can be any base matrix in the above examples. The input sequence of the decoder can be a soft value sequence of the LDPC code.

[0153] Furthermore, the method further includes: determining an expansion factor Z. The communication device at the receiving end may receive a signal containing LDPC-coded signals, obtain a soft value sequence of the LDPC code, and determine a corresponding expansion factor Z.

[0154] The decoder uses the LDPC matrix to decode the input sequence, which may be to use the LDPC matrix corresponding to the expansion factor Z to decode the soft value sequence of the LDPC code.

[0155] The LDPC matrix base matrix H B It can be any base matrix listed in the aforementioned embodiments or a base matrix with a changed row order, a changed column order, or both a changed row order and a changed column order relative to any base matrix listed in the aforementioned embodiments, and its base graph includes at least submatrix A and submatrix B, and may also include submatrix C, submatrix D and submatrix E. Each part can refer to the description in the aforementioned embodiments and will not be repeated here.

[0156] In one possible design, the basis matrix H of the LDPC code is B It can be stored in a memory, and the LDPC matrix corresponding to the expansion factor Z can be obtained to decode the soft value of the LDPC code;

[0157] In another possible implementation, since there are multiple basis matrices of the LDPC code, saving them in a matrix structure will take up a large storage space. The base graph of the LDPC code can also be saved in a memory, and the offset values ​​of the non-zero elements in each basis matrix can be saved row by row or column by column. Then, the LDPC matrix is ​​obtained according to the offset value of the base matrix corresponding to the base graph and the expansion factor Z.

[0158] It should be noted that these are just examples and are not intended to be limiting.

[0159] Decoding is the inverse process of encoding, and the basis matrix H used is B It has the same characteristics as the base matrix in the encoding method embodiment. B The LDPC matrix H obtained by expansion can also refer to the encoding method embodiment.

[0160] In the communication system, before the decoding method, the communication device may also perform one or more of the following operations: receiving a signal containing LDPC-based coding, demodulating the signal, deinterleaving and derate matching to obtain soft values ​​of the LDPC code.

[0161] In one possible implementation, one or more of the following may be saved:

[0162] a) is used to obtain parameters in any base matrix HB listed in the above-mentioned implementation modes, and the base matrix HB can be obtained based on the parameters; for example, the parameters may include one or more of the following: an offset value in the base matrix, or an expansion factor, or a base graph of the base matrix, or a code rate, etc.

[0163] b) any basis matrix HB listed in the above implementations;

[0164] c) a matrix expanded based on the base matrix HB;

[0165] d) A basis matrix after row / column transformation based on any basis matrix HB listed in the above implementations. In the present application, row / column transformation refers to row transformation, or column transformation, or row transformation and column transformation;

[0166] e) A matrix expanded based on the base matrix after the row / column transformation. In a possible implementation, encoding the input sequence using a low-density parity check LDPC matrix may be performed in one or more of the following ways during the encoding or decoding process:

[0167] i. Based on the above a), a base matrix HB is obtained, and encoding or decoding is performed based on the obtained base matrix HB; or rows / columns are exchanged based on the obtained base matrix HB, and encoding or decoding is performed based on the base matrix after row / column conversion. Here, encoding or decoding based on the base matrix may optionally include encoding or decoding based on an extended matrix of the base matrix;

[0168] ii. Encoding or decoding based on the base matrix stored in b) or d) (the stored base matrix HB, or the stored base matrix after the row / column transformation of the base matrix HB), or performing row / column transformation based on the stored base matrix, and encoding or decoding based on the base matrix after the row / column transformation. Here, encoding or decoding based on the base matrix may optionally also include extended matrix encoding or decoding based on the base matrix;

[0169] iii. Encode or decode based on c) or e).

[0170] The storage involved in this application may refer to storage in one or more memories. The one or more memories may be set separately or integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal. The one or more memories may also be partially set separately and partially integrated in a decoder, a processor, a chip, a communication device, or a terminal. The type of memory may be any form of storage medium, which is not limited by this application.

[0171] Figure 5 A schematic diagram of the structure of a communication device 500 is provided, and the device 500 can be used to implement the method described in the above method embodiment, and the description in the above method embodiment can be referred to. The communication device 500 can be a chip, a base station, a terminal or other network equipment.

[0172] The communication device 500 includes one or more processors 501. The processor 501 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process the communication protocol and communication data, and the central processing unit may be used to control the communication device (such as a base station, a terminal, or a chip, etc.), execute a software program, and process the data of the software program.

[0173] In one possible design, the communication device 500 includes one or more processors 501, and the one or more processors 501 can implement the functions of the above-mentioned encoder. In another possible design, the above-mentioned encoder may be a part of the processor 501, and the processor 501 can implement other functions in addition to implementing the functions of the encoder.

[0174] The communication device 500 encodes the input sequence using an LDPC matrix; the base graph of the LDPC matrix may be any base graph in the aforementioned examples or a base graph in which the row order is changed, the column order is changed, or both the row order and the column order are changed relative to any base graph in the aforementioned examples, and the base matrix H of the LDPC matrix B It can be any base matrix in the aforementioned embodiment or a base matrix with a changed row order, a changed column order, or a changed row order and a changed column order relative to any base matrix exemplified above. The input sequence of the encoder can be an information bit sequence.

[0175] In one possible design, one or more of the processors 501 may implement the functionality of the above-mentioned decoder. In another possible design, the above-mentioned decoder may be a part of the processor 501.

[0176] The communication device 500 can be used to decode an input sequence using an LDPC matrix; the base graph of the LDPC matrix can be any base graph in the aforementioned examples or a base graph in which the row order is changed, the column order is changed, or both the row order and the column order are changed relative to any base graph in the aforementioned examples, and the base matrix H of the LDPC matrix B It can be any base matrix in the above examples or a base matrix with a changed row order, a changed column order, or a changed row order and a changed column order relative to any base matrix in the above examples. The input sequence of the decoder can be a soft value sequence.

[0177] In an optional design, the processor 501 may also include instructions 503, which can be executed on the processor to enable the communication device 500 to perform the method described in the above method embodiment.

[0178] In yet another possible design, the communication device 500 may also include a circuit, which may implement the functions of the encoder, or the decoder, or the encoder and the decoder in the aforementioned method embodiment.

[0179] Optionally, the communication device 500 may include one or more memories 502, on which instructions 504 are stored, and the instructions can be executed on the processor so that the communication device 500 performs the method described in the above method embodiment. Optionally, data can also be stored in the memory. Instructions and / or data can also be stored in the optional processor. The processor and memory can be set separately or integrated together. Optionally, one or more memories 502 can store parameters related to the base matrix, such as offset values, base graphs, expansion to matrices based on base graphs, rows in base matrices, expansion factors, etc. Optionally, the one or more memories 502 can store base matrices or expand to matrices based on base matrices.

[0180] Optionally, the communication device 500 may further include a transceiver 505 and an antenna 506. The processor 501 may be referred to as a processing unit, which controls the communication device (terminal or base station). The transceiver 505 may be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which is used to implement the transceiver function of the communication device through the antenna 506.

[0181] Optionally, the communication device 500 may further include a device for generating a transport block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, or a modulator for modulation processing, etc. The functions of these devices may be implemented by one or more processors 501 .

[0182] Optionally, the communication device 500 may further include a demodulator for demodulation, a deinterleaver for deinterleaving, or a device for rate matching, etc. The functions of these devices may be implemented by one or more processors 501 .

[0183] Figure 6 A schematic diagram of a communication system 600 is provided, wherein the communication system 600 includes a communication device 60 and a communication device 61, wherein information data is received and sent between the communication device 60 and the communication device 61. The communication device 60 and the communication device 61 may be the communication apparatus 500, or the communication device 60 and the communication device 500 may each include the communication apparatus 500, and receive and send information data. In one example, the communication device 60 may be a terminal, and the corresponding communication device 61 may be a base station; in another example, the communication device 60 may be a base station, and the corresponding communication device 61 may be a terminal.

[0184] It is also known to those skilled in the art that the various illustrative logical blocks and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions described for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0185] The various illustrative logic units and circuits described in the embodiments of the present invention can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of the above. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0186] The steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two. The memory may be a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. For example, the memory may be connected to the processor so that the processor can read information from the memory and write information to the memory. Optionally, the memory may also be integrated into the processor. The processor and the memory may be arranged in an ASIC, and the ASIC may be arranged in a UE. Optionally, the processor and the memory may also be arranged in different components in the UE.

[0187] Through the description of the above embodiments, it is clear to those skilled in the art that the present invention can be implemented in hardware, firmware, or a combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present invention is generated in whole or in part. When implemented using a software program, the above functions can also be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. Computer-readable media include computer storage media and communication media, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a computer can access. By way of example but not limitation: computer readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. In addition. Any connection can be appropriately a computer readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then coaxial cable, optical fiber cable, twisted pair, DSL or wireless technologies such as infrared, wireless and microwave are included in the definition of the medium. As used in the present invention, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blue-ray discs, where disks usually copy data magnetically, while discs use lasers to optically copy data. The above combination should also be included in the scope of protection of computer readable media.

[0188] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An information processing method, characterized in that: include: Determine the expansion factor Z; The input sequence is encoded or decoded based on a low-density parity check LDPC matrix corresponding to the expansion factor Z, wherein a base graph of the LDPC matrix includes 42 rows and 52 columns, and the base graph includes the following rows and columns of non-zero elements, i represents the row number, j represents the column number, and i and j are integers greater than or equal to 0: i=32,j=0,5,12,42; i=33,j=2,7,10,43; i=34,j=0,12,13,44; i=35,j=1,5,11,45; i=36,j=0,2,7,46; i=37,j=10,13,47; i=38,j=1,5,11,48; i=39,j=0,7,12,49; i=40,j=2,10,13,50; i=41,j=1,5,11,51; The other elements in the above row of the base graph are zero elements.

2. The method according to claim 1, characterized in that The base graph also includes the following rows and columns of non-zero elements: i=0,j=0,1,2,3,6,9,10,11; i=1,j=0,3,4,5,6,7,8,9,11,12; i=2,j=0,1,3,4,8,10,12,13; i=3,j=1,2,4,5,6,7,8,9,10,13; i=4,j=0,1,11,14; i=5,j=0,1,5,7,11,15; i=6,j=0,5,7,9,11,16; i=7,j=1,5,7,11,13,17; i=8,j=0,1,12,18; i=9,j=1,8,10,11,19; i=10,j=0,1,6,7,20; i=11,j=0,7,9,13,21; i=12,j=1,3,11,22; i=13,j=0,1,8,13,23; i=14,j=1,6,11,13,24; i=15,j=0,10,11,25; i=16,j=1,9,11,12,26; i=17,j=1,5,11,12,27; i=18,j=0,6,7,28; i=19,j=0,1,10,29; i=20,j=1,4,11,30; i=21,j=0,8,13,31; i=22,j=1,2,32; i=23,j=0,3,5,33; i=24,j=1,2,9,34; i=25,j=0,5,35; i=26,j=2,7,12,13,36; i=27,j=0,6,37; i=28,j=1,2,5,38; i=29,j=0,4,39; i=30,j=2,5,7,9,40; i=31,j=1,13,41; The other elements in the above row of the base graph are zero elements.

3. The method according to claim 1 or 2, characterized in that: The length of the input sequence is K, the value of the expansion factor Z is the minimum value of multiple expansion factors that satisfy 10×Z≥K, and Z is a positive integer.

4. The method according to any one of claims 1 to 3, characterized in that: The value of the expansion factor Z is one of the following sets: 。 5. The method according to any one of claims 1 to 4, characterized in that: The LDPC matrix is ​​an expanded matrix of the base graph, wherein each non-zero element in the base graph is replaced by a circulant permutation matrix of size Z*Z, and each zero element in the base graph is replaced by a zero matrix of size Z*Z.

6. The method according to claim 5, characterized in that The Z*Z circulant permutation matrix is ​​the Z*Z identity matrix P to the right i,j The matrix obtained by cyclic shift is P i,j Satisfy P i,j =mod(V i,j ,Z), the V i,j is the offset value corresponding to the non-zero element in the i-th row and j-th column of the base graph.

7. A coding method, characterized in that: include: The input sequence is encoded based on the basis matrix and the expansion factor Z to obtain the encoded sequence, wherein the basis matrix includes a plurality of non-zero elements (i, j), wherein i is the row number and j is the column number, and the non-zero elements (i, j) correspond to a circulant transposed matrix of size Z*Z, and the circulant permutation matrix is ​​a unit matrix of size Z*Z transposed to the right by P i,j The matrix obtained by cyclic shift is P i,j Satisfy P i,j =mod(V i,j , Z), the value V corresponding to the non-zero element (i, j) i,j as follows: i=0,V i,0 =121,V i,1 =9,V i,2 =19,V i,3 =93,V i,6 =168,V i,9 =51,V i,10 =0,V i,11 =0; i=1,V i,0 =116,V i,3 =149,V i,4 =111,V i,5 =2,V i,6 =21,V i,7 =184,V i,8 =140,V i,9 =69,V i,11 =0,V i,12 =0; i=2,V i,0 =108,V i,1 =180,V i,3 =147,V i,4 =77,V i,8 =64,V i,10 =1,V i,12 =0,V i,13 =0; i=3,V i,1 =115,V i,2 =81,V i,4 =163,V i,5 =187,V i,6 =56,V i,7 =73,V i,8 =14,V i,9 =22,V i,10 =0,V i,13 =0; i=4,V i,0 =145,V i,1 =122,V i,11 =67,V i,14 =0; i=5,V i,0 =124,V i,1 =121,V i,5 =4,V i,7 =37,V i,11 =145,V i,15 =0; i=6,V i,0 =141,V i,5 =185,V i,7 =124,V i,9 =171,V i,11 =151,V i,16 =0; i=7,V i,1 =185,V i,5 =150,V i,7 =190,V i,11 =165,V i,13 =134,V i,17 =0; i=8,V i,0 =83,V i,1 =178,V i,12 =186,V i,18 =0; i=9,V i,1 =73,V i,8 =87,V i,10 =175,V i,11 =123,V i,19 =0; i=10,V i,0 =16,V i,1 =158,V i,6 =179,V i,7 =173,V i,20 =0; i=11,V i,0 =130,V i,7 =104,V i,9 =174,V i,13 =52,V i,21 =0; i=12,V i,1 =179,V i,3 =39,V i,11 =139,V i,22 =0; i=13,V i,0 =128,V i,1 =23,V i,8 =105,V i,13 =111,V i,23 =0; i=14,V i,1 =88,V i,6 =95,V i,11 =85,V i,13 =187,V i,24 =0; i=15,V i,0 =108,V i,10 =60,V i,11 =98,V i,25 =0; i=16,V i,1 =130,V i,9 =12,V i,11 =35,V i,12 =176,V i,26 =0; i=17,V i,1 =134,V i,5 =19,V i,11 =0,V i,12 =127,V i,27 =0; i=18,V i,0 =1,V i,6 =78,V i,7 =163,V i,28 =0; i=19,V i,0 =97,V i,1 =54,V i,10 =27,V i,29 =0; i=20,V i,1 =94,V i,4 =28,V i,11 =185,V i,30 =0; i=21,V i,0 =83,V i,8 =79,V i,13 =116,V i,31 =0; i=22,V i,1 =22,V i,2 =67,V i,32 =0; i=23,V i,0 =97,V i,3 =43,V i,5 =106,V i,33 =0; i=24,V i,1 =102,V i,2 =104,V i,9 =169,V i,34 =0; i=25,V i,0 =171,V i,5 =121,V i,35 =0; i=26,V i,2 =183,V i,7 =148,V i,12 =43,V i,13 =160,V i,36 =0; i=27,V i,0 =108,V i,6 =176,V i,37 =0; i=28,V i,1 =118,V i,2 =161,V i,5 =191,V i,38 =0; i=29,V i,0 =22,V i,4 =22,V i,39 =0; i=30,V i,2 =135,V i,5 =74,V i,7 =154,V i,9 =6,V i,40 =0; i=31,V i,1 =137,V i,13 =35,V i,41 =0; i=32,V i,0 =105,V i,5 =116,V i,12 =132,V i,42 =0; i=33,V i,2 =146,V i,7 =158,V i,10 =59,V i,43 =0; i=34,V i,0 =37,V i,12 =138,V i,13 =125,V i,44 =0; i=35,V i,1 =73,V i,5 =95,V i,11 =128,V i,45 =0; i=36,V i,0 =47,V i,2 =131,V i,7 =154,V i,46 =0; i=37,V i,10 =58,V i,13 =137,V i,47 =0; i=38,V i,1 =29,V i,5 =124,V i,11 =123,V i,48 =0; i=39,V i,0 =175,V i,7 =74,V i,12 =147,V i,49 =0; i=40,V i,2 =51,V i,10 =87,V i,13 =167,V i,50 =0; i=41,V i,1 =27,V i,5 =17,V i,11 =1,V i,51 =0。 8. The method according to claim 7, characterized in that The base matrix also includes a plurality of zero elements, each of which corresponds to a zero matrix of size Z*Z.

9. The method according to claim 7 or 8, characterized in that: The base matrix includes 42 rows and 52 columns. The number of non-zero elements in each row of the base matrix is: 8, 10, 8, 10, 4, 6, 6, 4, 5, 5, 5, 4, 5, 5, 4, 4, 4, 4, 3, 44, 3, 5, 3, 4, 4, 4, 4, 4, 3, 4, 4, 4, 4.

10. The method according to any one of claims 7 to 9, characterized in that The value of the expansion factor Z is one of the following sets:

11. The method according to any one of claims 7 to 10, characterized in that: The step of encoding the input sequence based on the base matrix and the expansion factor Z to obtain the encoded sequence comprises: Based on the expansion factor Z and the base matrix, an LDPC matrix H is obtained. The input sequence is encoded according to the LDPC matrix H to obtain an encoded sequence.

12. A communication device, characterized in that: The method comprises a module for executing the method described in any one of claims 1 to 6, or a module for executing the method described in any one of claims 7 to 11.

13. A communication device, characterized in that: The system comprises one or more processors, wherein the processors execute instructions so that the method according to any one of claims 1 to 6 or claims 7 to 11 is performed.

14. The communication device according to claim 12, further comprising one or more memories, wherein the memories are used to store one or more of the following parameters: expansion factor Z, base graph, LDPC matrix, or parameters related to the LDPC matrix.

15. A computer program product, characterized in that The method comprises instructions which, when executed, cause the method as claimed in any one of claims 1 to 11 to be performed.

16. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or instruction, and when the computer program or instruction is executed, the method according to any one of claims 1 to 11 is executed.

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