Transmission and reception system and semiconductor device using the same

Abstract

The invention relates to a transmission and reception system and a semiconductor device using the same. A transmitting and receiving system includes a transmitting circuit and a receiving circuit. The transmit circuit is configured to generate a transmit signal based on an input signal. The receiving circuit is configured to generate an output signal based on the transmit signal. The transmitting circuit is configured to provide a duty cycle offset complementary to a duty cycle offset of the receiving circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0151912 filed on November 6, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology, and more particularly, to a transmitting and receiving system and a semiconductor device using the same. Background Art

[0004] The semiconductor device includes a plurality of semiconductor chips and / or a plurality of circuits. The plurality of semiconductor chips and / or a plurality of circuits can be operated by receiving different power supply voltages. When a signal propagates through a plurality of semiconductor chips and / or a plurality of circuits, it is necessary to change the voltage level of the signal. Typically, a level shifter is used to change the voltage level of the signal. For example, when a first circuit operates in a first power domain, a second circuit operates in a second power domain, and a signal is provided from the first circuit to the second circuit, the level shifter can change the voltage level of the signal from the first power domain to the second power domain. Conversely, when a signal is provided from the second circuit to the first circuit, the level shifter can change the voltage level of the signal from the second power domain to the first power domain. As the operating speed of the semiconductor system increases, the signals used in the semiconductor system and the semiconductor device can have a higher frequency and a smaller amplitude. Therefore, if a signal is transmitted or received by a typical transmitting circuit or receiving circuit, or the voltage level of the signal is changed by a typical level shifter, a distortion or phase shift of the duty cycle may occur in the changed signal. Summary of the invention

[0005] In an embodiment, a transmission and receiving system may include a transmission circuit and a receiving circuit. The transmission circuit may be configured to output a transmission signal based on an input signal. The receiving circuit may be configured to generate an output signal by shifting a voltage level of the transmission signal. The transmission circuit may provide a duty cycle offset that is complementary to a duty cycle offset of the receiving circuit.

[0006] In an embodiment, the transmission and reception system may include a transmission circuit and a reception circuit. The transmission circuit may include a plurality of drive circuits, the plurality of drive circuits having different duty cycle offsets and each configured to drive an input signal. The transmission circuit may be configured to generate a transmission signal from one of the output signals of the plurality of drive circuits based on a transmission control signal. The reception circuit may be configured to shift a voltage level of the transmission signal from a first power supply voltage to a second power supply voltage to generate an output signal.

[0007] In an embodiment, a transmission and receiving system may include a transmission circuit and a receiving circuit. The transmission circuit may be configured to generate a transmission signal based on an input signal. The receiving circuit may include a plurality of level shifters, the plurality of level shifters having different duty cycle offsets and each level shifter configured to shift a voltage level of the transmission signal. The receiving circuit may be configured to generate an output signal based on at least one of the output signals of the plurality of level shifters. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a configuration of a transmission and reception system according to an embodiment.

[0009] Figure 2 is a diagram showing a configuration of a transmission circuit according to an embodiment.

[0010] Figure 3A is a diagram showing a configuration of a duty adjustment circuit according to an embodiment.

[0011] Figure 3B is a diagram showing a method according to an embodiment of the present invention. Figure 3A A timing diagram of the operation of the duty adjustment circuit is shown.

[0012] Figure 3C is a diagram showing a configuration of a duty adjustment circuit according to an embodiment.

[0013] Figure 3D is a diagram showing a method according to an embodiment of the present invention. Figure 3C A timing diagram of the operation of the duty adjustment circuit is shown.

[0014] Figure 4 is a diagram showing a configuration of a receiving circuit according to the embodiment.

[0015] Figure 5A is a diagram showing a configuration of a level shifter according to an embodiment.

[0016] Figure 5B is a diagram showing a configuration of a level shifter according to an embodiment.

[0017] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 4 The configuration of the hybrid circuit is shown in the diagram.

[0018] Figure 7 is a diagram showing a configuration of a semiconductor device according to an embodiment.

[0019] Figure 8 is a diagram showing a configuration of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0020] Figure 11 is a diagram showing a configuration of a transmission and reception system 100 according to an embodiment. Figure 1 , the transmitting and receiving system 100 may include a transmitting circuit 110 and a receiving circuit 120. The transmitting circuit 110 may receive an input signal IN, and may generate a transmitting signal TS based on the input signal IN. Each of the input signal IN and the transmitting signal TS may be a clock signal switched at a predetermined cycle. In an embodiment, the input signal IN and the transmitting signal TS may both be signals synchronized with the clock signal, and may both be bit streams or symbols that may randomly have logic levels 0 and 1. The transmitting circuit 110 may operate in a first power domain. The transmitting circuit 110 may receive a first high power supply voltage VDD1 and a low power supply voltage VDDL. The first high power supply voltage VDD1 may have a voltage level higher than the low power supply voltage VDDL. The first power domain may be a voltage range between the first high power supply voltage VDD1 and the low power supply voltage VDDL. The transmitting circuit 110 may generate a transmitting signal TS having a voltage level varying between the first high power supply voltage VDD1 and the low power supply voltage VDDL by driving the input signal IN.

[0021] The transmitting circuit 110 may be coupled to the receiving circuit 120 via a signal transmission line 101. The transmitting circuit 110 may transmit a transmission signal TS to the receiving circuit 120 via the signal transmission line 101 by driving the signal transmission line 101 based on an input signal IN. The signal transmission line 101 may be an interconnect, a channel, a link, or a bus as a physical signal path connecting the transmitting circuit 110 and the receiving circuit 120. In an embodiment, the transmitting circuit 110 may be provided in a first semiconductor chip, the receiving circuit 120 may be provided in a second semiconductor chip, and the signal transmission line 101 may be a signal path connecting the first semiconductor chip and the second semiconductor chip. In an embodiment, the transmitting circuit 110 and the receiving circuit 120 may be provided in one semiconductor chip, and the signal transmission line 101 may be a signal path within the one semiconductor chip.

[0022] The receiving circuit 120 may be coupled to the transmitting circuit 110 through the signal transmission line 101. The receiving circuit 120 may receive the transmission signal TS transmitted by the transmitting circuit 110 through the signal transmission line 101. The receiving circuit 120 may generate an output signal OUT based on the transmission signal TS. The receiving circuit 120 may operate in a second power domain. The receiving circuit 120 may receive a second high power supply voltage VDD2 and a low power supply voltage VDDL. The second high power supply voltage VDD2 may have a voltage level higher than the low power supply voltage VDDL. The second high power supply voltage VDD2 may have a voltage level different from the voltage level of the first high power supply voltage VDD1. The second high power supply voltage VDD2 may have a voltage level higher than the first high power supply voltage VDD1. In an embodiment, the second high power supply voltage VDD2 may have a voltage level lower than the first high power supply voltage VDD1. The second power domain may be a voltage range between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The receiving circuit 120 can generate an output signal OUT having a voltage level varying between a second high power supply voltage VDD2 and a low power supply voltage VDDL by driving a transmission signal TS. The receiving circuit 120 can convert the transmission signal TS generated in the first power domain into a signal having a second power domain. In order to change the power domain of the transmission signal, the receiving circuit 120 can also receive and use the first high power supply voltage VDD1. The receiving circuit 120 can be configured to shift the voltage level of the transmission signal TS to generate the output signal OUT. For example, the receiving circuit 120 may include a level shifting circuit 121. The level shifting circuit 121 can convert the transmission signal TS having a voltage level between the first high power supply voltage VDD1 and the low power supply voltage VDDL into a signal having a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL.

[0023] Both the transmitting circuit 110 and the receiving circuit 120 may have a duty cycle offset depending on physical and / or environmental factors. The duty cycle offset may refer to the direction of change of the duty cycle and / or the amount of change of the duty cycle. In an embodiment, when the input signal IN has a duty cycle of 50%, the transmitting circuit 110 may generate a transmitting signal TS having a duty cycle of 50%. A duty cycle of 50% may indicate that the ratio of the unit interval of the high level to the unit interval of the low level is 1:1. For example, a duty cycle of 50% may indicate that the length of the high level interval and the low level interval of the clock signal are the same. When the duty cycle increases, this may indicate that the duty cycle becomes greater than the duty cycle of 50% and the unit interval of the high level becomes longer than the unit interval of the low level. When the duty cycle decreases, this may indicate that the duty cycle becomes less than the duty cycle of 50%, and the unit interval of the low level is longer than the unit interval of the high level. In fact, the transmitting circuit 110 may have a duty cycle offset, and although the input signal IN has a duty cycle of 50%, the transmitting circuit 110 may still generate a transmitting signal TS having a duty cycle greater than or less than 50%. Similarly, the receiving circuit 120 may have a duty cycle offset, and although the transmitting signal TS has a duty cycle of 50%, the receiving circuit 120 may still generate an output signal OUT having a duty cycle greater than or less than 50%. In an embodiment, if the duty cycle of the output signal OUT is not 50%, another internal circuit operating based on the output signal OUT may fail. In an embodiment, the failure may reduce the reliability of the semiconductor device. The transmitting circuit 110 and the receiving circuit 120 may perform a duty cycle adjustment operation to generate an output signal OUT having a duty cycle of 50%.

[0024] The transmitting circuit 110 may provide a duty cycle offset complementary to the duty cycle offset of the receiving circuit 120. The transmitting circuit 110 may include a duty offset generating circuit 111 to provide a complementary duty cycle offset. The duty offset generating circuit 111 may selectively change the duty cycle of the input signal IN. The duty offset generating circuit 111 may generate a transmitting signal TS having a duty cycle substantially the same as the input signal IN without changing the duty cycle of the input signal IN. In other words, the duty offset generating circuit 111 may not change the duty cycle of the input signal IN to generate the transmitting signal TS. The duty offset generating circuit 111 may generate a transmitting signal TS having a duty cycle different from the duty cycle of the input signal IN by adjusting the duty cycle of the input signal IN. Whether the duty offset generating circuit 111 performs a duty adjustment operation may be determined in association with the duty cycle offset of the receiving circuit 120. For example, when the receiving circuit 120 itself does not have a duty cycle offset or when the duty cycle offset of the receiving circuit 120 is complementary to the inherent duty cycle offset of the transmitting circuit 110, the duty cycle offset generating circuit 111 may not perform the duty cycle adjustment operation. When the duty cycle offset of the receiving circuit 120 is complementary to the duty cycle offset of the transmitting circuit 110, the change in the duty cycle occurring in the receiving circuit 120 may cancel the change in the duty cycle occurring in the transmitting circuit 110. When the receiving circuit 120 has a duty cycle offset and the duty cycle offset of the receiving circuit 120 and the duty cycle offset of the transmitting circuit 110 are different from each other, the transmitting circuit 110 may perform the duty cycle adjustment operation. The duty offset generating circuit 111 may cancel the change in the duty cycle occurring in the receiving circuit 120 by generating in advance a change in the duty cycle complementary to the change in the duty cycle occurring in the receiving circuit 120.

[0025] The duty offset generating circuit 111 may include a plurality of driving circuits. The plurality of driving circuits may have different duty cycle offsets. The level shifting circuit 121 may include a plurality of level shifters. The plurality of level shifters may respectively generate a plurality of shift signals by changing the voltage level of the transmission signal TS. The plurality of level shifters may have different duty cycle offsets. The plurality of driving circuits and the plurality of level shifters will be described in more detail below.

[0026] Figure 2 2 is a diagram showing a configuration of a transmission circuit 200 according to an embodiment. The transmission circuit 200 may be applied as Figure 1 The transmitting circuit 110 shown in FIG. Figure 2, the transmitting circuit 200 may include a relay circuit 210, a duty adjustment circuit 220, and a transmitting selection circuit 230. The relay circuit 210 and the duty adjustment circuit 220 may correspond to a plurality of driving circuits included in the duty offset generating circuit 111. In an embodiment, for example, the relay circuit 210 and the duty adjustment circuit 220 may correspond to a plurality of driving circuits included in the duty offset generating circuit 111. In an embodiment, the plurality of driving circuits may have different duty cycle offsets, and each driving circuit may be configured to drive the input signal IN. In an embodiment, the transmitting circuit 200 may be configured to generate a transmission signal TS from one of the output signals of the plurality of driving circuits based on a transmission control signal TSEL. The relay circuit 210 may receive the input signal IN and generate a first signal RS based on the input signal IN. The relay circuit 210 may generate the first signal RS by buffering the input signal IN. The relay circuit 210 may generate a first signal RS having a duty cycle substantially the same as the input signal IN without adjusting the duty cycle of the input signal IN. In an embodiment, due to an inherent duty cycle offset of the relay circuit 210 , the duty cycle of the first signal RS may have a slight difference from the duty cycle of the input signal IN.

[0027] The duty adjustment circuit 220 may receive an input signal IN and generate a second signal OS based on the input signal IN. The duty adjustment circuit 220 may generate the second signal OS by changing the duty cycle of the input signal IN. The second signal OS may have a duty cycle different from that of the input signal IN. For example, the duty adjustment circuit 220 may generate a second signal OS having a duty cycle greater than that of the input signal IN by increasing the high level interval of the input signal IN. Conversely, the duty adjustment circuit 220 may generate a second signal OS having a duty cycle less than that of the input signal IN by reducing the high level interval of the input signal IN. The amount of change in the duty cycle of the duty adjustment circuit 220 may be greater than the amount of change in the inherent duty cycle of the relay circuit 210.

[0028] The transmission selection circuit 230 may receive the first signal RS and the second signal OS from the relay circuit 210 and the duty adjustment circuit 220, respectively, and may receive the transmission control signal TSEL. The transmission selection circuit 230 may output one of the first signal RS and the second signal OS based on the transmission control signal TSEL. The logic level of the transmission control signal TSEL may be changed by considering the duty cycle offset of the transmission circuit 200 and the reception circuit 120, so that the transmission circuit 200 and the reception circuit 120 may be switched. Figure 1 The duty cycle offset of the receiving circuit 120 is canceled. When the transmission control signal TSEL has a first logic level, the transmission selection circuit 230 may output the first signal RS. When the transmission control signal TSEL has a second logic level, the transmission selection circuit 230 may output the second signal OS.

[0029] The transmitting circuit 200 may generate a transmission signal TS from an output signal of the transmission selection circuit 230. The transmitting circuit 200 may further include a transmission driver 240. The transmission driver 240 may receive an output signal of the transmission selection circuit 230. The transmission driver 240 may generate a transmission signal TS based on the output signal of the transmission selection circuit 230. The transmission driver 240 may generate a transmission signal TS by driving the output signal of the transmission selection circuit 230. The transmission driver 240 may be coupled to the signal transmission line 101, and may output the transmission signal TS by driving the signal transmission line 101 based on the output signal of the transmission selection circuit 230.

[0030] When the transmission control signal TSEL has a first logic level, the transmission selection circuit 230 may output the first signal RS generated by the relay circuit 210. The transmission driver 240 may generate a transmission signal TS based on the first signal RS. Therefore, the transmission circuit 200 may generate a transmission signal TS having a duty cycle substantially the same as the input signal IN without substantially changing the duty cycle of the input signal IN. When the transmission control signal TSEL has a second logic level, the transmission selection circuit 230 may output a second signal OS generated by the duty adjustment circuit 220. The transmission driver 240 may generate a transmission signal TS based on the second signal OS. The second signal OS may have a duty cycle different from the duty cycle of the input signal IN. The second signal OS may have a duty cycle greater than the input signal IN, or may have a duty cycle smaller than the input signal IN. The transmission circuit 200 may generate a transmission signal TS having a changed duty cycle by changing the duty cycle of the input signal IN.

[0031] Figure 3A FIG. 3 is a diagram showing a configuration of a duty adjustment circuit 310 according to an embodiment. The duty adjustment circuit 310 may be applied as Figure 2 The duty adjustment circuit 220. Figure 3A The duty adjustment circuit 310 may receive the input signal IN and generate the second signal OS by adjusting the duty cycle of the input signal IN. The duty adjustment circuit 310 may generate the second signal OS having a larger duty cycle than the input signal IN by increasing the duty cycle of the input signal IN.

[0032] The duty adjustment circuit 310 may include an inverter 311, a first buffer 312, a delay circuit 313, a first NAND gate 314, a second NAND gate 315, and a second buffer 316. The inverter 311 may receive an input signal IN and invert the input signal IN. The first buffer 312 may receive an output signal of the inverter 311 and buffer the output signal of the inverter 311. The first buffer 312 may include an even number of inverters. The delay circuit 313 may receive an output signal of the inverter 311 and delay the output signal of the inverter 311 by a first delay time tD1. The first delay time tD1 may be changed differently to adjust the duty cycle offset and / or duty cycle variance of the duty adjustment circuit 310. The delay circuit 313 may include an odd number of inverters. As the number of inverters constituting the delay circuit 313 increases, the duty cycle offset and / or the amount of change in the duty cycle of the duty adjustment circuit 310 may increase. As the number of inverters constituting the delay circuit 313 decreases, the duty cycle offset and / or the amount of duty cycle variation of the duty adjustment circuit 310 may decrease.

[0033] The first NAND gate 314 may receive an output signal of the inverter 311 and an output signal of the delay circuit 313. The second NAND gate 315 may receive an output signal of the first buffer 312 and an output signal of the first NAND gate 314. The second buffer 316 may receive an output signal of the second NAND gate 315 and may generate a second signal OS by buffering the output signal of the second NAND gate 315. The second buffer 316 may include an even number of inverters.

[0034] Figure 3B It is shown Figure 3A 1 is a timing diagram of the operation of the duty adjustment circuit 310 shown in FIG. When the logic level of the input signal IN changes from a low logic level to a high logic level, the logic level of the output signal of the second NAND gate 315 can be directly changed from a low logic level to a high logic level. Conversely, when the logic level of the input signal IN changes from a high logic level to a low logic level, the output signal of the second NAND gate 315 can be delayed by a first delay time tD1, and the logic level of the output signal of the second NAND gate 315 can change from a high logic level to a low logic level. Figure 3B As shown, the duty adjustment circuit 310 can generate a second signal OS having a high level interval, which has been increased by the first delay time tD1 compared with the input signal IN indicated by the dotted line. The second signal OS can have a larger duty cycle than the input signal IN.

[0035] Figure 3C FIG. 3 is a diagram showing a configuration of a duty adjustment circuit 330 according to an embodiment. The duty adjustment circuit 330 may be applied as Figure 2 The duty adjustment circuit 220. Figure 3CThe duty adjustment circuit 330 may receive the input signal IN and generate the second signal OS by adjusting the duty ratio of the input signal IN. The duty adjustment circuit 330 may generate the second signal OS having a smaller duty ratio than the input signal IN by reducing the duty ratio of the input signal IN.

[0036] The duty adjustment circuit 330 may include an inverter 331, a first buffer 332, a delay circuit 333, a first NOR gate 334, a second NOR gate 335, and a second buffer 336. The inverter 331 may receive an input signal IN and invert the input signal IN. The first buffer 332 may receive an output signal of the first inverter 331 and buffer the output signal of the inverter 331. The first buffer 332 may include an even number of inverters. The delay circuit 333 may receive an output signal of the inverter 331 and delay the output signal of the inverter 331 by a second delay time tD2. The second delay time tD2 may be changed differently to adjust the duty cycle offset and / or the amount of change in the duty cycle of the duty adjustment circuit 330. The delay circuit 333 may include an odd number of inverters. As the number of inverters constituting the delay circuit 333 increases, the duty cycle offset and / or the amount of change in the duty cycle of the duty adjustment circuit 330 may increase. As the number of inverters constituting the delay circuit 333 decreases, the duty cycle offset and / or the amount of duty cycle variation of the duty adjustment circuit 330 may decrease.

[0037] The first NOR gate 334 may receive the output signal of the inverter 331 and the output signal of the delay circuit 333. The second NOR gate 335 may receive the output signal of the first buffer 332 and the output signal of the first NOR gate 334. The second buffer 336 may receive the output signal of the second NOR gate 335 and may generate the second signal OS by buffering the output signal of the second NOR gate 335. The second buffer 336 may include an even number of inverters.

[0038] Figure 3D It is shown Figure 3C 3 is a timing diagram of the operation of the duty adjustment circuit 330 shown in FIG. When the logic level of the input signal IN changes from a high logic level to a low logic level, the logic level of the output signal of the second NOR gate 335 can be directly changed from a high logic level to a low logic level. Conversely, when the logic level of the input signal IN changes from a low logic level to a high logic level, the output signal of the second NOR gate 335 can be delayed by a second delay time tD2, and the logic level of the output signal of the second NOR gate 335 can change from a low logic level to a high logic level. Figure 3DAs shown in , the duty adjustment circuit 330 can generate a second signal OS having a high level interval, which has been reduced by the second delay time tD2 compared with the input signal IN indicated by the dotted line, or can generate a second signal OS having a low level interval, which is increased by the second delay time tD2 compared with the input signal IN. The second signal OS can have a smaller duty cycle than the input signal IN.

[0039] Figure 4 4 is a diagram showing a configuration of a receiving circuit 400 according to an embodiment. The receiving circuit 400 may be applied as Figure 1 The receiving circuit 120 shown in FIG. Figure 4 , the receiving circuit 400 may include a first level shifter 410, a second level shifter 420, a mixing circuit 430 and a receiving selection circuit 440. The first level shifter 410 and the second level shifter 420 may constitute Figure 1 A plurality of level shifters included in the level shift circuit 121 of the embodiment of the present invention. The first level shifter 410 may be coupled to the signal transmission line 101 and may receive the transmission signal TS. The first level shifter 410 may generate a first shift signal LS1 by changing the voltage level of the transmission signal TS. The first level shifter 410 may convert the transmission signal TS having a first power domain into a first shift signal LS1 having a second power domain. The second level shifter 420 may be coupled to the signal transmission line 101 and may receive the transmission signal TS. The second level shifter 420 may generate a second shift signal LS2 by changing the voltage level of the transmission signal TS. The second level shifter 420 may convert the transmission signal TS having a first power domain into a second shift signal LS2 having a second power domain. The first level shifter 410 and the second level shifter 420 may have different duty cycle offsets.

[0040] In an embodiment, the change direction of the duty cycle of the first level shifter 410 may be opposite to the change direction of the duty cycle of the second level shifter 420. For example, when the first level shifter 410 increases the duty cycle of the transmission signal TS, the second level shifter 420 may reduce the duty cycle of the transmission signal TS. The first level shifter 410 may generate a first shift signal LS1 having a larger duty cycle than the transmission signal TS by increasing the high level interval of the transmission signal TS. The second level shifter 420 may generate a second shift signal LS2 having a smaller duty cycle than the transmission signal TS by increasing the low level interval of the transmission signal TS. Conversely, when the first level shifter 410 reduces the duty cycle of the transmission signal TS, the second level shifter 420 may increase the duty cycle of the transmission signal TS. The first level shifter 410 may generate a first shift signal LS1 having a smaller duty cycle than the transmission signal TS by increasing the low level interval of the transmission signal TS. The second level shifter 420 can generate a second shift signal LS2 having a larger duty ratio than the transmission signal TS by increasing the high level interval of the transmission signal TS. In this case, the change amount of the duty ratio of the first level shifter 410 can be substantially the same as or different from the change amount of the duty ratio of the second level shifter 420.

[0041] In an embodiment, the change direction of the duty cycle of the first level shifter 410 may be the same as the change direction of the duty cycle of the second level shifter 420. For example, the first level shifter 410 and the second level shifter 420 may increase the duty cycle of the transmission signal TS or may reduce the duty cycle of the transmission signal TS. The first level shifter 410 and the second level shifter 420 may respectively generate the first shift signal LS1 and the second shift signal LS2 by increasing the high level interval of the transmission signal TS, each signal having a duty cycle greater than the transmission signal TS. Conversely, the first level shifter 410 and the second level shifter 420 may respectively generate the first shift signal LS1 and the second shift signal LS2 by increasing the low level interval of the transmission signal TS, each signal having a duty cycle less than the transmission signal TS. In this case, the change amount of the duty cycle of the first level shifter 410 may be different from the change amount of the duty cycle of the second level shifter 420. For example, the duty cycle of the first level shifter 410 may vary more than that of the second level shifter 420. Conversely, the duty cycle of the second level shifter 420 may vary more than that of the first level shifter 410.

[0042] The mixing circuit 430 may mix the duty cycle offset of the first level shifter 410 and the duty cycle offset of the second level shifter 420. The mixing circuit 430 may additionally adjust the duty cycle offset of the receiving circuit 400 by mixing the duty cycle offsets of the first level shifter 410 and the second level shifter 420. The mixing circuit 430 may receive the first shift signal LS1 and the second shift signal LS2 from the first level shifter 410 and the second level shifter 420, respectively. The mixing circuit 430 may generate a mixed signal MS by mixing the first shift signal LS1 and the second shift signal LS2. The mixing circuit 430 may generate a mixed signal MS having a duty cycle between the duty cycle of the first shift signal LS1 and the duty cycle of the second shift signal LS2 by mixing the first shift signal LS1 and the second shift signal LS2. For example, the mixing circuit 430 may mix the first shift signal LS1 and the second shift signal LS2 at a ratio of 1 to 1. The mixed signal MS may have a duty cycle corresponding to the middle of the duty cycles of the first shift signal LS1 and the second shift signal LS2. In an embodiment, the mixing circuit 430 may mix the first shift signal LS1 and the second shift signal LS2 at a ratio different from the ratio of 1 to 1. In order to differently adjust the duty cycle offset of the receiving circuit 400, the mixing ratio of the mixing circuit 430 may also be changed differently.

[0043] The receiving selection circuit 440 may receive the mixed signal MS from the mixing circuit 430 and the second shift signal LS2 from the second level shifter 420. The receiving selection circuit 440 may receive the receiving control signal RSEL. The receiving selection circuit 440 may output one of the mixed signal MS and the second shift signal LS2 as the output signal OUT based on the receiving control signal RSEL. The logic level of the receiving control signal RSEL may be changed by considering the duty cycle offset of the transmitting circuit 110 and the receiving circuit 400 so that the receiving circuit 400 and the receiving circuit 400 may be offset. Figure 1 For example, when the reception control signal RSEL has a first logic level, the reception selection circuit 440 may output the second shift signal LS2 as the output signal OUT. When the reception control signal RSEL has a second logic level, the reception selection circuit 440 may output the mixed signal MS as the output signal OUT.

[0044] Figure 5A 2 is a diagram showing a configuration of a level shifter 510 according to an embodiment. The level shifter 510 may be applied as Figure 4At least one of the first level shifter 410 and the second level shifter 420 in the embodiment. When the level shifter 510 is applied as the first level shifter 410, the level shifter 510 can generate a first shift signal LS1 and a complementary signal LS1B by receiving a transmission signal TS. The level shifter 510 can convert a transmission signal TS having a first power domain into a first shift signal LS1 having a second power domain. The level shifter 510 can include an inverter 511, a first transistor 512, a second transistor 513, a third transistor 514, and a fourth transistor 515. The inverter 511 can receive the transmission signal TS and invert the transmission signal TS. The inverter 511 can receive a first high power supply voltage VDD1. The inverter 511 can invert and drive the transmission signal TS between the first high power supply voltage VDD1 and the low power supply voltage VDDL. The first transistor 512 and the second transistor 513 can both be N-channel MOS transistors. The gate of the first transistor 512 can receive the first transmission signal TS. The drain of the first transistor 512 may be coupled to the negative output node ON. The source of the first transistor 512 may be coupled to a terminal supplied with a low power supply voltage VDDL. The complementary signal LS1B may be output from the negative output node ON. The gate of the second transistor 513 may receive the output signal of the inverter 511. The drain of the second transistor 513 may be coupled to the positive output node OP. The source of the second transistor 513 may be coupled to a terminal supplied with a low power supply voltage VDDL. The first shift signal LS1 may be output from the positive output node OP. The third transistor 514 and the fourth transistor 515 may both be P-channel MOS transistors. The gate of the third transistor 514 may be coupled to the positive output node OP. The source of the third transistor 514 may receive the second high power supply voltage VDD2. The drain of the third transistor 514 may be coupled to the negative output node ON. The gate of the fourth transistor 515 may be coupled to the negative output node ON. The source of the fourth transistor 515 may receive the second high power supply voltage VDD2. The drain of the fourth transistor 515 may be coupled to the positive output node OP. The duty cycle shift of the level shifter 510 may be variously changed according to the voltage levels of the first and second high power voltages VDD1 and VDD2 and the sizes of the first to fourth transistors 512, 513, 514, and 515. The size of the transistor may be a ratio of the channel width to the channel length of the transistor. Figure 4 Each of the first level shifter 410 and the second level shifter 420 in the embodiment of the present invention may have substantially the same configuration as the level shifter 510. However, the size of the transistors constituting the first level shifter 410 may be different from the size of the transistors constituting the second level shifter 420, so that the first level shifter 410 and the second level shifter 420 have different duty cycle offsets.

[0045] Figure 5B2 is a diagram showing a configuration of a level shifter 520 according to an embodiment. The level shifter 520 may be applied as Figure 4 At least one of the first level shifter 410 and the second level shifter 420 in the level shifter 520. When the level shifter 520 is applied as the first level shifter 410, the level shifter 520 can generate a first shift signal LS1 by receiving the transmission signal TS. The level shifter 520 can convert the transmission signal TS having the first power domain into the first shift signal LS1 having the second power domain. The level shifter 520 may include a first inverter 521, a second inverter 522, a third inverter 523, and a fourth inverter 524. The first inverter 521 may receive a first high power supply voltage VDD1. The second to fourth inverters 522, 523, and 524 may receive a second high power supply voltage VDD2. The first inverter 521 may receive the transmission signal TS, and may invert and drive the transmission signal TS. The output signal of the first inverter 521 may have a voltage level between the first high power supply voltage VDD1 and the low power supply voltage VDDL. The second inverter 522 may receive the output signal of the first inverter 521, and may invert and drive the output signal of the first inverter 521. The output signal of the second inverter 522 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The third inverter 523 may receive the transmission signal TS, and may invert and drive the transmission signal TS. The output signal of the third inverter 523 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The fourth inverter 524 may receive the output signal of the third inverter 523, and may invert and drive the output signal of the third inverter 523. The output signal of the fourth inverter 524 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The output signals of the third inverter 523 and the fourth inverter 524 may be mixed at the output node 525. The first shift signal LS1 may be output through the output node 525. The duty ratio shift of the level shifter 520 may be variously changed according to the voltage levels of the first and second high power supply voltages VDD1 and VDD2 and the sizes of transistors constituting the first to fourth inverters 521 , 522 , 523 , and 524 . Figure 4 The first level shifter 410 and the second level shifter 420 in the embodiment of the present invention may have substantially the same configuration as the level shifter 520. However, the size of the transistors constituting the first level shifter 410 may be different from the size of the transistors constituting the second level shifter 420, so that the first level shifter 410 and the second level shifter 420 may have different duty cycle offsets.

[0046] Figure 6 It is shown Figure 4The configuration of the mixing circuit 430 is shown in FIG. Figure 6 , the mixing circuit 430 may include a first buffer 610, a second buffer 620, a first resistor 631, a second resistor 632, a capacitor 633, and a third buffer 640. The first buffer 610 may receive a first shift signal LS1 from the first level shifter 410, and may buffer the first shift signal LS1. The second buffer 620 may receive a second shift signal LS2 from the second level shifter 420, and may buffer the second shift signal LS2. The first resistor 631 may be coupled between the first buffer 610 and the mixing node MN. One end of the first resistor 631 may receive an output signal of the first buffer 610. The other end of the first resistor 631 may be coupled to the mixing node MN. The second resistor 632 may be coupled between the second buffer 620 and the mixing node MN. One end of the second resistor 632 may receive an output signal of the second buffer 620. The other end of the second resistor 632 may be coupled to the mixing node MN. The capacitor 633 may be coupled to the mixing node MN. One end of the capacitor 633 may be coupled to the mixing node MN. The other end of the capacitor 633 may be coupled to a terminal to which a low power supply voltage VDDL is supplied. The output signals of the first buffer 610 and the second buffer 620 may be mixed at the mixing node MN through the first resistor 631 and the second resistor 632. For example, the current driving force of the first buffer 610 may be substantially the same as the current driving force of the second buffer 620. The resistance value of the first resistor 631 may be substantially the same as the resistance value of the second resistor 632. The first shift signal LS1 and the second shift signal LS2 may be mixed at the mixing node MN at a ratio of 1 to 1. If the current driving force of the first buffer 610 and the second buffer 620 and / or the resistance values ​​of the first resistor 631 and the second resistor 632 are adjusted differently, the first shift signal LS1 and the second shift signal LS2 may be mixed at the mixing node MN at a ratio different from the ratio of 1 to 1.

[0047] The operation of the transmission and reception system 100 according to the embodiment can be referred to as Figure 1 , Figure 2 and Figure 4The description is as follows. When the duty cycle offset of the transmitting circuits 110 and 200 is not expected, the transmitting circuit 200 can generate a transmitting signal TS by outputting the first signal RS output by the relay circuit 210. The receiving circuits 120 and 400 can generate a first shift signal LS1 and a second shift signal LS2 by shifting the voltage level of the transmitting signal TS. The receiving selection circuit 440 can output the mixed signal MS generated by the mixing circuit 430 as the output signal OUT. The receiving circuit 400 can generate an output signal OUT with a duty cycle of 50% by generating an output signal OUT from the mixed signal MN, thereby offsetting the duty cycle offset of the transmitting circuit 200.

[0048] When the transmitting circuit 200 changes the duty cycle of the input signal IN through the duty adjustment circuit 220, the transmitting circuit 200 may generate a transmission signal TS having a changed duty cycle based on the duty cycle offset of the duty adjustment circuit 220. In this case, the duty cycle offset of the duty adjustment circuit 220 may be complementary to the duty cycle offset of the second level shifter 420. The second level shifter 420 of the receiving circuit 400 may generate a second shift signal LS2 by shifting the voltage level of the transmission signal TS. The receiving selection circuit 440 may output the second shift signal LS2 as the output signal OUT. The receiving circuit 400 may offset the duty cycle offset of the transmitting circuit 200 by outputting the second shift signal LS2 as the output signal OUT. The output signal OUT may have a duty cycle of 50%.

[0049] When the variance of the duty cycle of the duty adjustment circuit 220 is greater than or less than the variance of the duty cycle of the second level shifter 420, the receiving circuit 400 can generate the output signal OUT based on the mixed signal MS. Since the duty cycle offset of the duty adjustment circuit 220, the duty cycle offset of the first level shifter 410, and the duty cycle offset of the second level shifter 420 are independently and differently adjusted, the transmitting and receiving system 100 can generate the output signal OUT having substantially the same duty cycle as the input signal IN.

[0050] Figure 7 is a diagram showing a configuration of a semiconductor device 700 according to an embodiment. Figure 7, the semiconductor device 700 may include a first semiconductor chip 710 and a second semiconductor chip 720. The first semiconductor chip 710 may have a structure substantially the same as the second semiconductor chip 720, and may perform the same function as the second semiconductor chip 720, or may perform a function similar to the function of the second semiconductor chip 720. In an embodiment, the first semiconductor chip 710 may have a structure different from that of the second semiconductor chip 720, and may perform a function different from that of the second semiconductor chip 720. The first semiconductor chip 710 may operate in the same power domain as the second semiconductor chip 720, and may operate in a power domain different from that of the second semiconductor chip 720. The semiconductor device 700 may include at least one signal transmission line. The first semiconductor chip 710 and the second semiconductor chip 720 may be coupled by at least one signal transmission line. For example, the semiconductor device 700 may include a first signal transmission line 701 and a second signal transmission line 702. The first semiconductor chip 710 can be coupled to the second semiconductor chip 720 through the first signal transmission line 701 and the second signal transmission line 702, and can communicate with the second semiconductor chip 720 through the first signal transmission line 701 and the second signal transmission line 702. The first signal transmission line 701 can be a unidirectional signal path from the first semiconductor chip 710 to the second semiconductor chip 720. The second signal transmission line 702 can be a bidirectional signal path. For example, the first signal transmission line 701 and the second signal transmission line 702 can both be chiplet interconnects. The first transmit signal TS1 can be transmitted through the first signal transmission line 701. The second transmit signal TS2 can be transmitted through the second signal transmission line 702.

[0051] The first semiconductor chip 710 may include a first transmission circuit 711, a second transmission circuit 713, and a first receiving circuit 714. The first transmission circuit 711 may be coupled to the first signal transmission line 701, and may generate a first transmission signal TS1 by receiving a first internal signal IS11 of the first semiconductor chip 710. The first transmission circuit 711 may transmit the first transmission signal TS1 to the second semiconductor chip 720 through the first signal transmission line 701. The second transmission circuit 713 may be coupled to the second signal transmission line 702, and may generate a second transmission signal TS2 by receiving a second internal signal IS12 of the first semiconductor chip 710. The second transmission circuit 713 may transmit the second transmission signal TS2 to the second semiconductor chip 720 through the second signal transmission line 702. The first receiving circuit 714 may be coupled to the second signal transmission line 702, and may receive the second transmission signal TS2 transmitted by the second semiconductor chip 720 through the second signal transmission line 702. The first receiving circuit 714 may generate a second internal signal IS12 from the second transmission signal TS2.

[0052] The second semiconductor chip 720 may include a first receiving circuit 722, a first transmitting circuit 723, and a second receiving circuit 724. The first receiving circuit 722 may be coupled to the first signal transmission line 701, and may receive the transmission signal TS1 transmitted by the first semiconductor chip 710 through the first signal transmission line 701. The first receiving circuit 722 may generate a first internal signal IS21 of the second semiconductor chip 720 from the first transmission signal TS1. The first transmitting circuit 723 may be coupled to the second signal transmission line 702, and may generate a second transmission signal TS2 by receiving the second internal signal IS22 of the second semiconductor chip 720. The first transmitting circuit 723 may transmit the second transmission signal TS2 to the first semiconductor chip 710 through the second signal transmission line 702. The second receiving circuit 724 may be coupled to the second signal transmission line 702, and may receive the second transmission signal TS2 transmitted by the first semiconductor chip 710 through the second signal transmission line 702. The second receiving circuit 724 may generate a second internal signal IS22 from the second transmission signal TS2.

[0053] Figure 1 and Figure 2 The transmitting circuits 110 and 200 shown in the figure can both be applied as the first transmitting circuit 711 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown in the figure can both be applied as the first receiving circuit 722 , and the first receiving circuit 722 is coupled to the first transmitting circuit 711 through the first signal transmission line 701 . Figure 1 and Figure 2 The transmitting circuits 110 and 200 shown in the figure can both be applied as the second transmitting circuit 713 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown in the figure can both be applied as a second receiving circuit 724 coupled to the second transmitting circuit 713 through the second signal transmission line 702 . Figure 1 and Figure 2 The transmitting circuits 110 and 200 shown in the figure may both be applied as the first transmitting circuit 723 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown may both be applied as a first receiving circuit 714 coupled to a first transmitting circuit 723 via a second signal transmission line 702 .

[0054] Figure 8 is a diagram showing a configuration of a semiconductor device 800 according to an embodiment. The semiconductor device 800 may be a stacked semiconductor device in which a plurality of chips and / or dies are stacked. Figure 8, the semiconductor device 800 may include a base chip 810 and a core chip 820. The semiconductor device 800 may include two or more core chips. The base chip 810 may be disposed on the lower side of the semiconductor device 800. The core chip 820 may be stacked on the base chip 810. The base chip 810 may be used as a main chip of the semiconductor device 800, and may be used as an interface chip for communicating with an external device of the semiconductor device 800. The core chip 820 may be used as a slave chip, and may store a signal sent by the base chip 810 through communication with the base chip 810 or may output a signal already stored in the core chip 820 to the base chip 810. The base chip 810 and the core chip 820 may be electrically coupled by injecting through electrodes 801 and 802 such as through silicon vias (TSVs). A signal received from an external device may be provided from the base chip 810 to the core chip 820 through the through electrodes 801 and 802. A signal output by the core chip 820 may be sent to the base chip 810 and an external device through the through electrode 802. In order to connect the through electrodes 801 and 802 of the base chip 810 and the core chip 820, bumps 803 and 804 may be provided. In an embodiment, the bumps 803 and 804 may be micro bumps.

[0055] The base chip 810 may include a first transmitting circuit (TX1) 811, a second transmitting circuit (TX2) 813, and a first receiving circuit (RX1) 814. The first transmitting circuit 811 may be coupled to the through-electrode 801, and may transmit a first internal signal BIS1 of the base chip 810 to the core chip 820 through the through-electrode 801. The second transmitting circuit 813 may be coupled to the through-electrode 802, and may transmit a second internal signal BIS2 of the base chip 810 to the core chip 820 through the through-electrode 802. The first receiving circuit 814 may be coupled to the through-electrode 802, and may receive a signal transmitted by the core chip 820 through the through-electrode 802. The first receiving circuit 814 may generate a second internal signal BIS2 based on a signal transmitted through the through-electrode 802.

[0056] The core chip 820 may include a first receiving circuit (RX1) 822, a first transmitting circuit (TX1) 823, and a second receiving circuit (RX2) 824. The first receiving circuit 822 may be coupled to the through-electrode 801, and may receive a signal transmitted by the base chip 810 through the through-electrode 801. The first receiving circuit 822 may generate a first internal signal CIS1 of the core chip 820 based on the signal transmitted through the through-electrode 801. The first transmitting circuit 823 may be coupled to the through-electrode 802, and may transmit a second internal signal CIS2 of the core chip 820 to the base chip 810 through the through-electrode 802. The second receiving circuit 824 may be coupled to the through-electrode 802, and may receive a signal transmitted by the base chip 810 through the through-electrode 802. The second receiving circuit 824 may generate a second internal signal CIS2 based on the signal transmitted through the through-electrode 802.

[0057] Figure 1 and Figure 2 The transmitting circuits 110 and 200 shown in the figure can both be applied as the first transmitting circuit 811 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown in the figure can both be applied as the first receiving circuit 822 , and the first receiving circuit 822 is coupled to the first transmitting circuit 811 through the through-electrode 801 . Figure 1 and Figure 2 Both the transmitting circuits 110 and 200 shown in FIG. 8 can be applied as the second transmitting circuit 813 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown in FIG. 8 can both be applied as the second receiving circuit 824 , and the second receiving circuit 824 is coupled to the second transmitting circuit 813 through the through-electrode 802 . Figure 1 and Figure 2 The transmitting circuits 110 and 200 shown in the figure can both be applied as the first transmitting circuit 823 . Figure 1 and Figure 4 The receiving circuits 120 and 400 shown in the figure can both be applied as the first receiving circuit 814 , and the first receiving circuit 814 is coupled to the first transmitting circuit 823 through the through-electrode 802 .

[0058] Those skilled in the art to which the present technology belongs can understand that the present technology can be implemented in a variety of other forms without departing from the technical spirit or basic features of the present technology. Therefore, it should be understood that the above embodiments are illustrative in all aspects, rather than restrictive. The scope of the present technology is defined by the appended claims rather than by the detailed description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be understood to be included in the scope of the present technology.

Claims

1. A sending and receiving system, comprising: a transmission circuit that outputs a transmission signal based on an input signal; as well as a receiving circuit that shifts the voltage level of the transmit signal to generate an output signal, The transmitting circuit provides a duty cycle offset, and the duty cycle offset is complementary to the duty cycle offset of the receiving circuit.

2. The transmission and reception system according to claim 1, wherein: The transmitting circuit provides the duty cycle offset that is complementary to the duty cycle offset of the receiving circuit so that the duty cycle offsets of the transmitting circuit and the receiving circuit are canceled.

3. The transmission and reception system according to claim 1, wherein: The transmitting circuit provides a duty cycle offset that is complementary to the duty cycle offset of the receiving circuit to generate the output signal having a duty cycle of substantially 50%.

4. The transmitting and receiving system according to claim 1, wherein: The transmitting circuit operates in a first power domain, and The receiving circuit operates in a second power domain different from the first power domain.

5. The transmission and reception system according to claim 1, wherein: The sending circuit comprises: A relay circuit, which: generates a first signal by buffering the input signal; a duty adjustment circuit, which: generates a second signal by changing the duty cycle of the input signal; and a transmission selection circuit, which: outputs one of the first signal and the second signal based on a transmission control signal, The transmission circuit generates the transmission signal from the output signal of the transmission selection circuit.

6. The transmission and reception system according to claim 5, wherein: The duty adjustment circuit generates the second signal by increasing a high level interval of the input signal, and the duty ratio of the second signal is greater than that of the input signal.

7. The transmission and reception system according to claim 5, wherein: The duty adjustment circuit generates the second signal by increasing a low level interval of the input signal, and the duty ratio of the second signal is smaller than that of the input signal.

8. The transmission and reception system according to claim 1, wherein: The receiving circuit comprises: a first level shifter, which: generates a first shift signal by shifting the voltage level of the transmission signal; a second level shifter, which: generates a second shift signal by shifting the voltage level of the transmission signal; a mixing circuit that: outputs a mixed signal by mixing the first shifted signal and the second shifted signal; and A reception selection circuit is provided, which generates the output signal from one of the mixed signal and the second shifted signal based on a reception control signal.

9. The transmitting and receiving system according to claim 8, wherein: The first level shifter generates the first shift signal having a duty cycle greater than the transmission signal, and The second level shifter generates the second shift signal having a smaller duty cycle than the transmission signal.

10. The transmitting and receiving system according to claim 8, wherein: The first level shifter generates the first shift signal having a smaller duty cycle than the transmission signal, and The second level shifter generates the second shift signal having a larger duty ratio than the transmission signal.

11. The transmission and reception system according to claim 8, wherein: The first level shifter and the second level shifter generate the first shift signal and the second shift signal, respectively, and a duty cycle of each shift signal is greater than that of the transmission signal.

12. The transmission and reception system according to claim 11, wherein: An amount of change according to the duty ratio of the first level shifter is different from an amount of change according to the duty ratio of the second level shifter.

13. The transmission and reception system according to claim 8, wherein: The first level shifter and the second level shifter generate the first shift signal and the second shift signal, respectively, and a duty cycle of each shift signal is smaller than that of the transmission signal.

14. The transmission and reception system according to claim 13, wherein: The amount of change in the duty ratio according to the first level shifter is different from the amount of change in the duty ratio according to the second level shifter.

15. A sending and receiving system, comprising: a transmission circuit including a plurality of drive circuits having different duty cycle offsets and each driving an input signal, the transmission circuit generating a transmission signal from one of output signals of the plurality of drive circuits based on a transmission control signal; as well as A receiving circuit generates an output signal by shifting the voltage level of the transmission signal from a first power supply voltage to a second power supply voltage.

16. The transmission and reception system according to claim 15, wherein: The plurality of driving circuits each include: A relay circuit, which: generates a first signal by buffering the input signal; and A duty adjustment circuit generates a second signal by changing the duty ratio of the input signal.

17. The transmission and reception system according to claim 16, wherein: The transmitting circuit further comprises: a transmission selection circuit that: outputs one of the first signal and the second signal based on the transmission control signal, and The transmission circuit generates the transmission signal from an output signal of the transmission selection circuit.

18. The transmission and reception system according to claim 15, wherein: The receiving circuit comprises: a first level shifter, which: generates a first shift signal by shifting the voltage level of the transmission signal to the second power supply voltage; a second level shifter, which: generates a second shift signal by shifting the voltage level of the transmission signal to the second power supply voltage; a mixing circuit that: outputs a mixed signal by mixing the first shifted signal and the second shifted signal; and A reception selection circuit is provided, which generates the output signal from one of the mixed signal and the second shifted signal based on a reception control signal.

19. The transmission and reception system according to claim 16, wherein: The duty cycle offset of the first level shifter is different from the duty cycle offset of the second level shifter.

20. A sending and receiving system, comprising: a transmission circuit that: generates a transmission signal based on an input signal; and A receiving circuit comprising a plurality of level shifters having different duty cycle offsets and each level shifter shifting a voltage level of the transmission signal, wherein the receiving circuit generates an output signal based on at least one of the output signals of the plurality of level shifters.

21. The transmission and reception system according to claim 20, wherein: The transmitting circuit comprises: A relay circuit, which: generates a first signal by buffering the input signal; a duty adjustment circuit, which: generates a second signal by changing the duty cycle of the input signal; and a transmission selection circuit, which: outputs one of the first signal and the second signal based on a transmission control signal, The transmission circuit generates the transmission signal from an output signal of the transmission selection circuit.

22. The transmission and reception system according to claim 20, wherein: The plurality of level shifters include: a first level shifter that: generates a first shift signal by shifting the voltage level of the transmission signal from a first power supply voltage to a second power supply voltage; and A second level shifter has a duty cycle offset different from that of the first level shifter and generates a second shift signal by shifting the voltage level of the transmission signal from the first power supply voltage to the second power supply voltage.

23. The transmission and reception system according to claim 22, wherein: The receiving circuit also includes: a mixing circuit that: outputs a mixed signal by mixing the first shifted signal and the second shifted signal; and A reception selection circuit is provided, which generates the output signal from one of the mixed signal and the second shifted signal based on a reception control signal.

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