Self-adaptive frequency distributed clock synchronization method and system, storage medium and equipment

Abstract

The invention discloses a self-adaptive frequency distributed clock synchronization method and system, a storage medium and equipment, and belongs to the field of clock synchroniss.The method comprises the steps that a clock model and a random time delay model are constructed, and in the random time delay model, random time delay is modeled into normal distribution; on the basis of the constructed clock model and the time delay model, clock parameters of the nodes are updated through a maximum likelihood estimation method, and each node estimates a logic clock of the node through two pieces of synchronous data information of neighbor nodes of the node; and adjusting the clock synchronization frequency according to the updated clock parameters of the nodes and the load of the distributed system. According to the method, the influence of random time delay on synchronization precision in communication time delay is reduced, a completely distributed synchronization method is adopted, a reference clock is not needed, the requirement for network topology is low, and fault tolerance is high; and meanwhile, the clock synchronization frequency can be adaptively adjusted, and software and hardware overhead is reduced.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization, and in particular to distributed system clock synchronization. Background Art

[0002] Clock synchronization is the basis for each node to complete control and data synchronization in a distributed system. When each node performs coordination work such as task allocation and resource scheduling, accurate clock synchronization allows all nodes to perform scheduled tasks in a unified sequence, avoiding delays or sequence errors caused by clock errors; when exchanging data or synchronizing information between nodes, consistent timestamps are an important basis for marking the sequence of events occurring in different nodes. Accurate clocks can greatly reduce problems such as version conflicts and transaction processing errors caused by time.

[0003] Clock synchronization in a distributed system requires ensuring that the clocks of all participating nodes are accurately aligned. Any change in communication delay may lead to synchronization errors. Communication delay can generally be divided into two categories: fixed delay and random delay. Fixed delay refers to the delay caused by the constant propagation speed of the signal in a specific medium during the communication process. This delay is usually predictable because it mainly depends on the length of the signal transmission path and the propagation characteristics of the medium. Random delay refers to the delay change caused by various unpredictable factors during the communication process. These factors may include network congestion, differences in device processing capabilities, environmental interference, etc.

[0004] The characteristic of random delay is that it is difficult to accurately predict and control. Due to its unpredictability, it may cause instability and low precision of clock synchronization. Especially in resource-constrained device applications in distributed environments, the probability of random delay is high, and it is particularly important to reduce the impact of random delay on clock synchronization accuracy. Summary of the invention

[0005] The purpose of the present invention is to overcome the problems existing in the prior art, especially for clock synchronization in resource-constrained device applications in a distributed environment. It aims to adjust the synchronization frequency according to the system clock deviation to synchronize the clocks so that the system clocks of all nodes in the system tend to be consistent, so as to ensure the distributed collaborative work requirements of the distributed system. An adaptive frequency distributed clock synchronization method, system, storage medium and device are provided.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] In a first aspect, an adaptive frequency distributed clock synchronization method is provided, comprising:

[0008] Constructing a clock model and a random delay model, wherein the random delay is modeled as a normal distribution in the random delay model;

[0009] Based on the constructed clock model and delay model, the clock parameters of the nodes are updated using the maximum likelihood estimation method, where each node estimates its logical clock using two synchronization data information of its neighboring nodes;

[0010] Adjust the clock synchronization frequency according to the updated clock parameters of the node and the load of the distributed system.

[0011] In some embodiments, the step of constructing a clock model includes:

[0012] The clock of each node i is modeled as a hardware clock with a fixed frequency. The current hardware clock τ of each node i i (t)Satisfy:

[0013] τ i (t) = a i t+b i

[0014] Among them, a i is the hardware clock skew that determines the clock speed, b i is the hardware clock offset, t represents time;

[0015] The relative clock slope of the two nodes is estimated based on the local clock information of node i and the local clock information of the adjacent node j. i，j for:

[0016]

[0017] in, is a collection of nodes;

[0018] Define a logical clock as the synchronization object, the logical clock L i (t) is modeled as a hardware clock τ i A linear function of (t):

[0019]

[0020] in is the logical clock skew, is the logical clock offset.

[0021] In some embodiments, constructing a random delay model includes:

[0022] In one synchronization process, two synchronization information records from the same neighbor node j are required, and the relative clock slope estimate considering the delay is for:

[0023]

[0024] Among them, τj (t′1) represents the hardware clock reading of neighbor node j at the current time, τ j (t′0) represents the hardware clock reading of neighbor node j sent at the previous moment, τ i (t1) represents the hardware clock reading recorded by node i after receiving the data packet at the current time, τ i (t0) represents the hardware clock reading recorded by node i after receiving the data packet at the previous moment; Δt is the current synchronization period, Δd C Refers to the change in fixed delay, Δd R Refers to the changing value of random delay;

[0025] D R Modeled as a random variable N(μ, σ) that follows a normal distribution 2 ), therefore, Δd R ~N(0,2σ 2 ), its probability density function is:

[0026]

[0027] according to We can get:

[0028]

[0029] So the likelihood function is:

[0030]

[0031] make have to:

[0032]

[0033] Among them, N-1 is the number of records currently stored, For the mth calculation As a result, Δt m is the real time difference of the mth synchronization.

[0034] In some embodiments, when the link is symmetrical, the fixed delays of the two communications are equal, Δd C =0, then:

[0035]

[0036] In some embodiments, each node estimates its logical clock using two synchronization data information of its neighboring nodes, including:

[0037] Node i broadcasts its clock information to neighbor node j at a set frequency;

[0038] After receiving the data packet sent by neighbor node j, it records its own hardware clock reading and stores the data packet information;

[0039] Calculate the relative clock slope estimate based on two historical logs from the same neighbor node j;

[0040] The logic slope and logic offset of the local clock are updated according to the estimated relative clock slope.

[0041] In some embodiments, updating the logic slope and logic offset of the local clock according to the estimated relative clock slope includes:

[0042] According to the relative clock slope q of neighbor node j i，j Update the logical clock parameters of node i, when That is q i，j >1, update the logical slope of node i respectively and logical offset

[0043]

[0044] when That is, when qi,i=1, update the logical offset of node i

[0045]

[0046] In some embodiments, adjusting the clock synchronization frequency according to the updated clock parameters of the node and the load of the distributed system includes:

[0047] Given the initial condition of the frequency adjustment parameters of each node i, the upper frequency limit UL i =UL0, frequency lower limit LL i =LL0, current synchronization frequency SR i (t0) = UL i , the upper limit of the logic clock difference is ΔL limit =0, synchronization required load P i =P0;

[0048] Each time node i receives synchronization data from neighbor node j, it obtains the system load parameter P(t N )∈[0,1], read the latest synchronization data record:

[0049]

[0050] Calculate the logic clock difference ΔL(t N ):

[0051]

[0052] If the system load P(t N ) and the logic clock difference ΔL(t N )satisfy:

[0053] 1-P(t N )>P i

[0054] ΔL(t N )>ΔL limit

[0055] Update synchronization frequency SR i (t N ):

[0056] SR i =min{2SR i (t N-1 ), UL i}

[0057] Otherwise update the SR i (t N )for:

[0058]

[0059] In a second aspect, an adaptive frequency distributed clock synchronization system is provided, comprising:

[0060] A model building module, used to build a clock model and a random delay model, wherein the random delay is modeled as a normal distribution in the random delay model;

[0061] A node clock parameter update module is used to update the node clock parameters based on the constructed clock model and delay model using the maximum likelihood estimation method, wherein each node estimates its logical clock using two synchronization data information of its neighboring nodes;

[0062] The clock synchronization frequency adjustment module is used to adjust the clock synchronization frequency according to the clock parameters updated by the node and the load of the distributed system.

[0063] According to a third aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the adaptive frequency distributed clock synchronization method according to the first aspect is implemented.

[0064] In a fourth aspect, an electronic device is provided, comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, and the processor executes the adaptive frequency distributed clock synchronization method described in the first aspect when executing the computer instructions.

[0065] It should be further explained that the technical features corresponding to the above embodiments can be combined or replaced with each other to form a new technical solution without conflict.

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] (1) The present invention divides the communication delay in the clock synchronization process into fixed delay and random delay, wherein the random delay is modeled as a normal distribution, so as to use the maximum likelihood estimation method to estimate the relative clock skew, thereby reducing the impact of the random delay in the communication delay on the synchronization accuracy.

[0068] (2) The present invention adopts a fully distributed synchronization method and does not require a reference clock. Each node estimates the relative clock slope using two adjacent synchronization data information of neighboring nodes. The node does not need to know the clock information of all nodes, and there is no node that provides a standard clock. Therefore, the requirements for network topology are relatively low and the fault tolerance is high.

[0069] (3) The present invention can adaptively adjust the clock synchronization frequency and reduce the software and hardware overhead. The frequency of actively broadcasting clock synchronization data packets to neighboring nodes is adjusted according to the distributed system load information and the logical clock gap between neighboring nodes, which can effectively reduce the system software and hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 A flow chart of an adaptive frequency distributed clock synchronization method according to an embodiment of the present invention;

[0071] Figure 2 The figure is a schematic diagram of sending two synchronization data packets in one synchronization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The technical solution of the present invention is clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various configurations. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0073] It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned problems and the solutions proposed in the embodiments of the present application for the above-mentioned problems below should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as technical contents known to technical personnel in this field.

[0074] In view of the technical problems pointed out in the background technology, the embodiments provided by the present invention are as follows:

[0075] Example 1

[0076] In an exemplary embodiment, an adaptive frequency distributed clock synchronization method is provided, referring to Figure 1 , methods include:

[0077] S1. Constructing a clock model and a random delay model, wherein the random delay model is modeled as a normal distribution;

[0078] S2. Based on the constructed clock model and delay model, the clock parameters of the nodes are updated using the maximum likelihood estimation method, wherein each node estimates its logical clock using two synchronization data information of its neighboring nodes;

[0079] S3. Adjust the clock synchronization frequency according to the updated clock parameters of the node and the load of the distributed system.

[0080] Specifically, in the clock synchronization process, communication delay is the main problem affecting the synchronization accuracy. In the present invention, in step S1, the communication delay is divided into fixed delay and random delay, wherein the fixed delay is mainly the propagation delay, which is related to the link length and properties. The random delay is modeled as a normal distribution, and the problem is abstracted to deeply study and analyze the parameter estimation problem in synchronization.

[0081] After the model is built, in step S2, the clock parameters of the nodes are updated using the clock synchronization method based on maximum consistency. The clock synchronization method is used to synchronize the system clocks of each node in a distributed network system, and mainly includes the following key contents:

[0082] Local clock broadcast: Node i broadcasts its own clock information to neighbor node j at a set frequency;

[0083] Neighbor node information log storage: After receiving the data packet sent by neighbor node j, it records its own hardware clock reading and stores the data packet information;

[0084] Relative clock slope estimation: Calculate the relative clock slope estimate based on two historical logs from the same neighbor node j;

[0085] Local clock parameter update: The logic slope and logic offset of the local clock are updated according to the estimated relative clock slope.

[0086] Furthermore, in step S3, a method for adjusting the clock synchronization frequency according to the clock difference between itself and neighboring nodes is proposed. The clock synchronization frequency is the frequency at which node i actively sends synchronization data packets to neighboring node j. The factors that determine the frequency adjustment include the current system load and the neighboring logical clock difference.

[0087] Among them, the clock model and delay model are the basis of the entire framework. It is used to describe and model the relationship between the node hardware clock and the logical clock during the clock synchronization process, as well as the composition and properties of the communication delay. It provides the necessary basis for subsequent clock synchronization and frequency adjustment.

[0088] The clock synchronization method based on maximum consistency in S2 is based on the S1 model and provides a clock synchronization method in a distributed environment. This method sends clock synchronization packets to neighbors and uses the received packets to update its own logical clock parameters through steps such as local clock broadcast, neighbor node information log storage, relative clock slope estimation, and local logical clock update.

[0089] The adaptive synchronization frequency adjustment in S3 is an extension of S2. It adjusts the clock synchronization frequency based on the information obtained in S2 and the system load, taking into account the difference between the logical clocks of the node and its neighbor nodes.

[0090] Example 2

[0091] Based on the inventive concept of embodiment 1, this embodiment introduces a specific clock synchronization process in detail, wherein the clock model is constructed, including:

[0092] The clock of each distributed node i is modeled as a hardware clock with a fixed frequency, that is, the clock change rate remains unchanged. The current hardware clock reading τ of each node i i (t)Satisfy:

[0093] τ i (t) = a i t+b i (1)

[0094] Among them, a i is the hardware clock skew that determines the clock speed, b i is the hardware clock offset, and t represents time. Since the sensor node cannot obtain the real time t, it is impossible to directly calculate a through (1). i and b i However, the relative clock slope a of the two nodes can be estimated based on the local clock information of node i and the local clock information of the adjacent node j. i，j , relative clock slope a i，j for:

[0095]

[0096] in, Is a collection of distributed nodes.

[0097] In the present invention, the default hardware clock is not allowed to be modified, so it is necessary to define a logical clock as the synchronization object. The logical clock L i (t) is modeled as a hardware clock τ i A linear function of (t):

[0098]

[0099] in is the logical clock skew, is the logical clock offset.

[0100] In the absence of delay, the relative clock slope a i，j It can be calculated based on the hardware clock readings of the two nodes:

[0101]

[0102] Reference Figure 2 , construct a random delay model, including:

[0103] During a synchronization process, two synchronization information records from the same neighbor node j are required. Since the synchronization data packet needs to be sent and received through the network link when transmitting, there will be network delay. Figure 2 It can be seen that the relative clock slope estimate considering the delay is for:

[0104]

[0105] Among them, τ j (t′1) represents the hardware clock reading of neighbor node j at the current time, τ j (t′0) represents the hardware clock reading of neighbor node j sent at the previous moment, τ i (t1) represents the hardware clock reading recorded by node i after receiving the data packet at the current time, τ i (t0) represents the hardware clock reading recorded by node i after receiving the data packet at the previous moment. The real time difference between the two moments in the transmission process is t k -t′ k =d k ; Δt is the current synchronization period, Δd C refers to the change value of the fixed delay, and ΔdR refers to the change value of the random delay;

[0106] D R Modeled as a random variable N(μ, σ) that follows a normal distribution 2 ), therefore, Δd R ~N(0,2σ 2 ), its probability density function is:

[0107]

[0108] according to We can get:

[0109]

[0110] So the likelihood function is:

[0111]

[0112] make have to:

[0113]

[0114] Among them, N-1 is the number of records currently stored, For the mth calculation As a result, Δt m is the real time difference of the mth synchronization.

[0115] When the link is symmetrical, the fixed delays of the two communications are equal, Δd C =0, then:

[0116]

[0117] In step S2, clock synchronization is performed based on maximum consistency, specifically including:

[0118] 1) Each node must first be initialized, giving the initial conditions of the logical clock parameters Δt0=1, Set the initial synchronization period to T0.

[0119] 2) According to the current synchronization period T, when the hardware clock reading meets When node i sends its own clock information Broadcast to neighbor node j.

[0120] 3) Node i at t N When receiving a synchronization information packet from neighbor node j, the synchronization information is saved as a record If there is a historical record at this time, then calculate according to formula (10) and q i，j :

[0121]

[0122] Calculate Δt N :

[0123] Δt N =max{(τ i(t N )-τ i (t N-1 )),(τ j (t N )-τ j (t N-1 ))} (12)

[0124] Remove the last historical synchronization data record Save the estimation results And remove the earliest data in FIFO mode according to the set maximum storage quantity.

[0125] 4) According to the relative clock slope q of neighbor node j i，j Update the logical clock parameters of node i, when That is q i，j >1, update the logical slope of node i respectively and logical offset

[0126]

[0127] when That is, when qi,i=1, update the logical offset of node i

[0128]

[0129] Further, the adaptive synchronization frequency adjustment in step S3 includes:

[0130] 1) Given the initial condition of the frequency adjustment parameters of each node i, the upper frequency limit UL i =UL0, frequency lower limit LL i =LL0, current synchronization frequency SR i (t0) = UL i , the upper limit of the logic clock difference is ΔL limit =0, synchronization required load P i =P0;

[0131] 2) Each time node i receives synchronization data from neighbor node j, it obtains the system load parameter P(t N )∈[0,1], read the latest synchronization data record:

[0132]

[0133] Calculate the logic clock difference ΔL(t N ):

[0134]

[0135] If the system load P(tN ) and the logic clock difference ΔL(t N )satisfy:

[0136] 1-P(t N )>P i (16)

[0137] ΔL(t N )>ΔL limit (17)

[0138] Update synchronization frequency SR i (t N ):

[0139] SR i =min{2SR i (t N-1 ), UL i} (18)

[0140] Otherwise update the SR i (t N )for:

[0141]

[0142] At this point, the synchronization process of adjusting the clock synchronization frequency according to the clock gap between itself and neighboring nodes is completed. The fully distributed synchronization method does not require a reference clock. Each node estimates the relative clock slope using the two adjacent synchronization data information of its neighbors. The node does not need to know the clock information of all nodes, and there is no node that provides a standard clock. The requirements for network topology are low and the fault tolerance is high. At the same time, the frequency of actively broadcasting clock synchronization packets to neighboring nodes is adjusted according to the system load information and the logical clock gap between neighbors, which can effectively reduce the system software and hardware overhead.

[0143] Example 3

[0144] Based on the same inventive concept as that of Embodiment 1, an adaptive frequency distributed clock synchronization system is provided, comprising:

[0145] A model building module, used to build a clock model and a random delay model, wherein the random delay is modeled as a normal distribution in the random delay model;

[0146] A node clock parameter update module is used to update the node clock parameters based on the constructed clock model and delay model using the maximum likelihood estimation method, wherein each node estimates its logical clock using two synchronization data information of its neighboring nodes;

[0147] The clock synchronization frequency adjustment module is used to adjust the clock synchronization frequency according to the clock parameters updated by the node and the load of the distributed system.

[0148] Example 4

[0149] Based on the same inventive concept as Example 1, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the adaptive frequency distributed clock synchronization method provided by the embodiment of the present invention is implemented. Based on such an understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0150] Example 5

[0151] Based on the same inventive concept as Example 1, an electronic device is provided, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor executes the computer instructions, the adaptive frequency distributed clock synchronization method provided in the embodiment of the present invention is executed.

[0152] The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0153] Embodiments of the subject matter and functional operations described in this specification may be implemented in: tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode and transmit information to a suitable receiver device for execution by the data processing device.

[0154] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application-specific integrated circuits), and the apparatus can also be implemented as special purpose logic circuits.

[0155] Processors suitable for executing computer programs include, for example, general and / or special microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory and / or a random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include one or more large-capacity storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or the computer will be operably coupled to this large-capacity storage device to receive data from it or to transmit data to it, or both. However, the computer does not necessarily have such a device. In addition, the computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, just to name a few.

[0156] It should be understood that each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0157] The above specific implementation methods are detailed descriptions of the present invention. It cannot be determined that the specific implementation methods of the present invention are limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions and substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. An adaptive frequency distributed clock synchronization method, characterized in that: include: Constructing a clock model and a random delay model, wherein the random delay is modeled as a normal distribution in the random delay model; Based on the constructed clock model and delay model, the clock parameters of the nodes are updated using the maximum likelihood estimation method, where each node estimates its logical clock using two synchronization data information of its neighboring nodes; Adjust the clock synchronization frequency according to the updated clock parameters of the node and the load of the distributed system.

2. The adaptive frequency distributed clock synchronization method according to claim 1, characterized in that: The clock model is constructed, comprising: The clock of each node i is modeled as a hardware clock with a fixed frequency. The current hardware clock τ of each node i i (t)Satisfy: τ i (t)=a i t+b i Among them, a i is the hardware clock skew that determines the clock speed, b i is the hardware clock offset, t represents time; The relative clock slope of the two nodes is estimated based on the local clock information of node i and the local clock information of the adjacent node j. i,j for: in, is a collection of nodes; Define a logical clock as the synchronization object, the logical clock L i (t) is modeled as a hardware clock τ i Linear function of (t): in is the logical clock skew, is the logical clock offset.

3. The adaptive frequency distributed clock synchronization method according to claim 2, characterized in that: Construct a random delay model, including: In one synchronization process, two synchronization information records from the same neighbor node j are required, and the relative clock slope estimate considering the delay is for: Among them, τ j (t'1) represents the hardware clock reading sent by neighbor node j at the current time, τ j (t'0) represents the hardware clock reading of neighbor node j sent at the previous moment, τ i (t1) represents the hardware clock reading recorded by node i after receiving the data packet at the current time, τ i (t0) represents the hardware clock reading recorded by node i after receiving the data packet at the previous moment; Δt is the current synchronization period, Δd C Refers to the change in fixed delay, Δd R Refers to the changing value of random delay; D R Modeled as a random variable N(μ,σ 2 ), therefore, Δd R ~N(0,2σ 2 ), its probability density function is: according to We can get: So the likelihood function is: make have to: Among them, N-1 is the number of records currently stored, For the mth calculation As a result, Δt m is the real time difference of the mth synchronization.

4. The adaptive frequency distributed clock synchronization method according to claim 3, characterized in that: When the link is symmetrical, the fixed delays of the two communications are equal, Δd C =0, then:

5. The adaptive frequency distributed clock synchronization method according to claim 4, characterized in that: Each node estimates its logical clock using two synchronization data information of its neighboring nodes, including: Node i broadcasts its clock information to neighbor node j at a set frequency; After receiving the data packet sent by neighbor node j, it records its own hardware clock reading and stores the data packet information; Calculate the relative clock slope estimate based on two historical logs from the same neighbor node j; The logic slope and logic offset of the local clock are updated according to the estimated relative clock slope.

6. The adaptive frequency distributed clock synchronization method according to claim 5, characterized in that: The updating of the logic slope and logic offset of the local clock according to the estimated relative clock slope comprises: According to the relative clock slope q of neighbor node j i,j Update the logical clock parameters of node i, when That is q i,j >1, update the logical slope of node i respectively and logical offset when That is q i,j =1, update the logical offset of the i node 7. The adaptive frequency distributed clock synchronization method according to claim 6, characterized in that: The adjusting the clock synchronization frequency according to the updated clock parameters of the node and the load of the distributed system includes: Given the initial condition of the frequency adjustment parameters of each node i, the upper frequency limit UL i =UL0, frequency lower limit LL i =LL0, current synchronization frequency SR i (t0) = UL i , the upper limit of the logic clock difference is ΔL limit =0, synchronization required load P i =P0; Each time node i receives synchronization data from neighbor node j, it obtains the system load parameter P(t N )∈[0,1], read the latest synchronization data record: Calculate the logic clock difference ΔL(t N ): If the system load P(t N ) and the logic clock difference ΔL(t N )satisfy: 1-P(t N )>P i ΔL(t N )>ΔL limit Update synchronization frequency SR i (t N ): SR i =min{2SR i (t N-1 ),UL i } Otherwise update the SR i (t N )for:

8. An adaptive frequency distributed clock synchronization system, characterized in that: include: A model building module, used to build a clock model and a random delay model, wherein the random delay model is modeled as a normal distribution; A node clock parameter update module is used to update the node clock parameters based on the constructed clock model and delay model using the maximum likelihood estimation method, wherein each node estimates its logical clock using two synchronization data information of its neighboring nodes; The clock synchronization frequency adjustment module is used to adjust the clock synchronization frequency according to the clock parameters updated by the node and the load of the distributed system.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the adaptive frequency distributed clock synchronization method described in any one of claims 1 to 7 is implemented.

10. An electronic device comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, wherein: When the processor runs the computer instructions, it executes the adaptive frequency distributed clock synchronization method described in any one of claims 1-7.

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