Clock synchronization method and device, computer readable medium and electronic equipment

Abstract

The embodiment of the invention provides a clock synchronization method and device, a computer readable medium and electronic equipment. The clock synchronization method comprises the following steps: acquiring network state information of target equipment, wherein the target equipment is equipment needing to be subjected to clock synchronization with a clock synchronization server; if the network transmission quality between a clock synchronization server and target equipment is determined to be greater than or equal to a set threshold value according to the network state information, entering a clock adjustment stage, and correcting clock information of the target equipment in the clock adjustment stage; and if the clock skew between the target device and the clock synchronization server is adjusted to a set range, entering a clock holding stage, and determining whether to switch to the clock adjustment stage according to the network state information in the clock holding stage. According to the technical scheme of the embodiment of the invention, clock synchronization processing can be performed based on the network state information of the equipment, and the clock synchronization precision can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer and communication technology, and in particular to a clock synchronization method, device, computer-readable medium and electronic device. Background Art

[0002] Clock synchronization is based on a set reference time, and clock synchronization protocols are used to achieve clock consistency among multiple devices. Common clock synchronization protocols include NTP (Network Time Protocol) and PTP (Precision Time Protocol). However, the impact of network changes on the clock synchronization process is not considered in the specific implementation of the NTP protocol and the PTP protocol, which will affect the accuracy of clock synchronization due to network problems. Summary of the invention

[0003] The embodiments of the present application provide a clock synchronization method, apparatus, computer-readable medium, and electronic device, which can perform clock synchronization processing based on the network status information of the device, thereby facilitating improving the accuracy of clock synchronization.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0005] In the first aspect, an embodiment of the present application provides a clock synchronization method, comprising: obtaining network status information of a target device, wherein the target device is a device that needs to perform clock synchronization with the clock synchronization server; if it is determined based on the network status information that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, then entering a clock adjustment phase, and performing correction processing on the clock information of the target device within the clock adjustment phase; if the clock deviation between the target device and the clock synchronization server is adjusted to within a set range, then entering a clock holding phase, and determining whether to switch to the clock adjustment phase based on the network status information within the clock holding phase.

[0006] In the second aspect, an embodiment of the present application provides a clock synchronization device, comprising: an acquisition unit, configured to acquire network status information of a target device, wherein the target device is a device that needs to perform clock synchronization with the clock synchronization server; a processing unit, configured to enter a clock adjustment phase if it is determined based on the network status information that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, and to perform correction processing on the clock information of the target device within the clock adjustment phase; a control unit, configured to enter a clock holding phase if the clock deviation between the target device and the clock synchronization server is adjusted to within a set range, and to determine whether to switch to the clock adjustment phase based on the network status information within the clock holding phase.

[0007] In a third aspect, an embodiment of the present application provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the clock synchronization method as described in the above embodiment is implemented.

[0008] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: one or more processors; a storage device for storing one or more computer programs, wherein when the one or more computer programs are executed by the one or more processors, the electronic device implements the clock synchronization method as described in the above embodiments.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of an electronic device reads and executes the computer program from the computer-readable storage medium, so that the electronic device executes the clock synchronization method provided in the above-mentioned various optional embodiments.

[0010] In the technical solutions provided in some embodiments of the present application, the network status information of the target device can be obtained, and then when it is determined that the network transmission quality between the clock synchronization server and the target device is greater than or equal to the set threshold value according to the network status information, the clock adjustment phase is entered, and the clock information of the target device is corrected in the clock adjustment phase. If the clock deviation between the target device and the clock synchronization server is adjusted to within the set range, the clock holding phase is entered, and whether to switch to the clock adjustment phase is determined according to the network status information in the clock holding phase. It can be seen that in the technical solutions of the embodiments of the present application, the clock synchronization process of the target device can be controlled according to the network status information of the target device that needs to be clock synchronized, so that when the network transmission quality between the clock synchronization server and the target device is greater than or equal to the set threshold value, the clock adjustment phase is entered to correct the clock of the target device, ensuring that the clock synchronization process is performed when the network transmission quality is good, thereby improving the accuracy of clock synchronization. When the clock deviation between the target device and the clock synchronization server is adjusted to within the set range, the clock holding phase is entered, and during the clock holding phase, it is determined whether to switch to the clock adjustment phase based on the network status information. This allows the clock to be adjusted after the clock deviation is adjusted to within the set range, thereby avoiding the clock adjustment phase from being in place all the time and increasing the processing load of the clock synchronization server. In addition, it is possible to determine in time whether to switch to the clock adjustment phase by detecting the network status information of the target device, thereby ensuring that the clock information of the target device can be adjusted in time to achieve more precise clock accuracy.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of the synchronization process of the PTP protocol is shown;

[0013] Figure 2 A schematic diagram showing an exemplary system architecture to which the technical solution of the embodiments of the present application can be applied;

[0014] Figure 3 A flowchart of a clock synchronization method according to an embodiment of the present application is shown;

[0015] Figure 4 A flowchart of a clock synchronization method according to an embodiment of the present application is shown;

[0016] Figure 5 An architectural diagram of a clock synchronization system according to an embodiment of the present application is shown;

[0017] Figure 6A schematic diagram of a clock synchronization process according to an embodiment of the present application is shown;

[0018] Figure 7 A schematic diagram of a client data structure according to an embodiment of the present application is shown;

[0019] Figure 8 A block diagram of a clock synchronization device according to an embodiment of the present application is shown;

[0020] Fig. 9 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] The exemplary embodiments are now described in a more comprehensive manner with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to these examples; on the contrary, the purpose of providing these embodiments is to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0022] In addition, the features, structures or characteristics described in the present application may be combined in one or more embodiments in any suitable manner. In the following description, there are many specific details so that the embodiments of the present application can be fully understood. However, those skilled in the art will appreciate that when implementing the technical scheme of the present application, all the detailed features in the embodiments may not be needed, one or more specific details may be omitted, or other methods, elements, devices, steps, etc. may be adopted.

[0023] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0024] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0025] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0026] It is understandable that the present application may display a prompt interface or pop-up window before and during the process of collecting relevant data (such as network status data, application data, etc.), and the prompt interface or pop-up window is used to prompt the user that the relevant data is currently being collected, so that the present application only starts to execute the relevant steps of obtaining the relevant data after obtaining the user's confirmation operation on the prompt interface or pop-up window, otherwise (that is, when the user's confirmation operation on the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the relevant data are terminated, that is, the relevant data is not obtained. In other words, all data collected by the present application are collected with the user's consent and authorization, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0027] Before introducing the technical solution of the embodiment of the present application, the commonly used clock synchronization protocols, namely the NTP protocol and the PTP protocol, are first introduced.

[0028] The NTP protocol is a protocol used to synchronize the clocks of various devices in the network. It can provide a unified time reference for distributed systems, so that different devices can synchronize time with each other. In many application scenarios, such as server clusters, network devices, distributed systems, communication equipment, and power systems, the NTP protocol plays a very important role. The NTP protocol is implemented based on UDP (User Datagram Protocol) and obtains time information through requests and responses. The NTP protocol uses a hierarchical tree structure to describe and manage network devices, making operations such as adding, deleting, and modifying network devices very flexible and convenient.

[0029] The working principle of the NTP protocol is to first establish a network time reference within the system, and then synchronize the network devices according to the reference time through the NTP protocol. During the synchronization process, the NTP protocol will calibrate and adjust the clocks of network devices to ensure that the clocks between network devices remain consistent. Since the NTP protocol adopts a layered network structure, the accuracy requirements for time synchronization are different for devices at different levels. Generally speaking, the higher the level of the device, the higher the accuracy requirements for time synchronization. The NTP protocol is widely used in many fields. For example, in a server cluster, the NTP protocol can keep the clocks between servers consistent, thereby improving the availability and reliability of services; in network devices, the NTP protocol can keep the time of routers, switches and other devices consistent, improving the efficiency and stability of network operation; in communication equipment, the NTP protocol can keep the time of base stations, switches, routers and other devices consistent, improving the reliability and security of communication; in the power system, the NTP protocol can keep the time of power equipment consistent, improving the stability and reliability of the power system.

[0030] The PTP protocol is a network time protocol that can achieve time synchronization in the network so that devices in the network can keep the same time. The PTP protocol is a precise time synchronization protocol that can achieve sub-microsecond time synchronization accuracy in the network. The PTP protocol is defined by the IEEE 1588 standard and is designed to achieve precise time synchronization in various complex network environments. The PTP protocol is widely used in distributed systems. It can be used to achieve precise time synchronization, thereby improving the performance and reliability of distributed systems. At the same time, the PTP protocol can also be used to implement the management of distributed systems, such as virtual machine migration in virtualization technology, data synchronization in distributed databases, etc.

[0031] In the PTP protocol, the synchronization process is divided into one-step and two-step methods. In the one-step method, the PTP synchronization client directly sends a synchronization request (i.e., Sync message) to the PTP synchronization server. The synchronization request contains the clock information of the sending clock, and then the PTP synchronization server sends its own clock information to the PTP synchronization client, so that the PTP synchronization client can obtain the timestamp information of the PTP synchronization server, and then the PTP synchronization client calculates the network delay and clock offset based on this information and adjusts its own clock.

[0032] In the two-step synchronization process of the PTP protocol, Figure 1As shown, the PTP server acts as the master clock and the PTP client acts as the slave clock. When the PTP server sends a Sync message to the PTP client, it records the local timestamp t1 when sending. When the PTP client receives the Sync message, it records the local timestamp t2 when receiving. The PTP server then sends a Follow_Up message to the PTP client, which carries the information of the timestamp t1. Then, the PTP client needs to send a Delay_Req (delay request) to the PTP server again, and records the local timestamp t3 when sending. When the PTP server receives the Delay_Req message, it records the local timestamp t4 when receiving. The PTP server then sends a Delay_Resp (delay response) message to the PTP client, which carries the information of the timestamp t4. In this way, the PTP client obtains the four timestamps t1, t2, t3 and t4, and can then perform clock synchronization with the PTP server.

[0033] Specifically, in Figure 1 In the process shown, (t4-t1) includes the transmission delay of Sync, the processing time of the PTP client, and the transmission delay of the Delay_Req message, and (t3-t2) is the processing time of the PTP client, so ((t4-t1)-(t3-t2)) is: the transmission delay of Sync + the transmission delay of the Delay_Req message. At the same time, the PTP protocol assumes that the two-way delay is equal and the delay jitter is very small, that is, the downlink transmission delay Tms = the uplink transmission delay Tsm, then ((t4-t1)-(t3-t2)) / 2 is the one-way transmission delay delay, that is, delay = Tsm = Tms = ((t4-t1)-(t3-t2)) / 2 = ((t2-t1) + (t4-t3)) / 2.

[0034] The time difference between the slave clock of the PTP client and the master clock of the PTP server is the offset, which can be positive or negative. A positive value means that the slave clock time is after the master clock time, and a negative value means that the slave clock time is before the master clock time. The calculation of this offset is also very easy to understand. At the time t2 of the slave clock, the time of the master clock is t1+delay, so offset=t2-(t1+delayt)=t2-t1-delay=((t2-t1)+(t3-t4)) / 2.

[0035] It can be seen that in the two-step method of the PTP protocol, the PTP client and the PTP server need to communicate twice, so the synchronization process is relatively complicated. The two-step method of the PTP protocol can synchronize time more accurately because it can consider the impact of network delay on time synchronization, so the two-step method has higher accuracy.

[0036] The above introduces the NTP protocol and the PTP protocol. Although the NTP protocol has many advantages, it also has some problems in practical applications. For example, the NTP protocol currently uses the NTPv4 version, which relies on the network transmission of the UDP protocol. If the network is congested or interrupted, the synchronization effect of the NTP protocol will be affected; in addition, the time synchronization stability of the NTP protocol is not high, and the synchronization accuracy is often reduced due to the influence of the network; the problem with the PTP protocol is that the current implementation based on the PTP protocol cannot go out of the local area network and has poor scalability. Furthermore, the current implementations based on the NTP protocol and the PTP protocol assume that the uplink and downlink delays of the synchronization client and the synchronization server are the same, but in the 5G network, due to the large difference between the uplink delay and the downlink delay, which is usually about 4 times, it also affects the synchronization accuracy of the NTP protocol and the PTP protocol. Finally, the current NTP protocol and the PTP protocol do not consider the impact of network changes when implementing them, which will affect the accuracy of clock synchronization due to network problems.

[0037] Based on this, the technical solution of the embodiment of the present application proposes a new clock synchronization solution, specifically, Figure 2 As shown, server 201 is a clock synchronization server for providing a reference clock, and other terminal devices perform clock synchronization processing with the clock synchronization server through the network. Server 201 can obtain the network status information of the target device, which is a terminal device that needs to perform clock synchronization with server 201. If it is determined based on the network status information of the target device that the network transmission quality between server 201 and the target device is greater than or equal to the set threshold, the clock adjustment phase is entered, and the clock information of the target device is corrected during the clock adjustment phase; if the clock deviation between the target device and server 201 is adjusted to within the set range, the clock holding phase is entered, and during the clock holding phase, it is determined whether to switch to the clock adjustment phase based on the network status information. It can be seen that the technical solution of the embodiment of the present application can perform clock synchronization processing based on the network status information of the device, which is conducive to improving the accuracy of clock synchronization.

[0038] It should be noted that: the terminal device can be a smart phone, tablet computer, laptop computer, desktop computer, smart TV, smart home, vehicle terminal, aircraft, etc.; the server 201 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal device and the server 201 can be directly or indirectly connected by wired or wireless communication, and this application does not limit this.

[0039] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0040] Figure 3 The flowchart of a clock synchronization method according to an embodiment of the present application is shown. The clock synchronization method can be executed by a terminal device, or by a clock synchronization server, or by both the terminal device and the clock synchronization server. Figure 3 As shown, the clock synchronization method at least includes S310 to S330, which are described in detail as follows:

[0041] In S310, network status information of a target device is obtained, where the target device is a device that needs to perform clock synchronization with a clock synchronization server.

[0042] In some optional embodiments, when acquiring the network status information of the target device, collected data of the target device can be acquired, the collected data including at least one of physical layer data and application layer data of the target device, and then the network status is predicted and processed based on the collected data of the target device to obtain the network status information of the target device.

[0043] Optionally, the physical layer data of the target device includes network status information, etc.; the application layer data of the target device includes video resolution, video segment size, video segment download time, throughput, etc. The network status information includes SINR (Signal to Interference plus Noise Ratio), RSSI (Received Signal Strength Indicator), RSRP (Reference Signal Receiving Quality), RSRQ (Reference Signal Receiving Power), delay information, etc.

[0044] Optionally, when predicting the network status based on the collected data of the target device, the processing can be performed through a machine learning model. Specifically, sample data with label information (the label information is the quality of the network status, such as can be reflected by a specific numerical value) can be used to train the machine learning model. After the training is completed, the collected data of the target device can be input into the trained machine learning model, and then the network status information of the target device can be determined through the output of the trained machine learning model.

[0045] In S320, if it is determined based on the network status information of the target device that the network transmission quality between the clock synchronization server and the target device is greater than or equal to the set threshold, the clock adjustment phase is entered, and the clock information of the target device is corrected in the clock adjustment phase.

[0046] In an embodiment of the present application, when it is determined that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, the clock adjustment phase is entered, so that the clock adjustment can be performed when the network is better, thereby avoiding network problems affecting the clock synchronization effect, which is beneficial to improving the accuracy of clock synchronization.

[0047] In some optional embodiments, the clock information of the target device is corrected during the clock adjustment phase, that is, the clock information of the target device is adjusted according to the reference time provided by the clock synchronization server. For example, the clock offset between the target device and the clock synchronization server can be calculated based on the data transmission process between the target device and the clock synchronization server, and then the clock information of the target device is adjusted according to the clock offset. Specifically, assuming that the clock offset between the target device and the clock synchronization server is offset, and the local clock of the target device is t, then the corrected clock offset of the target device is t-offset.

[0048] In some optional embodiments, the clock offset between the target device and the clock synchronization server can be calculated using a two-step synchronization process similar to the PTP protocol, that is, assuming that the local timestamp of the downlink data packet sent by the clock synchronization server to the target device is t1, and the local timestamp of the target device receiving the downlink data packet is t2; the local timestamp of the uplink data packet sent by the target device to the clock synchronization server is t3, and the local timestamp of the uplink data packet received by the clock synchronization server is t4, then the clock offset between the target device and the clock synchronization server is offset = ((t2-t1)+(t3-t4)) / 2.

[0049] In some optional embodiments, since the uplink and downlink delays between the target device and the clock synchronization server may be different, in order to ensure accurate clock synchronization in this case, the clock offset may be compensated. Specifically, Figure 4 As shown, according to an embodiment of the present application, the process of correcting the clock information of the target device in the clock adjustment phase includes S410 to S440, which are described in detail as follows:

[0050] In S410, the clock synchronization processes between the target device and the clock synchronization server are arranged in chronological order to obtain a plurality of clock synchronization processes arranged in sequence.

[0051] In some optional embodiments, the target device and the clock synchronization server may perform multiple clock synchronization processes to achieve clock synchronization, so these clock synchronization processes may be arranged in chronological order, such as from the 1st clock synchronization process to the 100th clock synchronization process, and one clock synchronization process may include one downlink transmission process and one uplink transmission process between the target device and the clock synchronization server.

[0052] In S420, a sliding window of a set size slides over multiple clock synchronization processes according to a set step size. One sliding window includes N clock synchronization processes, where N is equal to the size of the sliding window.

[0053] Optionally, assuming that the size of the sliding window is 50 and the step size is 20, one sliding window includes 50 clock synchronization processes, and a new sliding window is updated after every 20 clock synchronization processes.

[0054] In S430, according to the clock synchronization process in the sliding window, the uplink and downlink asymmetry difference between the target device and the clock synchronization server is calculated.

[0055] In some optional embodiments, if a clock synchronization process includes an uplink transmission process and a downlink transmission process between a target device and a clock synchronization server, then the average uplink transmission delay and the average downlink transmission delay corresponding to the clock synchronization process in the sliding window can be calculated based on the uplink transmission process and the downlink transmission process included in each clock synchronization process, and then the difference between the average uplink transmission delay and the average downlink transmission delay is calculated and used as the uplink and downlink asymmetry difference. Optionally, in other embodiments of the present application, the difference between the average downlink transmission delay and the average uplink transmission delay can also be used as the uplink and downlink asymmetry difference.

[0056] Optionally, for a clock synchronization process, assuming that the local timestamp of the downlink data packet sent by the clock synchronization server to the target device is t1, and the local timestamp of the downlink data packet received by the target device is t2; the local timestamp of the uplink data packet sent by the target device to the clock synchronization server is t3, and the local timestamp of the uplink data packet received by the clock synchronization server is t4, then the downlink transmission delay of this clock synchronization process can be t2-t1, and the uplink transmission delay can be t4-t3. After calculating the uplink transmission delay and downlink transmission delay of each clock synchronization process, the average uplink transmission delay and average downlink transmission delay corresponding to the clock process in the sliding window can be calculated accordingly.

[0057] In some optional embodiments, when calculating the average uplink transmission delay and the average downlink transmission delay corresponding to the clock synchronization processes in the sliding window, the clock synchronization processes in which the uplink transmission processes or downlink transmission processes contained in each clock synchronization process have abnormal delay values ​​can be eliminated from the sliding window, such as clock synchronization processes with excessively large delay values, and then the average uplink transmission delay and the average downlink transmission delay corresponding to the remaining clock synchronization processes in the sliding window are calculated.

[0058] In S440, offset compensation is performed on the clock synchronization process for a set number of times after the sliding window according to the uplink and downlink asymmetry difference, and the clock information of the target device is corrected according to the compensated clock offset; wherein the set number of times is equal to the set step size.

[0059] In some optional embodiments, assuming that the size of the sliding window is 50 and the step size is 20, the uplink and downlink asymmetry difference can be calculated based on the first 50 clock synchronization processes, and then the uplink and downlink asymmetry difference is applied to the offset compensation processing of the 51st to 70th clock synchronization processes; and since the step size of the sliding window is 20, for the 71st to 90th clock synchronization processes, the 21st to 70th clock synchronization processes are used to calculate the uplink and downlink asymmetry difference, and then the uplink and downlink asymmetry difference is applied to the offset compensation processing of the 71st to 90th clock synchronization processes, and so on.

[0060] In some optional embodiments, when performing offset compensation processing on the i-th clock synchronization process after the sliding window, the clock offset between the target device and the clock synchronization server is calculated based on the sending timestamps and receiving timestamps corresponding to the uplink data packet and the downlink data packet contained in the i-th clock synchronization process, respectively; wherein 1≤i≤a set number of times; and then a polynomial sum is performed on the clock offset and the uplink and downlink asymmetry difference to obtain the compensated clock offset corresponding to the i-th clock synchronization process.

[0061] Optionally, assuming that the local timestamp of the downlink data packet sent by the clock synchronization server to the target device is t1, and the local timestamp of the target device receiving the downlink data packet is t2; the local timestamp of the uplink data packet sent by the target device to the clock synchronization server is t3, and the local timestamp of the uplink data packet received by the clock synchronization server is t4, then the clock offset between the target device and the clock synchronization server is offset = ((t2-t1)+(t3-t4)) / 2.

[0062] Optionally, performing a polynomial summation on the clock offset and the uplink and downlink asymmetry difference may be to superimpose half of the uplink and downlink asymmetry difference on the clock offset to obtain the compensated clock offset.

[0063] Continue to refer to Figure 3 As shown, in S330, if the clock deviation between the target device and the clock synchronization server is adjusted to within the set range, the clock holding phase is entered, and in the clock holding phase, it is determined whether to switch to the clock adjustment phase according to the network status information.

[0064] In some optional embodiments, the clock deviation between the target device and the clock synchronization server (for example, the clock offset in the above embodiment) can be calculated based on the sending timestamp and receiving timestamp of the uplink data packet between the target device and the clock synchronization server, and the sending timestamp and receiving timestamp of the downlink data packet between the clock synchronization server and the target device, so as to determine whether the clock deviation between the target device and the clock synchronization server is adjusted to a set range. Optionally, the set range can be set according to actual needs, for example, it can be set to 4ms.

[0065] In some optional embodiments, the process of determining whether to switch to the clock adjustment phase based on network status information during the clock holding phase may be that during the clock holding phase, if it is determined based on network status information that the network status between the clock synchronization server and the target device is in a continuously fluctuating state, then switching to the clock adjustment phase.

[0066] Among them, the continuous fluctuation state refers to the continuous jitter of the network between the target device and the clock synchronization server, which may cause a large difference in the clock between the target device and the clock synchronization server. Optionally, when detecting whether the network state between the target device and the clock synchronization server is in a continuous jitter state, the clock deviation of the clock synchronization data packet sent by the target device can be detected during the clock holding phase; if it is detected that the clock deviation of the clock synchronization data packet sent by the target device for M consecutive times is greater than the set threshold, it is determined that the network state between the clock synchronization server and the target device is in a continuous fluctuation state; wherein M is an integer greater than or equal to 1.

[0067] On the contrary, if it is detected that the clock deviation of the clock synchronization data packet sent by the target device is greater than the set threshold for a continuous number of times but does not reach M times, it means that the network state between the clock synchronization server and the target device is a short-term fluctuation (i.e., a non-continuous fluctuation state), which means that the network state has little effect on the clock between the target device and the clock synchronization server, and the clock can continue to be in the clock holding stage. It should be noted that the size of M can be set according to the actual situation, such as 10 times, 20 times or 50 times.

[0068] exist Figure 3 In the illustrated embodiment, when the network transmission quality between the target device and the clock synchronization server is greater than or equal to a set threshold, the clock adjustment phase is entered to correct the clock information of the target device. In an optional embodiment of the present application, if it is determined based on the network status information of the target device that the network transmission quality between the clock synchronization server and the target device is less than the set threshold, the target device can be controlled to reduce the sending frequency of the clock synchronization data packets. This can prevent the target device from continuing to send synchronization data packets at a higher sending frequency and causing further impact on the network.

[0069] In some optional embodiments, if it is determined that the clock holding phase needs to be exited, the collected data of the target device can be re-acquired, and the network status information of the target device can be determined based on the re-acquired collected data to determine whether to enter the clock adjustment phase. Optionally, if it is determined that the network status between the clock synchronization server and the target device is in a continuously fluctuating state based on the network status information during the clock holding phase, it is determined that the clock holding phase needs to be exited.

[0070] In the above embodiments of the present application, clock synchronization processing can be performed based on the network status information of the device, which can improve the accuracy of clock synchronization. This clock synchronization solution can be applied to the improvement of the NTP protocol to achieve a high-precision clock synchronization process. The following is an example of a specific application scenario:

[0071] In an application scenario of the present application, if the clock synchronization solution in the embodiment of the present application can be applied to the improvement of the NTP protocol, then Figure 5 As shown, the entire system architecture may include an NTP synchronization server, a client (running on a terminal device that requires clock synchronization), a network status, and an attack detection server.

[0072] Among them, the NTP synchronization server is a server used to achieve network time synchronization. Specifically, the NTP synchronization server can receive NTP synchronization requests from other devices (i.e., clients), and then adjust the clock information of the device according to the time information in the NTP synchronization request, thereby achieving network time synchronization. The main functions of the NTP synchronization server include: providing a unified time standard for devices in the network, thereby ensuring that the devices in the network can maintain the same time; improving the efficiency of network management, for example, in terms of fault location, log analysis, etc., a unified time standard can help administrators analyze and solve problems more easily; improving network security, for example, it can prevent attacks and access control problems caused by time inconsistencies.

[0073] NTP synchronization server can synchronize time between multiple devices, thereby improving the time synchronization accuracy and reliability of the entire network. NTP synchronization server is usually provided by the operating system or hardware device. For example, in the Linux system, NTP service can be used to provide NTP synchronization service. NTP synchronization server needs to regularly receive NTP requests from other devices and adjust the clock information of the device according to the time information in the request. In order to ensure the reliability and stability of NTP synchronization server, NTP synchronization server usually needs to have the following characteristics: High reliability: NTP synchronization server needs to be able to run stably and be able to resist various network failures and attacks; High precision: NTP synchronization server needs to be able to provide high-precision time synchronization service, so as to ensure that the devices in the network can maintain high-precision time synchronization; Multi-node synchronization: NTP synchronization server needs to be able to support multi-node synchronization, so as to improve the time synchronization accuracy and reliability of the entire network.

[0074] The network status and attack detection server is used to perform network status and attack detection. The implementation method of the network status and attack detection server is not limited. It only needs to have a computing processing unit, which can be a cloud server or a physical machine. In addition, the network status and attack detection server can be established independently or integrated with the NTP synchronization server.

[0075] based on Figure 5 The system architecture shown, in one embodiment of the present application, the overall clock synchronization process is as follows:

[0076] 1. Configure the NTP synchronization server, specify the address of the NTP synchronization server, and perform fast synchronization at startup. Specifically, you can configure the address of the NTP synchronization server for the devices that need clock synchronization, so that these devices can synchronize their clocks with the NTP synchronization server according to the address of the NTP synchronization server at startup.

[0077] 2. Clients that need to synchronize their clocks can create a local resource pool to store the difference between the local computer time and the reference time (i.e., the time of the NTP synchronization server). Optionally, if the client's local clock deviates greatly from the NTP synchronization server time during synchronization (possibly due to a poor network status), you can try to adjust the clock or not and wait for the next synchronization cycle.

[0078] 3. The client collects cross-layer information and transmits it to the network status and attack detection server in real time. Cross-layer involves data interaction between the physical layer and the application layer; the terminal has an interface for data collection, and the collected cross-layer historical data includes physical layer data and application layer data, such as network status information, throughput, video resolution, video segment size, and video segment download time. The network status information includes SINR, RSSI, RSRP, RSRQ, latency, etc. Then the network status and attack detection server detects the current network status through certain calculations, predictions, and analysis, and notifies the NTP synchronization server.

[0079] 4. The client starts the clock synchronization process and synchronizes with the NTP synchronization server. The specific synchronization process can be as follows: Figure 6 As shown, the synchronization process is divided into an adjustment phase (ie, the clock adjustment phase in the aforementioned embodiment) and a timekeeping phase (ie, the clock keeping phase in the aforementioned embodiment).

[0080] The adjustment phase involves large-scale clock correction based on the predicted network status, striving to quickly achieve optimal synchronization accuracy; the timekeeping phase involves small clock adjustments or no adjustments, minimizing interference caused by fluctuations.

[0081] In the initial stage of the clock synchronization process, if the predicted network status is good (such as low network delay, low jitter, large available bandwidth, etc.), then the adjustment stage can be entered to correct the client's clock information. When it is detected that the synchronization accuracy between the client and the NTP synchronization server reaches the ideal range, the punctual stage can be entered. Optionally, if the predicted network status is poor (such as high network delay, high jitter, small available bandwidth, etc.), the frequency of sending the client's clock synchronization data packet can be reduced.

[0082] Optionally, during the clock synchronization process, whether to continue in the adjustment phase or switch to the punctual phase is mainly determined based on the transmission of uplink and downlink data packets. For example, in a wide area network environment, if the following inequality holds, it is determined to switch to the punctual phase, otherwise, it continues to be in the adjustment phase: t2-t1-t4+t3≤8ms. Among them, t1 is the local timestamp of the NTP synchronization server sending the downlink data packet to the client, and t2 is the local timestamp of the client receiving the downlink data packet; t3 is the local timestamp of the client sending the uplink data packet to the NTP synchronization server, and t4 is the local timestamp of the NTP synchronization server receiving the uplink data packet.

[0083] Since the network is unstable in a wireless environment, it is easy to cause the loss or abnormality of synchronization messages (i.e., the synchronization data packets sent during the synchronization process), so it is necessary to handle the abnormal situation. Specifically, when it is predicted that the network will have obvious fluctuations, the network status is continuously detected to determine whether the network is a short-term fluctuation or a continuous fluctuation. If it is a short-term fluctuation, the punctual stage can be maintained, because the short-term fluctuation has little effect on the synchronization accuracy; if it is a continuous fluctuation, it is possible to switch from the punctual stage to the adjustment stage and restart the synchronization. When exiting the punctual stage, the parameters of the current network can be re-reported and updated based on the current clock adjustment results.

[0084] Optionally, the following method can be used to determine whether the network fluctuation is short-term or continuous: during the clock synchronization process between the client and the NTP synchronization server (for example, during a clock synchronization process), if the data packets sent between the client and the NTP synchronization server are in a network fluctuation state for 50 consecutive times (i.e., t2-t1-t4+t3>8ms), then the current mode is considered to be continuous fluctuation; otherwise, it is considered to be a short-term fluctuation.

[0085] It should be noted that, during the processing of step 4 above, the NTP synchronization server needs to obtain the messages sent by the network status and attack detection server in real time, and determine whether the next stage is the adjustment stage or the timekeeping stage.

[0086] In some optional embodiments, when predicting the network status, the network status and attack detection server may pre-process the data reported by the client and filter out the data used for network status detection, including data format, data size, data features, etc. After pre-processing, the data is converted into a time series form, specifically, Figure 7 As shown. Figure 7In the data format shown, number represents a sequence number; timestamp represents a timestamp; latitude represents latitude; longitude represents longitude; elevation represents altitude; pci represents a physical cell identifier, which is the abbreviation of Physical Cell Identifier; nci represents a network communication interface, which is the abbreviation of Network Communication Interface; tac represents the abbreviation of Tracking Area Code; ueID represents a user equipment identifier, which is the abbreviation of User Equipment Identity; RollingCounter represents a loop counter, which is used to indicate the number of data packets.

[0087] After converting the data into a time series format, the network status and attack detection server can start the algorithm module, configure the relevant parameters of the algorithm, set the algorithm's input features, output features, prediction features, model parameters, algorithm average times, prediction time, model training and testing ratio, number of iterations, model loss function, model optimization function, number of machine learning neurons, etc.; then the network status and attack detection server will perform a preliminary analysis of its own calculation results and notify the NTP synchronization server of the analysis results.

[0088] Since the upload and download speeds on the Internet are not equal, this is usually due to the asymmetry of the uplink and downlink delays of data packets caused by poor network conditions or attacks on the network. In order to eliminate the error caused by asymmetric links to clock synchronization, the NTP synchronization server can use a sliding window algorithm to compensate for the synchronization error.

[0089] Specifically, in an embodiment of the present application, the sliding window algorithm uses a fixed-size window to slide on the historical synchronization data, and calculates the average delay value in the sliding window as the error compensation value. The key to the sliding window algorithm is to determine the appropriate sliding window size and how to calculate it. Since a smaller sliding window can capture network fluctuations faster, but may be affected by noise, a larger sliding window can reduce the impact of noise, but the response speed to network fluctuations is slower. Therefore, the appropriate window size can be determined by experiment or according to the actual application scenario. In an embodiment of the present application, by considering the frequency characteristics of the synchronization message (i.e., the data packet sent between the client and the NTP server for clock synchronization) and the response time of the algorithm, after multiple experiments, the size of the sliding window can be set to 50 and the step size of the sliding window can be set to 20.

[0090] If the error compensation calculation is performed immediately when calculating the path delay according to the two-step process of the PTP protocol, the error compensation curve will have a large jitter amplitude. Therefore, a corresponding improvement scheme is proposed in the embodiment of the present application: that is, before performing dynamic time synchronization, the uplink and downlink asymmetric differences of the path are first measured, and sliding window compensation is performed, and then the dynamic time synchronization algorithm is started to perform time synchronization and correction. At the same time, considering the randomness of the path delay of the synchronization message, the arithmetic mean can be used as the average value of the delay within the sliding window. Optionally, when performing statistical analysis of the path delay within the sliding window, the maximum and minimum values ​​can be removed before calculating the arithmetic mean; or multiple iterations can be performed to filter out unreasonable path delay values, and finally obtain the optimal average value of the round-trip path.

[0091] The following uses 100 clock synchronization processes as an example to explain how the NTP synchronization server uses a sliding window algorithm to compensate for synchronization errors:

[0092] For the 1st to 50th clock synchronization process:

[0093] Since sliding window 1 is initialized during the first 50 clock synchronizations, the average downlink delay T in window 1 can be calculated according to the following formula: ms and the average upstream delay T sm .

[0094]

[0095]

[0096] Among them, t 1i Indicates the local timestamp of the downlink data packet sent by the NTP synchronization server to the client during the i-th clock synchronization process, t 2i Indicates the local timestamp of the downlink data packet sent by the NTP synchronization server when the client receives it during the i-th clock synchronization process; t 3i Indicates the local timestamp of the uplink data packet sent by the client to the NTP synchronization server during the i-th clock synchronization process, t 4i Indicates the local timestamp of the uplink data packet sent by the client when the NTP synchronization server receives it during the i-th clock synchronization process.

[0097] After calculating the average value of the path delay of sliding window 1, the following formula is used to calculate diff (i.e., the difference in uplink and downlink asymmetry of 50 synchronization processes in sliding window 1), that is, the difference between the average uplink transmission delay and the average downlink transmission delay is used as diff. Of course, in other embodiments of the present application, the difference between the average downlink transmission delay and the average uplink transmission delay can also be used as diff.

[0098] diff = T sm -T ms

[0099] For the 51st to 70th clock synchronization process:

[0100] Since the uplink and downlink asymmetric difference is calculated according to the clock synchronization process in sliding window 1, diff is used to compensate the clock offset in the next 20 clock synchronization processes (i.e., the 51st to 70th clock synchronization processes). The compensated clock offset is calculated by the following formula:

[0101]

[0102] Among them, t 1j Indicates the local timestamp of the downlink data packet sent by the NTP synchronization server to the client during the jth clock synchronization process, t 2j Indicates the local timestamp of the downlink data packet sent by the NTP synchronization server when the client receives it during the jth clock synchronization process; t 3j Indicates the local timestamp of the uplink data packet sent by the client to the NTP synchronization server during the jth clock synchronization process, t 4j Indicates the local timestamp of the uplink data packet sent by the client when the NTP synchronization server receives it during the jth clock synchronization process. Here, j satisfies: 51≤j≤70.

[0103] For the 71st to 90th clock synchronization process:

[0104] When the 70th clock synchronization is completed, the sliding step of sliding window 1 reaches 20, so sliding window 1 is updated to obtain sliding window 2, which contains the historical data of the 21st to 70th clock synchronization. Therefore, similar to the above, the diff corresponding to sliding window 2 is calculated first. Then the diff corresponding to sliding window 2 is used to compensate the clock offset of the 71st to 90th clock synchronization process.

[0105] For the 91st to 100th clock synchronization process:

[0106] When the 91st synchronization starts, sliding window 2 is updated to sliding window 3, which contains the historical data of the 41st to 90th clock synchronization. Therefore, the diff corresponding to sliding window 3 is calculated using the same method, and then the diff corresponding to sliding window 3 is used to compensate the clock offset of the 91st to 100th clock synchronization process. Repeating this process can always compensate for the clock offset.

[0107] The above is an explanation based on 100 clock synchronization processes as an example. The clock synchronization processes of other times are similar to the above process. The diff corresponding to the sliding window is calculated by the size and step size of the sliding window, and the clock offset of the clock synchronization processes after the sliding window (equal to the step size of the sliding window) is compensated accordingly.

[0108] The technical solutions of the above-mentioned embodiments of the present application can improve the synchronization accuracy of NTP by improving the protocol implementation method of NTP. On the other hand, in the implementation of the entire end-to-end synchronization architecture, modules for network status detection and attack detection are added to improve the stability of the synchronization process. After evaluation, the technical solutions of the embodiments of the present application are used to improve the NTP protocol, which can be comparable to the synchronization accuracy of the PTP time synchronization protocol, and is adaptable to various network states and the asymmetric uplink and downlink delays of 5G networks, thereby improving the scalability of the NTP protocol.

[0109] The following describes an apparatus embodiment of the present application, which can be used to execute the clock synchronization method in the above-mentioned embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the above-mentioned embodiment of the clock synchronization method of the present application.

[0110] Figure 8 A block diagram of a clock synchronization device according to an embodiment of the present application is shown. The clock synchronization device can be applied to a clock synchronization server or a terminal device.

[0111] Reference Figure 8 As shown, a clock synchronization device 800 according to an embodiment of the present application includes: an acquisition unit 802 , a processing unit 804 and a control unit 806 .

[0112] Among them, the acquisition unit 802 is configured to acquire the network status information of the target device, and the target device is a device that needs to perform clock synchronization with the clock synchronization server; the processing unit 804 is configured to enter the clock adjustment phase if it is determined according to the network status information that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, and to correct the clock information of the target device in the clock adjustment phase; the control unit 806 is configured to enter the clock holding phase if the clock deviation between the target device and the clock synchronization server is adjusted to within a set range, and to determine whether to switch to the clock adjustment phase according to the network status information in the clock holding phase.

[0113] In some embodiments of the present application, based on the aforementioned scheme, the control unit 806 is also configured to: if it is determined according to the network status information that the network transmission quality between the clock synchronization server and the target device is less than the set threshold, then control the target device to reduce the sending frequency of the clock synchronization data packet.

[0114] In some embodiments of the present application, based on the aforementioned scheme, the control unit 806 is configured as: during the clock holding phase, if it is determined according to the network status information that the network status between the clock synchronization server and the target device is in a continuously fluctuating state, then switch to the clock adjustment phase.

[0115] In some embodiments of the present application, based on the aforementioned scheme, the control unit 806 is also configured to: during the clock holding phase, detect the clock deviation of the clock synchronization data packet sent by the target device; if it is detected that the clock deviation of the clock synchronization data packet sent by the target device for M consecutive times is greater than a set threshold, it is determined that the network status between the clock synchronization server and the target device is in a continuously fluctuating state; wherein M is an integer greater than or equal to 1.

[0116] In some embodiments of the present application, based on the aforementioned scheme, the control unit 806 is also configured as: during the clock holding phase, if it is determined according to the network status information that the network status between the clock synchronization server and the target device is in a non-continuous fluctuation state, then continue to be in the clock holding phase.

[0117] In some embodiments of the present application, based on the aforementioned scheme, the processing unit 804 includes: an arrangement unit, configured to arrange the clock synchronization process between the target device and the clock synchronization server in chronological order to obtain multiple clock synchronization processes arranged in sequence; a sliding unit, configured to slide on the multiple clock synchronization processes according to a set step size based on a sliding window of a set size, and one sliding window contains N clock synchronization processes, and N is equal to the size of the sliding window; a calculation unit, configured to calculate the uplink and downlink asymmetry difference between the target device and the clock synchronization server according to the clock synchronization process in the sliding window; a compensation unit, configured to perform offset compensation processing on the clock synchronization process of a set number of times after the sliding window according to the uplink and downlink asymmetry difference, and correct the clock information of the target device according to the compensated clock offset; wherein the set number of times is equal to the set step size.

[0118] In some embodiments of the present application, based on the aforementioned solution, the clock synchronization process includes an uplink transmission process and a downlink transmission process between the target device and the clock synchronization server;

[0119] The calculation unit is configured to: calculate the average uplink transmission delay and the average downlink transmission delay corresponding to the clock synchronization process in the sliding window according to the uplink transmission process and the downlink transmission process included in each clock synchronization process; calculate the difference between the average uplink transmission delay and the average downlink transmission delay, and use it as the uplink and downlink asymmetry difference.

[0120] In some embodiments of the present application, based on the aforementioned scheme, the calculation unit is configured to: according to the uplink transmission process and the downlink transmission process included in each clock synchronization process, eliminate the clock synchronization process in which the uplink transmission process or the downlink transmission process contains abnormal delay values ​​from the sliding window; and calculate the average uplink transmission delay and the average downlink transmission delay corresponding to the remaining clock synchronization processes in the sliding window.

[0121] In some embodiments of the present application, based on the aforementioned scheme, the compensation unit is configured as follows: when performing offset compensation processing on the i-th clock synchronization process after the sliding window, the clock offset between the target device and the clock synchronization server is calculated according to the sending timestamps and receiving timestamps corresponding to the uplink data packet and the downlink data packet contained in the i-th clock synchronization process; wherein 1≤i≤the set number of times; a polynomial sum is performed on the clock offset and the uplink and downlink asymmetry difference to obtain the compensated clock offset corresponding to the i-th clock synchronization process.

[0122] In some embodiments of the present application, based on the aforementioned scheme, the control unit 806 is also configured to: calculate the clock deviation between the target device and the clock synchronization server according to the sending timestamp and receiving timestamp of the uplink data packet between the target device and the clock synchronization server, and the sending timestamp and receiving timestamp of the downlink data packet between the clock synchronization server and the target device, so as to determine whether the clock deviation is within the set range.

[0123] In some embodiments of the present application, based on the aforementioned scheme, the acquisition unit 802 is configured to: acquire collected data of the target device, wherein the collected data includes at least one of physical layer data and application layer data of the target device; perform predictive processing on the network status according to the collected data to obtain the network status information of the target device.

[0124] In some embodiments of the present application, based on the aforementioned scheme, the acquisition unit 802 is further configured to: if it is determined that the clock holding phase needs to be exited, re-acquire the acquisition data of the target device to determine the network status information of the target device based on the re-acquired acquisition data.

[0125] Fig. 9 A schematic diagram of the structure of a computer system of an electronic device suitable for implementing an embodiment of the present application is shown, and the electronic device may be the clock synchronization server in the aforementioned embodiment.

[0126] It should be noted that Fig. 9 The computer system 900 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0127] like Fig. 9 As shown, the computer system 900 may include a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 902 or the program loaded from the storage part 908 to the random access memory (RAM) 903, such as executing the method described in the above embodiment. In the RAM 903, various programs and data required for system operation are also stored. The CPU 901, ROM 902 and RAM 903 are connected to each other through a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0128] The following components can be connected to the I / O interface 905: an input section 906 including a keyboard, a mouse, etc.; an output section 907 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. A removable medium 911, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 910 as needed so that a computer program read therefrom is installed into the storage section 908 as needed.

[0129] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program is used to perform the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 909, and / or installed from a removable medium 911. When the computer program is executed by a central processing unit (CPU) 901, various functions defined in the system of the present application are executed.

[0130] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a computer program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0131] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and a computer program.

[0132] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0133] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more computer programs, and when the above one or more computer programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

[0134] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0135] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable an electronic device to execute the method according to the implementation methods of the present application.

[0136] For example, the electronic device may be a clock synchronization server, and the clock synchronization server may execute Figure 3 or Figure 4 The clock synchronization method shown.

[0137] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0138] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A clock synchronization method, characterized in that: include: Acquire network status information of a target device, where the target device is a device that needs to perform clock synchronization with the clock synchronization server; If it is determined according to the network status information that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, then entering a clock adjustment phase, and performing correction processing on the clock information of the target device in the clock adjustment phase; If the clock deviation between the target device and the clock synchronization server is adjusted to within a set range, the clock holding phase is entered, and during the clock holding phase, it is determined whether to switch to the clock adjustment phase according to the network status information.

2. The clock synchronization method according to claim 1, characterized in that: The clock synchronization method further comprises: If it is determined according to the network status information that the network transmission quality between the clock synchronization server and the target device is less than the set threshold, the target device is controlled to reduce the sending frequency of the clock synchronization data packet.

3. The clock synchronization method according to claim 1, characterized in that: Determining whether to switch to the clock adjustment phase according to the network status information in the clock holding phase includes: In the clock maintaining phase, if it is determined according to the network status information that the network status between the clock synchronization server and the target device is in a continuously fluctuating state, the clock adjusting phase is switched to.

4. The clock synchronization method according to claim 3, characterized in that: The clock synchronization method further comprises: In the clock holding phase, detecting the clock deviation of the clock synchronization data packet sent by the target device; If it is detected that the clock deviation of the clock synchronization data packets sent by the target device for M consecutive times is greater than the set threshold, it is determined that the network status between the clock synchronization server and the target device is in a continuously fluctuating state; wherein M is an integer greater than or equal to 1.

5. The clock synchronization method according to claim 3, characterized in that: The clock synchronization method further comprises: In the clock holding phase, if it is determined according to the network status information that the network status between the clock synchronization server and the target device is in a non-continuous fluctuation state, the clock holding phase continues.

6. The clock synchronization method according to claim 1, characterized in that: Correcting the clock information of the target device in the clock adjustment phase includes: Arranging the clock synchronization processes between the target device and the clock synchronization server in chronological order to obtain a plurality of clock synchronization processes arranged in sequence; Sliding a sliding window of a set size on the multiple clock synchronization processes according to a set step length, wherein one sliding window includes N clock synchronization processes, and N is equal to the size of the sliding window; Calculating the uplink and downlink asymmetry difference between the target device and the clock synchronization server according to the clock synchronization process within the sliding window; The clock synchronization process is offset compensated for a set number of times after the sliding window according to the uplink and downlink asymmetry difference, and the clock information of the target device is corrected according to the compensated clock offset; wherein the set number of times is equal to the set step size.

7. The clock synchronization method according to claim 6, characterized in that: The clock synchronization process includes an uplink transmission process and a downlink transmission process between the target device and the clock synchronization server; Calculating the uplink and downlink asymmetry difference between the target device and the clock synchronization server according to the clock synchronization process in the sliding window includes: According to the uplink transmission process and the downlink transmission process included in each clock synchronization process, calculating the average uplink transmission delay and the average downlink transmission delay corresponding to the clock synchronization process in the sliding window; A difference between the average uplink transmission delay and the average downlink transmission delay is calculated and used as the uplink and downlink asymmetry difference.

8. The clock synchronization method according to claim 7, characterized in that: According to the uplink transmission process and the downlink transmission process included in each clock synchronization process, calculating the average uplink transmission delay and the average downlink transmission delay corresponding to the clock synchronization process in the sliding window, including: According to the uplink transmission process and the downlink transmission process included in each clock synchronization process, the clock synchronization process in which the uplink transmission process or the downlink transmission process included in the sliding window has an abnormal delay value is removed; The average uplink transmission delay and the average downlink transmission delay corresponding to the remaining clock synchronization processes in the sliding window are calculated.

9. The clock synchronization method according to claim 6, characterized in that: Performing offset compensation processing on the clock synchronization process of a set number of times after the sliding window according to the uplink and downlink asymmetry difference, including: When performing offset compensation processing on the i-th clock synchronization process after the sliding window, the clock offset between the target device and the clock synchronization server is calculated according to the sending timestamps and receiving timestamps corresponding to the uplink data packet and the downlink data packet respectively included in the i-th clock synchronization process; wherein 1≤i≤the set number of times; The clock offset and the uplink and downlink asymmetry difference are summed polynomially to obtain the compensated clock offset corresponding to the i-th clock synchronization process.

10. The clock synchronization method according to claim 1, characterized in that: The clock synchronization method further comprises: Based on the sending timestamp and receiving timestamp of the uplink data packet between the target device and the clock synchronization server, as well as the sending timestamp and receiving timestamp of the downlink data packet between the clock synchronization server and the target device, the clock deviation between the target device and the clock synchronization server is calculated to determine whether the clock deviation is within the set range.

11. The clock synchronization method according to any one of claims 1 to 10, characterized in that: Get the target device's network status information, including: Acquire collected data of the target device, wherein the collected data includes at least one of physical layer data and application layer data of the target device; The network status is predicted and processed according to the collected data to obtain the network status information of the target device.

12. The clock synchronization method according to claim 11, characterized in that: The clock synchronization method further comprises: If it is determined that the clock holding phase needs to be exited, the collected data of the target device is re-acquired to determine the network status information of the target device according to the re-acquired collected data.

13. A clock synchronization device, characterized in that: include: an acquisition unit, configured to acquire network status information of a target device, wherein the target device is a device that needs to perform clock synchronization with the clock synchronization server; a processing unit configured to enter a clock adjustment phase if it is determined according to the network status information that the network transmission quality between the clock synchronization server and the target device is greater than or equal to a set threshold, and perform correction processing on the clock information of the target device in the clock adjustment phase; The control unit is configured to enter a clock holding phase if the clock deviation between the target device and the clock synchronization server is adjusted to within a set range, and determine whether to switch to the clock adjustment phase according to the network status information during the clock holding phase.

14. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the clock synchronization method according to any one of claims 1 to 12 is implemented.

15. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more computer programs, which, when executed by the one or more processors, enables the electronic device to implement the clock synchronization method as described in any one of claims 1 to 12.

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