Substrate layout structure for optimizing switch waveform of intelligent power module

Abstract

The invention discloses a substrate layout structure for optimizing the switching waveform of an intelligent power module, which belongs to the technical field of IGBT intelligent power module optimization and comprises a power bus DC +, a power bus DC-, IGBT chips M1-M6, an IGBT chip Mb, diode chips D1-D6 and a diode chip Db. By analyzing IGBT port voltage composition, combining a conductor inductance generation mechanism, accurately optimizing DBC substrate layout, reducing parasitic inductance and considering the actual operation effect of the IGBT module, the module operation is more stable, the voltage peak is reduced, the switching efficiency is improved, and the energy loss is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of IGBT intelligent power module optimization, and in particular relates to a substrate layout structure for optimizing a switch waveform of an intelligent power module. Background Art

[0002] The intelligent power module (IPM) is mainly composed of two parts: the power circuit and the drive protection circuit. It integrates logic, control, detection and protection circuit functions. Compared with traditional power modules, it has a significantly smaller size and longer power cycle life. It has a series of advantages such as high reliability, high integration and ease of use. It plays an indispensable role in many fields such as industrial automation, home appliances, new energy vehicles, renewable energy, energy storage systems and automotive electronics.

[0003] The basic structure of the intelligent power module includes: power circuit, drive protection circuit and lead terminal. Among them, the power circuit is responsible for energy conversion, the drive protection circuit ensures safe operation, and the lead terminal connects to external devices. The copper layer on the internal DBC substrate, the bonding wire and the connection terminal constitute the current flow path when the module is running. These components work together to ensure that the current can be transmitted stably and efficiently.

[0004] The power devices inside the IPM are power electronic devices. They are in a high-frequency switching state during operation and are easily affected by various factors, which can cause large voltage overshoots, leading to switching waveform distortion, additional energy loss, and easily causing device damage. Factors that cause voltage overshoots include parasitic inductance, switching speed and driving conditions, internal structure and materials of the module, and external circuit and load characteristics. Among them, parasitic electrical parameters are the key factors affecting the switching waveform. The commonly used parasitic inductance optimization solutions are to adjust the PCB layout and routing and use shielding or filtering technology, but inevitably ignore the parasitic inductance influence from the lower power circuit.

[0005] The parasitic inductance of the power circuit mainly exists in the copper layer and bonding wire links on the DBC substrate. The DBC substrate, bonding wires and connecting terminals inevitably introduce parasitic inductance when forming the current flow path, resulting in an increase in the current change rate and voltage spikes. Therefore, based on this problem, the parasitic inductance is optimized. By adjusting the DBC substrate layout, changing the narrow and special-shaped structure of the substrate, and optimizing the length of the current flow path, the parasitic inductance is reduced, reducing the impact on the switching waveform of the IGBT module. This effectively improves the operating efficiency and stability of the module, extends its service life, and reduces maintenance costs. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a substrate layout structure for optimizing the switching waveform of an intelligent power module.

[0007] The technical solution of the present invention is: a substrate layout structure for optimizing the switch waveform of an intelligent power module includes a power bus DC+, a power bus DC-, an IGBT chip M 1 -M 6 、IGBT chip M b , diode chip D 1 -D 6 and diode chip D b ;

[0008] IGBT chip M 1 One end of the IGBT chip M 3 One end and IGBT chip M 5 One end of the IGBT chip M is connected to the power bus DC- through a bonding wire; 1 The other end and diode chip D 1 One end of the IGBT chip M 3 The other end and diode chip D 3 One end of the IGBT chip M 5 The other end and diode chip D 5 One end of the diode chip D 1 The other end of the diode chip D 3 The other end and diode chip D 5 The other end is connected to the power bus DC+ through bonding wires;

[0009] IGBT chip M 4 One end of the IGBT chip M 6 One end and IGBT chip M 2 One end of the IGBT chip M is connected to the power bus DC+ through a bonding wire; 4 The other end and diode chip D 4 One end of the IGBT chip M 6 The other end and diode chip D 6 One end of the IGBT chip M 2 The other end and diode chip D 2 One end of the diode chip D 4 The other end of the diode chip D 6 The other end and diode chip D 2 The other end is connected to the power bus DC-+ through bonding wires;

[0010] IGBT chip M b One end of the IGBT chip M is connected to the power bus DC- through a bonding wire; b The other end and diode chip D b One end of the diode chip D bThe other end is connected to the power bus DC+ through a bonding wire.

[0011] Furthermore, the IGBT chip M 4 Self-perception The calculation formula is: ; In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit.

[0012] Furthermore, the IGBT chip M 4 Mutual inductance The calculation formula is:

[0013] ;

[0014] In the formula, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

[0015] Furthermore, the IGBT chip M 4 The port voltage The calculation formula is:

[0016] ;

[0017] In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit, and the current flowing through the chip M4, Indicates the current flowing in the gate control circuit. Indicates the current flowing through the diode chip. Indicates time, Indicates the conduction voltage drop of chip M4.

[0018] Furthermore, the IGBT chip M 4 The first optimization parameter The calculation formula is:

[0019] ;

[0020] In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the self-inductance of the current path between chip M4 and terminal DC-. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-.

[0021] Furthermore, the IGBT chip M 4 The second optimization parameter The calculation formula is:

[0022] ;

[0023] In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

[0024] Furthermore, the IGBT chip M 4 The third optimization parameter The calculation formula is:

[0025] ;

[0026] In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from the diode chip to terminal AC-U.

[0027] Furthermore, the IGBT chip M 4 The upper left corner and the lower right corner are both chamfered; the distance between the midpoint of the upper left chamfer and the midpoint of the lower right chamfer is 7.02 mm.

[0028] The beneficial effects of the present invention are:

[0029] (1) The present invention analyzes the voltage composition of the IGBT port and combines the conductor inductance generation mechanism to accurately optimize the DBC substrate layout and reduce parasitic inductance;

[0030] (2) The present invention reflects the parasitic inductance optimization effect on the switching waveform of the IGBT device, optimizing the comprehensive actual effect of the parasitic inductance rather than reducing a certain inductance value alone;

[0031] (3) The present invention takes into account the actual operating effect of the IGBT module. This optimization makes the module operation more stable, reduces voltage spikes, improves switching efficiency, and reduces energy loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a substrate layout structure for optimizing the switching waveform of an intelligent power module;

[0033] Figure 2 It is the topological structure diagram of IPM intelligent power module;

[0034] Figure 3 This is the external wiring diagram of the IPM intelligent power module;

[0035] Figure 4 A schematic diagram of the substrate layout structure of the original intelligent power module switching waveform;

[0036] Figure 5 IPM intelligent power module chip M 4 Schematic diagram of the narrow structure spacing on the copper layer;

[0037] Figure 6 This is the internal parasitic inductance distribution diagram of the IPM intelligent power module;

[0038] Figure 7 IPM module M 4 Chip double pulse test mutual inductance distribution diagram;

[0039] Figure 8 IPM module M 4 Chip turn-on and turn-off voltage waveform. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0041] like Figure 1 As shown, the present invention provides a substrate layout structure for optimizing the switch waveform of an intelligent power module, including a power bus DC+, a power bus DC-, an IGBT chip M 1 -M 6 、IGBT chip M b , diode chip D 1 -D 6 and diode chip D b ;

[0042] IGBT chip M 1 One end of the IGBT chip M 3 One end and IGBT chip M 5 One end of the IGBT chip M is connected to the power bus DC- through a bonding wire;1 The other end and diode chip D 1 One end of the IGBT chip M 3 The other end and diode chip D 3 One end of the IGBT chip M 5 The other end and diode chip D 5 One end of the diode chip D 1 The other end of the diode chip D 3 The other end and diode chip D 5 The other end is connected to the power bus DC+ through bonding wires;

[0043] IGBT chip M 4 One end of the IGBT chip M 6 One end and IGBT chip M 2 One end of the IGBT chip M is connected to the power bus DC+ through a bonding wire; 4 The other end and diode chip D 4 One end of the IGBT chip M 6 The other end and diode chip D 6 One end of the IGBT chip M 2 The other end and diode chip D 2 One end of the diode chip D 4 The other end of the diode chip D 6 The other end and diode chip D 2 The other end is connected to the power bus DC-+ through bonding wires;

[0044] IGBT chip M b One end of the IGBT chip M is connected to the power bus DC- through a bonding wire; b The other end and diode chip D b One end of the diode chip D b The other end is connected to the power bus DC+ through a bonding wire.

[0045] In the embodiment of the present invention, the IGBT chip M 4 Self-perception The calculation formula is:

[0046] ;

[0047] In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit.

[0048] In the embodiment of the present invention, the IGBT chip M 4 Mutual inductance The calculation formula is:

[0049] ;

[0050] In the formula, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

[0051] In the embodiment of the present invention, the IGBT chip M 4 The port voltage The calculation formula is:

[0052] ;

[0053] In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit, and the current flowing through the chip M4, Indicates the current flowing in the gate control circuit. Indicates the current flowing through the diode chip. Indicates time, Indicates the conduction voltage drop of chip M4.

[0054] In the embodiment of the present invention, the IGBT chip M 4 The first optimization parameter The calculation formula is:

[0055] ;

[0056] In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the self-inductance of the current path between chip M4 and terminal DC-. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-.

[0057] In the embodiment of the present invention, the IGBT chip M 4 The second optimization parameter The calculation formula is:

[0058] ;

[0059] In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

[0060] In the embodiment of the present invention, the IGBT chip M 4 The third optimization parameter The calculation formula is:

[0061] ;

[0062] In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from the diode chip to terminal AC-U.

[0063] In the embodiment of the present invention, the IGBT chip M 4 The upper left corner and the lower right corner are both chamfered; the distance between the midpoint of the upper left chamfer and the midpoint of the lower right chamfer is 7.02 mm.

[0064] The present invention proposes a substrate layout design scheme for optimizing the switching waveform of an IGBT intelligent power module. By accurately adjusting the copper layer layout on a DBC substrate, the parasitic inductance of the current flow path can be reduced, so that the voltage waveform of the IGBT device is smoother during high-frequency switching, energy loss is reduced, and the long-term operation reliability of the IPM is improved.

[0065] Figure 1 The layout diagram of the internal current flow path of the IGBT intelligent power module of the present invention is shown, in which the power bus terminal DC+ is connected to the main power circuit on the DBC substrate through a bonding wire, and then the electrical connection with each IGBT unit is realized through the copper layer on the DBC, and the current flow is realized between the upper and lower bridge arms through the bonding wire. Among them, the lead-out terminals of each phase and the connection terminals between the drive protection circuit and the power circuit are fixed by the shell structure, thereby ensuring a stable and reliable connection and reducing the problem of poor contact caused by vibration.

[0066] The present invention optimizes the substrate layout based on the IGBT intelligent power module, analyzes the components of the port voltage of the IGBT switch device, analyzes the cause of the voltage overshoot phenomenon, reduces the bending of the copper layer and shortens the connection path, and increases the flow cross-sectional area of ​​the copper layer to reduce the parasitic inductance in the current flow path, thereby optimizing the switching waveform and reducing the voltage spike.

[0067] During the IGBT device switching process of the above-mentioned intelligent power module, it was found that the port voltage of the IGBT is composed of the device conduction voltage drop, the voltage drop caused by the self-inductance of the current flow path, and the mutual inductance voltage drop caused by other parts of the power circuit to the target circuit. The voltage drop generation mechanism and influencing factors of each part are analyzed, and the layout is optimized as a guiding factor. In addition, the bending angle and flow length of the DBC copper layer, as well as the flow cross-sectional area and other parameters are comprehensively adjusted in combination with the conductor inductance generation mechanism to effectively reduce parasitic inductance, reduce IGBT port voltage overshoot, optimize the switching waveform, and improve the overall efficiency of the module.

[0068] Figure 2 What is displayed is the topological structure of the IGBT intelligent power module, which adopts a 7-unit structure of the main power circuit plus the braking circuit, and a drive protection circuit is designed on the upper layer of the power circuit. The upper drive protection circuit is electrically connected to the lower power circuit through the designed connection terminals. The main power circuit consists of 6 IGBT units and 6 freewheeling diode units, and the braking circuit contains 1 IGBT unit and 1 freewheeling diode unit. The three-phase terminals U, V, and W are led out between the upper and lower power tubes of each phase, and the Br terminal is led out between the braking circuit diode chip and the power tube. Each unit is connected through the copper layer on the DBC substrate to form an efficient current flow path. When the IPM intelligent power module is operating normally, the U, V, and W three-phase terminals are connected to the load, and the power bus DC+ and DC- are connected to the power supply, such as Figure 3 As shown, it ensures that the module operates stably under high-frequency switching conditions.

[0069] According to the topology of IGBT intelligent power module, such as Figure 2 As shown in the figure, the main power circuit consists of 6 IGBT units and 6 freewheeling diode units, the brake circuit contains 1 IGBT unit and 1 freewheeling diode unit, the three-phase terminals U, V, W are drawn between the upper and lower power tubes of each phase, and the Br terminal is drawn between the brake circuit diode chip and the power tube. When the module is running, the three-phase terminals U, V, W are loaded, and the power supply is connected between the bus terminals DC+ and DC-. The IGBT chip and diode chip of the upper bridge switch are respectively denoted as M 1 、M 3 、M 5 and D 1 , D 3 , D 5, the IGBT chip and diode chip of the lower bridge switch are respectively denoted as M 4 、M 6 、M 2 and D 4 , D 6 , D 2 The gate drive terminals and Kelvin source drive terminals of the upper bridge arm and the lower bridge arm are respectively denoted as G x , K x .

[0070] from Figure 5 It can be seen that each part of the module current flow path has self-inductance and mutual inductance between each current flow path. 4 The double pulse test analysis shows that the voltage at the IGBT port is affected by the voltage drop of the inductor on the current flow path, such as Figure 6 As shown in the figure, the IGBT port voltage is divided into several parts, namely the device conduction voltage drop, path self-inductance voltage drop and mutual inductance voltage drop, which also includes the parasitic electrical parameters of the gate drive circuit and Kelvin source. It can be seen that the chip M 4 The internal inductance of the port is mainly composed of the following parts: Where, L C and L E IGBT chip M 4 The inductance value of the self-inductance between the collector and the terminal U and the mutual inductance of other circuits, IGBT chip M 4 The inductance value of the emitter to the DC-terminal is the combined effect of the self-inductance and the mutual inductance of other loops. Inductance definition And Faraday's law of electromagnetic induction formula ; In the formula, is the magnetic flux, is the magnetic flux density, is the electromotive force and is the current flowing through the conductor. Based on this, the IGBT chip M 4 The inductance voltages of each part between the U phase and DC- in the circuit and the port voltage are combined and sorted to obtain the port voltage. It can be concluded that the parameters that need to be optimized are mainly divided into three parts.

[0071] The present invention uses solidworks software to build a three-dimensional model of the module, uses ANSYS Q3D software to extract and simulate the parasitic electrical parameters, and accurately quantifies the parasitic electrical parameters of each part. First, the module current flow area is divided into DC+ area, DC- area, AC-U area, AC-V area, AC-W area, and the gate control circuit G x Area and Kelvin source control loop Kx In ANSYS Q3D software, each current conduction area is measured for parasitic electrical parameters through a Sink and multiple Source measurement points. In this power module model, each current conduction area contains multiple current flow paths, so it is necessary to set a Sink measurement point and multiple Source measurement points. The parasitic electrical parameter extraction results are shown in Table 1.

[0072] Table 1

[0073]

[0074] From the parasitic electrical parameter extraction results, it can be seen that among the several parts that affect the IGBT port voltage, L c and L e dominates, so by focusing on optimizing the parasitic inductance L c , L e The partial module current flow path is used to reduce the voltage spike during the IGBT switching process.

[0075] According to the layout of the power module substrate, improvement measures are proposed: ① Remove the IGBT chip M 4 The rectangular area on top of the copper layer reduces the parasitic inductance L by reducing the current transfer path between conductors of different materials. e , shorten the path length between the chip emitter and the power bus terminal DC-. In layout 1 (before optimization), if Figure 4 As shown, the power chip M 4 The bonding line from the upper surface to the top rectangular area (denoted as B 1 ) is 11.04 mm long, and the bonding wire length from the rectangular area to the bus terminal DC- (denoted as B 2 ) is 7.14mm, because these two sections of bonding wire B 1 , B 2 There are multiple wires connected in parallel, so the length of the internal bonding wires is consistent. 1 , B 2 Connect through rectangular area, B 1 The rightmost bonding wire and B 2 The leftmost bonding wire spacing is the smallest, which is 2.17mm; 1 The leftmost side and B 2 The rightmost bonding wire has the largest spacing, which is 12.85 mm. 4 The minimum distance from the top surface to the terminal DC is 20.35mm (the sum of the lengths of the two bonding wires and their spacing), and the maximum distance is 31.03mm.

[0076] In layout 2 (after optimization), if Figure 1 As shown, due to the removal of the rectangular area, chip M4 Directly connect to the terminal DC- through a bonding wire, the bonding wire has the same shape and length of 19.85mm, which is shorter than the original layout; ② Increase the IGBT chip M 4 The overall area of ​​the copper layer and the cross-sectional area of ​​the current flow. Chip M before optimization 4 The copper layer area is 278.22mm 2 After optimization, the copper layer area is 314.95mm 2 , and optimize chip M at the same time 4 The cross-sectional area of ​​the narrow structure in the lower left corner makes the parasitic inductance L c The specific implementation is as follows:

[0077] (1) Optimize the current flow path to reduce parasitic inductance L e : According to the principle of parasitic inductance generation, the longer the conductor conduction path, the greater the corresponding self-inductance. In the original module substrate layout, the IGBT chip M 4 The upper surface emitter is connected to the upper surface anode of the diode chip through a bonding wire, and is again connected to the rectangular substrate copper layer through a bonding wire. The rectangular copper layer serves as the IGBT chip M. 4 The buffer area connected to the power bus terminal DC-. The buffer area of ​​the rectangular copper layer is removed here, leaving space for the top of the copper layer where the IGBT is located to extend upward. In the original layout, the distance between the top horizontal edge of the copper layer where chip M4 is located and the bottom horizontal edge of the terminal DC- is 9.51mm. After optimization, the distance at the same position is 6.65mm. As a result, the bonding wire on the upper surface of the diode chip is directly connected to the power bus terminal DC-, with a length of 19.85mm, that is, the current flow path is 19.85mm, which is shorter than the original minimum value of 20.35mm, reducing the parasitic inductance caused by this path, that is, reducing the parasitic inductance L e The numerical value of .

[0078] (2) Optimize the shape of the copper layer where the IGBT chip is located to reduce the parasitic inductance L c :According to the original module layout, if Figure 4 As shown, the parasitic inductance L c Mainly from IGBT chip M 4 The current flow path from the bottom layer to the AC output terminal AC-U, which affects the parasitic inductance L c The main factor of size is the shape and size of the copper layer. It can be seen from the original module layout that in the IGBT chip M 4 There are narrow structures in the copper layer area in the lower left corner, such as Figure 5As indicated, the upper left and lower right corners of the narrow area are chamfered, and the distance between the midpoint of the upper left chamfer and the midpoint of the lower right chamfer is 2.63mm. After optimization, the distance is 7.02mm. The inductance of a rectangular cross-section conductor varies with the size of the cross-sectional area. When the cross-sectional area of ​​the copper layer conductor is small, the parasitic inductance is large. The module layout optimization does not change the thickness of the original copper layer, so the parasitic inductance is reduced by increasing the width of the current-carrying copper layer. The expression is: ; Where l is the length of the wire, is the magnetic permeability of vacuum, b and c are the side lengths of the rectangular cross section of the conductor.

[0079] Therefore, a new internal layout of the IGBT intelligent power module is proposed. Figure 1 The parasitic inductance of the module is extracted using ANSYS Q3D software, and the extracted inductance matrix is ​​converted into a circuit sub-module using ANSYS Simplorer software. A double-pulse test simulation model is built to display the switching waveform of the simulated IGBT chip, as shown in the figure. Figure 7 As shown in the figure, it can be seen that the optimized layout structure reduces the voltage spike on the switching waveform and reduces the voltage overshoot phenomenon. Figure 8 It can be seen that in the simulation test, chip M4 is turned on at 42us, and the vertical axis is the voltage value. It can be seen that the voltage value suddenly increases to about 220V at 42us before optimization, which is the voltage overshoot phenomenon, that is, the optimization target of this patent. In the optimized curve, it can be seen that the chip is still turned on at 42us, but the voltage value at this moment only overshoots slightly to about 130V in an instant, and then transitions to the normal value of 120V. This patent successfully optimizes and reduces the voltage overshoot phenomenon by optimizing the substrate layout.

[0080] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A substrate layout structure for optimizing the switching waveform of an intelligent power module, characterized in that: Including power bus DC+, power bus DC-, IGBT chips M1-M6, IGBT chip M b , diode chips D1-D6 and diode chip D b ; One end of the IGBT chip M1, one end of the IGBT chip M3 and one end of the IGBT chip M5 are all connected to the power bus DC- through bonding wires; the other end of the IGBT chip M1 is connected to one end of the diode chip D1; the other end of the IGBT chip M3 is connected to one end of the diode chip D3; the other end of the IGBT chip M5 is connected to one end of the diode chip D5; the other end of the diode chip D1, the other end of the diode chip D3 and the other end of the diode chip D5 are all connected to the power bus DC+ through bonding wires; One end of the IGBT chip M4, one end of the IGBT chip M6 and one end of the IGBT chip M2 are all connected to the power bus DC+ through bonding wires; the other end of the IGBT chip M4 is connected to one end of the diode chip D4; the other end of the IGBT chip M6 is connected to one end of the diode chip D6; the other end of the IGBT chip M2 is connected to one end of the diode chip D2; the other end of the diode chip D4, the other end of the diode chip D6 and the other end of the diode chip D2 are all connected to the power bus DC-+ through bonding wires; The IGBT chip M b One end of the IGBT chip M is connected to the power bus DC- through a bonding wire; b The other end and diode chip D b The diode chip D b The other end is connected to the power bus DC+ through a bonding wire.

2. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The self-inductance of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit.

3. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The mutual inductance of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

4. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The port voltage of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, It represents the self-inductance of the current path between chip M4 and terminal DC-. represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from chip M4 to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal AC-U, Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit, and the current flowing through the chip M4, Indicates the current flowing in the gate control circuit. Indicates the current flowing through the diode chip. Indicates time, Indicates the conduction voltage drop of chip M4.

5. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The first optimization parameter of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the self-inductance of the current path between chip M4 and terminal AC-U. It represents the self-inductance of the current path between chip M4 and terminal DC-. It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal AC-U and the self-inductance on the path from M4 to terminal DC-.

6. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The second optimization parameter of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the gate control circuit. Represents the mutual inductance between the self-inductance of the chip M4 to the terminal DC-path and the self-inductance of the gate control, represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the Kelvin source circuit, Represents the mutual inductance between the self-inductance of the chip M4 to terminal DC-path and the self-inductance of the Kelvin source circuit.

7. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The third optimization parameter of the IGBT chip M4 The calculation formula is: ； In the formula, It represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from diode chip to terminal DC+. represents the mutual inductance between the self-inductance of the path from chip M4 to terminal AC-U and the self-inductance of the path from the diode chip to terminal AC-U, It represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from diode chip to terminal DC+. Represents the mutual inductance between the self-inductance on the path from chip M4 to terminal DC- and the self-inductance on the path from the diode chip to terminal AC-U.

8. The substrate layout structure for optimizing the switching waveform of the intelligent power module according to claim 1, characterized in that: The upper left corner and the lower right corner of the IGBT chip M4 are both chamfered; the distance between the midpoint of the upper left chamfer and the midpoint of the lower right chamfer is 7.02 mm.

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