Semiconductor device, memory system, and manufacturing method of semiconductor device

Abstract

This application provides a semiconductor device, a memory system, and a method for manufacturing the semiconductor device. The semiconductor device includes: a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, with each semiconductor pillar extending along a third direction; a shielding structure located between adjacent semiconductor pillars and extending along the first direction; a first connecting structure located on one side of the shielding structure along the third direction and connected to the shielding structure; and a first contact structure extending along the third direction and connected to the first connecting structure; wherein the first contact structure and the shielding structure are located on the same side of the first connecting structure, and the first direction, the second direction, and the third direction intersect each other.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Technology

[0002] In semiconductor manufacturing, as feature sizes continue to shrink, the coupling effect between adjacent transistors intensifies. To mitigate this coupling, shielding structures are often necessary. However, shielding structures and their related components suffer from small process windows and high manufacturing complexity, which also impact product performance and yield. Summary of the Invention

[0003] This application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems or other problems in the art.

[0004] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes: a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, with each semiconductor pillar extending along a third direction; a shielding structure located between adjacent semiconductor pillars and extending along the first direction; a first connecting structure located on one side of the shielding structure along the third direction and connected to the shielding structure; and a first contact structure extending along the third direction and connected to the first connecting structure; wherein the first contact structure and the shielding structure are located on the same side of the first connecting structure, and the first direction, the second direction, and the third direction intersect each other.

[0005] In some embodiments, the semiconductor device further includes a second connection structure located on the surface of the first connection structure away from the shielding structure, wherein the first contact structure extends to the second connection structure.

[0006] In some embodiments, the semiconductor device further includes: a capacitor connection structure connected to the end face of the semiconductor pillar near the first connection structure; wherein the end face of the capacitor connection structure away from the semiconductor pillar is substantially flush with the surface of the second connection structure away from the first connection structure.

[0007] In some embodiments, the semiconductor device further includes a capacitor connected to the end face of the capacitor connection structure away from the semiconductor pillar.

[0008] In some implementations, the first contact structure extends to the first connection structure.

[0009] In some embodiments, the first connecting structure extends along a second direction and comes into direct contact with a plurality of shielding structures arranged along the second direction.

[0010] In some embodiments, on a plane perpendicular to a third direction, the semiconductor device includes a memory region and a connection region located on the periphery of the memory region, a first connection structure extending within the connection region, and a first contact structure located within the connection region.

[0011] In some embodiments, the semiconductor pillar has a first sidewall adjacent to the shielding structure and a second sidewall opposite to the first sidewall; the semiconductor device further includes: a gate dielectric layer located on the second sidewall of the semiconductor pillar; a word line located on the surface of the gate dielectric layer and extending along a first direction; and a word line contact structure located on the same side of the first connection structure as the first contact structure and extending to the word line.

[0012] In some embodiments, the semiconductor device further includes: a bit line located on the side of the semiconductor pillars away from the first connection structure and connected to a plurality of semiconductor pillars arranged along a second direction; and a bit line contact structure located on the same side of the first connection structure as the first contact structure and extending to the bit line.

[0013] In some embodiments, at least two of the following surfaces are substantially flush: the surface of the first contact structure away from the first connection structure, the surface of the bit line contact structure away from the bit line, and the surface of the word line contact structure away from the word line.

[0014] In some embodiments, on a plane perpendicular to a third direction, the semiconductor device includes a memory region and a connection region located on the periphery of the memory region, wherein a first contact structure, a word line contact structure, and a bit line contact structure are located within the connection region and do not overlap with each other.

[0015] Secondly, some embodiments of this application provide a memory system. The memory system includes: a memory, including semiconductor devices as mentioned in any of the embodiments described above; and a controller coupled to the memory for controlling the memory to store data.

[0016] Thirdly, some embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein each semiconductor pillar extends along a third direction; forming a shielding structure extending along the first direction between adjacent semiconductor pillars, and forming a first connection structure connected to the shielding structure on one side of the shielding structure along the third direction; and forming a first contact structure extending along the third direction from a first side of the semiconductor pillars away from the first connection structure, wherein the first contact structure is connected to the first connection structure; wherein the first direction, the second direction, and the third direction intersect each other.

[0017] In some embodiments, the manufacturing method further includes: forming a second connection structure on the surface of the first connection structure away from the shielding structure; wherein forming a first contact structure extending in a third direction from a first side of the semiconductor pillar away from the first connection structure includes: forming a first contact structure extending to the second connection structure.

[0018] In some embodiments, the manufacturing method further includes forming a capacitor connection structure extending to the semiconductor pillar from a second side opposite to the first side; wherein the second connection structure and the capacitor connection structure are formed in the same process.

[0019] In some embodiments, forming a first contact structure extending in a third direction from a first side of the semiconductor pillar away from the first connection structure includes: forming a first contact structure extending to the first connection structure.

[0020] In some embodiments, the semiconductor pillar has a first sidewall adjacent to the shielding structure and a second sidewall opposite to the first sidewall; the manufacturing method further includes: forming a gate dielectric layer on the second sidewall of the semiconductor pillar; forming word lines extending in a first direction on the surface of the gate dielectric layer; and forming a word line contact structure extending to the word lines from the first side of the semiconductor pillar.

[0021] In some embodiments, the manufacturing method further includes: forming a bit line extending along a second direction on a first side of a semiconductor pillar, the bit line being connected to a plurality of semiconductor pillars arranged along the second direction; and forming a bit line contact structure extending to the bit line on the first side of the semiconductor pillar.

[0022] In some implementations, at least two of the first contact structure, bit line contact structure, and word line contact structure are formed in the same process.

[0023] In some embodiments, forming a plurality of semiconductor pillars arrayed along a first direction and a second direction includes: etching a semiconductor layer to form a plurality of semiconductor walls arranged along the first direction, wherein the semiconductor walls extend along the second direction; filling the outer periphery of the plurality of semiconductor walls with an insulating material; and etching the plurality of semiconductor walls and the insulating material to form a first trench and a second trench arranged alternately along the second direction, thereby dividing the plurality of semiconductor walls into a plurality of semiconductor pillars, wherein both the first trench and the second trench extend along the first direction.

[0024] In some embodiments, forming a shielding structure extending in a first direction between adjacent semiconductor pillars and forming a first connection structure connected to the shielding structure on one side of the shielding structure in a third direction includes: forming the shielding structure in a first trench; forming a conductive layer on a second side of the plurality of semiconductor pillars opposite to the first side; etching a portion of the conductive layer so that the remaining conductive layer serves as the first connection structure and is in direct contact with the shielding structure.

[0025] In some embodiments, etching a portion of the conductive layer so that the remaining conductive layer serves as a first connection structure and is in direct contact with the shielding structure further includes removing a portion of the shielding structure near the second side of the semiconductor pillar.

[0026] According to at least one embodiment of this application, the semiconductor device, memory system, and semiconductor device manufacturing method provided by this application, by placing the first contact structure and the shielding structure on the same side of the first connection structure, can simplify the manufacturing process of the first connection structure and the first contact structure used to lead out the shielding structure, improve the process window, reduce manufacturing difficulty, and help improve the yield and product performance of the semiconductor device. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0028] Figure 1A This is a perspective view of the semiconductor device provided in the embodiments of this application;

[0029] Figure 1B It is along Figure 1A The diagram shows a perspective view of the semiconductor device taken by line A-A'.

[0030] Figure 1C It is a partial perspective schematic diagram of a semiconductor device including a shielding structure, a first connection structure, and a first contact structure;

[0031] Figure 2 This is a perspective view of a semiconductor device provided in another embodiment of this application;

[0032] Figure 3 This is a perspective view of a semiconductor device provided in yet another embodiment of this application;

[0033] Figure 4 This is a perspective view of a semiconductor device provided in another embodiment of this application;

[0034] Figure 5 This is a block diagram of a system with a memory system provided in an embodiment of this application;

[0035] Figure 6 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an embodiment of this application;

[0036] Figures 7A to 18 This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process; and

[0037] Figures 19A to 19CThis is a schematic diagram of the structure of a semiconductor device during the manufacturing process according to another embodiment of this application. Detailed Implementation

[0038] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first connection structure discussed herein may also be referred to as the second connection structure, and vice versa.

[0040] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0042] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0044] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0045] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] This application provides a semiconductor device. Figures 1A to 1C This is a schematic diagram of the structure of the semiconductor device provided in an embodiment of this application. Wherein, Figure 1A This is a perspective view of the semiconductor device provided in the embodiments of this application. Figure 1B It is along Figure 1A The diagram shows a perspective view of a semiconductor device taken by line A-A'. Figure 1C This is a partial perspective view of a semiconductor device including a shielding structure, a first connection structure, and a first contact structure. For example, the semiconductor device 100 may be part of a dynamic random access memory (DRAM).

[0047] It should be noted that, in the following figures, directions D1, D2, and D3 illustrate the spatial relationships of components within a semiconductor device. For example, direction D3 is the extension direction of a semiconductor pillar, and directions D1 and D2 are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., are perpendicular) to this extension direction. For example, direction D1 is the word line direction, and direction D2 is the bit line direction. The same concepts will be used throughout this application to describe the spatial relationships of components within a semiconductor device.

[0048] like Figure 1A and Figure 1B As shown, the semiconductor device 100 includes a plurality of semiconductor pillars (e.g., 111a, 111b) arranged in an array along directions D1 and D2. For example, each semiconductor pillar (e.g., 111a, 111b) extends along direction D3. As will be described in detail below, the semiconductor pillars (e.g., 111a, 111b) may be formed on a semiconductor substrate, and the extension direction of the semiconductor pillars (e.g., 111a, 111b) (e.g., direction D3) may be perpendicular to the horizontal extension direction of the semiconductor substrate.

[0049] In the case where semiconductor device 100 is part of a DRAM memory, the DRAM memory may include multiple memory cells, and each memory cell may include a transistor and a capacitor. The transistors constituting the memory cells and their related components are described below as examples.

[0050] In some implementations, such as Figure 1A As shown, on a plane perpendicular to the D3 direction, the semiconductor device 100 may include a memory region 101 (within the dashed box) and a connection region 102 (outside the dashed box) located on the periphery of the memory region 101. For example, memory cells may be disposed within the memory region 101, and contact structures (e.g., a first contact structure 118, a word line contact structure 121, and a bit line contact structure 122) may be disposed within the connection region 102.

[0051] In some implementations, such as Figure 1B As shown, a semiconductor pillar (e.g., 111a) has a first sidewall 112 and a second sidewall 113 facing each other in the D1 direction. The first sidewall 112 is adjacent to a shielding structure 116, which will be described in detail below. The semiconductor device 100 may include a gate dielectric layer 114 located on the second sidewall 113. For example, the gate dielectric layer 114 is in direct contact with the second sidewall 113 and extends (e.g., continuously) in the D1 direction. The gate dielectric layer 114 may be in direct contact with the second sidewall 113 of each of a row of semiconductor pillars (e.g., 111a) arranged in the D1 direction. Exemplarily, the material of the gate dielectric layer 114 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y One or more of the following: high dielectric constant materials or other suitable insulating materials. For example, the material of the gate dielectric layer 114 may be silicon oxide (SiO2).

[0052] In some embodiments, the semiconductor device 100 may further include word lines 115 located on the surface of the gate dielectric layer 114. Word lines 115 may extend along the D1 direction (e.g., continuously). In some examples, word lines 115 may include an adhesive layer and a metal layer (not shown) bonded to each other. The adhesive layer may be located on the surface of the gate dielectric layer 114 and extend along the D1 direction (e.g., continuously). The metal layer may be located on the surface of the adhesive layer and extend along the D1 direction (e.g., continuously). In other words, the adhesive layer may be located between the metal layer and the gate dielectric layer 114. The adhesive layer helps improve the bonding performance between the metal layer and the gate dielectric layer 114. For example, the material of the adhesive layer may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the metal layer may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metallic material. In other examples, word line 115 may not have a composite structure, but may be made of a conductive material; this application does not impose specific limitations on this.

[0053] As described above, in some embodiments, a semiconductor pillar (e.g., 111a), a gate dielectric layer 114, and a word line 115 covering a portion of the second sidewall 113 of the semiconductor pillar (e.g., 111a) can constitute a transistor. In the transistor, the semiconductor pillar (e.g., 111a) serves as the channel, the word line 115 corresponding to the portion of the second sidewall 113 of the semiconductor pillar (e.g., 111a) serves as the gate, and the two ends of the semiconductor pillar (e.g., 111a) extending in the direction of extension serve as one of the source and drain electrodes, respectively. Since the extension direction of the semiconductor pillar (e.g., 111a) (e.g., the D3 direction) is perpendicular to the horizontal extension direction of the semiconductor substrate, this transistor can also be called a vertical channel transistor. Vertical channel transistors can effectively reduce the planar footprint and increase storage density. In this case, the word line 115 extending in the D1 direction can be used to control a row of transistors arranged along the D1 direction. Each transistor can be part of a memory cell.

[0054] In some implementations, such as Figure 1A As shown, viewed from the D3 direction, the word line 115 and the gate dielectric layer 114 can be hollow rectangles, extending within the memory region 101 and the interconnect region 102. The semiconductor device 100 may also include cutouts 123. For example, two cutouts 123 are located in the interconnect regions 102 on either side of the memory region 101 in the D1 direction, and penetrate the word line 115 and the gate dielectric layer 114 along the D3 direction to divide the word line 115 into a first portion and a second portion, such that the first and second portions are electrically isolated within the memory region 101. For example, the cutouts 123 may be filled with materials such as silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2).x N y (or any other suitable insulating material) or one or more. Optionally, there may be multiple word lines 115, spaced apart between adjacent semiconductor pillars (e.g., 111a).

[0055] As the feature size of transistors and their related components shrinks, the coupling effect between adjacent transistors intensifies. To improve this coupling effect, shielding structure 116 was developed. The shielding structure 116 and its related structures are described below by way of example.

[0056] Continue to refer to Figure 1A and Figure 1B The semiconductor device 100 also includes a shielding structure 116, a first connection structure 117, and a first contact structure 118. The shielding structure 116 is located between adjacent semiconductor pillars (e.g., 111a, 111b) and extends along the D1 direction (e.g., continuously). For example, the shielding structure 116 extends within the storage region 101 and the connection region 102. In some examples, the shielding structure 116 may be located on a first sidewall 112 of a semiconductor pillar (e.g., 111a) and in direct contact with the semiconductor pillar (e.g., 111a). In other examples, a dielectric layer (not shown) may be present between the shielding structure 116 and the semiconductor pillar (e.g., 111a). Exemplarily, the material of the shielding structure 116 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. Optionally, there may be multiple shielding structures 116, and the multiple shielding structures 116 may be arranged alternately with word lines 115 in the D2 direction.

[0057] like Figure 1A and 1CAs shown, the first connecting structure 117 is located on one side of the shielding structure 116 along the D3 direction and is connected to the shielding structure 116. In some embodiments, the first connecting structure 117 may be located within the connecting area 102, and may include a first portion 1171 and a second portion 1172. Viewed from the D3 direction, the first portion 1171 may be rectangular and connected to multiple shielding structures 116. The second portion 1172 may be connected to the side of the first portion 1171 away from the storage area 101. It should be noted that the first connecting structure 117 may be a single piece, the first portion 1171 and the second portion 1172 may not have a clear boundary, and the two surfaces of the first portion 1171 and the second portion 1172 may be substantially flush in the D3 direction (e.g., with an error of less than ±10%). For example, the material of the first connection structure 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0058] In some embodiments, the shielding structure 116 may have different dimensions in the D3 direction. For example, in the D3 direction, the size of the portion of the shielding structure 116 located within the storage area 101 is smaller than the size of the portion located within the partial connection area 102 (e.g., where the first connection structure 117 is disposed). The smaller size of the portion of the shielding structure 116 located within the storage area 101 in the D3 direction is used to match the size of the word line 115 in the D3 direction, thereby optimizing control performance. The larger size of the portion of the shielding structure 116 located within the partial connection area 102 in the D3 direction is used to directly contact the first connection structure 117. Exemplarily, the material of the first connection structure 117 may be the same as the material of the shielding structure 116; in this case, they may be a single structure without a distinct boundary.

[0059] Refer again Figure 1A and Figure 1C The first contact structure 118 extends along the D3 direction and connects to the first connecting structure 117. The first contact structure 118 and the shielding structure 116 are located on the same side of the first connecting structure 117. In some embodiments, the first contact structure 118 may be generally columnar, with one end face directly contacting the second portion 1172 of the first connecting structure 117, and its other end face located on the side of the shielding structure 116 away from the first connecting structure 117. In other words, the first contact structure 118 may extend to the second portion 1172 of the first connecting structure 117.

[0060] As described above, the shielding structure 116 is located on the back side of the channel of the transistor (the side without a gate), and a voltage (e.g., a ground voltage) is applied to the shielding structure 116, for example, through the first contact structure 118 and the first connection structure 117, to improve the coupling effect between one column of transistors and another column of transistors arranged along the D1 direction.

[0061] In some exemplary embodiments, the first contact structure and the shielding structure are not overlapped in the D3 direction, and the shielding structure is led out by an additional metal connection layer and through contacts. Compared to this exemplary embodiment, the semiconductor device provided according to the above embodiments of this application, by placing the first contact structure and the shielding structure on the same side of the first connection structure, can simplify the manufacturing process of the first connection structure and the first contact structure used to lead out the shielding structure, improve the process window, reduce manufacturing difficulty, and help improve the yield and product performance of the semiconductor device.

[0062] In some implementations, such as Figure 1A and 1B As shown, the semiconductor device 100 may further include a capacitor connection structure 119 and a capacitor. As described above, in addition to transistors, the memory cell may also include a capacitor (not shown). For example, a transistor and a capacitor constitute a memory cell. The capacitor connection structure 119 may be connected to the end face of a semiconductor pillar (e.g., 111a) near the first connection structure 117. For example, the capacitor connection structure 119 may be generally pillar-shaped, with one end face directly contacting the end face of the semiconductor pillar (e.g., 111a) near the first connection structure 117, and its other end face connected to the capacitor so that the capacitor is connected to one of the source or drain terminals of the transistor. For example, the dimension of the capacitor connection structure 119 in the D3 direction may be larger than the dimension of the first connection structure 117 in the D3 direction. Exemplarily, the material of the capacitor connection structure 119 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0063] In some embodiments, the capacitor may include a first electrode, an insulating layer, and a second electrode. The insulating layer may be located between the first and second electrodes. The first electrode may be in direct contact with the capacitor connection structure 119. In some examples, the capacitor may be generally cylindrical. The first electrode may be a barrel shape with one open end, the second electrode may be cylindrical and located inside the first electrode, and the insulating layer is located between the first and second electrodes. The closed end of the first electrode is in direct contact with the capacitor contact structure 119. In other examples, the first electrode, insulating layer, and second electrode may be stacked sequentially along the D3 direction. It should be noted that this application does not limit the specific structure of the capacitor. Furthermore, the number of capacitor connection structures 119 and capacitors may be the same as the number of semiconductor pillars (e.g., 111a) located within the storage region 101.

[0064] In some embodiments, the semiconductor device 100 may further include bit lines 120. Bit lines 120 may be located on the side of a semiconductor pillar (e.g., 111a) away from the first connection structure 117 and connected to a row of semiconductor pillars (e.g., 111a, 111b) arranged along D2. For example, bit lines 120 extend along the D2 direction within the memory region 101 and the connection region 102, and the ends of a row of semiconductor pillars (e.g., 111a) arranged along D2 away from the first connection structure 117 may be connected to each other and in direct contact with bit lines 120. Thus, one of the source or drain terminals of a row of transistors arranged along the D2 direction is connected to the same bit line 120. There may be multiple bit lines 120, which may be arranged along the D1 direction. For example, the material of bit line 120 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicides (e.g., silicides of one or more of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt)) or any other suitable conductive material.

[0065] In some embodiments, the semiconductor device 100 may further include a bit line contact structure 122. The bit line contact structure 122 is located on the same side of the first contact structure 118 as the first connection structure 117 and extends to the bit line 120. For example, the bit line contact structure 122 may be generally columnar, with one end face directly contacting the bit line 120 and the other end face located on the side of the bit line 120 away from the first connection structure 117. For example, the bit line contact structure 122 may be located within the connection region 102, and each bit line 120 may be connected to one bit line contact structure 122. Exemplarily, the material of the bit line contact structure 122 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicides (e.g., one or more silicides of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt)) or any other suitable conductive material.

[0066] In some embodiments, the semiconductor device 100 may further include a word line contact structure 121. The word line contact structure 121 is located on the same side of the first contact structure 117 as the first connection structure 118 and extends to the word line 115. For example, the word line contact structure 121 may be generally columnar, with one end face directly contacting the word line 115 and the other end face located on the side of the word line 115 away from the first connection structure 117. For example, the word line contact structure 121 may be located within the connection region 102, and each word line 115 may be connected to two word line contact structures 121, such that a first portion and a second portion of the word line 115 are each connected to one word line contact structure 121. Exemplarily, the material of the word line contact structure 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicides (e.g., silicides of one or more of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt)) or any other suitable conductive material. For example, the first contact structure 118 and the plurality of word line contact structures 121 are arranged substantially collinearly along the D2 direction.

[0067] In some embodiments, at least two of the following surfaces are substantially flush (e.g., with an error of less than ±10%): the surface of the first contact structure 118 away from the first connection structure 117, the surface of the bit line contact structure 122 away from the bit line 120, and the surface of the word line contact structure 121 away from the word line 115. Thus, the first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 can be formed in the same process from the side of the shielding structure 116 away from the first connection structure 117, thereby simplifying the manufacturing process, improving production efficiency, and reducing manufacturing costs.

[0068] In some embodiments, viewed from the D3 direction, the first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 are all located within the connection area 102, and serve as the lead-out structures for the shielding structure 116, the bit line 120, and the word line 115, respectively. The first contact structure 118, the bit line contact structure 122, and the word line contact structure 121 do not overlap with each other to avoid structural interference.

[0069] Figure 2 This is a perspective view of a semiconductor device provided in another embodiment of this application. For the purpose of brevity, the same content as in the previous embodiment will not be repeated in the following embodiments.

[0070] like Figure 2 As shown, in semiconductor device 200, a first connection structure 217 is located on one side of shielding structure 216 along the D3 direction and is connected to shielding structure 216. For example, the first connection structure 217 may be located within connection region 202 (outside the dashed box). Viewed from the D3 direction, the first connection structure 217 may be rectangular and connected to multiple shielding structures 216. One end face of the first contact structure 218 is in direct contact with the end of the first connection structure 217 in the D2 direction, and the other end face is located on the side of shielding structure 216 away from the first connection structure 217. In other words, the first contact structure 218 may extend to the end of the first connection structure 217 in the D2 direction. For example, the first contact structure 218 and multiple bit line contact structures 222 are arranged approximately collinearly along the D1 direction.

[0071] Figure 3 This is a perspective view of a semiconductor device provided in another embodiment of this application. (See diagram below.) Figure 3As shown, the semiconductor device 300 may further include a second connection structure 324. The second connection structure 324 may be located on the surface of the first connection structure 317 away from the shielding structure 316. For example, both the first connection structure 317 and the second connection structure 324 are located within the connection region 302 (outside the dashed box). Viewed from the D3 direction, the first connection structure 317 may be rectangular and connected to multiple shielding structures 316. The second connection structure 324 is in direct contact with the first connection structure 317, and in the D1 direction, the second connection structure 324 extends away from the storage region 301. Optionally, the surface of the second connection structure 324 away from the first connection structure 317 is substantially flush with the end face of the capacitor connection structure 319 away from the semiconductor pillar (e.g., 311a) (e.g., with an error of less than ±10%), allowing the second connection structure 324 and the capacitor connection structure 319 to be formed in the same process, thereby simplifying the manufacturing process. One end face of the first contact structure 318 is in direct contact with the second connection structure 324, and the other end face is located on the side of the shielding structure 316 away from the first connection structure 317. In other words, the first contact structure 318 extends to the second connection structure 324. For example, the first contact structure 318 and the plurality of word line contact structures 321 are arranged approximately collinearly along the D2 direction.

[0072] Figure 4 This is a perspective view of a semiconductor device provided in another embodiment of this application. Figure 4 As shown, in semiconductor device 400, the second connection structure 424 may be located on the surface of the first connection structure 417 away from the shielding structure 416. For example, in the D2 direction, the end face of the second connection structure 424 is substantially flush with the end face of the first connection structure 417 (e.g., with an error of less than ±10%). One end face of the first contact structure 418 is in direct contact with the first connection structure 417, and the other end face is located on the side of the shielding structure 416 away from the first connection structure 417. In other words, the first contact structure 418 extends to the first connection structure 417. For example, the first contact structure 418 and the plurality of bit line contact structures 422 are arranged substantially collinearly along the D1 direction.

[0073] In some embodiments, in the D2 direction, the end face of the second connecting structure 424 may protrude beyond the end face of the first connecting structure 417, and the first contact structure 418 extends to the second connecting structure 424 (not shown).

[0074] This application also provides a memory system. Figure 5 This is a block diagram of a system with a memory system provided in an embodiment of this application.

[0075] like Figure 5As shown, system 500 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 510 located therein). Figure 5 As shown, system 500 may include host 520 and memory system 510. Memory system 510 has one or more memories 511 and a controller 512. Host 520 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 520 may be configured to send or receive data to and from memory 511.

[0076] In some implementations, controller 512 is coupled to memory 511 and host 520 and is configured to control memory 511. For example, controller 512 may be configured to control memory 511 to perform operations such as read, erase, and program. Controller 512 may also manage data stored in memory 511 and communicate with host 520. For example, controller 512 may communicate with external devices (e.g., host 520) according to a specific communication protocol.

[0077] This application also provides a method for manufacturing a semiconductor device. Figure 6 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 6 As shown, a semiconductor device manufacturing method 600 (hereinafter referred to as manufacturing method 600) may include the following steps.

[0078] S610 forms a plurality of semiconductor pillars arranged in an array along a first direction and a second direction, wherein each semiconductor pillar extends along a third direction.

[0079] S620, a shielding structure extending in a first direction is formed between adjacent semiconductor pillars, and a first connection structure connected to the shielding structure is formed on one side of the shielding structure in a third direction.

[0080] S630, a first contact structure extending in a third direction is formed from a first side of the semiconductor pillar away from the first connection structure, wherein the first contact structure is connected to the first connection structure.

[0081] According to the semiconductor device manufacturing method provided in this embodiment, by forming a first connection structure connected to the shielding structure on one side of the shielding structure along a third direction, and forming a first contact structure extending along a third direction and connected to the first connection structure from a first side of the semiconductor pillar away from the first connection structure, the manufacturing process of the first connection structure and the first contact structure used to lead out the shielding structure can be simplified, the process window can be improved, the manufacturing difficulty can be reduced, and the yield and product performance of the semiconductor device can be improved.

[0082] Figures 7A to 18 This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process. For example, Figures 7A to 18 Can be used to form Figure 3 The semiconductor device 300 is shown below. (The following is in conjunction with...) Figures 7A to 18 as well as Figure 3 Steps S610 to S630 described above are illustrated by way of example.

[0083] S610

[0084] Figure 7A and Figure 7B An intermediate structure 700a is shown, comprising a semiconductor layer 731, a first dielectric layer 732, and a second dielectric layer 733. Figure 7A This is a top view of the intermediate structure 700a. Figure 7B It is along Figure 7A The diagram shows a cross-section taken by line B-B'.

[0085] In some implementations, such as Figure 7A and Figure 7B As shown, the semiconductor layer 731 can be a semiconductor substrate. For example, the material of the semiconductor substrate can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Alternatively, the semiconductor substrate can be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrates, etc.

[0086] In some embodiments, the material of the first dielectric layer 732 may include silicon oxide (SiO2), and the material of the second dielectric layer 733 may include silicon nitride (Si3N4). In some examples, the first dielectric layer 732 and the second dielectric layer 733 may be sequentially formed on the semiconductor layer 731 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other examples, the first dielectric layer 732 may be formed on the semiconductor layer 731 using dry oxidation or wet oxidation methods.

[0087] Figure 8A and Figure 8B An intermediate structure 700b is shown after forming multiple semiconductor walls 734 and filling with insulating material 735. Among them, Figure 8A This is a top view of the intermediate structure 700b. Figure 8B It is along Figure 8A The diagram shows a cross-sectional view taken along line B-B'. It should be noted that, to more clearly illustrate the spatial relationships of the components within the intermediate structure 700b, [the diagram is shown here]. Figure 8A The first dielectric layer 732 and the second dielectric layer 733 are omitted from the diagram, and the same manner of representation is used for similar top-view schematic diagrams below.

[0088] In some implementations, such as Figure 8A and Figure 8B As shown, the semiconductor layer 731 can be patterned using photolithography and etching (e.g., dry etching and / or wet etching) processes to form a plurality of semiconductor walls 734 extending along the D2 direction and arranged along the D1 direction. For example, the second dielectric layer 733 can be used as a hard mask for etching the semiconductor layer 731. The semiconductor walls 734 and the unetched semiconductor layer 731 are arranged perpendicularly in the D3 direction. Since the semiconductor walls 734 are formed by etching the semiconductor layer 731, the semiconductor walls 734 are made of the same material as the semiconductor layer 731. For example, viewed from the D3 direction, the plurality of semiconductor walls 734 have the same dimensions in the D2 direction, but their ends are not flush. Specifically, the ends of the odd-numbered semiconductor walls 734 are flush, and the ends of the even-numbered semiconductor walls 734 are flush. Further, an insulating material 735 can be filled around the periphery of the plurality of semiconductor walls 734 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to electrically isolate adjacent semiconductor walls 734.

[0089] Figure 9A and Figure 9B An intermediate structure 700c is shown after the formation of the first trench 736 and the initial second trench 737'. Among them, Figure 9A This is a top view of the intermediate structure 700c. Figure 9B It is along Figure 9A The diagram shows a cross-section taken by line C-C'. Figure 10A and Figure 10B An intermediate structure 700d is shown after the first sacrificial material 738 is filled into the first trench 736 and the initial second trench 737'. Wherein, Figure 10A This is a top view of the intermediate structure 700d.

[0090] Figure 10B It is along Figure 10A The diagram shows a cross-section taken by line C-C'. Figure 11A and Figure 11B The intermediate structure 700e is shown after the first sacrificial material 738 has been removed from the initial second trench 737'. Wherein, Figure 11A This is a top view of the intermediate structure 700e. Figure 11B It is along Figure 11A The diagram shows a cross-section taken by line C-C'. Figure 12A and Figure 12B The intermediate structure 700f is shown after the formation of the second trench 737. Among them, Figure 12A This is a top view of the intermediate structure 700f. Figure 12B It is along Figure 12A The diagram shows a cross-section taken by line C-C'.

[0091] In some implementations, such as Figure 9A and Figure 9B As shown, the semiconductor walls 734 and insulating material 735 formed above the semiconductor layer 731 can be patterned using photolithography and etching (e.g., dry etching and / or wet etching) processes to form a first trench 736 and an initial second trench 737' both extending along the D1 direction, and multiple semiconductor walls 734 (refer to...) Figure 8A The structure is divided into multiple initial semiconductor pillars 711'. First trenches 736 and initial second trenches 737' are alternately arranged in the D2 direction. For example, the dimension of the first trench 736 in the D2 direction may be equal to the dimension of the initial second trench 737' in the D2 direction. Alternatively, the dimension of the first trench 736 in the D1 direction may be smaller than the dimension of the initial second trench 737' in the D1 direction, and the ends of the multiple first trenches 736 and the multiple initial second trenches 737' are substantially flush in the D1 direction (e.g., with an error of less than ±10%). The ends of the first trenches 736 in the D1 direction are recessed relative to the ends of the initial second trenches 737' in the D1 direction.

[0092] Next, in some implementations, such as Figure 10A and Figure 10B As shown, a first sacrificial material 738 can be filled in the first trench 736 and the initial second trench 737' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the first sacrificial material 738 may include polysilicon, carbon, spin-on-carbon (SOC), spin-on-dielectric, or any other suitable sacrificial material.

[0093] Then, in some embodiments, a mask material layer (e.g., a photoresist layer and / or a hard mask layer) may be applied to the top surface of the intermediate structure 700d, and the initial second trench 737' may be exposed by patterning. Further, an etching process (e.g., dry etching and / or wet etching) may be used to remove the first sacrificial material 738 in the initial second trench 737', while retaining the first sacrificial material layer 738 in the first trench 736, such as... Figure 11A and Figure 11B As shown.

[0094] Next, in some implementation methods, such as Figure 12A and Figure 12B As shown, an etching process (e.g., wet etching) can be used to increase the size of the initial second trench 737' in the D2 direction to form a second trench 737 with a larger size in the D2 direction. Optionally, during the process of increasing the size of the initial second trench 737' in the D2 direction, the size of the initial second trench 737' in the D3 direction will also increase. For example, the depths of both the first trench 736 and the second trench 737 are smaller than the semiconductor wall 734 (see reference). Figure 8A The dimension in the D3 direction. Thus, the ends of several semiconductor pillars 711 arranged along the D2 direction can be connected to each other through unetched semiconductor walls 734.

[0095] Based on the above, as Figure 12A and Figure 12B As shown, the first trench 736 and the second trench 737 connect multiple semiconductor walls 734 (reference). Figure 8A The structure is divided into multiple semiconductor pillars 711. The semiconductor pillars 711 and the unetched semiconductor layer 731 are arranged perpendicularly in the D3 direction. Since the semiconductor pillars 711 are formed by etching the semiconductor layer 731, the semiconductor pillars 711 and the semiconductor layer 731 are made of the same material. For example, in a plane perpendicular to the D3 direction, the intermediate structure 700f may include a memory region 701 (within the dashed box) and a connection region 702 (outside the dashed box) located on the periphery of the memory region 701. A first trench 736 and a second trench 737 extend (e.g., continuously) within the memory region 701.

[0096] It should be noted that although the method of forming the second groove 737 by increasing the size of the initial second groove 737' in the D2 direction has been described in detail above, this application does not impose specific limitations on the method of forming the second groove 737. For example, it can be formed directly by patterning. Figure 12A and Figure 12B The first groove 736 and the second groove 737 are shown. Furthermore, the dimensional relationship between the first groove 736 and the second groove 737 in the D2 direction is not specifically limited in this application.

[0097] Figure 13A and Figure 13B The intermediate structure 700g is shown after the initial gate dielectric layer 714' and initial word line 715' are formed. Figure 13A This is a schematic diagram of a cross-section of the intermediate structure 700g taken perpendicular to the D1 direction. Figure 13B It is along Figure 13A The diagram shows a cross-section taken by line D-D'.

[0098] In some implementations, such as Figures 12A to 13B As shown, when the second trench 737 is in an unfilled state, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, or an oxidation method (e.g., dry oxidation or wet oxidation) can be used to form an initial gate dielectric layer 714' on the inner wall of the second trench 737. Since the second trench 737 can expose the second sidewall of the semiconductor pillar 711 perpendicular to the D2 direction, the initial gate dielectric layer 714' can be formed on the second sidewall of the semiconductor pillar 711.

[0099] Then, continue to refer to Figure 13A and Figure 13B An initial adhesive layer 7151' and an initial metal layer 7152' can be sequentially formed on the surface of the initial gate dielectric layer 714' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The initial adhesive layer 7151' and the initial metal layer 7152' can serve as the initial word line 715'. Optionally, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial word line 715' away from the semiconductor layer 731, such that the surface of the initial word line 715' away from the semiconductor layer 731 is lower than the surface of the semiconductor pillar 711 away from the semiconductor layer 731. Next, an insulating material can be filled on top of the initial word line 715' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0100] In some implementations, such as Figure 13B As shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a notch 723 that penetrates the initial word line 715' and the initial gate dielectric layer 714'. Optionally, the notch 723 may only penetrate the initial word line 715' without etching the initial gate dielectric layer 714'. For example, the notch 723 may be filled with materials such as silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of the following: (or any other suitable insulating material). For example, cut 723 is used to divide the annular (viewed from the D3 direction) initial word line 715' into a first part and a second part, and to make the first part and the second part electrically isolated within the storage area 701.

[0101] S620

[0102] Figure 14A and Figure 14B The intermediate structure 700h is shown after the formation of the conductive layer 739 and the photoresist layer 740. Among them, Figure 14A This is a top view of the intermediate structure 700h. Figure 14B It is along Figure 14A The diagram shows a cross-section taken by line E-E'. Figures 15A to 15C An intermediate structure 700i is shown after the shielding structure 716 and the first connecting structure 717 are formed. Among them, Figure 15A This is a top view of the 700i intermediate structure. Figure 15B It is along Figure 15A The diagram shows a cross-section taken by line C-C'. Figure 15C It is along Figure 15A The diagram shows a cross-section taken by line E-E'.

[0103] In some implementations, such as Figures 13A to 14B As shown, after forming the initial gate dielectric layer 714' and the initial word line 715', the first sacrificial material 738 in the first trench 736 can be removed. Further, a conductive layer 739 can be formed in the first trench 736 and on one side (hereinafter referred to as the second side) of the plurality of semiconductor pillars 711 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The conductive layer 739 in the first trench 736 can serve as a shielding structure 716. Further, photoresist can be spin-coated onto the top surface of the conductive layer 739, and the photoresist can be patterned using a photolithography process to form a shape such as... Figure 14A The photoresist layer 740 is shown. Subsequently, using the photoresist layer 740 as a masking layer, an etching process (e.g., dry etching and / or wet etching) is employed to remove a portion (e.g., the portion not covered by the photoresist layer 740) of the conductive layer 739 formed on the second side of the plurality of semiconductor pillars 711. The retained conductive layer 739 can serve as a first interconnect structure 717, such as... Figure 15A As shown. The first connection structure 717 can be connected (e.g., in direct contact) to a plurality of shielding structures 716 in the D3 direction. Optionally, during the formation of the first connection structure 717, a portion of the shielding structure 716 near the second side of the semiconductor pillar 711 may be removed to connect with the word line 715 to be formed (see reference). Figure 3 The dimensions in the D3 direction are matched.

[0104] Figure 16A and Figure 16B The intermediate structure 700j is shown after the formation of the insulating layer 741. Among them, Figure 16A This is a top view of the intermediate structure 700j. Figure 16B It is along Figure 16A The diagram shows a cross-section taken by line E-E'. Figures 17A to 17C An intermediate structure 700k is shown after the formation of the capacitor connection structure 719 and the second connection structure 724. Among them, Figure 17B It is along Figure 17A The diagram shows a cross-section taken by line C-C'. Figure 17C It is along Figure 17A The diagram shows a cross-section taken by line E-E'.

[0105] In some implementations, such as Figure 16A and Figure 16B As shown, an insulating layer 741 can be formed on the second side of a plurality of semiconductor pillars 711 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, the surface of the insulating layer 741 away from the semiconductor layer 731 is substantially flush (e.g., with an error of less than ±10%). Exemplarily, the material of the insulating layer 741 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y (or any other suitable insulating material) or one or more of these. Further, such as Figures 17A to 17C As shown, the capacitor connection structure 719 extending to the semiconductor pillar 711 can be formed using etching (e.g., dry etching and / or wet etching) and thin film deposition processes. Optionally, during the formation of the capacitor connection structure 719, a second connection structure 724 can be formed on the surface of the first connection structure 717 away from the shielding structure 716. In other words, the second connection structure 724 and the capacitor connection structure 719 can be formed in the same process to simplify the process and save manufacturing costs. In this embodiment, the second connection structure 724 can extend along the D1 direction from the D3 direction.

[0106] Figure 18 This is a cross-sectional schematic diagram of the intermediate structure 700l after capacitor 742 has been formed. In some embodiments, such as Figure 18 As shown, the capacitor 742 can be formed at the end of the capacitor connection structure 719 away from the semiconductor pillar 711 using any process known in the art. For example, the capacitor 742 is formed within the storage region 701. As described above, the capacitor 742 can be implemented in various structural forms, and is not limited to these. Figure 18 The column shape shown.

[0107] S630

[0108] In some implementations, it is possible to Figure 18 The intermediate structure 700l shown is flipped 180° to move away from the semiconductor pillar 711 away from the first connection structure 717 (reference). Figure 17B Subsequent processing is performed on one side (hereinafter referred to as the first side).

[0109] like Figure 18 As shown, in some embodiments, the semiconductor layer 731 can first be planarized using a CMP process. Then, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial gate dielectric layer 714' and the initial word line 715' away from the capacitor 742, thereby breaking the initial word line 715' in the D2 direction, thus forming the gate dielectric layer 314 and the word line 315, as shown. Figure 3 As shown. Alternatively, as Figure 3 As shown, during the formation of word line 315, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of shielding structure 316 away from capacitor (not shown) so that shielding structure 316 matches the dimensions of word line 315 in the D3 direction.

[0110] In some implementations, reference continues. Figure 3 The bit line 320 can be formed using photolithography and etching processes, as well as thin film deposition processes. For example, the bit line 320 extends along the D2 direction and is connected to the semiconductor wall 734 (reference). Figure 8A The unetched portion is in direct contact, thereby connecting bit line 320 to a plurality of semiconductor pillars (e.g., 311a) arranged along the D2 direction.

[0111] In some embodiments, photolithography and etching processes, as well as thin-film deposition processes, can be used to form a bit line contact structure 322 extending to the bit line 320, a word line contact structure 321 extending to the word line 315, and a first contact structure 318 extending to the second connection structure 324 from a first side of the semiconductor pillar (e.g., 311a). The first contact structure 318 is in direct contact with the second connection structure 324 and is connected to the first connection structure 317 through the second connection structure 324. Optionally, at least two of the first contact structure 318, the bit line contact structure 322, and the word line contact structure 321 can be formed in the same process.

[0112] Figures 19A to 19C An intermediate structure 800k is shown in another embodiment after the formation of the capacitor connection structure 819 and the second connection structure 824. Wherein, Figure 19B It is along Figure 19A The diagram shows a cross-section taken by line C-C'. Figure 19C It is along Figure 19A The diagram shows a cross-section taken by line E-E'.

[0113] like Figures 19A to 19CAs shown, the capacitor connection structure 819 extending to the semiconductor pillar 811 can be formed using etching (e.g., dry etching and / or wet etching) and thin film deposition processes. Optionally, during the formation of the capacitor connection structure 819, a second connection structure 824 can be formed on the surface of the first connection structure 817 away from the shielding structure 816. In other words, the second connection structure 824 and the capacitor connection structure 819 can be formed in the same process to simplify the process and save manufacturing costs. In this embodiment, the second connection structure 824 can extend along the D2 direction from the D3 direction.

[0114] It should be noted that in the method described above, the step of forming the second connection structure can be omitted, allowing the first contact structure to extend to the first connection structure so that the two can be connected through direct contact with the first connection structure. This application does not impose any specific restrictions on this.

[0115] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple semiconductor pillars are arranged in an array along a first direction and a second direction, and each of the semiconductor pillars extends along a third direction; A shielding structure is located between adjacent semiconductor pillars and extends along the first direction; A first connecting structure is located on one side of the shielding structure along the third direction and is connected to the shielding structure; as well as A first contact structure extends along the third direction and is connected to the first connection structure; The first contact structure and the shielding structure are located on the same side of the first connection structure, and the first direction, the second direction, and the third direction intersect each other.

2. The semiconductor device according to claim 1, wherein, Also includes: The second connection structure is located on the surface of the first connection structure away from the shielding structure, wherein the first contact structure extends to the second connection structure.

3. The semiconductor device according to claim 2, wherein, Also includes: A capacitor connection structure is connected to the end face of the semiconductor pillar near the first connection structure; The end face of the capacitor connection structure away from the semiconductor pillar is substantially flush with the surface of the second connection structure away from the first connection structure.

4. The semiconductor device according to claim 3, wherein, Also includes: A capacitor is connected to the end face of the capacitor connection structure away from the semiconductor pillar.

5. The semiconductor device according to claim 1, wherein, The first contact structure extends to the first connection structure.

6. The semiconductor device according to claim 1, wherein, The first connecting structure extends along the second direction and is in direct contact with the plurality of shielding structures arranged along the second direction.

7. The semiconductor device according to claim 6, wherein, On a plane perpendicular to the third direction, the semiconductor device includes a storage region and a connection region located on the periphery of the storage region, the first connection structure extending within the connection region, and the first contact structure located within the connection region.

8. The semiconductor device according to claim 1, wherein, The semiconductor pillar has a first sidewall close to the shielding structure and a second sidewall opposite to the first sidewall; The semiconductor device further includes: A gate dielectric layer is located on the second sidewall of the semiconductor pillar; Word lines, located on the surface of the gate dielectric layer and extending along the first direction; and The word line contact structure is located on the same side as the first contact structure and extends to the word line.

9. The semiconductor device according to claim 8, wherein, Also includes: Bit lines are located on the side of the semiconductor pillars away from the first connection structure and are connected to a plurality of semiconductor pillars arranged along the second direction; as well as The bit line contact structure is located on the same side of the first connection structure as the first contact structure and extends to the bit line.

10. The semiconductor device according to claim 9, wherein, At least two of the following surfaces are substantially flush: the surface of the first contact structure away from the first connection structure, the surface of the bit line contact structure away from the bit line, and the surface of the word line contact structure away from the word line.

11. The semiconductor device according to claim 10, wherein, On a plane perpendicular to the third direction, the semiconductor device includes a memory region and a connection region located on the periphery of the memory region, wherein the first contact structure, the word line contact structure, and the bit line contact structure are located within the connection region and do not overlap with each other.

12. A memory system, characterized in that, include: The memory includes the semiconductor device as described in any one of claims 1 to 11; as well as A controller, coupled to the memory, is used to control the memory to store data.

13. A method for manufacturing a semiconductor device, characterized in that, include: A plurality of semiconductor pillars are arranged in an array along a first direction and a second direction, wherein each of the semiconductor pillars extends along a third direction; A shielding structure extending in a first direction is formed between adjacent semiconductor pillars, and a first connection structure connected to the shielding structure is formed on one side of the shielding structure along the third direction; and A first contact structure extending in a third direction is formed from a first side of the semiconductor pillar away from the first connection structure, wherein the first contact structure is connected to the first connection structure; The first direction, the second direction, and the third direction intersect each other.

14. The manufacturing method according to claim 13, wherein, Also includes: A second connection structure is formed on the surface of the first connection structure that is away from the shielding structure; The formation of a first contact structure extending in a third direction from a first side of the semiconductor pillar away from the first connection structure includes: The first contact structure is formed to extend to the second connection structure.

15. The manufacturing method according to claim 14, wherein, Also includes: A capacitor connection structure extending to the semiconductor pillar is formed from the second side opposite to the first side of the semiconductor pillar; The second connection structure and the capacitor connection structure are formed in the same process.

16. The manufacturing method according to claim 13, wherein, Forming a first contact structure extending in the third direction from a first side of the semiconductor pillar away from the first connection structure includes: The first contact structure is formed, extending to the first connection structure.

17. The manufacturing method according to claim 13, wherein, The semiconductor pillar has a first sidewall close to the shielding structure and a second sidewall opposite to the first sidewall; The manufacturing method further includes: A gate dielectric layer is formed on the second sidewall of the semiconductor pillar; Word lines extending along the first direction are formed on the surface of the gate dielectric layer; and A word line contact structure extending to the word line is formed from the first side of the semiconductor pillar.

18. The manufacturing method according to claim 17, wherein, Also includes: A bit line extending along the second direction is formed on the first side of the semiconductor pillar, and the bit line is connected to a plurality of semiconductor pillars arranged along the second direction; A bit line contact structure extending to the bit line is formed on the first side of the semiconductor pillar.

19. The manufacturing method according to claim 18, wherein, At least two of the first contact structure, the bit line contact structure, and the word line contact structure are formed in the same process.

20. The manufacturing method according to claim 13, wherein, Forming an array of multiple semiconductor pillars arranged along a first direction and a second direction includes: The semiconductor layer is etched to form a plurality of semiconductor walls arranged along the first direction, wherein the semiconductor walls extend along the second direction; An insulating material is filled around the outer periphery of the plurality of semiconductor walls; and The plurality of semiconductor walls and the insulating material are etched to form a first trench and a second trench arranged alternately along the second direction, thereby dividing the plurality of semiconductor walls into the plurality of semiconductor pillars, wherein the first trench and the second trench both extend along the first direction.

21. The manufacturing method according to claim 20, wherein, Forming a shielding structure extending along a first direction between adjacent semiconductor pillars, and forming a first connection structure connected to the shielding structure on one side of the shielding structure along the third direction, includes: The shielding structure is formed in the first trench; A conductive layer is formed on the second side of the plurality of semiconductor pillars, opposite to the first side; A portion of the conductive layer is etched, leaving the remaining conductive layer as the first connection structure and in direct contact with the shielding structure.

22. The manufacturing method according to claim 21, wherein, Etching a portion of the conductive layer, so that the remaining conductive layer serves as the first connection structure and is in direct contact with the shielding structure, further includes: Remove a portion of the shielding structure from the second side near the semiconductor pillar.

Images