Semiconductor device structure with vertical transistor over subsurface bit line

Abstract

The invention discloses a semiconductor device structure. The semiconductor device structure comprises a semiconductor substrate, an active region, a shallow trench isolation region and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is located in the semiconductor substrate, the active region comprises a transistor, the transistor comprises a gate structure, a first conductive region and a second conductive region, and the gate structure is provided with a bottom surface located below the semiconductor surface. The shallow trench isolation region surrounds the active region. The interconnect layer extends beyond the transistor and is electrically coupled to the transistor at a connection location below the gate structure. The first conductive region includes a lightly doped region, and a top surface of the lightly doped region is aligned with or substantially aligned with an edge of the gate structure. Compared with the prior art, the semiconductor device structure has the advantages that the area of the semiconductor device structure can be reduced, and the gate-induced drain leakage current is relatively low.

Description

Technical Field

[0001] The present invention relates to a semiconductor device structure, and more particularly to a transistor-over-bitline cell (TOB-cell) comprising a capacitor located above a vertical transistor, wherein the vertical transistor is located above an underground bit line to reduce the area of ​​the transistor cell on the bit line, and the transistor cell on the bit line has a lower gate-induced-drain-leakage current (GIDL). Background Art

[0002] In the prior art, one of the most important volatile-memory integrated circuits is a dynamic random access memory (DRAM) using a 1T1C memory cell. The DRAM not only provides the best cost-performance function and serves as a main memory and / or buffer memory for computing and communication applications, but also serves as the best driving force for maintaining Moore's Law by shrinking the minimum feature size on silicon wafers (from a few microns to about 20 nanometers (nm)). Currently, the technology nodes available for the DRAM are above 10 to 12 nanometers, but the technology nodes above 10 to 12 nanometers cannot match the most advanced technology nodes (e.g., 5 nanometers) available in current logic technology, wherein the main problem of the above incompatibility is that it is still difficult to further shrink the structure of the 1T1C memory cell through very aggressive design rules. The very aggressive design rules are used to shrink the access transistor (i.e., 1T) and the three-dimensional (3D) storage capacitor (i.e., 1C) within the 1T1C memory cell, and the three-dimensional storage capacitor is, for example, a stacked capacitor above a portion of the access transistor and above an isolation region, or is, for example, a very deep trench capacitor located below the access transistor.

[0003] The well-known difficulties faced in scaling down the 1T1C memory cell despite the huge investment and R&D in technology, design and equipment are described in detail. Some examples of the well-known difficulties are listed below: (1) The structure of the access transistor suffers from the inevitable and more serious leakage current problem, thereby reducing the storage function of the 1T1C memory cell (e.g., reducing the refresh time of the dynamic random access memory); (2) The complexity of the geometry and surface morphology of the layout of the word line, bit line and storage capacitor and the connection between the word line, the bit line, the storage capacitor and the gate, source and drain of the access transistor become worse and worse when scaling down the dynamic random access memory; (3) The trench capacitor suffers from the problem of too large aspect ratio of the depth of the trench capacitor to the opening size, and the process of the trench capacitor is almost stopped at the 14 nanometer node process; (4) The stack capacitor suffers from worse surface morphology, and after the active region of the access transistor is twisted from 20 degrees to more than 50 degrees, there is almost no space left as the contact space between the storage electrode of the storage capacitor and the source of the access transistor. In addition, the allowable space for the bit line to contact the drain of the access transistor is getting smaller and smaller, but the self-alignment feature must be maintained with difficulty; (5) Unless a high dielectric constant (high-k) insulator material can be found to obtain a higher storage capacitor value, the worsening leakage current problem of the access transistor will require increasing the capacitance of the stack capacitor and continuing to increase the height of the stack capacitor to obtain a larger capacitor area; (6) Because there is no technological breakthrough to solve the above difficulties under the increasingly demanding conditions of higher density / capacity and performance, all the growing demands for better reliability, quality and flexibility of the dynamic random access memory chip are becoming increasingly difficult to meet, etc.

[0004] However, there is no better technology in the prior art to solve the above difficulties, so how to design a new structure of the 1T1C memory cell to solve the above difficulties has become an important issue for designers of the 1T1C memory cell. Summary of the invention

[0005] One embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, an active region, a shallow trench isolation (STI) region and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is located in the semiconductor substrate, wherein the active region includes a transistor, the transistor includes a gate structure, a first conductive region and a second conductive region, and the gate structure has a bottom surface located below the semiconductor surface. The shallow trench isolation (STI) region surrounds the active region. The interconnection layer extends beyond the transistor and electrically couples the transistor at a connection position below the gate structure. The first conductive region includes a lightly doped region, and the top surface of the lightly doped region is aligned or substantially aligned with an edge of the gate structure.

[0006] In one embodiment of the present invention, the interconnection layer is disposed in the shallow trench isolation region and below the semiconductor surface, and the interconnection layer is isolated from the semiconductor substrate.

[0007] In one embodiment of the present invention, the second conductive region includes two sub-regions respectively located on two side walls of the gate structure, and the first conductive region is lower than the second conductive region.

[0008] In an embodiment of the present invention, the transistor further includes two vertical channel regions separated from each other, and the first conductive region is electrically connected to two sub-regions of the second conductive region through the two vertical channel regions.

[0009] In one embodiment of the present invention, the semiconductor device structure further includes a highly doped semiconductor region, wherein the highly doped semiconductor region is adjacent to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the semiconductor surface, and the doping type of the highly doped semiconductor region is different from the doping type of the first conductive region.

[0010] In one embodiment of the present invention, the interconnect layer is coupled to the first conductive region of the transistor at the connection position through a connection contact, or the interconnect layer is directly coupled to the first conductive region at the connection position, wherein the connection contact is a highly doped semiconductor plug.

[0011] In one embodiment of the present invention, the semiconductor device structure further comprises a capacitor, wherein the capacitor is electrically connected to the second conductive region, and the interconnect layer is a bit line electrically connected to the first conductive region.

[0012] In an embodiment of the present invention, the semiconductor device structure further includes a word line, wherein the word line is electrically connected to the gate structure, and the word line passes through the second conductive region.

[0013] In one embodiment of the present invention, the semiconductor device structure further includes a dielectric plug, wherein the dielectric plug is located between the gate structure and the first conductive region.

[0014] In one embodiment of the present invention, the semiconductor device structure further includes a capacitor, wherein the capacitor is electrically connected to the second conductive region, the second conductive region includes two sub-regions respectively located on two side walls of the gate structure, the capacitor includes a storage electrode, and the storage electrode includes two electrode pillars respectively connected to the two sub-regions of the second conductive region.

[0015] In an embodiment of the present invention, a side surface of the interconnection layer is adjacent to a side surface of a connection contact, and the connection contact is directly connected to the first conductive region of the transistor.

[0016] In one embodiment of the present invention, the interconnect layer extends along the shallow trench isolation region and is located below the semiconductor surface.

[0017] In one embodiment of the present invention, the shallow trench isolation region includes a first spacer layer and a second spacer layer, the first spacer layer is in contact with the active region, the second spacer layer is in contact with another active region, the material of the first spacer layer is different from the material of the second spacer layer, and the shallow trench isolation region is located between the active region and the another active region.

[0018] In an embodiment of the present invention, a side surface of the interconnection layer is adjacent to a side surface of the first conductive region of the transistor.

[0019] In one embodiment of the present invention, the semiconductor device structure further includes a capacitor, wherein the capacitor is electrically connected to the second conductive region, the second conductive region includes two sub-regions respectively located on the two side walls of the gate structure, the capacitor includes a storage electrode, and the storage electrode includes two electrode columns respectively connected to the two sub-regions of the second conductive region, wherein the two electrode columns are epitaxial layers.

[0020] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, an active region, a shallow trench isolation region and a transistor. The semiconductor substrate has a semiconductor surface. The shallow trench isolation region surrounds the active region. The transistor is located in the active region, and the transistor includes a gate structure, a first conductive region and a second conductive region. The second conductive region is above the first conductive region and includes two sub-regions respectively located on the two side walls of the gate structure. The first conductive region includes a lightly doped region, and the top surface of the lightly doped region is aligned or substantially aligned with an edge of the gate structure.

[0021] In an embodiment of the present invention, the transistor further includes two vertical channel regions separated from each other, and the first conductive region is electrically connected to two sub-regions of the second conductive region through the two vertical channel regions.

[0022] In one embodiment of the present invention, the semiconductor device structure further includes a capacitor, wherein the capacitor is electrically connected to each of the two sub-regions of the second conductive region, and the capacitor includes two electrode columns respectively connected to the two sub-regions of the second conductive region.

[0023] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a semiconductor bulk substrate, an active region, a shallow trench isolation region, and an interconnection layer. The semiconductor bulk substrate has an original surface. The active region is located in the semiconductor bulk substrate, wherein the active region includes a plurality of transistors, and each transistor includes a gate structure, a first conductive region, and a second conductive region, wherein the gate structure has a bottom surface located below the original surface, and the first conductive region is coupled to the semiconductor bulk substrate. The shallow trench isolation region surrounds the active region. The interconnection layer extends beyond at least one transistor of the plurality of transistors and is electrically coupled to the at least one transistor at a connection position below the gate structure of the at least one transistor. The first conductive region of the at least one transistor includes a lightly doped region and a highly doped region, the lightly doped region surrounds the highly doped region, and the top surface of the lightly doped region is aligned or substantially aligned with an edge of the gate structure of the at least one transistor.

[0024] In one embodiment of the present invention, the interconnect layer is a bit line, and the interconnect layer extends beyond the plurality of transistors and electrically couples each transistor at a connection location under a gate structure of each transistor.

[0025] In one embodiment of the present invention, the interconnection layer is arranged in the shallow trench isolation region and is located below the original surface, the interconnection layer is isolated from the semiconductor body substrate, and the first conductive region of the at least one transistor is directly or indirectly connected to a side wall of the interconnection layer.

[0026] In one embodiment of the present invention, the at least one transistor further includes two vertical channel regions separated from each other, and the first conductive region of the at least one transistor is electrically connected to two sub-regions of the second conductive region of the at least one transistor through the two vertical channel regions, wherein the semiconductor device structure further includes a highly doped semiconductor region, the highly doped semiconductor region is adjacent to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface, and the doping type of the highly doped semiconductor region is different from the doping type of the first conductive region of the at least one transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A The present invention is a flowchart of a method for manufacturing a bit line transistor cell (1T1C cell) array according to an embodiment of the present invention.

[0028] Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H Yes Description Figure 1A Schematic diagram of .

[0029] Figure 2 It is a schematic diagram illustrating a top view and a cross-sectional view along the X direction after depositing a pad nitride layer and a pad oxide layer and forming a shallow trench isolation.

[0030] Figure 3 Schematic diagram illustrating the deposition and etching back of the nitride layer-1 to form a nitride spacer layer-1, and the deposition of a spin-on dielectric layer and a photoresist layer.

[0031] Figure 4 Schematic diagram of etching away the upper edge nitride spacer layer-1 and the spin-coated dielectric layer not covered by the photoresist layer.

[0032] Figure 5 Schematic diagram illustrating the stripping of the photoresist layer and the spin coating of the dielectric to form an oxide layer-1.

[0033] Figure 6 is a schematic diagram illustrating a metal layer deposited in a trench and planarized by the chemical mechanical polishing technique.

[0034] Figure 7is a schematic diagram illustrating the deposition of a photoresist layer and the etching of a metal layer corresponding to the end of the active region.

[0035] Figure 8 FIG. 1 is a schematic diagram illustrating the removal of the photoresist layer and etching back the metal layer to form a subsurface bit line.

[0036] Fig. 9 is a schematic diagram illustrating deposition of oxide layer-2 in the trench.

[0037] Fig.10 It is a schematic diagram illustrating depositing an oxide layer-3, a nitride layer-2 and a photoresist layer, and then removing unnecessary portions of the oxide layer-3, the nitride layer-2 and the photoresist layer.

[0038] Fig.11 The invention is a schematic diagram illustrating the removal of a photoresist layer, a pad nitride layer and a pad oxide layer to expose a planar surface.

[0039] Fig.12 Schematic diagram for explaining the formation of a groove and the formation of an oxide spacer-1 and a nitride spacer-1.

[0040] Fig.13 Schematic diagram of removing exposed silicon in the groove to form a trench hole and an oxidation spacer layer-2 and a nitride spacer layer-2.

[0041] Fig.14 The schematic diagram is for explaining the removal of silicon exposed in the trench hole and the thermal generation of thermal oxide to expose the sidewall of the bit line under the surface, and the deposition of in-situ doped n+ polysilicon.

[0042] Fig.15 is a schematic diagram illustrating the removal of in-situ doped n+ polysilicon and thermal oxide, the growth of an (N+) drain region, and the thermal generation of an oxide plug in the trench region.

[0043] Fig.16 is a schematic diagram illustrating the removal of oxide spacer-2, thermal growth of thermal oxide, and deposition, planarization, and etching back of titanium nitride and tungsten layers.

[0044] Fig.17 is a schematic diagram illustrating the deposition of a nitride layer, followed by the deposition and etching of an oxide layer.

[0045] Fig.18 It is a schematic diagram illustrating the etching of the nitride layer and the oxide layer, and the growth of the n-type lightly doped drain.

[0046] Fig.19 is a schematic diagram illustrating depositing an oxide layer, creating an outdiffusion region, and etching away oxide layer-3, nitride layer-2, pad nitride layer, and pad oxide layer to form a recess.

[0047] Fig. 20is a schematic diagram illustrating forming an oxide spacer-3 and a nitride spacer-3, and anisotropically etching the exposed silicon to form a deep trench.

[0048] Fig.21 is a schematic diagram illustrating the growth of an in-situ doped p-type silicon layer and the growth of a thermal oxide to completely fill the trench.

[0049] Fig. 22 It is to illustrate the growth of a vertical layer, the formation of a high dielectric constant dielectric layer as a storage node insulator on the vertical layer, and the formation of a conductive layer (Si x Ge 1-x ) as a schematic diagram of the common electrode of the capacitor.

[0050] Fig.23 It is a flow chart of a method for manufacturing a transistor-on-bit-line cell (TOB-cell) array disclosed in a second embodiment of the present invention.

[0051] Fig.24 and Fig.25 is a schematic diagram illustrating drains of vertical transistors forming the transistor cell array on the bit line.

[0052] Fig.26 , Fig. 27 , Fig.28 and Fig.29 is a schematic diagram illustrating a gate structure and a word line of a vertical transistor forming the transistor cell array on the bit line.

[0053] Fig.30 is a schematic diagram illustrating sources of vertical transistors forming the transistor cell array on the bit line.

[0054] Fig.31 and Fig.32 is a schematic diagram illustrating a capacitor tower above a vertical transistor forming the transistor cell array on the bit line.

[0055] The reference numerals are described as follows:

[0056] 202 substrate

[0057] 204 Pad Oxide Layer

[0058] 206 pad nitride layer

[0059] 208 Plane Surface

[0060] 210 Groove

[0061] 214, 1704, 1902, 2604, 2904, 3102 oxide layer

[0062] 304 Spin-on Dielectric

[0063] 306, 702, 1106 photoresist layer

[0064] 502 Oxide Layer-1

[0065] 602 Metal Layer

[0066] 902, UGBL Subsurface Bit Line

[0067] 1002, CVD-STI-Oxide2 Oxide layer-2

[0068] 1102 Oxide layer-3

[0069] 1104 Nitride layer-2

[0070] 1202, 1904, 3104 grooves

[0071] 1204 Oxidation Spacer-1

[0072] 1206 Nitrided spacer-1

[0073] 1302 slot hole

[0074] 1304 Oxidation Spacer-2

[0075] 1306 Nitrided spacer-2

[0076] 1402, 1602, 2104 thermal oxide

[0077] 1404 In-situ doping of n+ polysilicon

[0078] 1502, 2401 (N+) drain region

[0079] 1504 Oxide Pin

[0080] 1604, 2802 Titanium nitride layer

[0081] 1606, 2804 Tungsten layer

[0082] 1702, 2902 Nitride layer

[0083] 1801, 3002 Silicon sidewall

[0084] 1802, 3004 n-type lightly doped drain

[0085] 2002 Oxidation Spacer-3

[0086] 2004 Nitrided spacer-3

[0087] 2102 In-situ doping of p-type silicon layer

[0088] 2202 Vertical Layer

[0089] 2204 High dielectric constant dielectric layer

[0090] 2206 Conductive layer

[0091] OSS Original Silicon Surface

[0092] STI Shallow Trench Isolation

[0093] 2402 Vertical Nitride Spacer

[0094] 2502 In-situ doping of n-type lightly doped drain

[0095] 2602 In-situ doping of N+ silicon region

[0096] 2702 Thermal Oxide Layer

[0097] 2704 High-k gate dielectric layer

[0098] 10-50, 102-176, 2302-2320 steps DETAILED DESCRIPTION

[0099] The present invention provides a very compact 1T1C dynamic random access memory (DRAM) cell structure by using a unique three-dimensional fabrication method to stack a transistor (1T) and a capacitor (1C) in a dynamic random access memory (DRAM) cell structure in a very compact plane. A major inventive feature of the present invention is that the access transistor (i.e., 1T) is located above the underground bit line (UGBL) structure, so the new dynamic random access memory cell structure is named as a transistor-over-bitline cell (TOB-cell). In addition, another major inventive feature of the present invention is that the fabrication method of the dynamic random access memory cell structure relies on only a few processing steps that require advanced photolithography and exposure tools, but the most critical processing steps rely on the use of novel self-alignment and / or self-structuring processing methods to enable the bit line transistor cell to have a high degree of miniaturization capability, for example, the bit line transistor cell can be reduced to a cell area of ​​4.5x 2.5F (or 5x 2.5F), wherein the minimum feature size F has been developed down to about 6 nanometers (nm) range.

[0100] In order to focus on the invention of the bit line transistor unit and its main inventive features, the following manufacturing method only focuses on the specific construction of the 1T1C unit (that is, the bit line transistor unit), without detailing the formation of the entire dynamic random access memory unit chip, and the formation of the entire dynamic random access memory unit chip should include other additional processes to form the peripheral circuits of the entire dynamic random access memory unit chip.

[0101] First embodiment

[0102] Please refer to the following Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1H ,in Figure 1A The present invention is a flowchart of a method for manufacturing a transistor-on-bit-line cell (TOB-cell) array according to an embodiment of the present invention.

[0103] Step 10: Start;

[0104] Step 15: On a substrate (e.g., a p-type silicon substrate), define an active region of the transistor cell array on the bit line and form a shallow trench isolation (STI).

[0105] STI);

[0106] Step 20: forming an asymmetric spacer layer along the sidewall of the active region;

[0107] Step 25: forming a subsurface conductive line (eg, a bit line) between the asymmetric spacer layers and below an original silicon surface (OSS);

[0108] Step 30: forming a drain region of an access transistor of the transistor cell array on the bit line and a connection between the subsurface bit line and the drain region of the access transistor of the transistor cell array on the bit line;

[0109] Step 35: forming gates of access transistors of the transistor cell array on the word lines and the bit lines;

[0110] Step 40: forming a source region of an access transistor of the transistor cell array on the bit line;

[0111] Step 45: forming a capacitor on the access transistor;

[0112] Step 50: End.

[0113] Please refer to Figure 1B and Figure 2 , step 15 comprises:

[0114] Step 102: thermally generate a pad oxide layer 204 on the planar surface 208 of the substrate, and deposit a pad nitride layer 206 on the pad oxide layer 204 ( Figure 2 );

[0115] Step 104: define an active region of the transistor cell array on the bit line, and remove the substrate material (eg, silicon material) corresponding to the planar surface 208 outside the active region to form a trench 210 ( Figure 2 );

[0116] Step 106 : Deposit and etch back an oxide layer 214 in the trench 210 to form the shallow trench isolation (STI) below the planar surface 208 .

[0117] Please refer to Figure 1C , Figure 3 , Figure 4 , Figure 5 , step 20 comprises:

[0118] Step 108: Deposit and etch back a nitride layer-1 to form a nitride spacer-1 ( Figure 3 );

[0119] Step 110: Deposit spin-on dielectrics (SOD) 304 in the trench 210 and planarize by chemical mechanical polishing (CMP) technology. Figure 3 );

[0120] Step 112: Deposit a photoresist layer 306 over the spin-on dielectric 304 and the pad nitride layer 206 ( Figure 3 );

[0121] Step 114: Etch away the upper edge nitride spacer layer-1 and the spin-on dielectric 304 that are not covered by the photoresist layer 306 ( Figure 4 );

[0122] Step 116: Stripping the photoresist layer 306 and the spin-on dielectric 304, and growing (eg, thermally growing) an oxide layer-1

[0123] 502( Figure 5 ).

[0124] Please refer to Figure 1D , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , step 25 comprises:

[0125] Step 118: Deposit a metal layer 602 in the trench 210 and planarize it by chemical mechanical polishing ( Figure 6 );

[0126] Step 120: Deposit and pattern a photoresist layer 702 ( Figure 7 );

[0127] Step 122: Etch the metal layer 602 corresponding to the end of the active region to form a plurality of conductive lines ( Figure 7 ); Step 124: remove the photoresist layer 702 and etch back the metal layer 602 (the plurality of conductive lines) to form an underground bit line (UGBL) 902 or an underground conductive line ( Figure 8 );

[0128] Step 126: Deposit an oxide layer-2 1002 in the trench 210 and planarize it by chemical mechanical polishing ( Fig. 9 ).

[0129] Please refer to Figure 1E , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 Step 30 includes: Step 128: depositing an oxide layer-3 1102, a nitride layer-2 1104, and a patterned photoresist layer 1106,

[0130] Then, unnecessary portions of the oxide layer-3 1102 and the nitride layer-2 1104 are etched away ( Fig.10 ); Step 130: remove the patterned photoresist layer 1106, the pad nitride layer 206, and the pad oxide layer 204,

[0131] and exposing the planar surface 208 ( Fig.11 );

[0132] Step 132: Dig the exposed planar surface 208 to form a groove 1202 ( Fig.12 );

[0133] Step 134: first forming an oxide spacer-1 1204 along the edge of the groove 1202, and then forming a nitride spacer-1 1206 ( Fig.12 );

[0134] Step 136: Remove the exposed silicon in the groove 1202 downward in a straight vertical shape to form a trench hole 1302 ( Fig.13 );

[0135] Step 138: First, an oxide spacer 2 1304 is formed along the edge of the trench hole 1302, and then a nitride spacer 2 1306 is formed ( Fig.13 );

[0136] Step 140: Remove the exposed silicon in the trench hole 1302 and thermally generate thermal oxide 1402 ( Fig.14 );

[0137] Step 142: Remove the lower edge nitride spacer-1 on the sidewall of the subsurface bit line to expose the sidewall of the subsurface bit line, and deposit in-situ doped n+ polysilicon 1404 in the trench to connect the exposed sidewall of the subsurface bit line ( Fig.14 );

[0138] Step 144: Remove the in-situ doped n+ polysilicon 1404 and thermal oxide 1402 ( Fig.15 );

[0139] Step 146: Use selective epitaxy growth (SEG) technology to grow (N+) drain region 1502 ( Fig.15 );

[0140] Step 148: Thermally generate oxide plugs 1504 in the trench region ( Fig.15 );

[0141] Please refer to Figure 1F and Fig.16 , step 35 comprises:

[0142] Step 150: Remove the oxide spacer layer-2 1304 ( Fig.16 );

[0143] Step 152: Thermally generate thermal oxide 1602 ( Fig.16 );

[0144] Step 154: depositing a titanium nitride layer 1604 and a tungsten layer 1606, and then etching back the titanium nitride layer 1604 and the tungsten layer 1606 ( Fig.16 );

[0145] Please refer to Figure 1G , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , step 40 comprises:

[0146] Step 156: Deposit a nitride layer 1702, then deposit and etch an oxide layer 1704 ( Fig.17 );

[0147] Step 158: Etching portions of the nitride layer 1702 and the oxide layer 1704 to expose the silicon sidewall 1801 near and below the OSS, and growing an n-type lightly doped drain (LDD) 1802 through the exposed silicon sidewall 1801 using the selective epitaxial growth (SEG) technique. Fig.18 );

[0148] Step 160: Deposit the oxide layer 1902, and use the chemical mechanical polishing technique to make the flat surface of the oxide layer 1902 flush with the surface of the nitride layer-2 1104 ( Fig.19 , please also refer to Fig.18 ); Step 162: Use rapid thermal annealing (RTA) to create an outer diffusion region for the source region and drain region grown above ( Fig.19 );

[0149] Step 164: Etch away the oxide layer-3 1102, the nitride layer-2 1104, the pad nitride layer 206 and the pad oxide layer 204 to form a groove 1904 next to the oxide layer 1902 and expose the OSS ( Fig.19 , please also refer to Fig.18 );

[0150] Step 166: Form an oxide spacer-3 2002 and a nitride spacer-3 2004 ( Fig. 20 );

[0151] Step 168: Based on the oxide spacer-3 2002 and the nitride spacer-3 2004, anisotropically etch the exposed silicon to form a deep trench 2006 ( Fig. 20 );

[0152] Please refer to Figure 1H , Fig.21 , Fig. 22 , step 45 comprises:

[0153] Step 170: Grow a thin in-situ doped p-type silicon layer 2102 ( Fig.21 );

[0154] Step 172: Grow thermal oxide 2104 to completely fill the trench ( Fig.21 );

[0155] Step 174, remove the oxide spacer-3 2002, the nitride spacer-3 2004, the oxide spacer-1 1204 and the nitride spacer-1 1206, and then use the selective epitaxial growth technology to grow the vertical layer 2202 ( Fig. 22 );

[0156] Step 176: Form a high-k dielectric layer 2204 on the vertical layer 2202 as a storage node insulator, and then form a conductive layer (e.g., Si x Ge 1-x )2206 as the common electrode of the capacitor ( Fig. 22 ).

[0157] The above manufacturing method is described in detail as follows. The above manufacturing method starts from a p-type silicon wafer (i.e., a p-type substrate 202), wherein in another embodiment of the present invention, the present invention can start from a p-type well in a three-well structure of a complementary metal oxide semiconductor (CMOS) process, so that the substrate can be biased at a negative voltage.

[0158] In step 102, if Figure 2 As shown in (a), a pad oxide layer 204 is thermally generated above a planar surface 208, and then a pad nitride layer 206 is deposited above the pad oxide layer 204, wherein if the substrate is a silicon substrate, the planar surface 208 is also called a horizontal silicon surface (HSS) or an original silicon surface (OSS), and the subsequent drawings are described using the planar surface 208 or OSS as an example.

[0159] In step 104, an active region of the transistor cell array on the bit line may be defined by photolithographic technique, wherein Figure 2 As shown in (a), since the pad nitride layer 206 is used as a mask, the active region of the transistor cell array on the bit line corresponds to the pad oxide layer 204 and the pad nitride layer 206, and the plane surface 208 outside the pad nitride layer 206 is exposed. Since the plane surface 208 outside the pad nitride layer 206 is exposed, the silicon material corresponding to the plane surface 208 outside the pad nitride layer 206 can be removed by anisotropic etching technology to produce a trench (or recess) 210, wherein, for example, the trench 210 can reach a depth of 300-350 nanometers below the plane surface 208.

[0160] In step 106, an oxide layer 214 is deposited to fill the trench 210, and then the oxide layer 214 is etched back to form the shallow trench isolation below the planar surface 208 in the trench 210. In addition, Figure 2 (b) corresponds to Figure 2 (a) is a top view, where Figure 2 (a) is along the Figure 2 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0161] In step 108, if Figure 3 As shown in (a), the nitride layer-1 is deposited and the nitride layer-1 is etched back using the anisotropic etching technology to form the nitride spacer-1 along the two edges (i.e., the upper edge and the lower edge) of the trench 210. In another embodiment of the present invention, the nitride spacer-1 can be replaced by silicon oxycarbon nitride (SiOCN) as a spacer on one side.

[0162] In step 110, if Figure 3 As shown in (a), a spin-on dielectric 304 is deposited on the shallow trench isolation in the trench 210 to fill the trench 210. The spin-on dielectric 304 is then planarized by the chemical mechanical polishing technique to make the top of the spin-on dielectric 304 flush with the top of the pad nitride layer 206.

[0163] In step 112, if Figure 3 As shown in (a), the lower edge of the nitride spacer-1 along the lower edge of the groove 210 is protected by the photoresist layer 306, but the upper edge of the nitride spacer-1 along the upper edge of the groove 210 is not protected by the photoresist layer 306. That is to say, after the photoresist layer 306 is deposited on the spin-on dielectric 304 and the pad nitride layer 206, because the photoresist layer 306 on the upper edge nitride spacer-1 is removed but the photoresist layer 306 on the lower edge nitride spacer-1 is retained, the lower edge nitride spacer-1 can be retained but the upper edge nitride spacer-1 will be removed. In addition, Figure 3 (b) corresponds to Figure 3 (a) is a top view, where Figure 3 (a) is along the Figure 3 (b) is a cross-sectional view of the cutting line in the Y direction shown in FIG. Figure 4 As shown, the upper edge nitride spacer layer-1 and the spin-on dielectric 304 not covered by the photoresist layer 306 may be etched away by an isotropic etching technique.

[0164] In step 116, if Figure 5As shown, the photoresist layer 306 and the spin-on dielectric 304 are stripped, wherein the spin-on dielectric 304 has a much higher etching rate than the thermally generated oxide layer and the deposited oxide layer. Then the oxide layer-1 502 is thermally generated to form an oxide spacer-1, wherein the oxide spacer-1 covers the upper edge of the trench 210, and the oxide layer-1 502 does not grow beyond the pad nitride layer 206. Figure 5 As shown, step 116 results in the formation of asymmetric spacers (i.e., the lower edge nitride spacer-1 and the oxide spacer-1) at two symmetrical edges of the trench 210 (i.e., the upper edge and the lower edge of the trench 210). For example, the thickness of the oxide spacer-1 is about 1 nanometer and the thickness of the lower edge nitride spacer-1 is about 1 to 1.5 nanometers. Figure 5 The structure of the present invention and the above-mentioned related steps are a main technical feature of the present invention, which is called asymmetric spacers on two symmetrical edges of a trench or a concave (ASoSE).

[0165] In step 118, if Figure 6 As shown, a metal layer 602 (or a conductive material that needs to withstand subsequent process conditions (e.g., doped polysilicon)) is deposited to fill the trench 210 and planarized by the chemical mechanical polishing technique so that the top of the metal layer 602 is flush with the top of the pad nitride layer 206 (e.g., Figure 6 In addition, in one embodiment of the present invention, the metal layer 602 may be a thin titanium nitride layer plus tungsten. Figure 4 , Figure 5 , Figure 6 It is along the Figure 3 (b) is a cross-sectional view taken along the cutting line in the Y direction.

[0166] In step 120, if Figure 7 As shown, a photoresist layer 702 is deposited to cover the lower edge nitride spacer layer-1 and the oxidized spacer layer-1, but expose the lower edge nitride spacer layer-1 and the oxidized spacer layer-1 corresponding to the two edges of the end of the active region. Then in step 122, as shown in FIG. Figure 7 As shown, the metal layer 602 corresponding to the end of the active region is etched to separate the plurality of conductive lines (ie, the metal layer 602 ).

[0167] In step 124, if Figure 8As shown in (a), after removing the photoresist layer 702, the metal layer 602 in the trench 210 is etched back to a reasonable thickness to form a subsurface bit line (or subsurface conductive line) 902, wherein the top of the subsurface bit line 902 is much lower than the planar surface 208 (for example, the thickness of the subsurface bit line 902 is about 40 nanometers). Figure 8 As shown in (a), the subsurface bit line 902 is located on the top of the shallow trench isolation and the two side walls of the subsurface bit line 902 are respectively restricted by the asymmetric spacer layer (that is, the lower edge nitride spacer layer-1 and the oxidation spacer layer-1). In addition, Figure 8 (a) is along the Figure 8 (b) is a cross-sectional view taken along the cutting line in the Y direction.

[0168] In step 126, if Fig. 9 (Along as Figure 8 As shown in (b) of the cross-sectional view of the cutting line in the Y direction, the oxide layer-2 1002 (also called CVD-STI-oxide2) needs to have a sufficient thickness to fill the trench 210 above the bit line 902 below the surface, and then the oxide layer-2 1002 is polished by the chemical mechanical polishing technology to retain a portion of the oxide layer-2 1002, wherein the top of the retained portion of the oxide layer-2 1002 is flush with the top of the pad nitride layer 206, and covers the lower edge nitride spacer-1 and the oxide spacer-1. Fig. 9 As shown, step 126 can make the subsurface bit line 902 (that is, the interconnection wire) embedded in all insulators (that is, an isolation region) in the trench 210 and confined by all the insulators (the subsurface bit line 902 will then be connected to the drain of the access transistor of the transistor cell array on the bit line), wherein Fig. 9 The structure shown is called an insulator-surrounded subsurface bit line, and the subsurface bit line 902 (UGBL) is another main technical feature of the present invention.

[0169] In step 128, if Fig.10As shown in (a), first, an oxide layer-3 1102, a nitride layer-2 1104, and a patterned photoresist layer 1106 are deposited. Then, unnecessary portions of the oxide layer-3 1102 and the nitride layer-2 1104 are removed using etching technology. In addition, a transistor / word line pattern can be defined by a composite layer composed of the oxide layer-3 1102 and the nitride layer-2 1104, wherein the composite layer composed of the oxide layer-3 1102 and the nitride layer-2 1104 is composed of a plurality of strip-shaped oxide layers-3 1102 and nitride layers-2 1104 in a direction perpendicular to the active region direction, and for example, if the transistor unit on the bit line is designed under the condition that the minimum feature size F is approximately 6nm, the width of a single transistor / word line pattern can be 1.5 to 2F. Therefore, if Fig.10 (a) and Fig.10 As shown in (b), longitudinal (the Y direction) stripes (composed of oxide layer-3 1102 and nitride layer-2 1104) for defining the access transistor and the word line, and a cross-point square for defining the active region will be formed, wherein the active region is the cross-point square located between the two longitudinal stripes, and Fig.10 (a) is along the Fig.10 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0170] like Fig.10 As shown in (b), Fig.10 The top view shown in (b) shows a fabric-like checkerboard pattern with longitudinal stripes of oxide-3 1102 and nitride-2 1104 above the pad nitride layer 206 and the pad oxide layer 204, and also shows the fabric-like checkerboard pattern in the horizontal direction (i.e., as shown in FIG. Fig.10 (b) in the X direction) of the active region and the shallow trench isolation. Fig.11 As shown in (b), the active region allows the access transistor to be formed by a self-alignment technique. This fabric-like checkerboard pattern of the self-aligned structure for manufacturing the gate structure of the access transistor and the word line in one process step is another main technical feature of the present invention.

[0171] In step 130, if Fig.11 As shown in (a), the photoresist layer 1106 is retained to etch away the pad nitride layer 206, but the pad oxide layer 204 is retained, and as shown in Fig.11As shown in (b), the photoresist layer 1106 and the pad oxide layer 204 are removed by an etching technique (e.g., a reactive ion etching process (RIE)). As a result, the planar surface 208 (ie, OSS) is exposed as shown in FIG. Fig.11 (b) The cross-point square area shown in FIG. 1 , wherein the cross-point square area corresponds to the active area (located at Fig.10 (a) and Fig.10 (b) shows the intersection point square). In addition, Fig.11 (a) and Fig.11 (b) is along Fig.10 (b) A cross-sectional view along the cutting line in the X direction as shown.

[0172] In step 132, if Fig.12 As shown in (a), the OSS exposed by the square area of ​​the intersection (that is, the exposed plane surface 208) is excavated by the anisotropic etching technique to form a groove 1202, wherein the groove 1202 subsequently becomes a region containing a gate structure of an access transistor and can extend downward to a certain distance below the original silicon surface of the OSS (for example, about 6 to 8 nm below the OSS). In addition, the shallow trench isolation (for example, about 5 nm in depth) is excavated by the anisotropic etching technique to form a pipe-shaped groove (along the Figure 8 (b) in the Y direction for word line interconnection in a subsequent local area, wherein the depth of the pipe-shaped groove (eg, about 5 nm) is shallower than the depth of the groove 1202 (eg, about 6 nm). Fig.12 (a) is along Fig.12 (a) is a cross-sectional view taken along the X direction.

[0173] In step 134, if Fig.12 As shown in (a), an oxide spacer-1 1204 is first formed along the edge of the groove 1202, and then a nitride spacer-1 1206 is formed. As an example, the sum of the width of the oxide spacer-1 1204 and the width of the nitride spacer-1 1206 may be about 2.5 nm, wherein the sum of the width of the oxide spacer-1 1204 and the width of the nitride spacer-1 1206 is crucial because the silicon below the oxide spacer-1 1204 and the nitride spacer-1 1206 will be used as the channel region of the access transistor to be formed later.

[0174] In step 136, if Fig.13As shown in (a), the nitride spacer layer-1 1206 is used as a mask, and the anisotropic etching technology is used to remove the exposed silicon in the groove 1202 in a straight vertical shape to form a trench hole 1302 (for example, the depth of the trench hole 1302 is about 70nm). In addition, the anisotropic etching technology is used to dig the shallow trench isolation (for example, about 50nm deep) to form a pipe-shaped groove (along the Figure 8 (b) is used for word line interconnection in subsequent local areas.

[0175] In step 138, if Fig.13 As shown in (a), an oxide spacer-2 1304 is first formed along the edge of the trench hole 1302, and then a nitride spacer-2 1306 is formed. Here, for example, the sum of the width of the oxide spacer-2 1304 and the width of the nitride spacer-2 1306 can be about 1.5 nm. In addition, Fig.13 (a) is along Fig.13 (a) is a cross-sectional view taken along the X direction.

[0176] In step 140, if Fig.14 As shown in (a), the nitride spacer-2 1306 is used as a mask, and the anisotropic etching technology is used to further remove the silicon exposed in the trench hole 1302 to form a trench region, wherein the depth of the trench region is about 50nm, for example. Then, thermal oxide 1402 is thermally generated around the sidewall and bottom of the trench region. In one embodiment of the present invention, Fig.14 As shown in (a), the trench region in the active region is adjacent to an under-surface bit line (UGBL) located in a shallow trench isolation region surrounding the active region.

[0177] In step 142, if Fig.14 (a) shows that the subsurface bit line is removed (see Fig. 9 ) on the sidewall of the lower edge of the nitrided spacer-1 to expose the sidewall of the bit line below the surface, and the nitrided spacer-2 1306 is also removed. Then, as Fig.14 As shown in (a), in-situ doped n+ polysilicon 1404 is deposited to fill the trench region. In one embodiment of the present invention, the in-situ doped n+ polysilicon 1404 will connect the exposed sidewalls of the subsurface bit lines. In addition, Fig.14 (a) is along Fig.14 (b) is a cross-sectional view taken along the X direction.

[0178] In step 144, if Fig.15As shown in (a), the isotropic etching technique is used to remove the in-situ doped n+ polysilicon 1404 and the thermal oxide 1402 for subsequent formation of the drain region of the access transistor. In step 144, due to the protection of the spacer layer (e.g., the oxide spacer layer-1 1204, the nitride spacer layer-1 1206 or the oxide spacer layer-2 1304), the portion of the in-situ doped n+ polysilicon 1404 connected to the exposed sidewall of the subsurface bit line will be retained and play the role of an underground bitline connector (UBC).

[0179] In step 146, if Fig.15 As shown in (a), the selective epitaxial growth technique is used to grow a thin layer (e.g., about 10 nm) of n+ in-situ doped polysilicon to form an (N+) drain region 1502 above the subsurface bit line connector (UBC), wherein because the subsurface bit line connector also uses in-situ doped n+ polysilicon, it is ensured that the (N+) drain region 1502 and the subsurface bit line connector can be well connected.

[0180] In another embodiment of the present invention, in step 142, as Fig.14 As shown in (a), the subsurface bit lines are first removed (see Fig. 9 ) on the sidewalls to expose the sidewalls of the subsurface bit lines. Then, there is no need to deposit in-situ doped n+ polysilicon 1404 to fill the trench area, but only to use etching technology to remove the thermal oxide 1402 to expose the sidewalls and bottom surface of the silicon, wherein the exposed sidewalls and bottom surface of the silicon can serve as the substrate for the selective epitaxial growth (SEG) technology. Thereafter, the selective epitaxial growth technology is used to grow a thin layer (e.g., about 10 nm) of n+ in-situ doped polysilicon to form the (N+) drain region 1502, and then the (N+) drain region 1502 can be directly connected to the exposed sidewalls of the subsurface bit lines. Since the (N+) drain region 1502 is automatically connected to the sidewalls of the subsurface bit lines, there is no need to form another connecting pin between the (N+) drain region 1502 and the subsurface bit lines.

[0181] In step 148, if Fig.15 As shown in (a), an oxide plug 1504 is then thermally generated in the trench region. In addition, Fig.15 (a) is along Fig.15 (b) is a cross-sectional view taken along the X direction.

[0182] Next, a description is given of how to form the local word lines and the gate structure of the access transistor. In step 150, as shown in FIG. Fig.16As shown in (a), the oxide spacer-2 1304 is then removed to expose the silicon region for the channel region of the access transistor.

[0183] In step 152, if Fig.16 As shown in (a), a thermal oxide 1602 is thermally grown on the exposed silicon region, wherein the thermal oxide 1602 can serve as a dielectric layer of the access transistor, and the dielectric layer of the access transistor can also be any other high-K composite gate insulator.

[0184] In step 154, if Fig.16 As shown in (a), a titanium nitride layer 1604 is first deposited, and then a tungsten layer 1606 is deposited to form the gate structure and the local word line that are automatically connected. The titanium nitride layer 1604 and the tungsten layer 1606 are then etched back until the top surface of the titanium nitride layer 1604 / tungsten layer 1606 is lower than the OSS (e.g., about 5 nm lower than the OSS). In addition, Fig.16 (a) is along Fig.16 (b) is a cross-sectional view taken along the X direction.

[0185] In step 156, if Fig.17 As shown in (a), a nitride layer 1702 is deposited (wherein the nitride layer 1702 is used to protect the titanium nitride layer 1604 / tungsten layer 1606 from being degraded by contact with any oxide material), and then an oxide layer 1704 is deposited. Then, an etching method is used to remove part of the oxide layer 1704 to retain the gate structure and the composite structure with a capping layer above the local word line, wherein the capping layer is composed of the oxide layer 1704 and the nitride layer 1702. In addition, Fig.17 (a) is along Fig.17 (a) is a cross-sectional view taken along the X direction.

[0186] In step 158, if Fig.18 As shown in (a), the nitride layer 1702 and the oxide layer 1704 are then etched to expose the silicon sidewall 1801 near and below the OSS. Then, an n-type lightly doped drain (LDD) 1802 having single crystal silicon is grown through the exposed silicon sidewall 1801 using the selective epitaxial growth (SEG) technique. In addition, Fig.18 (a) is along Fig.18 (b) is a cross-sectional view taken along the X direction.

[0187] In step 160, if Fig.19 As shown in (a), an oxide layer 1902 is first deposited to fill the trench above the gate structure, and then the chemical mechanical polishing technology is used to make the flat surface of the oxide layer 1902 and the surface of the nitride layer-2 1104 flush.

[0188] In step 162, if Fig.19 As shown in (a), a rapid thermal annealing is then used to establish the outdiffusion region for the n-type lightly doped drain 1802 and the (N+) drain region 1502. In one embodiment of the present invention, the outdiffusion region of the n-type lightly doped drain 1802 will be aligned with the top surface of the titanium nitride layer 1604 or the tungsten layer 1606, and the outdiffusion region of the (N+) drain region 1502 will be aligned with the bottom surface of the titanium nitride layer 1604 or the tungsten layer 1606.

[0189] In step 164, if Fig.19 As shown in (a), the oxide layer-3 1102, the nitride layer-2 1102, the pad nitride layer 206 and the pad oxide layer 204 between the oxide layers 1902 are further etched away to form a groove 1904 and expose the OSS. In addition, Fig.19 (a) is along Fig.19 (b) is a cross-sectional view taken along the X direction.

[0190] In step 166, if Fig. 20 As shown in (a), an oxide spacer-3 2002 and a nitride spacer-3 2004 are then formed on the sidewalls of the recess 1904, wherein the thickness of the oxide spacer-3 2002 and the nitride spacer-3 2004 must be thick enough to cover the n-type lightly doped drain 1802 and the outer diffusion region of the (N+) drain region 1502.

[0191] In step 168, if Fig. 20 As shown in (a), on the basis of the oxidation spacer-3 2002 and the nitride spacer-3 2004, the silicon exposed in the recess 1904 is anisotropically etched to form a deep trench 2006. In addition, Fig. 20 (a) is along Fig. 20 (b) is a cross-sectional view taken along the X direction.

[0192] In step 170, if Fig.21As shown, the selective epitaxial growth technique is then used to grow an in-situ doped p-type silicon layer 2102 (where, for example, the in-situ doped p-type silicon layer 2102 may be an in-situ heavily doped p-type single crystal silicon layer), wherein the doping type of the in-situ doped p-type silicon layer 2102 is different from the doping type of the drain region / source region. The purpose of step 170 is to form an additional p-type connection to the p-type body of the access transistor, which allows a negative substrate voltage (e.g., about -0.3V) to provide bias to the p-type substrate 202 of the access transistor (this practice has been fully adopted by the transistor-over-bitline cell (TOB-cell) to avoid any noise on the pn junction of the access transistor, wherein the noise on the pn junction causes the charge stored in the storage capacitor to be additionally leaked).

[0193] In step 172, if Fig.21 As shown, a thermal oxide 2104 is grown (wherein the thermal oxide 2104 not only completely fills the trench defined by the in-situ doped p-type silicon layer 2102 but also has some additional overflow), and the overflowing thermal oxide 2104 is removed using the isotropic etching technology, so that the top surface of the residual thermal oxide 2104 is flush with the OSS. Then, the oxide spacer-3 2002, the nitride spacer-3 2004, the oxide spacer-1 1204 and the nitride spacer-1 1206 are removed to fully expose the OSS reserved for the source region of the access transistor.

[0194] In step 174, if Fig. 22 As shown, the selective epitaxial growth technique is then used to grow a vertical layer 2202 on the exposed OSS (i.e., on the source region of the access transistor), wherein the vertical layer 2202 has a selective epitaxial material (selective epi material) in situ doped with n+ (e.g., phosphorus). The key technical feature here is that these epitaxial growth columns (i.e., vertical layer 2202) above the source region of the access transistor (also above the in-situ doped p-type silicon layer 2102) can serve as storage nodes / electrodes of the storage capacitor. In addition, these epitaxial growth columns are self-built vertical structures, just like having two legs for the storage capacitor.

[0195] In step 176, if Fig. 22 As shown, a thin high-k dielectric layer 2204 may then be formed over the vertical layer 2202 as a storage node insulator. A conductive layer 2206 (e.g., Si with boron dopants) may then be formed. x Ge 1-x) as the common electrode of the capacitor. In addition, Fig.21 and Fig. 22 is along Fig. 20 (b) is a cross-sectional view taken along the X direction.

[0196] Second embodiment

[0197] In order to reduce the gate-induced-drain-leakage current (GIDL) in a small-sized MOSFET, it is preferred to align or substantially align the drain edge of the MOSFET with the gate edge of the MOSFET. The following second embodiment will describe how to align the drain edge and the gate edge of the vertical transistor disclosed in the present invention.

[0198] Please refer to the following Fig.23 ,in Fig.23 It is a flow chart of a method for manufacturing a transistor-on-bit-line cell (TOB-cell) array disclosed in a second embodiment of the present invention.

[0199] Step 2302: Remove the in-situ doped n+ polysilicon 1404 and thermal oxide 1402, use the selective epitaxial growth (SEG) technique to form an (N+) drain region 2401, and form a vertical nitride spacer 2402 ( Fig.24 );

[0200] Step 2304: Remove the (N+) drain region 2401 to form an in-situ doped n-type lightly doped drain 2502.

[0201] and removing the portion of the in-situ doped n-type lightly doped drain 2502 ( Fig.25 );

[0202] Step 2306: Form and etch down an in-situ doped N+ silicon region 2602, then form an oxide layer 2604, and then remove the vertical nitride spacer 2402 and the oxide spacer-2 1304 ( Fig.26 );

[0203] Step 2308: Thermally generate a thermal oxide layer 2702, and then deposit a high-k gate dielectric layer 2704 ( Fig. 27 );

[0204] Step 2310: Deposit a titanium nitride layer 2802 and a tungsten layer 2804, and then etch back the titanium nitride layer 2802 and the tungsten layer 2804 ( Fig.28 );

[0205] Step 2312: Deposit a nitride layer 2902, then deposit and etch down an oxide layer 2904 ( Fig.29 ); Step 2314: etching away portions of the nitride layer 2902 and the oxide layer 2904 to expose the silicon sidewall 3002,

[0206] Then, the n-type lightly doped drain 3004 ( Fig.30 );

[0207] Step 2316: Deposit an oxide layer 3102 and use the chemical mechanical polishing (CMP) technique to make the top surface of the oxide layer 3102 and the nitride layer 2

[0208] The top surface of 1104 is flush ( Fig.31 , please also refer to Fig.30 );

[0209] Step 2318: Use rapid thermal anneal (RTA) to create an out-diffuse region for the n-type lightly doped drain 3004 and the in-situ doped n-type lightly doped drain 2502 ( Fig.31 );

[0210] Step 2320: Etch away the oxide layer-3 1102, the nitride layer-2 1104, the pad nitride layer 206 and the pad oxide layer 204 to form a groove 3104 next to the oxide layer 3102 and expose the original silicon surface OSS ( Fig.31 , please also refer to Fig.30 ).

[0211] In step 2302, if Fig.24 (a), where Fig.24 (a) is a continuation Fig.14 Afterwards, a thin layer (e.g., about 8-10 nm) of n+ in-situ doped polysilicon is grown using the selective epitaxial growth (SEG) technique to form an (N+) drain region 2401 above the subsurface bit line connector to ensure that the (N+) drain region 2401 is well connected to the subsurface bit line connector. A vertical nitride spacer 2402 is then formed to cover the oxide spacer-2 1304 and also a small portion of the (N+) drain region 2401. In addition, Fig.24 (a) is along the Fig.24 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0212] In step 2304, if Fig.25As shown in (a), the (N+) drain region 2401 is then removed to expose the edge of the silicon in the active region. The exposed edge of the silicon is then used as a seed and the selective epitaxial growth technique is used to form an in-situ doped n-type lightly doped drain 2502. The vertical nitrided spacer 2402 is then used as a mask and the anisotropic etching technique is used to remove a portion of the in-situ doped n-type lightly doped drain 2502. Fig.25 As shown in (a), the top surface of the remaining in-situ doped n-type lightly doped drain 2502 is aligned with the bottom surface of the vertical nitride spacer 2402. In addition, Fig.25 (a) is along the Fig.25 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0213] In step 2306, if Fig.26 As shown in (a), based on the remaining in-situ doped n-type lightly doped drain 2502, the in-situ doped N+ silicon region 2602 is formed by the selective epitaxial growth. Then, the vertical nitridation spacer 2402 is used as a mask and the anisotropic etching technology is used again to remove part of the in-situ doped N+ silicon region 2602. Therefore, the top surface of the remaining in-situ doped N+ silicon region 2602 will be lower than the top surface of the remaining in-situ doped n-type lightly doped drain 2502.

[0214] Then, an oxide layer (e.g., thermal oxide layer) 2604 is formed to cover the remaining in-situ doped N+ silicon region 2602. It is worth noting that the top surface of the oxide layer 2604 is aligned or substantially aligned with the top surface of the remaining in-situ doped n-type lightly doped drain 2502. The vertical nitride spacer 2402 and the oxide spacer-2 1304 are then removed to expose the silicon region used for the access transistor or the channel region of the vertical transistor. In addition, Fig.26 (a) is along the Fig.26 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0215] In step 2308, if Fig. 27 As shown in (a), a thermal oxide layer 2702 is thermally generated on the exposed silicon region, and then a high dielectric constant (high-k) gate dielectric layer 2704 is deposited to cover the thermal oxide layer 2702. In addition, Fig. 27 (a) is along the Fig. 27 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0216] In step 2310, if Fig.28As shown in (a), a titanium nitride layer 2802 and a tungsten layer 2804 are deposited in the region reserved for the gate structure and the local word line to form the gate structure and the local word line that are automatically connected. The titanium nitride layer 2802 / tungsten layer 2804 is etched until the top surface of the titanium nitride layer 2802 / tungsten layer 2804 is lower than the original silicon surface OSS (for example, about 10 to 5 nm lower than the original silicon surface OSS). At this time, as shown in FIG. Fig.28 As shown, the high-k gate dielectric layer 2704 is also etched down. In addition, Fig.28 (a) is along the Fig.28 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0217] In step 2312, if Fig.29 As shown in (a), a nitride layer 2902 is deposited, wherein the nitride layer 2902 is used to protect the titanium nitride layer 2802 / tungsten layer 2804 from being degraded by contact with any oxide material, and the nitride layer 2902 partially fills the trench hole. Then an oxide layer 2904 is deposited and etched down to remove part of the oxide layer 2904 to retain the gate structure and the composite structure with a capping layer above the local word line, wherein the capping layer is composed of the oxide layer 2904 and the nitride layer 2902. In addition, Fig.29 (a) is along the Fig.29 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0218] In step 2314, if Fig.30 As shown in (a), the nitride layer 2902 and the oxide layer 2904 are then etched away to expose the silicon sidewall 3002 close to and below the original silicon surface OSS. Then, the n-type lightly doped drain 3004 is grown through the exposed silicon sidewall 3002 using the selective epitaxial growth technique to serve as the source of the vertical transistor. In addition, Fig.30 (a) is along the Fig.30 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0219] In step 2316, please also refer to Fig.30 (a) and Fig.31 (a) First, an oxide layer 3102 is deposited to fill the trench above the oxide layer 2904 and the n-type lightly doped drain 3004 , and the top surface of the oxide layer 3102 is made flush with the top surface of the nitride layer-2 1104 using the chemical mechanical polishing technique.

[0220] Then in step 2318, if Fig.31As shown in (a), rapid thermal anneal (RTA) is used to create an outdiffusion region for the n-type lightly doped drain 3004 and the in-situ doped n-type lightly doped drain 2502 (with the remaining in-situ doped N+ silicon region and the remaining n-type lightly doped drain region). It is worth noting here that, as Fig.31 As shown in (a), the top surface of the remaining in-situ doped n-type lightly doped drain 2502 is aligned or substantially aligned with the edge of the gate structure of the vertical transistor. In this way, the gate induced drain leakage (GIDL) problem of the vertical transistor will be reduced.

[0221] Then in step 2320, if Fig.31 As shown in (a), the oxide layer 3102, the nitride layer 21104, the pad nitride layer 206 and the pad oxide layer 204 are further etched away to form a groove 3104 next to the oxide layer 3102 and expose the original silicon surface OSS. In addition, Fig.31 (a) is along the Fig.31 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0222] Afterwards Fig.32 As shown, steps 166 to 176 may be executed after step 2320 to complete the new dynamic random access memory cell structure (also called transistor-over-bitline cell (TOB-cell)) of the second embodiment.

[0223] In summary, the bitline transistor cell disclosed in the present invention can be reduced to a cell area of ​​3.0 x 2.5F by means of an underground bit line (UGBL) and an underground bitline connector (UBC) located below the gate structure of the vertical transistor of the bitline transistor cell, wherein the minimum feature size F can be extended to a range of about 6nm. Furthermore, because the top surface of the n-type lightly doped drain of the vertical transistor is aligned or substantially aligned with the edge of the gate structure of the vertical transistor, the present invention can reduce the gate induced drain leakage (GIDL) problem of the vertical transistor.

[0224] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that Include: A semiconductor substrate having a semiconductor surface; an active region located in the semiconductor substrate, wherein the active region includes a transistor, the transistor includes a gate structure, a first conductive region and a second conductive region, and the gate structure has a bottom surface located below the semiconductor surface; a shallow trench isolation region surrounding the active region; and an interconnect layer extending beyond the transistor and electrically coupling the transistor at a connection location below the gate structure; The first conductive region includes a lightly doped region, and a top surface of the lightly doped region is aligned with or substantially aligned with an edge of the gate structure.

2. The semiconductor device structure according to claim 1, wherein The interconnection layer is disposed in the shallow trench isolation region and below the semiconductor surface, and the interconnection layer is isolated from the semiconductor substrate.

3. The semiconductor device structure according to claim 1, wherein The second conductive region includes two sub-regions respectively located on two side walls of the gate structure, and the first conductive region is lower than the second conductive region.

4. The semiconductor device structure according to claim 3, characterized in that The transistor further includes two vertical channel regions separated from each other, and the first conductive region is electrically connected to two sub-regions of the second conductive region through the two vertical channel regions.

5. The semiconductor device structure according to claim 4, characterized in that It also includes a highly doped semiconductor region, wherein the highly doped semiconductor region is adjacent to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the semiconductor surface, and the doping type of the highly doped semiconductor region is different from the doping type of the first conductive region.

6. The semiconductor device structure according to claim 1, wherein The interconnection layer is coupled to the first conductive region of the transistor at the connection position through a connection contact, or the interconnection layer is directly coupled to the first conductive region at the connection position, wherein the connection contact is a highly doped semiconductor plug.

7. The semiconductor device structure according to claim 1, wherein A capacitor is also included, wherein the capacitor is electrically connected to the second conductive region, and the interconnect layer is a bit line electrically connected to the first conductive region.

8. The semiconductor device structure according to claim 7, characterized in that A word line is also included, wherein the word line is electrically connected to the gate structure and passes through the second conductive region.

9. The semiconductor device structure according to claim 1, wherein A dielectric plug is also included, wherein the dielectric plug is located between the gate structure and the first conductive region.

10. The semiconductor device structure as described in claim 1 is further characterized in that it includes a capacitor, wherein the capacitor is electrically connected to the second conductive region, the second conductive region includes two sub-regions respectively located on two side walls of the gate structure, the capacitor includes a storage electrode, and the storage electrode includes two electrode columns respectively connected to the two sub-regions of the second conductive region.

11. The semiconductor device structure according to claim 1, wherein A side surface of the interconnection layer is adjacent to a side surface of a connection contact, and the connection contact is directly connected to the first conductive region of the transistor.

12. The semiconductor device structure according to claim 1, wherein The interconnect layer extends along the shallow trench isolation region and is located below the semiconductor surface.

13. The semiconductor device structure according to claim 12, wherein The shallow trench isolation region includes a first spacer layer and a second spacer layer, the first spacer layer is in contact with the active region, the second spacer layer is in contact with another active region, the material of the first spacer layer is different from the material of the second spacer layer, and the shallow trench isolation region is located between the active region and the another active region.

14. The semiconductor device structure according to claim 1, wherein A side surface of the interconnection layer is adjacent to a side surface of the first conductive region of the transistor.

15. The semiconductor device structure according to claim 1, wherein It also includes a capacitor, wherein the capacitor is electrically connected to the second conductive region, the second conductive region includes two sub-regions respectively located on the two side walls of the gate structure, the capacitor includes a storage electrode, and the storage electrode includes two electrode columns respectively connected to the two sub-regions of the second conductive region, wherein the two electrode columns are epitaxial layers.

16. A semiconductor device structure, characterized in that Include: A semiconductor substrate having a semiconductor surface; an active region and a shallow trench isolation region, wherein the shallow trench isolation region surrounds the active region; and a transistor located in the active region, wherein the transistor comprises a gate structure, a first conductive region and a second conductive region; The second conductive region is above the first conductive region and includes two sub-regions respectively located on two side walls of the gate structure; The first conductive region includes a lightly doped region, and a top surface of the lightly doped region is aligned with or substantially aligned with an edge of the gate structure.

17. The semiconductor device structure according to claim 16, wherein The transistor further includes two vertical channel regions separated from each other, and the first conductive region is electrically connected to two sub-regions of the second conductive region through the two vertical channel regions.

18. The semiconductor device structure according to claim 16, wherein A capacitor is also included, wherein the capacitor is electrically connected to each of the two sub-regions of the second conductive region, and the capacitor includes two electrode columns respectively connected to the two sub-regions of the second conductive region.

19. A semiconductor device structure, characterized in that Include: A semiconductor body substrate having an original surface; an active region located in the semiconductor body substrate, wherein the active region includes a plurality of transistors, and each transistor includes a gate structure, a first conductive region, and a second conductive region, wherein the gate structure has a bottom surface located below the original surface, and the first conductive region is coupled to the semiconductor body substrate; a shallow trench isolation region surrounding the active region; and an interconnect layer extending beyond at least one of the plurality of transistors and electrically coupling the at least one transistor at a connection location below a gate structure of the at least one transistor; The first conductive region of the at least one transistor includes a lightly doped region and a highly doped region, the lightly doped region surrounds the highly doped region, and a top surface of the lightly doped region is aligned or substantially aligned with an edge of the gate structure of the at least one transistor.

20. The semiconductor device structure according to claim 19, wherein The interconnect layer is a bit line, and the interconnect layer extends beyond the plurality of transistors and electrically couples each transistor at a connection location respectively under a gate structure of each transistor.

21. The semiconductor device structure according to claim 19, wherein The interconnection layer is arranged in the shallow trench isolation region and below the original surface, the interconnection layer is isolated from the semiconductor body substrate, and the first conductive region of the at least one transistor is directly or indirectly connected to a side wall of the interconnection layer.

22. The semiconductor device structure according to claim 19, wherein The at least one transistor further includes two vertical channel regions separated from each other, and the first conductive region of the at least one transistor is electrically connected to two sub-regions of the second conductive region of the at least one transistor through the two vertical channel regions, wherein the semiconductor device structure further includes a highly doped semiconductor region, the highly doped semiconductor region is adjacent to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface, and the doping type of the highly doped semiconductor region is different from the doping type of the first conductive region of the at least one transistor.

Images