Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. A semiconductor device includes: a substrate; the first source and drain electrode layer comprises a first source electrode, a first drain electrode, a second source electrode and a second drain electrode; the first type semiconductor layer comprises a first channel layer and a second channel layer; the first grid electrode layer comprises a first grid electrode, a second grid electrode and a third grid electrode; a first gate oxide layer; a first via hole is formed in the second gate oxide layer, and the first gate is exposed out of the first via hole; the second type semiconductor layer comprises a third channel layer and a fourth channel layer; and the second source and drain electrode layer comprises a third source electrode, a third drain electrode, a fourth source electrode and a fourth drain electrode. According to the technical scheme provided by the invention, the process for preparing the capacitance-free dynamic random access memory can be effectively compatible with the subsequent process for preparing the vertical complementary field effect transistor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In modern storage and computing architecture, storage devices play an increasingly important role. Most of the current large-capacity storage is a dynamic random access memory (DRAM) with one transistor and one capacitor, that is, 1T1C DRAM. Its manufacturing process has special requirements for capacitors and transistors, which are difficult to match with the advanced manufacturing process of current logic circuits. In addition, the von Neumann storage and computing system often separates DRAM from the central control processing unit CPU, and its data interaction requires long-distance communication; therefore, the data transmission speed between storage and computing gradually mismatches. In this context, 2T0C storage devices, also known as capacitorless DRAM, have better size miniaturization because they do not require the preparation of capacitors, providing a good solution.

[0003] A vertical complementary field effect transistor (CFET) is a type of P-type and N-type field effect transistor that are stacked vertically so that the two share a gate electrode as a signal input, while the drain is connected as a signal output, and the two sources are grounded and powered respectively. This design allows the size of the N-type CFET and P-type CFET to be adjusted according to performance requirements, and the channels of the N-type CFET and P-type CFET can use different semiconductor materials to achieve mobility matching, thereby increasing the drive current. In addition, the vertical stacking structure helps to reduce device size and improve chip integration.

[0004] The arrangement of CFET can effectively integrate multiple functional devices and reduce their power consumption. However, the process of CFET prepared in the back-end is a vertical process, which requires two transistors to be stacked vertically within a unit area, which requires a top-gate transistor and a back-gate transistor; and in the preparation of 2T0C DRAM, both transistors use the same transistor structure, either all top-gate or all back-gate, which is difficult to be effectively compatible with the process of preparing CFET in the back-end. Summary of the invention

[0005] The present application provides a semiconductor device and a method for preparing the same, aiming to make the process for preparing capacitor-free DRAM effectively compatible with the process for preparing CFET in the later stage.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, which is divided into a first region and a second region, wherein the first region is used to form a capacitor-free dynamic random access memory, and the second region is used to form a vertical complementary field effect transistor, and the device includes:

[0007] substrate substrate;

[0008] A first source-drain electrode layer is formed on the upper substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in the first region, and a second source and a second drain formed in the second region;

[0009] A first type semiconductor layer is formed on a side of the first source-drain electrode layer away from the substrate, the first type semiconductor layer includes a first channel layer formed in a first region and a second channel layer formed in a second region, two ends of the first channel layer are electrically connected to the first source and the first drain, respectively, and two ends of the second channel layer are electrically connected to the second source and the second drain, respectively;

[0010] A first gate layer, the first gate layer includes a first gate located on a side of the first channel layer away from the substrate, a second gate located on a side of the second channel layer away from the substrate, and a third gate located in the first region, a first gate oxide layer is formed on a side of the first gate layer close to the substrate, and a second gate oxide layer is formed on a side of the first gate layer away from the substrate, a first via hole is formed on the second gate oxide layer, and the first via hole exposes the first gate;

[0011] A second type semiconductor layer is formed on a side of the second gate oxide layer away from the substrate, the second type semiconductor layer includes a third channel layer and a fourth channel layer, the third channel layer is formed on a side of the third gate away from the substrate, and the fourth channel layer is formed on a side of the second gate away from the substrate;

[0012] A second source-drain electrode layer is formed on the side of the second gate oxide layer away from the base substrate, the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain, the third source and the third drain are electrically connected to the two ends of the third channel layer, respectively, the fourth source and the fourth drain are electrically connected to the two ends of the fourth channel layer, respectively, and the third drain is electrically connected to the first gate through the first via hole.

[0013] In some embodiments, the semiconductor device is characterized in that a second via hole is further formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain is electrically connected to the fourth drain through the second via hole.

[0014] In some embodiments, the second via includes a first sub-via and a second sub-via, the first sub-via passes through the first gate oxide layer, the second sub-via passes through the second gate oxide layer, and the projections of the first sub-via and the second sub-via on the substrate at least partially overlap.

[0015] In some embodiments, the first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; or, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

[0016] In some embodiments, the N-type semiconductor material layer is at least one of other oxide semiconductor materials such as IGZO, IWO, ITO, etc., and the P-type semiconductor material layer is at least one of P-type oxide semiconductor materials such as TeOx, SnO, P-type two-dimensional materials, P-type carbon nanotubes, etc.

[0017] In a second aspect, the present application also provides a method for preparing a flat panel detector substrate, comprising:

[0018] providing a substrate base plate;

[0019] Forming a first source-drain electrode layer on the base substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in the first region, and a second source and a second drain formed in the second region;

[0020] A first type semiconductor layer is formed on a side of the first source-drain electrode layer away from the base substrate, wherein the first type semiconductor layer includes a first channel layer formed in a first region and a second channel layer formed in a second region, wherein two ends of the first channel layer are electrically connected to the first source electrode and the first drain electrode, respectively, and two ends of the second channel layer are electrically connected to the second source electrode and the second drain electrode, respectively;

[0021] forming a first gate layer, the first gate layer comprising a first gate located on a side of the first channel layer away from the substrate, a second gate located on a side of the second channel layer away from the substrate, and a third gate located in the first region, a first gate oxide layer is formed on a side of the first gate layer close to the substrate, and a second gate oxide layer is formed on a side of the first gate layer away from the substrate, a first via hole is formed on the second gate oxide layer, and the first via hole exposes the first gate;

[0022] A second type semiconductor layer is formed on a side of the second gate oxide layer away from the substrate, wherein the second type semiconductor layer includes a third channel layer and a fourth channel layer, wherein the third channel layer is formed on a side of the third gate away from the substrate, and the fourth channel layer is formed on a side of the second gate away from the substrate;

[0023] A second source-drain electrode layer is formed on the side of the second gate oxide layer away from the base substrate, and the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain. The third source and the third drain are electrically connected to the two ends of the third channel layer, respectively, and the fourth source and the fourth drain are electrically connected to the two ends of the fourth channel layer, respectively, and the third drain is electrically connected to the first gate through the first via hole.

[0024] In some embodiments, before forming the fourth drain, the method further includes:

[0025] A second via hole is formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

[0026] In some embodiments, the second via hole includes a first sub-via hole and a second sub-via hole, and the second via hole is formed by:

[0027] After forming the first gate oxide layer, forming the first sub-via hole, wherein the first sub-via hole penetrates the first gate oxide layer;

[0028] After forming the second gate oxide layer, the second sub-via is formed, and the second sub-via penetrates the second gate oxide layer; the projections of the first sub-via and the second sub-via on the base substrate at least partially overlap.

[0029] In some embodiments, the first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; or, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

[0030] In some embodiments, the N-type semiconductor material layer is at least one of other oxide semiconductor materials such as IGZO, IWO, ITO, etc., and the P-type semiconductor material layer is at least one of P-type oxide semiconductor materials such as TeOx, SnO, P-type two-dimensional materials, P-type carbon nanotubes, etc.

[0031] The technical solution provided by the embodiment of the present application, wherein the semiconductor device includes a first region and a second region, wherein the first region forms a back-end complementary capacitor-free DRAM, and the second region forms a CFET, thereby realizing the simultaneous provision of capacitor-free DRAM and CFET in the same semiconductor device, and the two are also corresponding in each layer structure, so that both can be prepared through a set of process flows, and for the capacitor-free DRAM, its top-gate transistor and back-gate transistor can also be prepared in coordination. Such a back-end CFET can be compatible with the integration of different channel materials, prepare functional modules with different requirements, and realize the multifunctional integration of the back-end CFET.

[0032] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0034] Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of another semiconductor device structure provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application;

[0037] Figures 4 to 9 for Figure 3 Schematic diagram of the structures corresponding to each step in the preparation method shown. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0039] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0040] In the description of the present application, “plurality” means two or more.

[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0042] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0043] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0044] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0045] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0047] Most of the existing semiconductor manufacturing processes are based on silicon, which inevitably introduces high-temperature steps in transistors; further multi-layer transistor manufacturing will be restricted by high temperatures, causing the lower-layer transistors to fail, so traditional processes are mainly based on single-layer devices. Transistors manufactured using back-end compatible channels (such as oxide semiconductors) have lower manufacturing temperatures and the potential for large-scale manufacturing, making multi-layer stacked transistors possible.

[0048] In addition, the NP complementary transistor arrangement can effectively integrate multiple functional devices and reduce their power consumption. However, for the vertical complementary transistor CFET prepared in the back-end, its process is a vertical process, which requires two transistors to be stacked vertically in a unit area, which requires a top-gate transistor and a back-gate transistor; in the preparation of today's capacitor-free DRAM, both transistors use a common transistor structure, but usually all use top gate or all use back gate, making it difficult to be effectively compatible with the back-end CFET process.

[0049] In view of the above problems existing in the related art, the present application provides a semiconductor device. Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0050] like Figure 1As shown, the semiconductor device 10 provided in the embodiment of the present application can be divided into a first region and a second region, the first region is used to form a capacitor-free DRAM, and the second region is used to form a CFET. In the embodiment of the present application, the capacitor-free DRAM includes a top gate transistor and a back gate transistor, the gates of the two are arranged in the same layer, and can be prepared in coordination, and the CFET includes a top gate transistor and a back gate transistor, and they share the same gate; in addition, the other film layers of the capacitor-free DRAM and the CFET can also be arranged in the same layer and obtained in the same preparation step. Specifically, the semiconductor device provided in the embodiment of the present application may include:

[0051] Base substrate 101;

[0052] A first source-drain electrode layer 102 is formed on the base substrate 101, the first source-drain electrode layer 102 includes a first source 1021 and a first drain 1022 formed in a first region, the first source 1021 and the first drain 1022 are the source and the drain of the top-gate transistor of the capacitor-free DRAM, and a second source 1023 and a second drain 1024 are formed in a second region, the second source 1023 and the second drain 1024 are the source and the drain of the top-gate transistor of the CFET;

[0053] A first type semiconductor layer 103 is formed on a side of the first source-drain electrode layer 102 away from the substrate 101, the first type semiconductor layer 103 includes a first channel layer 1031 formed in a first region and a second channel layer 1032 formed in a second region, two ends of the first channel layer are electrically connected to the first source 1021 and the first drain 1022, respectively, and serves as a channel layer of the top-gate transistor of the above-mentioned capacitor-free DRAM, and two ends of the second channel layer 1032 are electrically connected to the second source 1023 and the second drain 1024, respectively, and serves as a channel layer of the top-gate transistor of the above-mentioned CFET;

[0054] A first gate layer 104, the first gate layer 104 includes a first gate 1041 located on a side of the first channel layer 1031 away from the substrate 101, which serves as a gate of the top gate transistor of the capacitor-free DRAM, a second gate 1042 located on a side of the second channel layer 1032 away from the substrate 101, which serves as a gate of the top gate transistor of the CFET, and a third gate 1043 located in the first region, which serves as a gate of the back gate transistor of the capacitor-free DRAM;

[0055] In addition, in order to achieve gate insulation, a first gate oxide layer 105 may be further formed on the side of the first gate layer 104 close to the base substrate 101, and a second gate oxide layer 106 may be formed on the side of the first gate layer 104 away from the base substrate 101, and a first via hole 109 is formed on the second gate oxide layer 106, and the first via hole 109 exposes the first gate 1041;

[0056] A second type semiconductor layer 107 is formed on a side of the second gate oxide layer 106 away from the substrate 101, the second type semiconductor layer 107 includes a third channel layer 1071 and a fourth channel layer 1072, the third channel layer 1071 is formed on a side of the third gate away from the substrate 101, and serves as a channel layer of a back-gate transistor of the above-mentioned capacitor-free DRAM, and the fourth channel layer 1072 is formed on a side of the second gate 1042 away from the substrate 101, and serves as a channel layer of a back-gate transistor of the CFET;

[0057] A second source-drain electrode layer 108 is formed on the side of the second gate oxide layer 106 away from the substrate 101. The second source-drain electrode layer 108 includes a third source 1081 and a third drain 1082, as well as a fourth source 1083 and a fourth drain 1084. The third source 1081 and the third drain 1082 are electrically connected to the two ends of the third channel layer 1071, respectively, and serve as the source and drain of the back-gate transistor of the above-mentioned capacitor-free DRAM, and the third drain 1082 is electrically connected to the first gate 1041 through the first via 109, and the fourth source 1083 and the fourth drain 1084 are electrically connected to the two ends of the fourth channel layer 1072, respectively, and serve as the source and drain of the back-gate transistor of the CFET.

[0058] The capacitor-free DRAM provided by the above embodiment of the present application has a drain of the back-gate transistor, i.e., the third drain 1082, electrically connected to the gate of the top-gate transistor, i.e., the first gate 1041, through the first via 109. The back-gate transistor and the top-gate transistor can be used as a write tube and a read tube respectively.

[0059] The CFET located in the second region of the semiconductor device includes a back-gate transistor and a top-gate transistor, such as Figure 1 As shown in the figure, the top-gate transistor and the back-gate transistor are stacked in the vertical direction. By adjusting the order of the process steps, the upper and lower positions of the two transistors can be interchanged without affecting the function of the back-end CFET device. The CFET is equivalent to an independent N transistor and an independent P transistor. Through lead interconnection, each can realize its own required function, but only occupies one unit area.

[0060] The technical solution provided by the embodiment of the present application, wherein the semiconductor device includes a first region and a second region, wherein the first region forms a back-end complementary capacitor-free DRAM, and the second region forms a CFET, thereby realizing the simultaneous provision of capacitor-free DRAM and CFET in the same semiconductor device, and the two are also corresponding in each layer structure, so that both can be prepared through a set of process flows, and for the capacitor-free DRAM, its top-gate transistor and back-gate transistor can also be prepared in coordination. Such a back-end CFET can be compatible with the integration of different channel materials, prepare functional modules with different requirements, and realize the multifunctional integration of the back-end CFET.

[0061] In some embodiments, Figure 2 As shown, the semiconductor device is also formed with a second via 110, which penetrates the first gate oxide layer 105 and the second gate oxide layer 1032, and the second drain 1024 is electrically connected to the fourth drain 1084 through the second via. When the CFET is opened by the via process, the back-gate transistor and the top-gate transistor share the second gate 1042 as the signal input terminal. When the input signal is at a high level, the back-gate transistor connected to the power supply terminal is turned off, and the top-gate transistor connected to the ground line is turned on. The fourth drain 1084 and the second drain 1024 are interconnected as the output terminal. At this time, the back-gate transistor pulls the output terminal voltage down to the low level of the ground terminal. Conversely, when the input terminal is at a low level, the top-gate transistor is turned on, the back-gate transistor is turned off, and the top-gate transistor pulls the output terminal voltage up to the high level of the power supply terminal to realize the inverter function.

[0062] In some embodiments, the second via 110 includes a first sub-via 1101 and a second sub-via 1102, the first sub-via 1101 penetrates the first gate oxide layer 105, the second sub-via 1102 penetrates the second gate oxide layer 106, and the projections of the first sub-via 1101 and the second sub-via 1102 on the base substrate 101 at least partially overlap. Therefore, in the preparation process of the semiconductor device, the first sub-via 1101 can be prepared after the first gate oxide layer 105 is prepared, and then the second sub-via 1101 can be prepared after the second gate oxide layer 106 is prepared.

[0063] In some embodiments, the first type semiconductor layer 103 is an N-type semiconductor material layer, and the second type semiconductor layer 107 is a P-type semiconductor material layer; or, the first type semiconductor layer 103 is a P-type semiconductor material layer, and the second type semiconductor layer 107 is an N-type semiconductor material layer.

[0064] Among them, the N transistor is a back-gate transistor, and the P transistor is a top-gate transistor; the top gate or back gate of the two can be replaced with each other, but it should be noted that the material with lower leakage (usually N transistor) needs to be used as the write tube of the 2T0C DRAM memory to ensure sufficiently good storage retention characteristics.

[0065] In some embodiments, the N-type semiconductor material layer can be made of any material with low leakage, post-processable and good uniformity. For example, IGZO, IWO, ITO and other oxide semiconductor materials. The P-type semiconductor material layer can be made of any material that can be post-processed, can be prepared on a large scale and has good uniformity. For example, P-type oxide semiconductor materials such as TeOx and SnO, P-type two-dimensional materials, P-type carbon nanotubes, etc.

[0066] In some embodiments, the capacitor-free DRAM located in the first region of the semiconductor device can be composed of a top-gate P-type read tube and a back-gate N-type write tube, wherein the third drain 1082 of the N-type write tube is connected to the write tube bit line, the third gate 1043 is connected to the write tube word line, and the third source 1081 is connected to the first gate 1041 of the P-type read tube. When data needs to be written, the data is supplied to the write tube bit line in the form of voltage; a high voltage is set at the end of the write tube word line to turn on the N-type write tube, and the voltage at the storage node (Storage Node, SN) is pulled down or pulled up by the write tube bit line. When this unit does not need to write data, the write tube word line is grounded or a negative voltage is set to turn off the write tube and keep the data of SN. The two ends of the read tube are respectively connected to the read tube word line and the bit line, and grounded in the non-selected state to turn off the P-type read tube. When selected to read data, the read tube bit line is given a higher voltage and the read tube word line is given a lower voltage, so that the current is read out to judge the potential at the storage node, thereby realizing the memory function.

[0067] The present application also provides a method for preparing a semiconductor device, by which the above-mentioned Figure 1 A semiconductor device 10 in the illustrated embodiment. Figure 3 A schematic diagram of a method for preparing a semiconductor device provided in an embodiment of the present application, wherein the specific structure can be referred to Figure 1 As shown, the semiconductor device 10 can be divided into a first region and a second region, the first region is used to form a capacitor-free DRAM, and the second region is used to form a CFET. In the embodiment of the present application, the capacitor-free DRAM includes a top-gate transistor and a back-gate transistor, the gates of the two are arranged in the same layer, and can be prepared in coordination, and the CFET includes a top-gate transistor and a back-gate transistor, and they share the same gate; in addition, the other film layers of the capacitor-free DRAM and the CFET can also be arranged in the same layer and obtained in the same preparation step. The specific preparation process is as follows Figure 3 As shown, the preparation method comprises the following steps:

[0068] Step 301: Provide a substrate 101, the substrate 101 may be made of a single crystal silicon wafer.

[0069] Step 302: forming a first source-drain electrode layer 102, wherein the first source-drain electrode layer 102 includes a first source 1021 and a first drain 1022 formed in a first region, and a second source 1023 and a second drain 1024 formed in the second region, wherein the first source 1021 and the first drain 1022 are the source and the drain of the top-gate transistor of the above-mentioned capacitor-less DRAM, and the second source 1023 and the second drain 1024 are the source and the drain of the top-gate transistor of the above-mentioned CFET;

[0070] In this step, the first source-drain electrode layer 102 can be made of various metal materials, such as palladium (Pd). Figure 4 As shown, the first source-drain electrode layer 102 may be formed by depositing palladium (Pd) on the base substrate 101 by electron beam evaporation.

[0071] Step 303: forming a first type semiconductor layer 103, the first type semiconductor layer 103 includes a first channel layer 1031 formed in a first region and a second channel layer 1032 formed in a second region, two ends of the first channel layer 1031 are electrically connected to the first source 1021 and the first drain 1022, respectively, and two ends of the second channel layer 1032 are electrically connected to the second source 1023 and the second drain 1024, respectively, wherein the first channel layer 1031 can be used as a channel layer of a top-gate transistor of the above-mentioned capacitor-free DRAM, and the second channel layer 1032 can be used as a channel layer of a top-gate transistor of a CFET;

[0072] In this step, according to the type of the prepared top-gate transistor, the first type semiconductor layer 103 may be a P-type semiconductor material layer or an N-type semiconductor material layer. For example, the P-type semiconductor material layer may be TeO x At this time, if Figure 5 As shown, a tellurium (Te) target is used to deposit on the first source-drain electrode layer 102 away from the substrate 101 by reactive sputtering, and oxygen O is introduced during the process. 2 , and TeO x The Te:O composition ratio in the sputtering process is determined by the O 2 / (Ar+O 2 ) is determined by the gas flow rate. x The area where the channel layer is located can use Cl 2 and BCl 3 It is defined by dry etching.

[0073] Step 304: forming a first gate oxide layer 105;

[0074] like Figure 6 As shown, aluminum oxide Al is deposited on the side of the first type semiconductor layer 103 away from the substrate 101 by atomic layer deposition (Atomic Layer Deposition, ALD). 2 O 3 and hafnium oxide HfO 2 The stack is used as the first gate oxide layer 105 . In this step, the ambient temperature during deposition can be set to 150° C.

[0075] Step 305: forming a first gate layer 104, the first gate layer 104 comprising a first gate 1041 located on a side of the first channel layer 1031 away from the substrate 101, a second gate 1042 located on a side of the second channel layer 1032 away from the substrate 101, and a third gate 1043 located in the first region.

[0076] like Figure 7 As shown, the material of the first gate layer can be a metal material. In the embodiment of the present application, titanium Ti / palladium Pd is deposited on the side of the first gate oxide layer 105 away from the substrate 101 to form a first gate layer 104, wherein the first gate layer 104 includes a first gate 1041 located on the side of the first channel layer 1031 away from the substrate 101, and the first gate 1041 serves as the top gate of the capacitor-free DRAM; a second gate 1042 located on the side of the second channel layer 1032 away from the substrate 101, and the second gate 1042 serves as the top gate of the CFET and is also used as the common gate of the CFET; a third gate 1043 located in the first region serves as the back gate of the capacitor-free DRAM.

[0077] Step 306: forming a second gate oxide layer 106 and a first via hole 109; forming a first gate oxide layer 105 on a side of the first gate layer 104 close to the base substrate 101, and forming a second gate oxide layer 106 on a side of the first gate layer 104 away from the base substrate 101, and forming a first via hole 109 on the second gate oxide layer 106, wherein the first via hole 109 exposes the first gate 1041;

[0078] like Figure 8 As shown, hafnium oxide HfO2 is grown on the side of the first gate layer 104 close to the substrate 101 by ALD at 150°C as the second gate oxide layer 106. At the same time, this step also opens a hole in the second gate oxide layer 106 deposited on the first gate 1041 of the capacitorless DRAM to form a first via 109, exposing the metal of the first gate 1041 for easy interconnection with the third drain 1082.

[0079] Step 307: forming a second type semiconductor layer 107, the second type semiconductor layer 107 comprising a third channel layer 1071 and a fourth channel layer 1072, the third channel layer 1071 being formed on a side of the third gate 1043 away from the substrate 101, and the fourth channel layer 1072 being formed on a side of the second gate 1042 away from the substrate 101; wherein the third channel layer 1071 can be used as a channel layer of a back-gate transistor of the above-mentioned capacitor-less DRAM, and the fourth channel layer 1072 can be used as a channel layer of a back-gate transistor of a CFET;

[0080] like Fig. 9 As shown, a second type semiconductor layer 107 is formed on the side of the second gate oxide layer 106 away from the substrate 101 by atomic layer deposition. The second type semiconductor layer 107 may be a P-type semiconductor material layer, or an N-type semiconductor material layer, for example, an N-type semiconductor material layer, which may be IGZO;

[0081] Step 308: forming a second source-drain electrode layer 108, the second source-drain electrode layer 108 includes a third source 1081 and a third drain 1082, and a fourth source 1083 and a fourth drain 1084, the third source 1081 and the third drain 1082 are electrically connected to two ends of the third channel layer 1071, respectively, the fourth source 1083 and the fourth drain 1084 are electrically connected to two ends of the fourth channel layer 1072, and the third drain 1082 is electrically connected to the first gate 1041 through the first via 109, the third source 1081 and the third drain 1082 are used as the source and drain of the back-gate transistor of the above-mentioned capacitor-free DRAM, respectively, and the fourth source 1083 and the fourth drain 1084 are used as the source and drain of the back-gate transistor of the above-mentioned CFET, respectively;

[0082] In this step, chemical vapor deposition can be used to form a second source-drain electrode layer 108 on the side of the second type semiconductor layer 107 away from the substrate 101. Through this step, the above-mentioned Figure 1 The semiconductor device in the illustrated embodiment.

[0083] Finally, palladium (Pd) can be deposited by chemical vapor deposition to serve as a contact point for connecting the second source-drain electrode layer 108 to an external circuit. Unnecessary palladium layers and possible other material layers are removed by wet etching to define the channel layer region of the second type semiconductor layer 107 .

[0084] In some embodiments, Figure 2As shown, it also includes a second via hole 110, which can be formed by etching the first gate insulating layer 105 and the second gate insulating layer 106 by inductively coupled plasma before forming the fourth drain 1084. The second via hole 110 penetrates the first gate insulating layer 105 and the second gate insulating layer 106, and the second drain 1024 is electrically connected to the fourth drain 1084 through the second via hole 110; the second via hole 110 can be formed once or in two times.

[0085] Exemplarily, the second via 110 includes a first sub-via 1101 and a second sub-via 1102, and is formed in two steps respectively. For example, after forming the first gate oxide layer 105, the first gate insulating layer 105 is etched by inductively coupled plasma to form the first sub-via 1101, and the first sub-via 1101 penetrates the first gate oxide layer 105;

[0086] After forming the second gate oxide layer 106 , the second gate oxide layer 106 may be etched by inductively coupled plasma to form a second sub-via 1102 , which penetrates the second gate oxide layer 106 ; the projections of the first sub-via 1101 and the second sub-via 1102 on the base substrate 101 at least partially overlap.

[0087] In the embodiment of the present application, the N-type channel material can be any material with low leakage, post-processable and good uniformity. For example, IGZO, IWO, ITO and other oxide semiconductor materials. The P-type channel material can be any material that can be post-processed, can be prepared on a large scale and has good uniformity. For example, P-type oxide semiconductor materials such as TeOx and SnO, P-type two-dimensional materials, P-type carbon nanotubes, etc.

[0088] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device is divided into a first area and a second area, the first area is used to form a capacitor-free dynamic random access memory, and the second area is used to form a vertical complementary field effect transistor. The device includes: substrate substrate; A first source-drain electrode layer is formed on the base substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in a first region, and a second source and a second drain formed in the second region; A first type semiconductor layer is formed on a side of the first source-drain electrode layer away from the substrate, the first type semiconductor layer includes a first channel layer formed in a first region and a second channel layer formed in a second region, two ends of the first channel layer are electrically connected to the first source and the first drain, respectively, and two ends of the second channel layer are electrically connected to the second source and the second drain, respectively; A first gate layer, the first gate layer includes a first gate located on a side of the first channel layer away from the substrate, a second gate located on a side of the second channel layer away from the substrate, and a third gate located in the first region, a first gate oxide layer is formed on a side of the first gate layer close to the substrate, and a second gate oxide layer is formed on a side of the first gate layer away from the substrate, a first via hole is formed in the second gate oxide layer, and the first via hole exposes the first gate; A second type semiconductor layer is formed on a side of the second gate oxide layer away from the substrate, the second type semiconductor layer includes a third channel layer and a fourth channel layer, the third channel layer is formed on a side of the third gate away from the substrate, and the fourth channel layer is formed on a side of the second gate away from the substrate; A second source-drain electrode layer is formed on a side of the second gate oxide layer away from the substrate, the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain, the third source and the third drain are electrically connected to two ends of the third channel layer, respectively, the fourth source and the fourth drain are electrically connected to two ends of the fourth channel layer, and the third drain is electrically connected to the first gate through the first via hole.

2. The semiconductor device according to claim 1, wherein: A second via hole is also formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

3. The semiconductor device according to claim 2, characterized in that The second via includes a first sub-via and a second sub-via, the first sub-via passes through the first gate oxide layer, the second sub-via passes through the second gate oxide layer, and projections of the first sub-via and the second sub-via on the substrate at least partially overlap.

4. The semiconductor device according to claim 1, wherein: The first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; Alternatively, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

5. The semiconductor device according to claim 4, characterized in that The N-type semiconductor material layer is at least one of IGZO, IWO and ITO, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type two-dimensional material and P-type carbon nanotube.

6. A method for preparing a semiconductor device, characterized in that: The semiconductor device is divided into a first region and a second region, the first region is used to form a capacitor-free dynamic random access memory, and the second region is used to form a vertical complementary field effect transistor. The preparation method includes: providing a substrate base plate; Forming a first source-drain electrode layer on the base substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in a first region, and a second source and a second drain formed in the second region; A first type semiconductor layer is formed on a side of the first source-drain electrode layer away from the substrate, wherein the first type semiconductor layer includes a first channel layer formed in a first region and a second channel layer formed in a second region, two ends of the first channel layer are electrically connected to the first source electrode and the first drain electrode, respectively, and two ends of the second channel layer are electrically connected to the second source electrode and the second drain electrode, respectively; forming a first gate layer, the first gate layer comprising a first gate located on a side of the first channel layer away from the substrate, a second gate located on a side of the second channel layer away from the substrate, and a third gate located in the first region, a first gate oxide layer is formed on a side of the first gate layer close to the substrate, and a second gate oxide layer is formed on a side of the first gate layer away from the substrate, a first via hole is formed on the second gate oxide layer, and the first via hole exposes the first gate; A second type semiconductor layer is formed on a side of the second gate oxide layer away from the substrate, wherein the second type semiconductor layer includes a third channel layer and a fourth channel layer, wherein the third channel layer is formed on a side of the third gate away from the substrate, and the fourth channel layer is formed on a side of the second gate away from the substrate; A second source-drain electrode layer is formed on the side of the second gate oxide layer away from the base substrate, and the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain. The third source and the third drain are electrically connected to the two ends of the third channel layer, respectively, and the fourth source and the fourth drain are electrically connected to the two ends of the fourth channel layer, respectively, and the third drain is electrically connected to the first gate through the first via hole.

7. The preparation method according to claim 6, characterized in that: Before forming the fourth drain, the method further comprises: A second via hole is formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

8. The preparation method according to claim 7, characterized in that: The second via hole includes a first sub-via hole and a second sub-via hole, and the forming of the second via hole includes After forming the first gate oxide layer, forming the first sub-via hole, wherein the first sub-via hole penetrates the first gate oxide layer; After forming the second gate oxide layer, the second sub-via is formed, and the second sub-via penetrates the second gate oxide layer; the projections of the first sub-via and the second sub-via on the substrate at least partially overlap.

9. The preparation method according to claim 6, characterized in that: The first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; Alternatively, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

10. The preparation method according to claim 9, characterized in that: The N-type semiconductor material layer is at least one of IGZO, IWO and ITO, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type two-dimensional material and P-type carbon nanotube.

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