Semiconductor device and dynamic logic circuit

Abstract

The invention provides a semiconductor device with improved operation speed and a dynamic logic circuit. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes first to third transistors having the same conductivity type and a capacitor. The gates of the first to third transistors are electrically connected to the write word line, the first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. One of a source and a drain of the first transistor is electrically connected to the write bit line, and the other is electrically connected to a gate of the second transistor. The second transistor and the third transistor are electrically connected in series between the read bit line and the first wiring. The channel formation regions of the first to third transistors include, for example, a metal oxide layer.

Description

This invention application is a divisional application of the invention patent application with international application number PCT / IB2018 / 058852, international application date November 12, 2018, application number 201880072662.6 entering the Chinese national phase, and name “Semiconductor Device and Dynamic Logic Circuit”. Technical Field

[0001] One embodiment of the invention disclosed in the specification of the present application relates to a semiconductor device, an operating method thereof, a method of using the same, a method of manufacturing the same, etc. One embodiment of the present invention is not limited to the technical field illustrated.

[0002] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), and a device including the circuit. In addition, a semiconductor device refers to all devices that can work by utilizing semiconductor characteristics. For example, an integrated circuit, a chip with an integrated circuit, or an electronic component that contains a chip in its package is an example of a semiconductor device. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes semiconductor devices themselves, or sometimes include semiconductor devices. Background Art

[0003] A transistor whose channel formation region includes a metal oxide (hereinafter sometimes referred to as a "metal oxide transistor", "oxide semiconductor transistor" or "OS transistor") is known. For example, in an embedded memory device described in non-patent document 1, an OS transistor is used as a write transistor of a 1T1C (1 transistor and 1 capacitor) unit. In a memory device described in non-patent document 2, an OS transistor is used as a write transistor of a 2T1C type gain unit, and a Si transistor is used as a read transistor.

[0004] In this specification, as in Non-Patent Documents 1 and 2, a memory device having an OS transistor in a memory cell may be referred to as an OS memory device.

[0005] Logic circuits can be classified into static logic circuits, dynamic logic circuits, and pseudo logic circuits. Since dynamic logic circuits are circuits that work by temporarily holding data in dynamic nodes, leakage current of transistors causes a more serious problem than static logic circuits. For example, Patent Document 1 discloses a technique for suppressing voltage drop at dynamic nodes by using OS transistors. [References] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2017-17693

[0007] [Non-patent document 1] T.Onuki et al., "Embedded Memory and ARM Cortex-M0 CoreUsing 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FETIntegrated With 65-nm Si CMOS," IEEE J.Solid-State Circuits, Vol.52, No.4, pp.925-932, 2017. [Non-patent document 2] T.Ishizu et al., "A 140MHz 1Mbit 2T1C Gain-Cell Memory with 60-nm Indium-Gallium-Zinc Oxide Transistor Embedded into 65-nm CMOSLogic Process Technology," Symp.VLSI Circuits Dig.Tech.Papers, pp.162-163, 2017. Summary of the invention

[0008] An object of one embodiment of the present invention is to provide a novel semiconductor device including a single conductive type transistor and an operating method thereof, reduce the number of transistors in a semiconductor device, increase the operating speed of a semiconductor device, reduce the power consumption of a semiconductor device, or achieve high rewrite resistance of a semiconductor device.

[0009] One embodiment of the present invention does not need to achieve all of the above-mentioned objects. The description of multiple objects does not hinder the existence of each other's objects. Objects other than the above-mentioned objects can be naturally known from the description of this specification, etc., and may become the objects of one embodiment of the present invention.

[0010] (1) One embodiment of the present invention is a semiconductor device including a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell, wherein the memory cell includes first to third transistors of a single conductivity type and a capacitor. The gates of the first to third transistors are electrically connected to the write word line, the first terminal of the capacitor, and the read word line, respectively, the second terminal of the capacitor is electrically connected to the read bit line, one of the source and the drain of the first transistor is electrically connected to the write bit line, and the other is electrically connected to the gate of the second transistor, and the second transistor and the third transistor are electrically connected in series between the read bit line and the first wiring.

[0011] (2) In the above aspect (1), each of the first to third transistors is provided with a back gate, and the first to third voltages are input to each back gate.

[0012] (3) One embodiment of the present invention is a dynamic logic circuit including an input node, first to fourth wirings, and first to fourth transistors of a single conductivity type, wherein a first signal is input to the gate of the first transistor, the source and drain of the first transistor are electrically connected to the first wiring and the input node, respectively, the second to fourth transistors are electrically connected in series between the second wiring and the third wiring, the second signal is input to the gate of the second transistor, the inversion signal of the second signal is input to the gate of the fourth transistor, the gate of the third transistor is electrically connected to the input node, the third transistor includes a back gate, and the back gate is electrically connected to the fourth wiring.

[0013] (4) One embodiment of the present invention is a dynamic logic circuit including an input node, a first dynamic node, a second dynamic node, and first to sixth transistors of a single conductivity type, wherein the first dynamic node is electrically connected to the drains of the first to third transistors, the second dynamic node is electrically connected to the drains of the fourth to sixth transistors, the input node is electrically connected to the sources of the first transistor and the fourth transistor, a first voltage is input to the sources of the second, third, fifth, and sixth transistors, a first signal is input to the gates of the first and sixth transistors, a second signal is input to the gates of the fourth and third transistors, and a third signal is input to the gates of the second and fifth transistors.

[0014] (5) One embodiment of the present invention is a buffer circuit including a first input node, a second input node, an output node, a first capacitor, a second capacitor, and first to sixth transistors of a single conductivity type, wherein the first terminal of the first capacitor is electrically connected to the first input node, the first terminal of the second capacitor is electrically connected to the second input node, the second terminal of the first capacitor is electrically connected to the source of the first transistor, the drain of the second transistor, and the gate of the third transistor, the second terminal of the second capacitor is electrically connected to the source of the fourth transistor, the drain of the fifth transistor, and the gate of the sixth transistor, and the output node is electrically connected to the source of the third transistor and the drain of the sixth transistor.

[0015] In this specification, ordinal numbers such as "first", "second", "third" are sometimes added to indicate the order. Or, ordinal numbers are sometimes added to avoid confusion between constituent elements. In this case, the ordinal number does not limit the number of constituent elements. For example, "first" can be replaced with "second" or "third" to illustrate one embodiment of the present invention.

[0016] In this specification, when it is stated that "X is connected to Y", the following cases are also included in the disclosure scope of this specification: X is electrically connected to Y; X is functionally connected to Y; and X is directly connected to Y. Therefore, the connection relationships are not limited to those shown in the drawings or text, and connection relationships other than those shown in the drawings or text are also disclosed in the drawings or text. X and Y are both objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0017] A transistor includes at least three terminals: a gate, a source, and a drain. A transistor sometimes also includes a back gate. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other is used as the drain. Therefore, in this specification, "source" and "drain" can be interchanged. In addition, in this specification, the two terminals other than the gate are sometimes referred to as the first terminal, the second terminal, etc.

[0018] A node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit structure or the device structure. In addition, a terminal, a wiring, etc. may also be referred to as a node.

[0019] Voltage usually refers to the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced by potential. Note that potential is relative. Therefore, even if it is recorded as "GND", it does not necessarily mean 0V.

[0020] In this specification, for convenience, words and phrases such as "upper" and "lower" that indicate configuration are sometimes used to describe the positional relationship of components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in this specification are not limited and can be appropriately replaced according to the situation.

[0021] In addition, in this specification, "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". For example, "insulating film" may be interchanged with "insulating layer".

[0022] According to one embodiment of the present invention, a novel semiconductor device including a single conductive type transistor and its operating method can be provided, the number of transistors in the semiconductor device can be reduced, the operating speed of the semiconductor device can be increased, the power consumption of the semiconductor device can be reduced, or high rewrite resistance of the semiconductor device can be achieved.

[0023] The description of multiple effects does not prevent the existence of each other's effects. In addition, one mode of the present invention does not need to have all the above effects. In one mode of the present invention, the purposes, effects and novel features other than the above will be apparent from the description and drawings in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A is a block diagram showing a configuration example of a storage device, Figure 1B is a circuit diagram showing a structural example of a memory cell. Figure 2 is a circuit diagram showing a structural example of a memory cell array. Figure 3 is a circuit diagram showing a configuration example of a row decoder. Figure 4 is a circuit diagram showing a configuration example of a decoder. Figure 5 is a circuit diagram showing a configuration example of a peripheral circuit. Fig. 6A is a circuit diagram showing a configuration example of an output circuit, Figure 6B is a timing chart showing an operation example of the output circuit. Figure 7 is a timing chart showing an operation example of the storage device. Figure 8 is a timing chart showing an operation example of the storage device. Fig. 9 It is a schematic diagram of the output waveform of the readout bit line and the readout circuit. Fig.10 is a circuit diagram showing a structural example of a memory cell. Fig.11 1 is a perspective schematic diagram showing a configuration example of a chip of an application processor. Fig. 12A is a block diagram showing a configuration example of an arithmetic processing device, Fig. 12B is a block diagram schematically illustrating an example of a stack of a processing engine and an embedded storage device. Fig.13 is a schematic diagram showing a structural example of an electronic device. Fig.14A and Fig. 14B is a cross-sectional view showing a structural example of an OS transistor. Fig.15A This is the circuit diagram of the 4-stage shift register that was manufactured. Fig. 15B 1 is a diagram showing operating waveforms of a 4-stage shift register. Fig.16 It is a diagram showing the calculation results of the read access time of the memory cell. Fig.17A and Fig. 17B Shmoo plots (VDDM / VH vs. tWPW) and (VDDM / VH vs. tRAC) of the memory device at room temperature. Fig.18A is the circuit diagram of the test circuit, Fig.18B is a diagram showing the measurement results of the current-voltage characteristics of the readout transistor, Fig.18C is a diagram showing calculation results of the threshold voltage of the read transistor. Fig.19A is the circuit diagram of the test circuit, Fig.19B It shows the voltage V SN Graph of the calculation results. Fig. 20A This is a microscope photo of the storage device. Fig. 20B is a table showing the specifications of the storage device. DETAILED DESCRIPTION

[0025] The following describes an embodiment of the present invention. Note that one embodiment of the present invention is not limited to the following description, and a person skilled in the art can easily understand that the embodiment and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the contents described in the following embodiment and examples.

[0026] The multiple embodiments and examples shown below can be appropriately combined. In addition, when multiple structural examples (including examples of manufacturing methods, examples of working methods, examples of using methods, etc.) are shown in one embodiment, both the structural examples of each other can be appropriately combined, and one or more structural examples described in other embodiments can be appropriately combined.

[0027] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values ​​shown in the drawings. For example, the unevenness of signals, voltages or currents caused by noise or timing deviations may be included.

[0028] [Implementation Method 1] As an example of a semiconductor device, a memory device formed of an OS transistor will be described. Figure 1A The memory device 100 shown includes a memory cell array 110 and a peripheral circuit 120. Voltages such as VDDM, VSSM, and Vbg1 to Vbg3 are input to the memory device 100. The voltages VDDM and VSSM are respectively a high power supply voltage and a low power supply voltage. For example, the voltage VSSM is a ground potential (GND).

[0029] The memory cell array 110 and the peripheral circuit 120 are composed of OS transistors. The memory cell array 110 includes a plurality of memory cells 11. For example, the memory cells 11 are arranged in 32 rows and 32 columns. The peripheral circuit 120 includes a row decoder 122, a write circuit 124, a read circuit 125, and an output circuit 126. Data DIN[31:0], address signals RA[4:0], RAB[4:0], and various control signals are input to the peripheral circuit 120. For example, the storage width of the memory device 100 is 32 bits, and the data DIN[31:0] and DOUT[31:0] are write data and read data, respectively.

[0030] As metal oxides used in OS transistors, there are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide and In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf), etc. In addition, the oxide containing indium and zinc may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium, etc. In addition, in this specification, metal oxynitrides such as In-M-Zn oxynitride are included in the category of metal oxides.

[0031] In order to improve the reliability and electrical characteristics of OS transistors, it is preferred to use metal oxides including crystalline parts such as CAAC-OS and nc-OS. CAAC-OS is the abbreviation of c-axis-aligned crystalline oxide semiconductor. CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the direction of the lattice arrangement changes between the area where the lattice arrangement is consistent and other areas where the lattice arrangement is consistent in the area where multiple nanocrystals are connected. nc-OS is the abbreviation of nanocrystalline oxide semiconductor.

[0032] Since the band gap of metal oxide is large (e.g., 2.5 eV or more), the off-state current of OS transistor is extremely low. For example, the off-state current can be set to less than 1×10 -20 A. Less than 1×10 -22 A or less than 1×10 -24A. The extremely small off-state current can achieve an on / off ratio of the drain current of more than 20 digits and less than 150 digits. As a result, the amount of charge leaked from the retention node through the OS transistor in the memory element using the OS transistor is extremely small, so it can be used as a nonvolatile memory element.

[0033] Since the band gap of metal oxide is large, electrons are not easily excited, and the effective mass of holes is large, OS transistors are sometimes less likely to experience avalanche breakdown than general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can sometimes be suppressed. By being able to suppress hot carrier degradation, OS transistors can be driven with a high drain voltage.

[0034] OS transistors are accumulation-type transistors with electrons as majority carriers. Therefore, compared with inversion transistors with pn junctions (typically Si transistors), the OS transistors are less affected by DIBL (Drain-Induced Barrier Lowering), one of the short channel effects. In other words, OS transistors are more resistant to short channel effects than Si transistors.

[0035] Due to its high resistance to short channel effects, the channel length of OS transistors can be reduced without reducing the reliability of OS transistors. Therefore, the integration of circuits can be improved by using OS transistors. As the channel length is miniaturized, the drain electric field becomes stronger, but as mentioned above, OS transistors are less prone to avalanche breakdown than Si transistors.

[0036] Since OS transistors are highly resistant to short channel effects, the gate insulating layer can be made thicker than that of Si transistors. For example, even micro OS transistors with a channel length and a channel width of less than 50nm can sometimes be provided with a thicker gate insulating layer of about 10nm. Since the gate parasitic capacitance is reduced by the thick gate insulating layer, the operating speed of the circuit can be increased. The gate leakage current is reduced, so the static power consumption can be reduced.

[0037] 〈〈Storage Unit〉〉 like Figure 1B As shown, the memory cell 11 is electrically connected to the write word line WWL, the read word line RWL, the write bit line WBL, the read bit line RBL, the wiring PL and BGC1 to BGC3. For example, the voltages VDDM, Vbg1, Vbg2 and Vbg3 are input to the wiring PL and BGC1 to BGC3, respectively.

[0038] The memory cell 11 is a 3T1C type gain cell and includes transistors M1 to M3, a capacitor CS1, and a node SN. The transistors M1 to M3 are respectively a write transistor, a read transistor, and a select transistor. The node SN is a holding node.

[0039] The gate, source, drain and back gate of transistor M1 are electrically connected to write word line WWL, node SN, write bit line WBL and wiring BGC1, respectively. The gate, source, drain and back gate of transistor M2 are electrically connected to node SN, read bit line RBL, source of transistor M3 and wiring BGC2, respectively. The gate, drain and back gate of transistor M3 are electrically connected to read word line RWL, wiring PL and BGC3, respectively. The first terminal and the second terminal of capacitor CS1 are electrically connected to node SN and read bit line RBL, respectively.

[0040] Data is written by charging and discharging the node SN, and data is read by turning on the transistor M3. Thus, the memory cell 11 is not limited in the number of rewrites in principle, and data is written and read with low energy, and data is retained without consuming power. Since the transistor M1 is an OS transistor with an extremely low off-state current, the memory cell 11 has a high data retention characteristic.

[0041] By inputting voltages Vbg1 to Vbg3 to the back gates of transistors M1 to M3, the threshold voltages (hereinafter sometimes referred to as Vt) of transistors M1 to M3 can be set. It is preferred to provide a back gate at least in transistor M2. As described later, by shifting the Vt of transistor M2 to the negative voltage side by voltage Vbg2, high data retention characteristics can be obtained and the readout speed can be increased.

[0042] 〈〈Memory Cell Array〉〉 Figure 2 2 shows an example of a circuit structure of the memory cell array 110. Two adjacent rows share a wiring PL. In the memory cell array 110, for example, two adjacent columns may share a wiring PL. Alternatively, two adjacent rows may share a part or all of the wirings BGC1 to BGC3.

[0043] In this specification, when it is necessary to specify one of a plurality of read bit lines RBL, it is recorded as read bit line RBL〈0〉 or the like. In addition, when it is recorded as read bit line RBL, it represents an arbitrary read bit line RBL. The same applies to other components. For example, read bit line RBL〈0〉 represents the read bit line of row 0, and memory cell 11〈31,0〉 represents memory cell 11 of row 31 and column 0. In order to distinguish the elements of a specified memory cell 11 from the elements of other memory cells 11, symbols with row numbers and column numbers are sometimes used. For example, transistor M1〈0,0〉 represents transistor M1 of memory cell 11〈0,0〉.

[0044] 〈〈Peripheral Circuit〉〉 The peripheral circuit 120 is composed of transistors of a single conductivity type (here, n-channel type). It is relatively easy to control the conductivity type of silicon by impurity introduction technology. In contrast, it is very difficult to control the conductivity type of metal oxide semiconductors. For example, n-type semiconductors can be manufactured in metal oxides containing indium (for example, In oxide) or in metal oxides containing zinc (for example, Zn oxide), but p-type semiconductors have not yet been manufactured. A complementary logic circuit (also called a CMOS logic circuit) at a practical level composed only of OS transistors has not yet been manufactured. Therefore, as the peripheral circuit 120, a logic circuit composed of single conductivity type (here, n-channel type) transistors is used instead of a complementary logic circuit. In this specification, a circuit composed of single conductivity type transistors is sometimes referred to as a "single conductivity type circuit".

[0045] A dynamic logic circuit is used as the peripheral circuit 120. The dynamic logic circuit needs to maintain the voltage of the dynamic node during the evaluation period. Si transistors do not have sufficient shutdown characteristics, so the dynamic logic circuit composed of Si transistors does not maintain the voltage of the dynamic node when the operating frequency is too low or when the clock signal stops. In contrast, the off-state current of the OS transistor in the dynamic logic circuit composed of OS transistors (hereinafter sometimes referred to as "OS dynamic logic circuit") is extremely low, so the leakage of charge from the dynamic node can be suppressed. In other words, since the frequency of the clock signal does not need to be set higher than the required frequency, dynamic power consumption can be suppressed. Furthermore, clock gating and power gating can be performed. The characteristics of such an OS dynamic logic circuit are specifically described in Example 1.

[0046] Generally speaking, a dynamic logic circuit can further reduce the number of transistors compared to a static logic circuit. In an OS dynamic logic circuit, there is no need to provide a circuit (e.g., a holding circuit) for maintaining the voltage of a dynamic node. Thus, by using an OS dynamic logic circuit in the peripheral circuit 120, the area of ​​the memory device 100 can be reduced.

[0047] Below, refer to Figures 3 to 5 , Fig. 6A , Figure 6B , Figures 7 to 9 The specific structure of the peripheral circuit 120 will be described.

[0048] <Line Decoder 122> like Figure 3 As shown, the row decoder 122 is input with voltages VDDM, VSSM, address signals RA[4:0], RAB[4:0], and signals WE, RE, PREN, and PREP.

[0049] The signal WE and the signal RE are a write enable signal and a read enable signal, respectively. The signals WE and RE set the state of the storage device 100. When the signals WE and RE are both "L" (low level), the storage device 100 is in a standby state. The storage device 100 writes data when the signal WE is "H" (high level), and reads data when the signal RE is "H".

[0050] The signal PREP and the signal PREN are inversely related. In the OS dynamic logic circuit, the signals PREN and PREP are used as clock signals to control the precharge or predischarge of the dynamic node.

[0051] The row decoder 122 includes a decoder 130 and a word line driver 132. The decoder 130 has a function of decoding the address signals RA[4:0] and RAB[4:0] to specify a row to be accessed. The word line driver 132 has a function of selecting a write word line WWL or a read word line RWL of the row specified by the decoder 130 (also called asserting).

[0052] (Decoder 130) The decoder 130 is composed of a precharge type pass transistor logic circuit, including a transistor M19 and a plurality of circuits 20. The plurality of circuits 20 are arranged in a manner to form a complete binary tree structure of height 4, and the number of circuits 20 is 31 (=2 5 -1). A transistor M19 is provided between the input node of the circuit 20 provided at the root of the binary tree structure and the power supply line for the voltage VDDM. A signal PREN is input to the gate of the transistor M19. The transistor M19 is used as a pull-up circuit. The signal PREN is used as an enable signal of the decoder 130.

[0053] Note that in this specification, a power supply line for the voltage VDDM may be referred to as a “VDDM line.” Other power supply lines may also be referred to similarly.

[0054] The word line driver 132 includes 32 circuits 22. The circuits 22 are electrically connected to the circuits 20 provided at the leaves of the binary tree structure. Two output nodes of the circuit 22<j> (j is an integer from 0 to 31) are electrically connected to the write word line WWL<j> and the read word line RWL<j>, respectively.

[0055] Figure 4 The following is a structural example of a circuit 20 configured at a depth p (p is an integer from 0 to 4). The circuit 20 is a transfer transistor logic circuit composed of transistors M20 and M21. In the circuit 20, the node A0 is an input node, and the nodes X1 and X0 are output nodes. The address signals RA[4-p] and RAB[4-p] are input to the gates of the transistors M20 and M21, respectively.

[0056] The circuit 20 is used as a 1-input-2-output demultiplexer. When the address signal RA[4-p] is "H" (="1"), the node A0 is connected to the node X1, and when the address signal RA[4-p] is "L" (="0"), the node A0 is connected to the node X0.

[0057] In transistor M19, the back gate is connected to the gate. As a result, the Vt of transistor M19 changes dynamically. When transistor M19 is turned on, a positive voltage equal to the gate is input to the back gate, and the Vt of transistor M19 drifts to the negative voltage side, so the current driving capability of transistor M19 is improved. As a result, the drop in output voltage caused by Vt (hereinafter sometimes referred to as "Vt drop") can be suppressed. Similarly, the Vt of transistors M20 and M21 also changes dynamically.

[0058] The node A0 of the circuit 20 of the last stage is electrically connected in series with six OS transistors. By electrically connecting the back gate and the gate of each OS transistor, the operating speed of the decoder 130 can be increased and the voltage drop of the output node can be suppressed.

[0059] (Word line driver 132) like Figure 5 As shown, circuit 22 is a discharge type dynamic logic circuit, including transistors M23 to M28, nodes A1, Y1, and Y2. Node A1 is an input node, electrically connected to node X0 or X1 of the last stage circuit 20. Nodes Y1 and Y2 are dynamic nodes, electrically connected to the write word line WWL and the read word line RWL, respectively.

[0060] The gates of transistors M23 and M24 are input with a signal PREP, the gates of transistors M25 and M28 are input with a signal RE, and the gates of transistors M26 and M27 are input with a signal WE. The back gates of transistors M23 to M28 are electrically connected to the gates, respectively. By forming the circuit 22 with OS transistors electrically connected to the back gates and the gates, it is possible to increase the operating speed without inputting a Vt control voltage from the outside.

[0061] Transistors M23 and M25 are electrically connected in parallel between node Y1 and a power supply line for voltage VSSM (hereinafter referred to as "VSSM line"). Transistors M24 and M26 are electrically connected in parallel between node Y2 and the VSSM line. Transistor M27 controls conduction between node A1 and node Y1, and transistor M28 controls conduction between node A1 and node Y2.

[0062] The period when the signal PREP is "H" is the discharge period, and the period when the signal PREP is "L" is the evaluation period. During the discharge period, the voltages of nodes Y1 and Y2 are initialized to "L". Specifically, since transistors M23 and M24 are turned on, voltage VSSM is input to nodes Y1 and Y2, respectively. As a result, during the discharge period, the write word line WWL and the read word line RWL are in a non-selected state.

[0063] Signals WE and RE are used as enable signals for circuit 22. During the evaluation period, when signal WE or RE becomes "H", circuit 22 becomes active, and the logic of node Y1 or node Y2 is determined according to the logic of node A1. Specifically, when signal WE is "H", it is determined whether the write word line WWL is in a selected state or a non-selected state. On the other hand, when signal RE becomes "H", it is determined whether the read word line RWL is in a selected state or a non-selected state.

[0064] When the signal WE is "H", the voltage VSSM is input to the read word line RWL, so the read word line RWL maintains a non-selected state. The write word line WWL is electrically connected to the node A1, so it becomes a selected state when the voltage of the node A1 is "H", and maintains a non-selected state when the voltage of the node A1 is "L". When the signal RE is "H", the voltage VSSM is input to the write word line WWL, so the write word line WWL maintains a non-selected state. The read word line RWL is electrically connected to the node A1, so it is in a selected state when the voltage of the node A1 is "H", and maintains a non-selected state when the voltage of the node A1 is "L".

[0065] <Write Circuit 124> In the write circuit 124, each write bit line WBL is provided with Figure 5 The circuit 24 shown includes nodes A3, Y3, and transistors M41 to M44.

[0066] Nodes A3 and Y3 are input nodes and output nodes, respectively. In circuit 24 (i is an integer from 0 to 31), data DIN[i] is input to node A3, and node Y3 is electrically connected to write bit line WBL.

[0067] Transistors M41 to M44 are electrically connected in series between the VSSM line and the VDDM line. The gate of transistor M42 is node A3, and the connection node between the drain of transistor M41 and the source of transistor M42 is node Y3. Signals PREP, PREN, and WE are input to the gates of transistors M41, M43, and M44, respectively. In transistors M41 to M44, the back gates are electrically connected to the gates. By forming circuit 24 with OS transistors electrically connected to the back gates and the gates, the operating speed of circuit 24 can be increased without inputting a Vt control voltage from the outside.

[0068] Circuit 24 is a discharge type dynamic logic circuit, and node Y3 is a dynamic node. Signals PREP and PREN are used as clock signals of circuit 24. The period when signal PREP is "H" is the discharge period, and the period when signal PREP is "L" is the evaluation period. During the discharge period, voltage VSSM is input to node Y3 to discharge node Y3. During the evaluation period, when signal WE is "H", the logic of node Y3 becomes the same as the logic of node A3. In other words, when signal WE of "H" is input, circuit 24 inputs data DIN to write bit line WBL.

[0069] <Readout Circuit 125> In the read circuit 125, a circuit 25 (see Figure 5 ). Circuit 25 includes transistors M51 to M54, nodes A4, and Y4. Node A4 is an input node and is electrically connected to a read bit line RBL. Node Y4 is an output node and outputs data RO read from the read bit line RBL. Node Y4 is electrically connected to circuit 26 provided in output circuit 126. As described later, circuit 26 is used as an output buffer circuit.

[0070] Transistors M52, M51, and M53 are electrically connected in series between the VSSM line and the VDDM line. The connection node between the drain of transistor M51 and the source of transistor M53 is node Y4. The gate of transistor M51 is electrically connected to node A4, and signals CRE and CREB are input to the gates of transistors M52 and M53, respectively. Signal CRE and signal CREB are inversely related. The back gates of transistors M51 and M52 are electrically connected to voltages BGR1 and BGR2 by power supply lines. In transistor M53, the back gate is electrically connected to the gate.

[0071] In transistor M54, the gate is electrically connected to the back gate, and a signal RST is input to the gate. Transistor M54 controls the conduction between node A4 and the voltage VCH power line. Transistor M54 is used as a reset circuit for initializing the voltage of node A4. Signal RST controls the initialization of node A4. When transistor M54 is turned on, node A4 is fixed to voltage VCH. The initialization work of node A4 is to discharge the read bit line RBL and make the voltage of the read bit line RBL "L". As a result, voltage VCH is lower than voltage VDDM and is a low voltage (for example, a voltage equal to voltage VSSM).

[0072] Circuit 25 is a charging type dynamic logic circuit. Node Y4 is a dynamic node. Signals CRE and CREB are used as clock signals of circuit 25. The period when signal CREB is "H" is the charging period, and the period when signal CREB is "L" is the evaluation period. During the charging period, voltage VDDM is input to node Y4. During the evaluation period, transistor M53 is turned off and transistor M52 is turned on, so the voltage of node Y4 changes according to the voltage of node A4. Specifically, when the voltage of node A4 is "H" / "L", the voltage of node Y4 is "L" / "H".

[0073] The back gate voltage of transistors M51 and M52 is adjustable, so the readout speed can be increased. Preferably, at least the back gate voltage of transistor M51 can be adjusted. For example, in order to improve the on-state current characteristic of transistor M51, voltage BGR1 is preferably greater than voltage VSSM. By drifting Vt of transistor M51 to the negative voltage side, the time required for the voltage of node Y4 to become a voltage that can perform data determination during the evaluation period can be shortened. For example, by using a voltage equal to "H" supplied as signal CRE or a voltage equal to voltage VDDM as voltage BGR1, the number of voltages used by circuit 25 is not increased.

[0074] For example, the voltage BGR2 may be equal to the voltage BGR1. By improving the on-state current characteristics of both transistors M51 and M52, the time required for the voltage at the node Y4 to reach a voltage that can be used for data determination can be further shortened.

[0075] <Output circuit 126> The output circuit 126 includes 32 circuits 26. The circuits 26 generate data DO from data RO and temporarily hold the data DO. Fig. 6A As shown, circuit 26 includes nodes A5, A6, B5, B6, Y5, transistors M60 to M67, and capacitors CO1 and CO2. Voltages VDDM, VDDM1 to VDDM3, VSSM, VSSM1 to VSSM3, VBGINV, VBGO, VBGDD, VBGSS, and signals SGD1 and SGD2 are input to circuit 26. Node A5 is electrically connected to node Y4 of circuit 25. For example, voltage VDDM3 is a high power supply voltage, and voltage VDDM1 is a voltage higher than voltage VDDM2. Voltages VSSM1, VSSM2, and VSSM3 are low power supply voltages. In the present embodiment, voltage VDDM is set to 3.3V, voltage VDDM1 is set to 4.0V, and voltage VDDM3 is set to 5.0V. In addition, voltage VSSM, voltage VSSM1, voltage VSSM2, and voltage VSSM3 are set to 0V.

[0076] Transistors M60 and M61 constitute an inverter circuit 26A. The inverter circuit 26A inverts data RO to generate data ROB. Transistor M61 has a diode-connected structure, and voltage VBGINV is input to the back gate. In transistor M60, the gate is electrically connected to the back gate. The gate of transistor M60 is electrically connected to node A5, and data RO is input. Node B5 is an output node of the inverter circuit 26A.

[0077] For example, by shifting the Vt of the transistor M61 toward the negative voltage side by the voltage VBGINV, the operating speed of the inverter circuit 26A can be increased. Alternatively, the back gate and the gate of the transistor M61 can be electrically connected to dynamically change the Vt.

[0078] Capacitors CO1, CO2, and transistors M62 to M67 constitute an output buffer circuit 26B. The output buffer circuit 26B is a differential input, capacitive coupling type buffer circuit. The two terminals of capacitor CO1 are electrically connected to nodes A5 and A6, respectively, and the two terminals of capacitor CO2 are electrically connected to nodes B5 and B6, respectively. Nodes A6 and B6 are electrically connected to the gates of transistors M66 and M67, respectively. The connection node between the source of transistor M66 and the drain of transistor M67 is node Y5.

[0079] The gates of transistors M62 and M64 are respectively input with voltages VGS1 and VGS2, and the gates of transistors M63 and M65 are respectively input with signals SGD1 and SGD2. The back gates of transistors M62 to M65 are respectively input with voltage VBGO, and the back gates of transistors M66 and M67 are respectively input with voltages VBGDD and VBGSS.

[0080] Transistors M62 and M64 are used as current sources for inputting bias currents to nodes A6 and B6. Transistors M63 and M65 are used as reset circuits for initializing nodes A6 and B6, respectively. Transistors M66 and M67 form a buffer circuit for outputting signals corresponding to the voltages of nodes A6 and B6 from node Y5.

[0081] Since the back gate voltages of transistors M62 to M67 can be adjusted, the driving capability of the output buffer circuit 26B can be improved and stable operation can be achieved. Fig. 6A In the example shown, the voltage VBGO is input to the back gates of the transistors M62 to M65, but different voltages may be input to some of the back gates. Alternatively, the gate and the back gate are electrically connected in some of the transistors M62 to M67.

[0082] Reference Figure 6BAn example of the operation of the circuit 26 is described. First, the circuit 26 is initialized. Specifically, an initial voltage is input to the nodes A6 and B6. The signals SGD1 and SGD2 are set to "H" to turn on the transistors M63 and M65. For example, the signal SGD1 is set to 7.0V and the signal SGD2 is set to 3.3V. As a result, the voltage VDDM1 (4.0V) is supplied to the node A6, and the voltage VDDM2 (1.0V) is input to the node B6. The voltages VDDM1, VDDM2, VBGDD, VBGSS, etc. are set to voltages that turn on the transistor M66 and turn off the transistor M67 through the initialization operation.

[0083] exist Figure 6B In the example of FIG. 1 , during the initialization operation period, the "H" signals RST and CREB and the "L" signal CRE are input to the circuit 25, and the "H" data RO is input to the node A5. Thus, the voltage VSSM3 is input to the node B5.

[0084] When the signals SGD1 and SGD2 are set to "L" (voltage VSSM), the transistors M63 and M65 are turned off, and the initialization work of the nodes A6 and B6 is completed. After the initialization work, the node A5 is capacitively coupled to the node A6 and the node B5 is capacitively coupled to the node B6, so the voltages of the nodes A6 and B6 change according to the voltages of the nodes A5 and B5, respectively. When the data RO input to the node A5 changes from "H" to "L", the voltage of the node A6 decreases and the transistor M66 is turned off. In addition, the transistor M60 is turned off and the voltage of the node B5 rises. As a result, the voltage of the node B6 also rises and the transistor M67 is turned on, and the node Y5 outputs "L" (voltage VSSM) as the data DO. In contrast, when "H" is input to the node A5 as the data RO, the node Y5 outputs "H" as the data DO.

[0085] When the voltage VDDM1 is equal to the voltage VDDM, when "H" is input to the node A5, a voltage smaller than the voltage VDDM by the Vt of the transistor M66 is output as the data DO. By making the voltage VDDM1 greater than the voltage VDDM, the voltage drop of the data DO when "H" is input to the node A5 can be suppressed. In addition, by separating the node A5 and the node A6 by the capacitor CO1 and performing the above-mentioned initialization operation, the output of the data DO can be switched by the charge and discharge of the node A5 during actual operation. Similarly, by separating the node B5 and the node B6 by the capacitor CO2 and performing the above-mentioned initialization operation, the output of the data DO can be switched by the charge and discharge of the node B5 during actual operation. That is, the charge and discharge of the nodes A6 and B6 are not required, thereby increasing the operating speed of the circuit 26.

[0086] 〈〈Work Examples〉〉 Figure 7 , Figure 8 is a timing chart for explaining an example of the operation of the storage device 100. Figure 8 In the figure, tWCY is the write cycle time, tWPW is the write pulse width, tRCY is the read cycle time, and tRAC is the read access time. (a1), (a2), (a3) ​​are addresses, and ( / a1), ( / a2), ( / a3) are inverted addresses of (a1), (a2), (a3). Data RO[31:0] is data read from the memory cell array 110 by the read circuit 125. Data (a1) is data written to the memory cell 11 at the address (a1), and data (a2) is data read from the memory cell 11 at the address (a2).

[0087] 〈Initialization work, standby state〉 The initialization operation is an operation to set the operation of the memory device 100 to a state in which writing and reading operations can be performed, and is performed, for example, after the power is turned on. Specifically, initial voltages are input to the read bit line RBL and the nodes A6 and B6 of the circuit 26, respectively.

[0088] like Figure 7 As shown, signals PREP, CREB, SGD1, and SGD2 become "H". Signals WE and RE are "L". In circuit 25, voltage VCH is input to read bit line RBL. In circuit 25, transistor M53 is turned on and node Y4 is fixed to voltage VDDM. Therefore, read circuit 125 outputs ffffffff (hexadecimal) as data RO[31:0]. Voltages VDDM1 and VDDM2 are input to nodes A6 and B6 of circuit 26. When signals SGD1 and SGD2 become "L", storage device 100 enters standby state.

[0089] 〈Writing Work〉 Reference Figure 8 An example of the writing operation will be described. When the signals WE and RE are "H" ("1") and "L" ("0"), respectively, the memory device 100 performs the writing operation.

[0090] During period T1, the write word line WWL and the write bit line WBL are discharged. The signal PREP is "H". The row decoder 122 inputs the voltage VSSM to the write word lines WWL<0> to WWL<31>, and the write circuit 124 inputs the voltage VSSM to the write bit lines WBL<0> to WBL<31>. During the write operation, the row decoder 122 fixes the read word lines RWL<0> to RWL<31> to the voltage VSS.

[0091] During period T2, data is written to the memory cell 11 specified by the address signal RA[4:0]. The signals PREP and PREN are "L" and "H". The write circuit 124 writes data DIN[0] to DIN

[31] to the write bit lines WBL〈0〉 to WBL〈31〉, respectively. The row decoder 122 becomes active and decodes the address signals RA[4:0] and RAB[4:0]. For example, when the address (a1) is "00001", the row decoder 122 outputs a selection signal of "H" to the write word line WWL〈1〉. As a result, the memory cells 11〈1,0〉 to 11〈1,31〉 become selected. The transistors M1〈1,0〉 to M1〈1,31〉 are turned on, and the data DIN[0] to DIN

[31] are written to the nodes SN〈1,0〉 to SN〈1,31〉, respectively. When the signals PREP and PREN become "H" and "L", the writing operation of one cycle is completed and all the memory cells 11 are in a non-selected state.

[0092] Reading Work Reference Figure 8 An example of the read operation will be described. When the signals WE and RE are "L" and "H", the memory device 100 performs the read operation.

[0093] During period T3, the read bit line RBL is reset and the read word line RWL is discharged. Signals PREP, RST, CRE, and CREB are "H", "H", "L", and "H", respectively. The read word lines RWL〈0〉 to RWL〈31〉 are fixed to a voltage VSSM by the row decoder 122. The read bit lines RBL〈0〉 to RBL〈31〉 are fixed to a voltage VCH by the read circuit 125, and the output node (node ​​Y4) of the circuit 25 is fixed to a voltage VDDM. The write word lines WWL〈0〉 to WWL〈31〉 are fixed to a voltage VSS by the row decoder 122 when performing the read operation.

[0094] During period T4, data (a2) is read from the memory cell array 110. Signals PREP and PREN are "L" and "H". The row decoder 122 becomes active and decodes the address signals RA[4:0] and RAB[4:0]. For example, when the address (a2) is "00010", the row decoder 122 outputs a selection signal of "H" to the read word line RWL〈2〉, so that the memory cells 11〈2,0〉 to 11〈2,31〉 become selected. Transistors M3〈2,0〉 to M3〈2,31〉 are turned on respectively, and the retained data of the memory cells 11〈2,0〉 to 11〈2,31〉 are written to the read bit lines RBL〈0〉 to RBL〈31〉 respectively. The read circuit 125 reads the data of the read bit lines RBL〈0〉 to RBL〈31〉 and outputs it as data RO[31:0] to the output circuit 126. More specifically, the voltage of the node Y4 of the circuit 25 is determined according to the voltage of the read bit line RBL. According to the voltage of the node Y4, the circuit 26 outputs "0" ("L") or "1" ("H") as the data DO. The read access time tRAC is the time from when the signals CRE and PREN change from "L" to "H" to when the voltage of the node Y4 is determined to be "0" or "1".

[0095] Reference Figure 5 , Figure 8 , Fig. 9 An operation example of the memory cell 11 and the circuit 25 will be described. Fig. 9 The output waveforms of read bit line RBL and node Y4 during the read operation are schematically shown.

[0096] When the signal RST becomes "H", the transistor M54 is turned on and the read bit line RBL is discharged. Since the parasitic capacitance of the read bit line RBL is large, it is effective to input the specified voltage to the read bit line RBL not by charging but by discharging in order to increase the read speed. When the signal RST becomes "L", the transistor M54 is turned off and the read bit line RBL becomes electrically floating. When the signal RST becomes "H", the transistor M53 is turned on, so the data "1" ("H") is written to the node Y4.

[0097] Next, the signal RST is set to "L", and the voltage of the read word line RWL is set to "H". The transistor M3 is turned on. When data "0" is written to the node SN, the transistor M2 is turned off, so the voltage of the read bit line RBL and the node Y4 does not change. In other words, the data RO is maintained as "1" ("H").

[0098] On the other hand, when data "1" is written to node SN, transistor M2 is turned on. As a result, read bit line RBL is charged using the drain current of transistor M2. Since node SN is capacitively coupled to read bit line RBL, as the voltage of read bit line RBL rises, the voltage of node SN also rises due to the bootstrap effect. As a result, the drain current of transistor M2 increases, and the charging speed of read bit line RBL increases. Then, when transistor M52 is turned on, node Y4 is discharged, and data RO becomes "0" ("L").

[0099] Note that data RO is inverted data of the data held by the memory cell 11. Thus, data DO is also inverted data. In order to make the logic of data DO the same as the logic of the data held by the memory cell 11, the circuit structure of the circuit 26 may be changed to invert data RO. For example, node B5 is electrically connected to capacitor CO1, and node A5 is electrically connected to capacitor CO2.

[0100] In addition, when the capacitor CS1 causes the node SN to be capacitively coupled to the VSSM line, the voltage of the read bit line RBL changes as shown by the dotted line. In this case, the bootstrap effect is not obtained, so the charging speed of the read bit line RBL is slow. During the period when the read word line RWL is in the selected state, the voltage of the read bit line RBL sometimes does not rise to a voltage that can perform data judgment. In other words, by using the bootstrap effect, the read access time tRAC can be shortened, and the read error can be reduced.

[0101] In order to increase the read speed, it is preferred to use the voltage Vbg2 to drift the Vt of the transistor M2 toward the negative voltage side to improve the on-state current characteristics. In this case, the following problem occurs: the leakage current from the non-selected memory cell 11 to the read bit line RBL increases. The leakage current from the non-selected memory cell 11 not only shortens the data retention time, but also causes data read errors. Therefore, in the transistor M3, the off-state current characteristics are prioritized over the on-state current characteristics, so the voltage Vbg3 is lower than the voltage Vbg2.

[0102] In order to retain data for a long time, the off-state current of the transistor M1 is preferably low. Therefore, the voltage Vbg1 is preferably equal to or lower than the voltage Vbg3.

[0103] Since the memory cell 11 has a 3T1C type structure, the Vt drop of the voltage of the read bit line RBL significantly occurs, but the Vt drop of the voltage of the read bit line RBL can be prevented by utilizing the bootstrap effect. In other words, by applying a 3T1C type gain cell having a bootstrap effect as the memory cell 11, a memory device 100 that realizes high data retention characteristics and high operating speed can be provided. Furthermore, it is effective to adopt a charge type dynamic logic circuit as the read circuit 125 in shortening the read access time tRAC.

[0104] (Deformation example of storage unit) Fig.10 Another structural example of a memory cell having a bootstrap effect is shown. Fig.10 The memory cell 12 shown is a modified example of the memory cell 11, and includes transistors M5 to M7, a capacitor CS5, a node SN, and a node N6. The transistors M5 to M7 are respectively a write transistor, a read transistor, and a select transistor. The back gates of the transistors M5 to M7 are electrically connected to the wirings BGC1 to BGC3, respectively. The first terminal and the second terminal of the capacitor CS5 are electrically connected to the nodes SN and N6, respectively. The node N6 is a connection node between the transistor M6 and the transistor M7. The voltages Vbg1 to Vbg3 are set in the same manner as the memory cell 11.

[0105] The memory cell 12 operates in the same manner as the memory cell 11. When the read word line RWL is selected, the transistor M7 is turned on. When the node SN maintains "1", the node N6 is charged by the drain current of the transistor M6. Thus, by the bootstrap effect, the voltage of the node SN rises as the voltage of the node N6 rises. As a result, the speed at which the voltage of the read bit line RBL rises increases.

[0106] No p-channel transistor is used as the memory device 100. Since the number of masks can be reduced, the manufacturing cost can be reduced. Complementary circuits need to be designed so that latch-up does not occur, but the memory device 100 avoids latch-up, so the layout freedom is high and the pattern can be configured at a high density.

[0107] Since a single-conductivity dynamic logic circuit is used, the number of transistors in the peripheral circuit 120 is small. In order to achieve miniaturization and low power consumption of the storage device 100, it is effective to reduce the number of transistors in the peripheral circuit 120. In Table 1, the number of transistors in the peripheral circuit 120 and the number of transistors in the peripheral circuit of the OS storage device of Non-Patent Document 2 are compared. Note that the number of transistors per 32 bit lines of the peripheral circuit 120 is the number of transistors of the read circuit 125, excluding the number of transistors of the output circuit 126. The peripheral circuit of Non-Patent Document 2 is composed of a CMOS static logic circuit. The number of transistors in Non-Patent Document 2 is the approximate number of transistors corresponding to the CMOS static logic circuit of the row decoder 122, the write circuit 124, and the read circuit 125.

[0108] [Table 1]

[0109] As described above, by adopting this embodiment, an OS storage device having high operating speed, high rewrite resistance, high data retention characteristics, low power consumption and a reduced number of transistors can be provided. In Example 2 below, specific performance of the OS storage device of this embodiment is described.

[0110] [Implementation Method 2] The manufacturing process of OS transistors is compatible with the CMOS manufacturing process, and a single conductivity type memory device using OS transistors can be stacked on a CMOS logic circuit. In this embodiment, a semiconductor device including a CMOS circuit using Si transistors and a single conductivity type circuit using OS transistors is described.

[0111] When the memory device of Embodiment 1 is composed of only OS transistors, it is suitable for a memory device of a relatively small scale (for example, 128 bits to 1 M bits).

[0112] For example, the storage device of Embodiment 1 is used for Fig.11 An application processor (AP) 200 is shown with an embedded storage device 205 . Fig.11 Schematic diagram of the chip of AP200. AP200 is a system-on-chip. The chip constituting AP200 has a stacked structure of a CMOS transistor layer 221 and an OS transistor layer 222. In the CMOS transistor layer 221, various functional circuits constituting AP200 are provided, for example, a CPU 210, a bus 211, peripheral circuits 213 and 215, and an input / output interface circuit 217 are provided. In the peripheral circuits 213 and 215, a power supply circuit, a communication circuit, an image processing circuit, an audio processing circuit, etc. are provided.

[0113] A plurality of embedded storage devices 205 are provided in the OS transistor layer 222. The number of embedded storage devices 205 may be one. Data communication between the embedded storage device 205 and the CPU 210 or the like is performed in the CPU 210 via the bus 211. For example, the embedded storage device 205 stores configuration data of the AP 200. In the above-mentioned application, an external EEPROM chip may be used, but in order to realize low cost, miniaturization, low power consumption, etc. of the AP 200, it is effective to use the embedded storage device 205.

[0114] A plurality of OS transistor layers 222 may be stacked on the CMOS transistor layer 221. For example, when two layers of OS transistor layers 222 are provided, a peripheral circuit embedded in the memory device 205 is provided in the lower layer and a memory cell array is provided in the upper layer. Alternatively, a peripheral circuit and a memory cell array are provided in the lower layer and a memory cell array is provided in the upper layer.

[0115] Of course, semiconductor devices to which the memory device of Embodiment 1 can be applied are not limited to application processors, and the memory device of Embodiment 1 can be provided in various semiconductor devices such as a microcontroller unit (MCU), a CPU, a GPU, an FPGA, a camera device, and a display device.

[0116] For example, Fig. 12A The illustrated operation processing device 230 includes a plurality of embedded storage devices 235. The storage device of Embodiment 1 can be used as the embedded storage device 235. The operation processing device 230 also includes a bus interface (I / F) 231 and a plurality of processing engines (PE, Processing Engine) 233. Data is transferred between the operation processing device 230 and an external storage device 239 via the bus I / F 231. For example, a DRAM, a flash memory, an SRAM, etc. can be used as the external storage device 239.

[0117] The chip of the operation processing device 230 has the same stacked structure as AP200. The embedded storage device 235 is set in the OS transistor layer, and the bus I / F 231 and PE233 are set in the CMOS transistor layer. PE233 is composed of a CMOS logic circuit using Si transistors and performs operation processing. Fig. 12B As shown, the embedded memory device 235 is stacked on the PE 233. The embedded memory device 235 includes a memory cell array 236 and a peripheral circuit 237. The memory cell array 236 and the peripheral circuit 237 are composed of OS transistors. Since the number of transistors in the embedded memory device 235 is small, the embedded memory device 235 is stacked on the PE 233 without significantly increasing the occupied area of ​​the transistors. Fig. 12BThe control circuit 224 shown is composed of a CMOS logic circuit. The control circuit 224 generates a control signal for the embedded memory device 235 and controls data transfer between the PE 233 and the bus I / F 231, for example.

[0118] In order to perform parallel computing, multiple PE233 are arranged in an array. In order for the computing device to effectively perform parallel computing, an embedded storage device with low power consumption, high operating speed and high rewrite resistance is required. The embedded storage device 235 can meet such requirements. By arranging the embedded storage device 235 adjacent to the PE233, the time and power required for data transmission can be reduced, and the PE233 can be operated with high efficiency. Since a low-power and high-performance computing device 230 can be provided, the computing device 230 is suitable for scientific computation, machine learning (for example, deep learning), etc., for example, it can be used as an accelerator for machine learning.

[0119] like Fig.13 As shown, the processor chip 7010 in which the storage device 100 according to Embodiment 1 is mounted can be mounted in various electronic devices.

[0120] The robot 7100 includes an illumination sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a moving mechanism, etc. The processor chip 7010 controls the above peripheral devices.

[0121] The microphone has the function of detecting audio signals such as the user's voice and surrounding sounds. In addition, the speaker has the function of emitting audio signals such as sounds and warning sounds. The robot 7100 can analyze the audio signals input through the microphone and emit the required audio signals from the speaker. The robot 7100 can communicate with the user by using the microphone and the speaker.

[0122] The camera has a function of capturing images of the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to determine the presence or absence of obstacles during movement.

[0123] The flying object 7120 includes propellers, a camera, a battery, etc., and has an autonomous flight function. The processor chip 7010 controls the above peripheral devices. For example, the processor chip 7010 can determine the presence or absence of obstacles during movement by analyzing the image data taken by the camera.

[0124] The sweeping robot 7140 includes a display configured on the top surface, multiple cameras configured on the side, a brush, operation buttons and various sensors. Although not shown in the figure, the sweeping robot 7140 is equipped with tires, a suction port, etc. The sweeping robot 7140 can walk automatically, detect garbage, and suck garbage from the suction port on the bottom. For example, the processor chip 7010 can determine the presence or absence of obstacles such as walls, furniture or steps by analyzing the images taken by the camera. In addition, when objects such as wiring that may be wrapped around the brush are detected through image analysis, the rotation of the brush can be stopped.

[0125] The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, etc. For example, the processor chip 7010 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency.

[0126] The processor chip 7010 can be installed in a television receiving (TV) device 7200, a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, 7260, etc. For example, the processor chip 7010 provided in the TV device 7200 can be used as an image engine. For example, the processor chip 7010 performs image processing such as noise removal and up-conversion of resolution. The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the processor chip 7010.

[0127] PC 7220 and 7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a display device 7233 may be connected to PC 7230 wirelessly or by wire. A game console 7240 is an example of a portable game console. A game console 7260 is an example of a fixed game console. The game console 7260 is connected to a controller 7262 wirelessly or by wire. A processor chip 7010 may be installed in the controller 7262.

[0128] [Implementation method 3] Next, refer to Fig.14A and Fig. 14B A structural example of an OS transistor is described. Fig.14A and Fig. 14B The left side of shows a cross section of the OS transistor in the channel length direction, and the right side shows a cross section of the OS transistor in the channel width direction.

[0129] Fig.14AThe OS transistor 5001 shown is formed on an insulating surface. Here, the OS transistor 5001 is formed on an insulating layer 5021. The OS transistor 5001 is covered by insulating layers 5028 and 5029. The OS transistor 5001 includes insulating layers 5022 to 5031, metal oxide layers 5011 to 5013, and conductive layers 5050 to 5054.

[0130] The insulating layer, metal oxide layer, conductive layer, etc. in the drawings may be a single layer or a stacked layer. When manufacturing these layers, various film forming methods such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), chemical vapor deposition (CVD), and atomic layer deposition (ALD) may be used. CVD methods include plasma CVD, thermal CVD, and organometallic CVD.

[0131] The metal oxide layers 5011 to 5013 are collectively referred to as metal oxide layers 5010. Fig.14A As shown, the metal oxide layer 5010 includes a portion in which a metal oxide layer 5011, a metal oxide layer 5012, and a metal oxide layer 5013 are sequentially stacked. When the OS transistor 5001 is in an on state, a channel is mainly formed in the metal oxide layer 5012.

[0132] The gate electrode of the OS transistor 5001 is composed of a conductive layer 5050, and a pair of electrodes used as a source electrode or a drain electrode are composed of conductive layers 5051 and 5052. The metal oxide layer 5010 and the conductive layers 5050 to 5052 are covered by an insulating layer 5031 as a barrier layer. The back gate electrode is composed of a stack of a conductive layer 5053 and a conductive layer 5054. The OS transistor 5001 may not include a back gate electrode. The same is true for the OS transistor 5003 described later. The gate insulating layer on the gate (front gate) side is composed of an insulating layer 5027, and the gate insulating layer on the back gate side is composed of a stack of insulating layers 5024 to 5026.

[0133] Fig.14A The metal oxide layer 5010 is shown as an example of a three-layer structure, but the present invention is not limited thereto. The metal oxide layer 5010 may be, for example, a two-layer structure without the metal oxide layer 5011 or the metal oxide layer 5013, or may be composed of any one layer from the metal oxide layer 5011 to the metal oxide layer 5013. In addition, the metal oxide layer 5010 may be composed of four or more metal oxide layers.

[0134] The conductive material used for the conductive layers 5050 to 5054 includes the following materials: semiconductors represented by polycrystalline silicon doped with impurity elements such as phosphorus; silicides such as nickel silicide; metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitrides containing the above metals as components (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride), etc. In addition, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide may also be used.

[0135] For example, it is preferable that the conductive layer 5053 is a conductive layer having a barrier property against hydrogen (for example, a tantalum nitride layer), and the conductive layer 5054 is a conductive layer (for example, a tungsten layer) having a higher conductivity than the conductive layer 5053. With this structure, the stack of the conductive layer 5053 and the conductive layer 5054 has a function of wiring and a function of suppressing the diffusion of hydrogen into the metal oxide layer 5010.

[0136] As insulating materials used for the insulating layers 5021 to 5031, there are the following materials: aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, and the like. The insulating layers 5021 to 5031 are composed of a single layer or a stacked layer including these insulating materials. The layers constituting the insulating layers 5021 to 5031 may contain a plurality of insulating materials.

[0137] In this specification and the like, an oxynitride refers to a compound containing a larger amount of oxygen than nitrogen, and a nitrogen oxide refers to a compound containing a larger amount of nitrogen than oxygen.

[0138] In the OS transistor 5001, the metal oxide layer 5010 is preferably surrounded by an insulating layer (hereinafter referred to as a barrier layer) having a barrier property to oxygen and hydrogen. By adopting this structure, the release of oxygen from the metal oxide layer 5010 can be suppressed and the intrusion of hydrogen into the metal oxide layer 5010 can be suppressed, thereby improving the reliability and electrical characteristics of the OS transistor 5001. For example, the insulating layer 5031 is used as a barrier layer, and at least one of the insulating layers 5021, 5022, and 5024 is used as a barrier layer. The barrier layer can be formed using materials such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and silicon nitride.

[0139] Fig. 14BThe OS transistor 5003 shown is a modified example of the OS transistor 5001. The main difference between the two is the structure of the gate electrode. A metal oxide layer 5013, an insulating layer 5027 and a conductive layer 5050 are provided in the openings formed in the insulating layers 5028 and 5031. That is, the gate electrode is formed in a self-aligned manner by utilizing the above-mentioned openings. In addition, since the width of the gate electrode can be controlled according to the size of the above-mentioned openings, an OS transistor with a short channel length can be easily manufactured. In addition, since the gate electrode (5050) does not include an area overlapping with the source electrode and the drain electrode (5051, 5052) through the gate insulating layer (5027), the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drain can be reduced and the frequency characteristics can be improved. [Example 1]

[0140] In this embodiment, an OS dynamic logic circuit is described.

[0141] The 4-stage shift register 180 is manufactured by a 60nm OS transistor process. Fig.15A As shown, the 4-stage shift register 180 includes shift registers 181_1 to 181_4, which are input with clock signals φ1 to φ4, voltages VDDD, and VSSS. Shift register 181_1 is an OS dynamic logic circuit, including transistors M81 to M86, nodes IN, Y8, and Y9. Nodes Y8 and Y9 are dynamic nodes. The gate of transistor M83 is an input node, and node Y9 is an output node. Node Y9 is electrically connected to the input node of shift register 181_2. Transistor M81 is an OS transistor, and the channel formation region of transistors M81 to M86 is formed by a crystalline In-Ga-Zn oxide layer. Shift registers 181_2 to 181_4 have the same circuit structure as shift register 181_1.

[0142] Fig. 15B The measurement results of the operating waveforms of the 4-stage shift register 180 are shown. The voltages VSSS and VDDD are 0V and 3.3V respectively. The "L" and "H" of the clock signals φ1 to φ4 are 0V and 5.0V respectively. Fig. 15BIn the figure, signal IN is a pulse signal input to node IN, and signals OUT1 to OUT4 are output signals of shift registers 181_1 to 181_4. Signal IN is shifted sequentially by shift registers 181_1 to 181_3. When the pulse signal drifted by shift register 181_3 is output and clock signal φ4 drops, the input of clock signals φ1 to φ4 and voltage VDDD stops. After 1 second, clock signals φ1 to φ4 and voltage VDDD are input again, so shift register 181_4 outputs the shifted pulse. In other words, after power gating, the 4-stage shift register 180 operates normally. This is because: in power gating, the voltages of nodes Y8 and Y9 of shift registers 181_1 to 181_4 are maintained.

[0143] Thus, this embodiment shows that a dynamic logic circuit using OS transistors can perform power gating even without providing a circuit for maintaining the voltage of a dynamic node. [Example 2]

[0144] In this embodiment, the design, manufacture, performance, etc. of the storage device 100 according to the first embodiment are described.

[0145] 〈Working speed〉 exist Fig.16 In the example, the read access time tRAC of the data "1" in the memory cells 11 and 19 is calculated by simulation. Fig.16 The calculation results are shown. The W / L (channel width / channel length) of transistors M1 to M3 is 60nm / 60nm. The capacitance of capacitor CS1 is 1.2fF. The back gate voltages (Vbg1 to Vbg3) of transistors M1 to M3 are -5V, 8V, and 2V, and the voltages VSSM and VDDM are 0V and 3.3V. The parameters of the manufacturing process are typical values, and the temperature is room temperature (RT).

[0146] The memory cell 19 is a comparative example, and the first terminal and the second terminal of the capacitor CS1 are electrically connected to the node SN and the VSSM line. Except for this point, the structure of the memory cell 19 is the same as that of the memory cell 11. Although the read word line RWL is in the selected state, the bootstrap effect does not occur in the memory cell 19. On the other hand, the bootstrap effect occurs in the memory cell 11, so the read access time tRAC of the memory cell 11 is shortened by 33%. In this way, in order to increase the read speed, it is effective to increase the node SN by the bootstrap effect.

[0147] The memory device 100 is manufactured by a 60 nm OS transistor process. The channel formation region of the OS transistor is formed of a crystalline In-Ga-Zn oxide layer. Fig.17A , Fig. 17BThe shmooth diagrams (VDDM / VH vs. tWPW) and (VDDM / VH vs. tRAC) of the manufactured memory device 100 at room temperature are shown respectively. The voltage VH is the voltage of "H" of the control signal (WE, RE, PREP, etc.). The back gate voltages of the transistors M1 to M3 of the memory cell 11 are -7V, 5V, and 0V. The back gate voltages of the transistors M51 and M52 of the circuit 25 are 5V. When the voltage VDDM / VH is 3.3V / 5.0V, the pulse width tWPW and the read access time tRAC are 20ns and 45ns, respectively. In other words, the write / read time is 20ns / 45ns, and the write / read energy can be 97.9pJ / 58.6pJ.

[0148] 〈Rewrite Resistance 1〉 The test circuit 15 using the 2T1C gain unit is used to perform a write / read (rewrite) cycle test when the ambient temperature is room temperature (27°C). Fig.18A As shown, the test circuit 15 includes transistors M11, M12, capacitor CS11, node SN, write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, and wiring PL. Transistor M11 is a write transistor, and transistor M12 is a read transistor. Transistors M11 and M12 are both OS transistors including a back gate, and the channel formation region is formed by a crystalline In-Ga-Zn oxide layer. W / L of transistors M11 and M12 is 500nm / 500nm and 60nm / 60nm.

[0149] In the write / read cycle test, the back gate of transistor M11 is fixed to -7V, and the back gate of transistor M12 is in an electrically floating state. A voltage of 1.8V is input to the read bit line RBL, and a voltage of 0V is input to the wiring PL. The pulse width tWPW in the write cycle and the read cycle are 10ns and 100ns respectively. The "H" / "L" of the write word line WWL is 3.3V / 0V, and the "H" / "L" of the write bit line WBL is 1.8V / 0V.

[0150] In the write cycle, data "1" and "0" are alternately written to the node SN. Each time the number of write cycles of data "1" (or "0") reaches 10, the cumulative number of write cycles of data "1" (or "0") reaches 10. n (n is an integer from 0 to 14) to perform a read cycle. In the read cycle, data "1" or "0" is first written to the node SN, and then the data read operation is repeated to measure the I PL -V RWL characteristic. I PL is the current flowing through wiring PL, V RWL is the voltage of the read word line RWL. In the read cycle of data "1", the voltage V RWLThe voltage changes from -3.0 V to 1.0 V at intervals of +0.05 V, and changes from 0 V to 4.0 V at intervals of +0.05 V in a read cycle of data "0". Fig.18B I shows that data "1" / "0" is maintained at node SN PL -V RWL Characteristic curve. Using square root extrapolation from the measured I PL -V RWL The characteristic curve calculates the Vt of transistor M12. Fig.18C The calculation results are shown in Figure 1. The difference in Vt between holding data "1" and holding data "0" is 10 14 After the first write cycle, it is about 2.5V. 14 After the first write cycle, the two states can also be distinguished with sufficient margin.

[0151] The results of the write / read cycle test show that the memory device 100 using the test circuit 15 can withstand 10 14 cycles, which means that the memory device 100 using the test circuit 15 has high rewrite resistance.

[0152] Rewrite Patience 2 use Fig.19A The test circuit 16 shown performs a write / read (rewrite) cycle test at an ambient temperature of 85°C. The test circuit 16 is a 2T1C gain unit similar to the test circuit 15. The difference between the test circuit 16 and the test circuit 15 is that the test circuit 16 uses a transistor M13 of a p-channel Si transistor (bulk transistor) instead of the transistor M12. Like the transistor M12, the transistor M13 is also used as a read transistor.

[0153] In the write / read cycle test using the test circuit 16, the back gate of the transistor M11 is fixed to -3 V. A voltage of 0 V is input to the read bit line RBL, and a voltage of 1.2 V is input to the wiring PL. The "H" / "L" of the write word line WWL is 2.5 V / -0.8 V, and the "H" / "L" of the write bit line WBL is 1.2 V / 0 V.

[0154] Similar to the write / read cycle test using the test circuit 15 , in the write cycle, data “1” and “0” are alternately written to the node SN.

[0155] In addition, the cumulative number of write cycles of data "1" (or "0") reaches 10 n (n is an integer from 0 to 14), and a read cycle is performed. In the write / read cycle test using the test circuit 16, I is measured when the read cycle is performed. PL , from I PL The voltage V at the node SN is calculated from the value ofSN .

[0156] Fig.19B Shown V SN The calculation results are as follows. 14 After the write cycle, V when data "1" is maintained SN is 0.63V, V when data is kept at "0" SN is 0.01V. When the data is kept "1", V SN When the data is kept "0", V SN The difference is about 0.62V. Therefore, even in 10 14 After a write cycle, two states can also be distinguished.

[0157] The results of the write / read cycle test show that the memory device 100 using the test circuit 16 can withstand 10 cycles even at an ambient temperature of 85°C. 14 cycles, which means that the memory device 100 using the test circuit 16 has high rewrite resistance.

[0158] <Specification> Fig. 20A A microscope photograph of the memory device 100 using the test circuit 15 is shown. Note that the output circuit 126 is not shown. Fig. 20A middle.

[0159] Fig. 20B The specifications of the memory device 100 are shown. At room temperature, the static power (standby power) of the memory device 100 in the standby state is 9.9nW, and the active power when performing writing and reading operations is 97.9μW / MHz and 258.6μW / MHz. When the load capacitance of the circuit 25 is assumed to be 10fF, the active power is calculated to be 123.6W / MHz. Based on the above standby power and the calculated active power, the active power is estimated to be 133.7μW / MHz when the storage capacity of the memory cell array 110 is expanded to 1Mbit. Therefore, the power consumption of the memory device 100 is low.

[0160] <in conclusion> The 1k-bit OS memory device is manufactured using a 60nm OS transistor process. The write time is 20ns and the read time is 45ns. In addition, the OS memory device can withstand 10 14 The OS storage device manufactured can meet the performance requirements of embedded storage devices, such as high operating speed and low power consumption. Explanation of symbols

[0161] 11, 12, 19: storage unit; 15, 16: test circuit; 20, 22, 24, 25, 26: circuit; 26A: inverter circuit; 26B: output buffer circuit; 100: storage device; 110: storage cell array; 120: peripheral circuit; 122: row decoder; 124: write circuit; 125: read circuit; 126: output circuit; 130: decoder; 132: word line driver; 180: 4-stage shift register; 181_1, 181_2, 181_3, 181_4: shift register; 200: application processor (AP); 205: embedded storage device; 210: CPU; 211: bus; 21 3,215: peripheral circuit; 217: input / output interface circuit; 221: CMOS transistor layer; 222: OS transistor layer; 224: control circuit; 230: operation processing device; 233: processing engine (PE); 235: embedded storage device; 236: storage cell array; 237: peripheral circuit; 239: external storage device; 5001,5003: OS transistor; 5010,5011,5012,5013: metal oxide layer; 5021,5022,5023,5024,5025,5026,5027,5028,5029,5030,5031: insulation layer; 5050,5051 051, 5052, 5053, 5054: conductive layer; 7010: processor chip; 7100: robot; 7120: flying object; 7140: sweeping robot; 7160: car; 7200: television receiving (TV) device; 7210: smart phone; 7220: personal computer (PC); 7230: personal computer (PC); 7232: keyboard; 7233: display device; 7240: game console; 7260: game console; 7262: controller; A0, A1, A3, A4, A5, A6, B5, B6, N6, SN, X0, X1, Y1, Y2, Y3, Y4, Y5: node; CO1, CO2, CS1, CS5, CS11: capacitors; M1, M2, M3, M5, M6, M7, M11, M12, M19, M20, M21, M23, M24, M25, M26, M27, M28, M41, M42, M43, M44, M51, M52, M53, M54, M60, M61, M62, M63, M64, M65, M66, M67, M81, M82, M83, M84, M85, M86: transistors; BGL1, BGL2, BGL3, PL: wiring; RBL: read bit line; RWL: read word line; WBL: write bit line; WWL: write word line. This application is based on Japanese Patent Application No. 2017-225312 filed with the Japan Patent Office on November 24, 2017 and Japanese Patent Application No. 2018-169677 filed with the Japan Patent Office on September 11, 2018, the entire contents of which are incorporated herein by reference.

Claims

1. A dynamic logic circuit, comprising: Input node; a first wiring, a second wiring, a third wiring, and a fourth wiring; as well as a first transistor, a second transistor, a third transistor and a fourth transistor of a single conductivity type, wherein a first signal is input to a gate of the first transistor, The source and drain of the first transistor are electrically connected to the first wiring and the input node, respectively. The second transistor, the third transistor, and the fourth transistor are electrically connected in series between the second wiring and the third wiring, A second signal is input to the gate of the second transistor, An inversion signal of the second signal is input to the gate of the fourth transistor, The gate of the third transistor is electrically connected to the input node, The third transistor comprises a back gate, Furthermore, the back gate is electrically connected to the fourth wiring.

2. The dynamic logic circuit according to claim 1, further comprising a fifth wiring, wherein the second transistor comprises a back gate, And the back gate is electrically connected to the fifth wiring.

3. A dynamic logic circuit, comprising: Input node; A first dynamic node and a second dynamic node; as well as a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor of a single conductivity type, wherein the drains of the first transistor, the second transistor and the third transistor are electrically connected to the first dynamic node, The drains of the fourth transistor, the fifth transistor and the sixth transistor are electrically connected to the second dynamic node. The sources of the first transistor and the fourth transistor are electrically connected to the input node, A first voltage is input to each source of the second transistor, the third transistor, the fifth transistor, and the sixth transistor, A first signal is input to gates of the first transistor and the sixth transistor, A second signal is input to the gates of the fourth transistor and the third transistor, And, a third signal is input to gates of the second transistor and the fifth transistor.

4. The dynamic logic circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor all include a back gate, And in each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, the back gate is electrically connected to the gate.

5. A semiconductor device comprising: A first layer including a plurality of processing engines; and a second layer on the first layer, The second layer includes a plurality of embedded storage devices, each of which includes a peripheral circuit and a storage cell array. The memory cell array includes a plurality of memory cells arranged in a matrix. each of the plurality of embedded storage devices overlaps with each of the plurality of processing engines, Each of the plurality of processing engines comprises a silicon transistor, The peripheral circuit includes a transistor including an oxide semiconductor, Each of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor, Each of the first transistor, the second transistor, and the third transistor includes a gate, a back gate, and the oxide semiconductor, And, different voltages are input to the back gate of the first transistor, the back gate of the second transistor, and the back gate of the third transistor.

6. A semiconductor device comprising: A first layer including a plurality of processing engines; and a second layer on the first layer, The second layer includes a plurality of embedded storage devices, each of which includes a peripheral circuit and a storage cell array. The memory cell array includes a plurality of memory cells arranged in a matrix. each of the plurality of embedded storage devices overlaps with each of the plurality of processing engines, Each of the plurality of processing engines comprises a silicon transistor, Each of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor, Each of the first transistor, the second transistor, and the third transistor includes a gate, a back gate, and an oxide semiconductor, And, different voltages are input to the back gate of the first transistor, the back gate of the second transistor, and the back gate of the third transistor.

7. The semiconductor device according to claim 5 or 6, At least one of the plurality of processing engines is electrically connected to the memory cell array through the peripheral circuit.

8. The semiconductor device according to claim 5 or 6, wherein each of the plurality of memory cells further comprises a holding node and a capacitor, A first terminal of the capacitor is electrically connected to the gate of one of the first transistor, the second transistor, and the third transistor, And the second terminal of the capacitor is electrically connected to the read bit line.

9. The semiconductor device according to claim 5 or 6, All transistors in the memory cell array include the oxide semiconductor.

10. The semiconductor device according to claim 5 or 6, All transistors in the peripheral circuit and the memory cell array include the oxide semiconductor.

11. A semiconductor device comprising: a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, a seventh wiring, an eighth wiring, and a ninth wiring; as well as a first storage unit, a second storage unit and a third storage unit, The first storage unit is adjacent to the second storage unit in a row direction. The first storage unit is adjacent to the third storage unit in a column direction, The first storage unit, the second storage unit and the third storage unit all include a holding node, a first transistor, a second transistor, a third transistor and a capacitor. The first transistor, the second transistor, and the third transistor each include a channel formation region, the channel formation region including a metal oxide, In each of the first memory cell and the second memory cell, a gate of the first transistor is electrically connected to the first wiring, In each of the first memory cell and the second memory cell, a gate of the second transistor is electrically connected to the holding node, In each of the first memory cell and the second memory cell, a gate of the third transistor is electrically connected to the second wiring, In the third memory cell, the gate of the first transistor is electrically connected to the third wiring, In the third memory cell, the gate of the second transistor is electrically connected to the holding node, In the third memory cell, the gate of the third transistor is electrically connected to the fourth wiring, In each of the first memory cell and the third memory cell, one of a source and a drain of the first transistor is electrically connected to the fifth wiring, In each of the first memory cell and the third memory cell, the other of the source and the drain of the first transistor is electrically connected to the holding node, In the second memory cell, one of the source and the drain of the first transistor is electrically connected to the sixth wiring, In the second memory cell, the other of the source and the drain of the first transistor is electrically connected to the holding node, In each of the first memory cell and the third memory cell, the second transistor and the third transistor are electrically connected in series between the seventh wiring and the eighth wiring, In the second memory cell, the second transistor and the third transistor are electrically connected in series between the ninth wiring and the eighth wiring, In each of the first memory cell, the second memory cell, and the third memory cell, a first terminal of the capacitor is electrically connected to the holding node, In each of the first memory cell and the third memory cell, the second terminal of the capacitor is electrically connected to the seventh wiring, Furthermore, in the second memory cell, the second terminal of the capacitor is electrically connected to the ninth wiring.

12. The semiconductor device according to claim 11, The first transistor, the second transistor and the third transistor all include a back gate. A first voltage is applied to the back gate of the first transistor, A second voltage is applied to the back gate of the second transistor, A third voltage is applied to the back gate of the third transistor, the second voltage is higher than the first voltage, And the second voltage is higher than the third voltage.

13. The semiconductor device according to claim 11 or 12, wherein the first wiring and the third wiring both have a function of writing word lines, The second wiring and the fourth wiring both have a function of a read word line, The fifth wiring and the sixth wiring both have a function of a write bit line, The seventh wiring and the ninth wiring both have the function of a read bit line, And, a voltage is applied to the eighth wiring.

14. The semiconductor device according to claim 11 or 12, further comprising a dynamic logic circuit electrically connected to the first wiring and the second wiring, wherein the dynamic logic circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor all include a channel formation region, and the channel formation region includes a metal oxide. Furthermore, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor all include a gate and a back gate electrically connected to the gate.

15. A semiconductor device comprising: CMOS logic circuits; as well as The storage device on the CMOS logic circuit, The CMOS logic circuit includes a CPU and a bus. The storage device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring and a storage unit. The memory cell includes a holding node, a first transistor, a second transistor, a third transistor, and a capacitor. The first transistor, the second transistor, and the third transistor all include a channel formation region, and the channel formation region includes a metal oxide. The gate of the first transistor is electrically connected to the first wiring, One of a source and a drain of the first transistor is electrically connected to the third wiring, the other of the source and the drain of the first transistor being electrically connected to the holding node, The gate of the second transistor is electrically connected to the holding node, The gate of the third transistor is electrically connected to the second wiring, the second transistor and the third transistor are electrically connected in series between the fourth wiring and the fifth wiring, a first terminal of the capacitor is electrically connected to the holding node, A second terminal of the capacitor is electrically connected to the fourth wiring, Furthermore, data communication between the storage device and the CPU is performed through the bus.

16. A semiconductor device comprising: CMOS logic circuits; as well as The storage device on the CMOS logic circuit, The CMOS logic circuit includes a CPU and a bus. The storage device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, a seventh wiring, an eighth wiring and a storage unit. The memory cell includes a holding node, a first transistor, a second transistor, a third transistor, and a capacitor. The first transistor, the second transistor, and the third transistor all include a channel formation region, and the channel formation region includes a metal oxide. The gate of the first transistor is electrically connected to the first wiring, One of a source and a drain of the first transistor is electrically connected to the third wiring, the other of the source and the drain of the first transistor being electrically connected to the holding node, The back gate of the first transistor is electrically connected to the sixth wiring, The gate of the second transistor is electrically connected to the holding node, The gate of the third transistor is electrically connected to the second wiring, the second transistor and the third transistor are electrically connected in series between the fourth wiring and the fifth wiring, The back gate of the second transistor is electrically connected to the seventh wiring, The back gate of the third transistor is electrically connected to the eighth wiring, a first terminal of the capacitor is electrically connected to the holding node, A second terminal of the capacitor is electrically connected to the fourth wiring, Furthermore, data communication between the storage device and the CPU is performed through the bus.

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