Semiconductor device

Abstract

A semiconductor device may include: a first source transfer transistor that controls a connection between a global source line and a first local source line; a second source transfer transistor controlling a connection between the global source line and a second local source line; a first memory block that operates using a first source voltage supplied through the first local source line; and a second memory block that operates using a second source voltage supplied through the second local source line.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices. Background Art

[0002] The integration degree (also called integration density) of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, further improvement in the integration degree of a semiconductor device using a memory cell formed in a single layer above a substrate has reached a limit that is difficult to surpass, and a three-dimensional semiconductor device having memory cells stacked in multiple layers above a substrate has been proposed. However, further improvements in the structure, operation method, and operation reliability of the three-dimensional semiconductor device are still needed, and further improvements in the structure, operation method, and operation reliability of the three-dimensional semiconductor device are being studied. Summary of the invention

[0003] According to an embodiment disclosed in the present invention, a semiconductor device is provided, which includes: a first source transfer transistor, which controls the connection between a global source line and a first local source line; a second source transfer transistor, which controls the connection between the global source line and the second local source line; a first storage block, which uses a first source voltage provided through the first local source line; and a second storage block, which uses a second source voltage provided through the second local source line.

[0004] According to an embodiment disclosed in the present invention, a semiconductor device may include: a first source transfer transistor, which controls the connection between a first global source line and a first local source line; a second source transfer transistor, which controls the connection between a second global source line and a second local source line; and a storage block, which includes a first sub-storage block using a first source voltage provided by the first local source line and a second sub-storage block using a second source voltage provided by the second local source line.

[0005] According to an embodiment disclosed in the present invention, a semiconductor device may include: a peripheral circuit; a gate structure including stacked gate lines; a bonding structure located between the peripheral circuit and the gate structure and electrically connecting the peripheral circuit and the gate structure; a local source line located on the gate structure; and a source transfer transistor controlling the connection between the local source line and at least one global source line.

[0006] According to an embodiment disclosed in the present invention, a semiconductor device may include: a global source line; a first local source line and a second local source line, which are electrically connected to the global source line; a first transfer transistor and a second transfer transistor, which respectively control the electrical connection between the global source line and each of the first local source line and the second local source line; a first storage block; a second storage block; a voltage generating circuit, which is electrically connected to the global source line, the voltage generating circuit is constructed to generate a first source voltage and a second source voltage, and provide the first source voltage and the second source voltage to the global source line, wherein the first storage block operates using the first source voltage provided by the first local source line; and wherein the second storage block operates using the second source voltage provided by the second local source line.

[0007] These and other features and advantages of the present invention will become better understood from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a simplified block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a simplified block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3A and Figure 3B FIG. 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B is a circuit diagram of a memory cell array of a semiconductor device according to an embodiment disclosed in the present invention.

[0012] Figure 5A and Figure 5B is a diagram illustrating a configuration of a semiconductor device according to an embodiment disclosed in the present invention.

[0013] FIG. 6A to FIG. 6D FIG. 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 7 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0015] Figure 8 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention. DETAILED DESCRIPTION

[0016] Embodiments disclosed herein provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0017] The integration degree of a semiconductor device can be improved by stacking memory cells in three dimensions. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0018] Hereinafter, embodiments according to the technical spirit disclosed in the present invention will be described with reference to the accompanying drawings.

[0019] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings.

[0020] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). As such, variations in the illustrated configurations and shapes are foreseeable due to, for example, manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present invention as defined in the appended claims.

[0021] The present invention is described herein with reference to cross-sectional views and / or plan views of idealized embodiments of the present invention. However, the embodiments of the present invention should not be construed as limiting the inventive concept. Although some embodiments of the present invention will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be modified without departing from the principles and spirit of the present invention.

[0022] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the spirit and scope of the present invention, the first element described below may also be referred to as the second element or the third element.

[0023] It should also be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on the other element, directly connected to or coupled to the other element, or one or more intervening elements may be present. Furthermore, the connection / coupling may not be limited to physical connections, and may include non-physical connections such as wireless connections.

[0024] In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0026] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] The term "a" or "an" element refers to one or more elements. Therefore, the terms "a", "an", "one or more" and "at least one" can be used interchangeably.

[0028] It should be further understood that when the terms "include", "comprising", "including" and "comprising" are used in this specification, they specify the presence of the mentioned elements and do not exclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs based on this disclosure.

[0030] It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of this disclosure and the related art, and will not be interpreted as an idealized or overly formal meaning unless expressly so defined herein.

[0031] Below, in the accompanying drawings, a direction perpendicular to the top surface of the substrate is defined as a first direction FD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as a second direction SD and a third direction TD, respectively. The substrate may correspond to a single-layer or multi-layer substrate. The second direction SD may correspond to an extension direction of a word line, and the third direction TD may correspond to an extension direction of a bit line. The second direction SD and the third direction TD may cross each other substantially perpendicularly. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0032] Figure 1 is a simplified block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0033] Reference Figure 1 , the semiconductor device 100 may include a memory cell array 110 , an address decoder 120 , a voltage generating circuit 130 , a read / write circuit 140 , and a control circuit 150 .

[0034] The memory cell array 110 may include memory cells. According to an embodiment, the memory cell array 110 may include a memory block, and each memory block may include a page. Here, the memory block may be a unit of an erase operation, and the page may be a unit of a read operation. The memory cell array 110 may be connected to the address decoder 120 through row lines such as a source select line SSL, a word line WL, a drain select line DSL, and a local source line SL. The memory cell array 110 may be connected to the read / write circuit 140 through column lines such as a bit line BL.

[0035] The control circuit 150 may receive a command CMD and an address ADD from the controller. The control circuit 150 may generate a control signal according to the received command CMD to perform internal operations such as a programming operation, a reading operation, and an erasing operation. The control circuit 150 may output the control signal to the voltage generating circuit 130, the address decoder 120, and the read / write circuit 140.

[0036] The voltage generating circuit 130 may generate an internal voltage having various voltage levels depending on the internal operation to be performed, and may provide the generated internal voltage or multiple generated internal voltages to the address decoder 120. For example, the generated internal voltage may be an operation voltage for performing a programming operation, a reading operation, an erasing operation. According to an embodiment, the internal voltage may be a source voltage to be provided to a local source line. The source voltage may have a positive level or a negative level.

[0037] According to an embodiment, the voltage generation circuit 130 may generate a program voltage, a pass voltage, a source voltage, a bit line voltage, etc. for performing a program operation. The voltage generation circuit 130 may generate a read voltage, a pass voltage, a source voltage, a bit line voltage, etc. for performing a read operation. The read operation may be a verification operation for verifying a program operation or an erase operation. The voltage generation circuit 130 may generate an erase voltage, a gate induced drain leakage (GIDL) voltage, a source voltage, etc. for performing an erase operation.

[0038] The address decoder 120 may activate a source selection line, a word line, a drain selection line, or a local source line according to an address ADD received from the control circuit 150. A voltage level of a global line may be transferred to a local line.

[0039] The read / write circuit 140 may be connected to the memory cell array 110 through the bit lines BL. During a program operation, the read / write circuit 140 may operate as a write driver and input data Data to be stored in the memory cell array 110. During a read operation or a verification operation, the read / write circuit 140 may operate as a sense amplifier and output data Data stored in the memory cell array 110.

[0040] Figure 2 is a simplified block diagram illustrating a configuration of a semiconductor device according to an embodiment disclosed in the present invention. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0041] Reference Figure 2 , the semiconductor device may include a memory cell array 210 , an address decoder 220 , and a voltage generating circuit 230 .

[0042] The memory cell array 210 may include a plurality of memory blocks. Each memory block may include a memory string MS. The memory string MS in each memory block may be connected between the bit lines BL1 to BLk and the local source line SL. Here, k may be an integer greater than 2. Each memory string MS may include at least one drain select transistor DST, a plurality of memory cells MC, and at least one source select transistor SST.

[0043] The gate electrode of the memory cell MC may be connected to the word line WL. The source selection line SSL may be connected to the gate electrode of the source selection transistor SST. The connection between the memory string MS and the local source line SL may be controlled by the source selection line SSL. When the source selection transistor SST is turned on, the memory string MS and the local source line SL may be connected. The drain selection line DSL may be connected to the gate electrode of the drain selection transistor DST. The connection between the memory string MS and the bit lines BL1 to BLk may be controlled by the drain selection line DSL. When the drain selection transistor DST is turned on, the memory string MS and the bit lines BL may be connected.

[0044] The voltage generating circuit 230 may generate the operating voltage required for the programming operation, the reading operation, and the erasing operation of the memory cell, and may transmit the generated operating voltage to the global line. According to an embodiment, during the programming operation, the voltage generating circuit 230 may transmit the programming voltage or the pass voltage to the global word line GWL, and may transmit the source voltage to the global source line GSL. During the reading operation, the voltage generating circuit 230 may transmit the reading voltage or the pass voltage to the global word line GWL, and may transmit the source voltage to the global source line GSL. During the erasing operation, the voltage generating circuit 230 may transmit the erasing voltage to at least one of the global drain selection line GDSL and the global source selection line GSSL, may transmit the ground voltage to the global word line GWL, and may transmit the source voltage to the global source line GSL.

[0045] The address decoder 220 may include a block selection circuit 222 and a transfer circuit 224. The transfer circuit 224 may include a transfer transistor for controlling the connection between the global line and the local line. The transfer circuit 224 may include at least one source transfer transistor SPT, at least one source selection transfer transistor SSPT, a plurality of word line transfer transistors WLPT, and at least one drain selection transfer transistor DSPT. The source transfer transistor SPT may control the connection between the global source line GSL and the local source line SL. The source selection transfer transistor SSPT may control the connection between the global source selection line GSSL and the source selection line SSL. The word line transfer transistor WLPT may control the connection between the global word line GWL and the word line WL. The drain selection transfer transistor DSPT may control the connection between the global drain selection line GDSL and the drain selection line DSL.

[0046] The block selection circuit 222 may generate a block selection signal BLKSEL in response to an address and transmit the generated block selection signal BLKSEL to the transmission circuit 224. The discharge transistor Tr_D may discharge a line transmitting the block selection signal BLKSEL in response to a discharge signal DISCH.

[0047] The transfer circuit 224 may be controlled by a block selection signal BLKSEL. The transfer circuit 224 may operate in response to the block selection signal BLKSEL of the block selection circuit 222. The block selection signal BLKSEL may be applied to the gate electrode of the transfer transistor, and when the transfer transistor is turned on, the global line and the local line may be electrically connected.

[0048] When the block selection signal BLKSEL is activated, the global source line GSL and the local source line LSL may be connected, and a source voltage may be applied to the local source line SL. When the block selection signal BLKSEL is activated, the global source selection line GSSL and the source selection line SSL may be connected. When the block selection signal BLKSEL is activated, the global word line GWL and the word line WL may be connected. When the block selection signal BLKSEL is activated, the global drain selection line GDSL and the drain selection line DSL may be connected.

[0049] According to the above configuration, the global source line GSL and the local source line SL can be connected through the source transfer transistor SPT, and the source voltage can be applied to the local source line SL. Here, the local source line SL can be a local source line SL separated in units of memory blocks or a local source line separated in units of sub-blocks. Therefore, the source voltage can be applied in units of memory blocks or in units of sub-blocks.

[0050] Figure 3A and Figure 3B FIG. 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0051] Reference Figure 3A , the semiconductor device may include a global source line GSL, local source lines SL1 to SLm, source transfer transistors SPT1 to SPTm, and a memory plane PL. Here, m may be an integer greater than 2. The memory plane PL may include a plurality of memory blocks MB1 to MBm. The local source lines SL1 to SLm may be separated in units of memory blocks.

[0052] The memory blocks MB1 to MBm may be connected to the local source lines SL1 to SLm, respectively. The memory blocks MB1 to MBm may be operated using the source voltage supplied through the local source lines SL1 to SLm. The source transfer transistors SPT1 to SPTm may control the connection between the global source line GSL and the local source lines SL1 to SLm. The source transfer transistors SPT1 to SPTm may operate in response to the block selection signals BLKSEL1 to BLKSELm. According to an embodiment, when the first block selection signal BLKSEL1 is activated, the first source transfer transistor SPT1 may be turned on, and the global source line GSL and the first local source line SL1 may be electrically connected. The source voltage of the global source line GSL may be transmitted to the first local source line SL1. When the second block selection signal BLKSEL2 is activated, the second source transfer transistor SPT2 may be turned on, and the source voltage of the global source line GSL may be transmitted to the second local source line SL2. When the mth block selection signal BLKSELm is activated, the mth source transfer transistor SPTm may be turned on, and the source voltage of the global source line GSL may be transferred to the mth local source line SLm.

[0053] Reference Figure 3B , the semiconductor device may include global source lines GSL1 to GSLn, local source lines S_SL1 to S_SLn, source transfer transistors SPT1 to SPTn, and a memory block MB. Here, n may be an integer greater than 2. The memory block MB may include a plurality of sub-memory blocks S_MB1 to S_MBn. The local source lines S_SL1 to S_SLn may be separated in units of sub-memory blocks.

[0054] The sub-memory blocks S_MB1 to S_MBn may be connected to local source lines S_SL1 to S_SLn, respectively. The source transfer transistors SPT1 to SPTn may control the connection between the global source lines GSL1 to GSLn and the local source lines S_SL1 to S_SLn. The source transfer transistors SPT1 to SPTn may operate in response to a block selection signal BLKSEL. According to an embodiment, when the block selection signal BLKSEL is activated, the first source transfer transistor SPT1 may be turned on, and the first global source line GSL1 and the first local source line S_SL1 may be electrically connected. The source voltage of the first global source line GSL1 may be transmitted to the first local source line S_SL1. When the block selection signal BLKSEL is activated, the nth source transfer transistor SPTn may be turned on, and the source voltage of the nth global source line GSLn may be transmitted to the nth local source line S_SLn.

[0055] According to the above construction, the connection of the global source line and the local source line can be controlled by the source transfer transistor. Therefore, the same source voltage may not be applied to the entire memory plane. The source voltage can be applied to the selected memory block or the selected sub-memory block, and the unselected memory block can be floated or grounded.

[0056] The local source lines SL1 to SLm may be separated in units of memory blocks, or the local source lines S_SL1 to S_SLn may be separated in units of sub-memory blocks. Accordingly, a source voltage may be applied in units of memory blocks, or a source voltage may be applied in units of sub-memory blocks. Source voltages of different levels may be applied to the selected local source lines and the unselected local source lines. Therefore, the source capacitance may be reduced, the operation consumption current may be reduced, and the operation characteristics may be improved.

[0057] Figure 4A and Figure 4B is a circuit diagram of a memory cell array of a semiconductor device according to an embodiment disclosed in the present invention. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0058] Reference Figure 4A and Figure 4B , the memory block MB may include a plurality of memory strings MS, and the plurality of memory strings MS may be connected between the bit lines BL1 to BLk and the local source line SL. Each memory string MS may include at least one drain select transistor DST, a plurality of memory cells MC, and at least one source select transistor SST connected in series. In addition, each memory string MS may also include at least one dummy memory cell connected between the drain select transistor DST and the memory cell MC and / or between the source select transistor SST and the memory cell MC.

[0059] The gate electrodes of the memory cells MC may be connected to their corresponding word lines WL. A word line voltage (program voltage, pass voltage, read voltage, etc.) required to drive the memory cells may be applied to each word line WL. The gate electrodes of the drain select transistors DST may be connected to their corresponding drain select lines DSL. The gate electrodes of the source select transistors SST may be connected to their corresponding source select lines SSL.

[0060] Drain selection transistors DST arranged in the same row may be connected to the same drain selection lines DSL1 to DSLx. Drain selection transistors DST arranged in different rows may be connected to different drain selection lines DSL1 to DSLx. Here, x may be an integer greater than 2. Memory cells MC of the same height may be connected to the same word line WL.

[0061] Reference Figure 4A , the source selection transistors SST of the same height may be connected to the same source selection line SSL. Therefore, the local source line SL may be divided in units of memory blocks MB, and an erase operation may be performed in units of memory blocks.

[0062] Reference Figure 4B , the source selection transistors SST arranged in the same row may be connected to the same source selection lines SSL1 to SSLx. The source selection transistors SST arranged in different rows may be connected to different source selection lines SSL1 to SSLx. Therefore, the local source lines SL1 to SLx may be divided in units of sub-memory blocks, and an erase operation may be performed in units of sub-memory blocks.

[0063] According to the above configuration, the memory cells can be stacked three-dimensionally. In addition, the erase operation can be performed in units of memory blocks or in units of sub-memory blocks.

[0064] Figure 5A and Figure 5B 2 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0065] Reference Figure 5A and Figure 5B , the semiconductor device may include a memory block MB, a local source line SL, and a transmission circuit PSC. The memory block MB may include stacked memory cells. According to an embodiment, the memory block MB may include a memory string connected between the local source line SL and the bit line BL, and may also include a source selection line SSL, a word line WL, and a drain selection line DSL. The transmission circuit PSC may include a source transfer transistor SPT, a source selection transfer transistor SSPT, a word line transfer transistor WLPT, and a drain selection transfer transistor DSPT.

[0066] Reference Figure 5A , the local source line SL may be located on the memory block MB. The local source line SL may be formed in units of memory blocks.

[0067] The connection between the global source line GSL and the local source line SL can be controlled by a source transfer transistor SPT. The connection between the global source selection line GSSL and the source selection line SSL can be controlled by a source selection transfer transistor SSPT. The connection between the global word line GWL and the word line WL can be controlled by a word line transfer transistor WLPT. The drain selection transfer transistor DSPT can control the connection between the global drain selection line GDSL and the drain selection line DSL.

[0068] Reference Figure 5B , local source lines S_SL1 to S_SLn may be located on a memory block MB. The local source lines S_SL1 to S_SLn may be formed in units of sub-memory blocks. The transfer circuit PSC may include source transfer transistors SPT1 to SPTn. The local source lines S_SL1 to S_SLn of the same memory block MB may be controlled by the same transfer circuit PSC. The first source transfer transistor SPT1 may control the connection of the first global source line GSL1 and the first local source line S_SL1. The nth source transfer transistor SPTn may control the connection of the nth global source line GSLn and the nth local source line S_SLn. The first source transfer transistor SPT1 to the nth source transfer transistor SPTn may be controlled by the same block selection signal BLKSEL. When the block selection signal BLKSEL is activated, the first to nth source transfer transistors SPT1 to SPTn may be turned on, and the first to nth global source lines GSL1 to GSLn may be connected to the first to nth local source lines S_SL1 to S_SLn.

[0069] According to the above configuration, the source voltage can be adjusted in memory block units or in sub-memory block units by dividing the local source lines in memory block units or in sub-memory block units. Therefore, the operation characteristics of the semiconductor device can be improved.

[0070] Table 1 illustrates bias conditions of a read operation, a program operation, and an erase operation of a semiconductor device according to an embodiment disclosed in the present invention. For reference, the read operation may be a verification operation.

[0071]

Table 1

[0072] Read programming Erase BL <![CDATA[V BL ]]> Vcc Verase Selected SL Vneg Vcc1 Verase Unselected SL <![CDATA[0V or V BL > Vcc2 0V Selected WL Vread Vpgm 0V Unselected WL VpassR VpassP 0V Selected SSL Vpass 0V Vgid SSL not selected 0V 0V Vgid Selected DSL Vpass Vcc Vgid DSL not selected 0V Vcc → 0V Vgid

[0073] According to the implementation mode, as shown in FIG. Figure 5AAs described, the local source line SL may be divided in units of memory blocks. In this case, different source voltages may be applied to a selected memory block and an unselected memory block among a plurality of memory blocks belonging to a memory plane.

[0074] During a read operation, different voltages may be applied to the selected local source line SL and the unselected local source line SL. A negative source voltage may be applied to the selected local source line SL, and a ground voltage or a bit line voltage V may be applied to the unselected local source line SL. BL . Bit line voltage V BL Here, the bit line voltage V BL It can be a precharge voltage. A read voltage Vread can be applied to the selected word line WL, and a pass voltage VpassR can be applied to the unselected word line WL. Here, the read voltage Vread can have a level at which the memory cell is turned on or off according to the data stored in the memory cell. The pass voltage VpassR can have a level that turns on the memory cell regardless of the data stored in the memory cell. A pass voltage Vpass can be applied to the selected source selection line and the selected drain selection line, and a ground voltage can be applied to the unselected source selection line and the unselected drain selection line. Here, the pass voltage Vpass can be a voltage that turns on the source selection transistor and the drain selection transistor. Accordingly, a negative source voltage can be transmitted to the selected local source line SL, and the precharge voltage of the bit line can be increased. The unselected local source line SL can be floated, or a ground voltage or a bit line voltage V can be applied to the unselected local source line SL. BL Therefore, the cell current can be increased without increasing the interference between the bit lines.

[0075] During a programming operation, a first operating voltage Vcc1 may be applied to a selected local source line SL among the local source lines SL, and a second operating voltage Vcc2 of a level different from that of the first operating voltage Vcc1 may be applied to the unselected local source lines SL. A programming voltage Vpgm may be applied to the selected word line WL, and a pass voltage VpassP may be applied to the unselected word line WL. Here, the pass voltage VpassP may be used to boost the channel of the unselected memory cell, and may have a level lower than that of the programming voltage Vpgm. A ground voltage may be applied to the source selection line, and may be grounded after the operating voltage Vcc is applied to the drain selection line.

[0076] According to an embodiment, by applying a second operating voltage Vcc2 having a level higher than that of the first operating voltage Vcc1 to the unselected local source line SL, an operating voltage of a relatively high level may be applied to the unselected local source line SL, and the boost level may be increased. By increasing the channel boost of the unselected storage string, the operating window may be increased. According to an embodiment, when the boost level is increased by GIDL, by applying a second operating voltage Vcc2 having a level lower than that of the first operating voltage Vcc1 to the unselected local source line SL, an operating voltage of a relatively low level may be applied to the unselected local source line SL and the boost level may be reduced. According to an embodiment, by applying operating voltages of different levels to the unselected local source line SL, the channel boost may be adjusted in units of sub-blocks.

[0077] According to the implementation mode, as shown in FIG. Figure 5B As described, the local source line SL may be divided in units of sub memory blocks. In this case, different source voltages may be applied to a selected sub memory block and unselected sub memory blocks among a plurality of sub memory blocks belonging to a memory block.

[0078] During the erase operation, an erase voltage Verase may be applied to a selected local source line S_SL1 among the local source lines S_SL1 to S_SLn, and a ground voltage may be applied to unselected local source lines S_SL2 to S_SLn. A ground voltage may be applied to a word line WL, and a GIDL voltage Vgid1 may be applied to a source selection line SSL and a drain selection line DSL. Accordingly, an erase operation may be performed only on a sub-storage block connected to the selected local source line S_SL1. Therefore, an erase operation may be performed in units of sub-storage blocks.

[0079] During the programming operation, a first operating voltage Vcc1 may be applied to a selected local source line S_SL1 among the local source lines S_SL1 to S_SLn, and a second operating voltage Vcc2 having a level higher than that of the first operating voltage Vcc1 may be applied to the unselected local source lines S_SL2 to S_SLn. Accordingly, the channel boosting of the unselected memory string may be increased and the operating window may be increased. In addition, by applying operating voltages of different levels to the unselected local source lines SL, the channel boosting may be adjusted in units of sub-blocks.

[0080] FIG. 6A to FIG. 6D 2 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0081] Reference Fig. 6A, the semiconductor device may include a substrate 60, a peripheral circuit PC formed above the substrate 60, a memory cell array CA disposed above the peripheral circuit PC, and a bonding structure BS disposed between the peripheral circuit PC and the memory cell array CA. The peripheral circuit PC may be located on the substrate 60 and may include circuits such as a page buffer, a row decoder, and a sense amplifier. For example, the peripheral circuit PC may include a transistor TR and a corresponding first interconnect structure IC1.

[0082] The memory cell array CA may include a gate structure GST, a local source line SL, a plurality of channel structures CH passing through the gate structure GST, a second interconnection structure IC2, and a third interconnection structure IC3. The gate structure GST may include a gate line 61 and an insulating layer 62 stacked alternately. The gate line 61 may be a word line, a source selection line, a drain selection line, etc. The channel structures CH may be spaced apart from each other and may extend through the gate structure GST. Each channel structure CH may include a channel layer 63, a memory layer 64 surrounding the channel layer 63, and an insulating core 65 in the channel layer 63.

[0083] The local source line SL may be located on the gate structure GST. The local source line SL may be formed in memory block units or in sub-memory block units. The local source line SL may include a conductive layer and may be a single layer or multiple layers. Fig. 6A In the embodiment shown, the local source line SL may include a first conductive layer 66 and a second conductive layer 67 formed on the first conductive layer 66. The first conductive layer 66 and the second conductive layer 67 may have different resistivities. For example, the first conductive layer 66 may include polysilicon, and the second conductive layer 67 may include metal. The channel structure CH may extend into the local source line SL through the gate structure GST. The channel layer 63 and the local source line SL may be connected to each other (i.e., electrically connected). The channel layer 63 and the local source line SL may be directly connected or may be connected through an epitaxial pattern.

[0084] The peripheral circuit PC and the memory cell array CA may be electrically connected through a bonding structure BS. The bonding structure BS may include a first bonding pad BP1 and a second bonding pad BP2. The first bonding pad BP1 and the second bonding pad BP2 may each include a metal such as, for example, copper. The first bonding pad BP1 and the second bonding pad BP2 may be in direct contact with each other. The first bonding pad BP1 and the second bonding pad BP2 may have the same or different cross-sectional areas. For example, in Fig. 6A In the illustrated embodiment, the first bonding pad BP1 may have a larger cross-sectional area than that of the second bonding pad BP2 .

[0085] The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1. Through the first interconnect structure IC1, the first bonding pad BP1 and the peripheral circuit PC may be electrically connected. Each first interconnect structure IC1 may include a contact plug 1, a line 2, etc. The second interconnect structure IC2 and the third interconnect structure IC3 may be located in the second interlayer insulating layer IL2. The second interconnect structure IC2 may be located below the gate structure GST and may be electrically connected to the memory cell array CA. The third interconnect structure IC3 may be located on the gate structure GST and may be electrically connected to the memory cell array CA. The second bonding pad BP2 and the memory cell array CA may be electrically connected through the second interconnect structure IC2 and the third interconnect structure IC3.

[0086] The third interconnect structure IC3 may include a first wire M1, a second wire M2, a first contact plug CT1, and a second contact plug CT2. The first wire M1 may be a wire for transmitting an internal operating voltage, and the second wire M2 may be a wire for transmitting a source voltage.

[0087] The shape and arrangement of the second line M2 may vary according to the local source line SL. Figure 6B , the first line M1 may extend in a direction crossing the memory block MB, and the second line M2 may be located between the first lines M1. The second line M2 and the local source line SL may be connected by a contact plug CT. Figure 6C , the local source line SL may be formed in units of memory blocks, and the second line M2 may also be formed in units of memory blocks. Fig.6D , the local source line SL may be formed in units of sub-memory blocks, and the second line M2 may also be formed in units of sub-memory blocks.

[0088] According to the above structure, the peripheral circuit PC and the memory cell array CA can be manufactured as separate wafers and then electrically connected through the bonding structure BS. In addition, because the local source line SL is located on the gate structure GST, the local source line SL can be separated in units of memory blocks or in units of sub-memory blocks.

[0089] The structures and manufacturing methods according to the above-described embodiments can be applied to semiconductor devices of various structures. Figure 7 and Figure 8 A schematic configuration of a semiconductor device to which the above-described embodiments are applicable is illustrated.

[0090] Figure 7 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0091] Reference Figure 7, the semiconductor device may include a substrate SUB, a peripheral circuit PC disposed over the substrate SUB, and a memory cell array CA disposed over the peripheral circuit PC. Therefore, according to the present embodiment, the peripheral circuit PC and the memory cell array CA may be formed on the same substrate.

[0092] The substrate SUB may include a semiconductor material. For example, the semiconductor material may include at least one of a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. Here, the group IV semiconductor may include single crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). The group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. The group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0093] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include an organic material. According to an embodiment, the substrate SUB may include graphene.

[0094] The substrate SUB may be a bulk wafer or an epitaxial layer grown by a selective epitaxial growth (SEG) method. The substrate SUB may be a layer formed by a metal induced lateral crystallization (MILC) method and may partially include a metal. The substrate SUB may have a single crystal, a polycrystalline, or an amorphous state. The substrate SUB may include impurities of group II, group III, group IV, group V, or group VI. According to an embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0095] The peripheral circuit PC may be located between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, etc. According to an embodiment, the peripheral circuit PC may include an NMOS transistor, a PMOS transistor, a resistor, a capacitor, etc. The peripheral circuit PC may also include an interconnect structure. The interconnect structure may be used as a path for transmitting an operating voltage and may include a contact plug, a line, etc.

[0096] The memory cell array CA may include memory cells. According to an embodiment, the memory cell array CA may include a memory string connected between a source line and a bit line, and each memory string may include stacked memory cells. According to an embodiment, the memory cell array CA may include a memory cell connected between a word line and a bit line. The memory cell array CA may also include an interconnect structure.

[0097] Figure 8 is a diagram showing the structure of a semiconductor device according to an embodiment disclosed in the present invention.

[0098] Reference Figure 8 , the semiconductor device may include a substrate SUB, a peripheral circuit PC disposed above the substrate SUB, a bonding structure BS disposed between the peripheral circuit PC and the memory cell array CA, and a memory cell array CA disposed above the bonding structure BS. Here, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may further include a supporting base SP_B disposed above the memory cell array CA.

[0099] The substrate SUB may be used as a support member in the process of forming the peripheral circuit PC, and the support base SP_B may be used as a support member in the process of forming the memory cell array CA. According to an embodiment, after manufacturing each of the first wafer including the memory cell array CA and the second wafer including the peripheral circuit PC, the first wafer and the second wafer may be electrically connected through the bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer may be removed. The support base SP_B may be completely removed or may be partially left on the memory cell array CA.

[0100] The support substrate SP_B may be a semiconductor substrate, an insulating substrate, an SOI substrate, a GeOI substrate, etc. The support substrate SP_B may be a bulk wafer, an epitaxial layer grown by a SEG method, or a layer formed by a MILC method. The support substrate SP_B may have a single crystal, a polycrystalline, or an amorphous state. The support substrate SP_B may include impurities of group II, group III, group IV, group V, or group VI.

[0101] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. According to an embodiment, the memory cell array CA and the peripheral circuit PC can be bonded by a wafer-on-wafer bonding method, a chip-on-wafer bonding method, a chip-on-chip bonding method, etc. The bonding structure BS may include a bonding pad, a bonding layer, a bonding interface, etc. The bonding pad may include a metal and / or alloy of copper, aluminum, etc. The bonding interface may include a non-metal-non-metal interface, a metal-metal interface, etc. The memory cell array CA and the peripheral circuit PC may be electrically connected via the bonding structure BS.

[0102] For reference, the interconnection structure included in the memory cell array CA and / or the peripheral circuit PC can be directly connected without a bonding pad. According to an embodiment, a bonding layer included in the memory cell array CA and a bonding layer included in the peripheral circuit PC can be bonded to form a bonding interface, and the interconnection structure included in the memory cell array CA and the interconnection structure included in the peripheral circuit PC can be directly bonded. Accordingly, contact plugs, wires, etc. formed on different wafers can be electrically connected without separate bonding pads.

[0103] Other structures can be referred to above Figure 7 The structures described are the same or similar.

[0104] In addition, the semiconductor device may have a Figure 7 and Figure 8 The described embodiments are combined together or may have a structure in which the above reference is modified. Figure 7 and Figure 8 The structure of a part of the embodiment described. Figure 7 and Figure 8 In the described embodiments, the positions of the memory cell array CA and the peripheral circuit PC may be changed. At least one memory cell array CA and / or at least one peripheral circuit PC may be additionally incorporated into the reference Figure 7 According to an embodiment, a portion of the peripheral circuit PC may be located in the memory cell array CA.

[0105] Although the embodiments of the technical concept disclosed in the present invention have been described with reference to the accompanying drawings, this is only used to describe the embodiments of the concept disclosed in the present invention, and the present invention is not limited to the above-mentioned embodiments. Within the scope of the technical concept disclosed in the present invention, technicians in the field of the present invention can make various forms of replacement, modification, change and combination of the embodiments, and these also belong to the scope of the present invention.

[0106] CROSS-REFERENCE TO RELATED APPLICATIONS

[0107] This application claims priority to Korean Patent Application No. 10-2023-0151590 filed on November 6, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a first source transfer transistor controlling a connection between the global source line and the first local source line; a second source transfer transistor controlling a connection between the global source line and a second local source line; a first memory block using a first source voltage provided through the first local source line; as well as A second memory block uses a second source voltage provided through the second local source line.

2. The semiconductor device according to claim 1, further comprising: A voltage generating circuit generates the first source voltage and the second source voltage and supplies the first source voltage and the second source voltage to the global source line.

3. The semiconductor device according to claim 1, wherein The first memory block includes a drain selection line, and The semiconductor device further includes: a global drain select line; and A drain select pass transistor controls a connection between the global drain select line and the drain select line.

4. The semiconductor device according to claim 1, wherein The first memory block includes word lines, and The semiconductor device further includes: global word lines; and A word line pass transistor controls a connection between the global word line and the word line.

5. The semiconductor device according to claim 1, wherein The first memory block includes a source selection line, and The semiconductor device further includes: a global source select line; and A source select pass transistor controls a connection between the global source select line and the source select line.

6. The semiconductor device according to claim 1, wherein During a read operation, the first memory block is selected, and a negative voltage is applied to the first local source line as the first source voltage.

7. The semiconductor device according to claim 6, wherein: A ground voltage is applied to the second local source line as the second source voltage.

8. The semiconductor device according to claim 1, wherein During a program operation, the first memory block is selected, and a first operating voltage is applied to the first local source line as the first source voltage.

9. The semiconductor device according to claim 8, wherein: A second operating voltage having a level different from that of the first operating voltage is applied to the second local source line as the second source voltage.

10. A semiconductor device, comprising: a first source transfer transistor controlling a connection between a first global source line and a first local source line; a second source transfer transistor controlling a connection between a second global source line and a second local source line; as well as A memory block includes a first sub-memory block using a first source voltage supplied through the first local source line and a second sub-memory block using a second source voltage supplied through the second local source line.

11. The semiconductor device according to claim 10, further comprising: A voltage generating circuit generates the first source voltage and the second source voltage and supplies the first source voltage and the second source voltage to the first global source line and the second global source line.

12. The semiconductor device according to claim 10, wherein: During a program operation, the first sub-memory block of the memory block is selected, and a first operating voltage is applied to the first local source line as the first source voltage.

13. The semiconductor device according to claim 12, wherein: A second operating voltage having a level different from that of the first operating voltage is applied to the second local source line as the second source voltage.

14. The semiconductor device according to claim 10, wherein: During an erase operation, the first sub-memory block of the memory block is selected, and an erase voltage is applied to the first local source line as the first source voltage.

15. The semiconductor device according to claim 14, wherein: A ground voltage is applied to the second local source line as the second source voltage.

16. A semiconductor device, comprising: Peripheral circuits; A gate structure comprising stacked gate lines; a bonding structure, the bonding structure being located between the peripheral circuit and the gate structure and electrically connecting the peripheral circuit and the gate structure; a local source line, the local source line being located on the gate structure; and A source transfer transistor controls a connection between the local source line and at least one global source line.

17. The semiconductor device according to claim 16, wherein: The local source line comprises a first local source line and a second local source line, The at least one global source line includes a first global source line and a second global source line, and The source transfer transistors include a first source transfer transistor that controls a connection between the first global source line and the first local source line, and a second source transfer transistor that controls a connection between the second global source line and the second local source line.

18. The semiconductor device according to claim 16, wherein: The local source lines include a first local source line and a second local source line, and The source transfer transistors include a first source transfer transistor that controls a connection between the global source line and the first local source line, and a second source transfer transistor that controls a connection between the global source line and the second local source line.

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